LVDS Signals
LVDS Signals
LVDS Signals
Revision 1.2
PN-4584
May 2000
TIA PN-4584
Revision 1.2
Contents Page
1 SCOPE .................................................................................................................... 1
2.2 DTE................................................................................................................... 2
3 APPLICABILITY ...................................................................................................... 3
4 ELECTRICAL CHARACTERISTICS........................................................................ 5
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FOREWORD
This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on
Data Transmission Interfaces.
This Standard was developed in response to a demand from the data communications
community for a general purpose high-speed interface standard for use in high
throughput DTE-DCE interfaces.
The voltage levels specified in this Standard were specified such that maximum
flexibility would be provided, while providing a low power, high speed, differential
interface. Generator output characteristics are independent of power supply, and may
be designed for standard +5 V, +3.3 V or even power supplies as low as +2.5 V.
Integrated circuit technology may be BiCMOS, CMOS, or GaAs technology. The low
voltage (330 mV) swing limits power dissipation, while also reducing radiation of EMI
signals. Differential signaling provides multiple benefits over single-ended signaling,
notably common-mode rejection, and magnetic canceling.
This Standard includes two Annexes, both are informative only. Annex A provides
guidelines for application, addressing data signaling rate and cable length issues.
Annex B provides comparison information with other interface standards, and
references to this Standard.
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1 SCOPE
This Standard specifies the electrical characteristics of low voltage differential signaling
interface circuits, normally implemented in integrated circuit technology, that may be
employed when specified for the interchange of binary signals between:
The logic function of the generator and the receiver is not defined by this Standard, as it
is application dependent. The generators and receivers may be inverting, non-inverting,
or may include other digital blocks such as parallel-to-serial or serial-to-parallel
converters to boost the data signaling rate on the interchange circuit as required by the
application.
It is intended that this Standard will be referenced by other standards that specify the
complete interface (i.e., connector, pin assignments, function) for applications where
the electrical characteristics of a low voltage differential signaling interface circuit is
required. This Standard does not specify other characteristics of the DTE-DCE
interface (such as signal quality, protocol, maximum data signaling rate, bus structure,
and/or timing) essential for proper operation across the interface.
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For the purposes of this Standard, the following definitions, symbols and abbreviations
apply:
Data signaling rate - expressed in the units bit/s (bits per second), is the significant
parameter. It may be different from the equipment’s data transfer rate, which employs
the same units. Data signaling rate is defined as 1/tui where tui is the minimum interval
between two significant instants.
2.2 DTE
2.3 DCE
2.4 LVDS
Star (*) - represents the opposite input condition for a parameter. For example, the
symbol Q represents the receiver output state for one input condition, while Q*
represents the output state for the opposite input state.
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3 APPLICABILITY
The provisions of this Standard may be applied to the circuits employed at the interface
between equipments where information being conveyed is in the form of binary signals.
G R
D D
B
T C
E E
R G
The LVDS interface is intended for use where any of the following conditions prevail:
a. The data signaling rate is too great for effective unbalanced (single-ended)
operation.
b. The data signaling rate exceeds the capability of TIA/EIA-422-B,
TIA/EIA-485-A, or TIA/EIA-612 balanced (differential) electrical interfaces.
c. The balanced interconnecting media is exposed to extraneous noise sources
that may cause an unwanted voltage up to ±1 V measured differentially between
the signal conductor and circuit common at the load end of the cable with a 50 Ω
resistor substituted for the generator.
d. It is necessary to minimize electromagnetic emissions and interference with
other signals.
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The LVDS interface circuit will normally be utilized on data and timing, or control
circuits. Actual maximum data signaling rate is NOT defined by this Standard. The
limit is determined by the generator transition time characteristics, the media
characteristics, the distance between the generator and the load, and the
required signal quality.
Generators and receivers meeting this Standard need not operate to the theoretical
maximum data signaling rate. They may be designed to operate over narrower ranges
that satisfy more economically specified applications, for example at lower data
signaling rates. When a generator is limited to a narrower range of data signaling rates,
the transition time of the generator may be slowed accordingly to limit noise generation.
For example, at 100 Mbit/s the generator's transition time should be in the range of
500 ps to 3 ns (5% to 30% of the unit interval), and the signal transition time at the load
should not exceed 5 ns (50% of the unit interval).
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4 ELECTRICAL CHARACTERISTICS
The LVDS interface circuit is shown in Figure 2. The circuit consists of three parts: the
generator (G), the balanced interconnecting media, and the load. The load is
composed of a termination impedance and a receiver(s) (R). The receiver may
incorporate the termination impedance internal to the Integrated Circuit package. The
electrical characteristics of the generator and receiver are specified in terms of direct
electrical measurements while the balanced interconnecting media is described in
terms of its electrical characteristics.
A A'
G ZT R
B B'
Vcpd
C C'
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The signaling sense of the voltages appearing across the termination resistor is defined
in Figure 3 as follows:
b. The A terminal of the generator shall be positive with respect to the B terminal
for a binary 0 or ON state.
The logic function of the generator and the receiver is beyond the scope of this
Standard, and therefore is not defined.
1 0 1
OFF ON OFF
VB
+1.2 V
typical
VA
A +250 to
G ZT = 100 Ω +450 mV
B
C | VA - VB | 0V (Diff.)
-250 to
-450 mV
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With a test load of three resistors, 100 Ω ±1% between the A and B generator output
terminals, and 3.75 kΩ ±1% between each generator output terminal and a test supply
(VTEST), as shown in Figure 4, the steady-state magnitude of the differential output
voltage (VT), shall be greater than or equal to 247 mV and less than or equal to
454 mV with the test voltage varied from 0 V to +2.4 V. For the opposite binary state,
the polarity of VT shall be reversed (VT *). The steady-state magnitude of the difference
between VT and VT * shall be 50 mV or less.
247 mV ≤ | VT | ≤ 454 mV
247 mV ≤ | VT* | ≤ 454 mV
| VT | - | VT* | ≤ 50 mV
The 100 Ω resistor represents a typical termination load, and the 3.75 kΩ resistors
represent the combined impedance of 32 receiver loads connected to the bus. The
VTEST power supply represents the allowable range of biasing that the receivers may
present to the bus.
A
3.75 kΩ
STEADY STATE
LOGIC INPUT G 100 Ω VT
(1 OR 0) +
VTEST
0 to +2.4 V
B 3.75 kΩ
C
= Measured Parameter
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With a test load of two resistors, 49.9 Ω ±1% each, connected in series between the
generator output terminals, the steady-state magnitude of the generator offset voltage
(VOS), measured between the center point of the test load and the generator circuit
common shall be greater than or equal to 1.125 V and less than or equal to 1.375 V for
either binary state. The steady-state magnitude of the difference of VOS for one binary
state and VOS * for the opposite binary state shall be 50 mV or less.
49.9 Ω
STEADY STATE A
LOGIC INPUT G VOS
(1 OR 0)
49.9 Ω
B
C
= Measured Parameter
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With the generator output terminals short-circuited to the generator circuit common, the
magnitudes of the currents (ISA and ISB) following through each output terminal shall not
exceed 24.0 mA for either binary state.
| ISA | ≤ 24.0 mA
| ISB | ≤ 24.0 mA
ISA
STEADY STATE A
LOGIC INPUT G
(1 OR 0)
ISB
B
C
= Measured Parameter
With the generator output terminals short-circuited to each other, the magnitude of the
current (ISAB) following through the output terminals shall not exceed 12.0 mA for either
binary state.
| Isab | ≤ 12.0 mA
STEADY STATE A
LOGIC INPUT G ISAB
(1 OR 0)
C
= Measured Parameter
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During transitions of the generator output between alternating binary states (one-zero-
one-zero, etc.), the differential voltage measured across the 99.8 Ω ±1% test load (RL)
connected as shown in Figure 8, shall be such that the voltage monotonically changes
between 0.2 and 0.8 of VSS and is less than or equal to 0.3 of the unit interval.
Thereafter, the signal voltage shall not vary more than ±20% of the steady-state value
(Vring), until the next binary transition occurs. Transition times shall not be less than 260
ps. Edge rates less than 260 ps are not recommended to minimize adverse effects of
switching noise. VSS is defined as the voltage difference between the two steady-state
values of the generator output (VSS = 2|Vt|). Measurement equipment used for
compliance testing shall provide a bandwidth of 5 GHz minimum.
ALTERNATING
LOGIC INPUT G Vt RL
(1,0,1,0,...)
Vring
±20% VSS
0.8VSS 0.8VSS
+ Vt
VSS
0V Differential
- Vt
0.2VSS 0.2VSS
tui tr tf
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During transitions of the generator output between alternating binary states (one-zero-
one-zero, etc.), the resulting imbalance of the offset voltage (VOS) measured between
the matched 49.9 Ω ±1% test load resistors (RL) to circuit common (C) as shown in
Figure 9, should not vary more than 150 mVpp (peak-to-peak). Measurement
equipment used for compliance testing shall provide a bandwidth of 5 GHz minimum.
Scope probe shall present atleast 100 kΩ differential resistance with no more than 1 pF
differential capacitance loading.
A
49.9 Ω
ALTERNATING RL
LOGIC INPUT G Vt VOS
(1,0,1,0,...) RL
49.9 Ω
B
C
A-B
VSS
0V Differential
tui
GND
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The load is defined as an impedance between A' and B' and is composed of a
termination impedance and a receiver as shown in Figure 2.
The total load limit is specified in 4.4.3, and additional guidance is provided in 4.4.1 and
4.4.2 on multiple receiver operation and failsafe operation respectfully.
With the voltage Via (or Vib) ranging from 0 V to +2.4 V while Vib (or Via) is held at
+1.2 V ± 50 mV, the resultant input current Iia (or Iib) shall be no greater than 20 µA in
magnitude. These measurements apply with the receiver's power supply in both power-
on and power-off conditions.
A'
Via Iia
R
B'
Vib Iib
C'
= Measured Parameter
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The balance of the input currents (IA’ and IB’) shall be 6 µA or less for all test voltages
between 0 V and 2.4 V.
NOTE - Current into a terminal is positive, and current out of a terminal is negative.
| IA’ - IB’ | ≤ 6 uA
A'
IA'
R
+ B'
IB'
VTEST
0V to +2.4V C'
= Measured Parameter
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With the applied voltage (Vin) and forced current (Iin) listed in Table 1 applied to the
corresponding inputs, the resultant differential input voltage magnitude (Vid) shall be
between the values listed in Table 1. The test circuit is shown in Figure 12 and applies
only to receivers that provide an internal termination impedance. These measurements
apply with the receiver's power supply in both power-on and power-off conditions.
B'
A'
S1
ZT
Vid
A' R
Vin Iin
B'
S2
Vr
C'
= Measured Parameter
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4.0
OPERATING
REGION
3.5
90 Ω
132 Ω
3.0
2.5
2.0
0 100 200 300 400 500 600
The input impedance of the terminating receiver is dominated by the low impedance
differential termination impedance (ZT). The resulting input resistance calculated from
the measurements describe in Table 1 shall be greater than or equal to 90 Ω, and less
than or equal to 132 Ω. See 4.2.5 on media termination, and 4.4.3 on total load limit.
90 Ω ≤ ZT ≤ 132 Ω
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+600 mV
A'
Table 2 lists the minimum and maximum operating voltages of the receiver (input
voltage, differential input voltage, and common-mode input voltage), and the test circuit
is shown in Figure 15.
NOTE - The logic function of the receiver is not defined by this Standard.
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A'
= Measured Parameter
VID R
Via = Applied Voltage
B'
Vib Note:
C' VCM = (Via + Vib)/2,
VID = |Via - Vib|
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NOTE - Due to the high application frequency, care should be taken in choosing
proper components such as the termination resistor, and in layout of the printed
circuit board. The use of surface mount components is highly recommended to
minimize parasitic inductance, and lead length of the termination resistor. Wire
wound resistors are not recommended.
A A'
G ZT R
B B'
C'
C
A A' ZT
G R
B B'
C'
C
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The balanced interconnecting media shall consist of paired metallic conductors in any
configuration which will maintain balanced signal transmission.
NOTE - The actual media of the cable is not specified and may be: twisted pair
cable, twin-ax cable (parallel pair), flat ribbon cable, or PCB traces.
The performance of any balanced interconnecting media used shall be such to maintain
the necessary signal quality for the specific application. If necessary for system
consideration, shielding may be employed (see 7.2).
Annex A to this Standard provides guidance on performance and cable length versus
data signaling rate and cable recommendations for typical cable applications.
110 Ω +/- 20% from 10 MHz to the application upper frequency limit.
Additional parameters not specified which are application dependent (see Annex A)
are: Maximum Attenuation, Maximum Propagation Delay, Maximum Propagation Delay
Skew, Maximum Near End Crosstalk (NEXT), and Maximum Far End Crosstalk
(FEXT). Crosstalk, skew, and related pair balance parameters may impact applications
with multiple signal transmission lines.
The electrical requirements of PC Board traces shall also meet the requirements of
4.3.1.1 to 4.3.1.3.
It may be possible that other media may be employed, the definition and electrical
characteristics of such media is beyond the scope of this Standard.
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The generator has the capability to furnish the DC signal necessary to drive multiple (up
to 32) parallel connected receivers (without internal termination). However, the physical
arrangement of the multiple receivers involves consideration of stub line lengths,
location of the termination resistor, number of receivers, data signaling rate, circuit
common, etc., that may degrade dynamic characteristics of the signal at the receivers if
not properly implemented. It is recommended that stub lengths off the main line be as
short as possible. In general, the propagation delay of the stub, should not exceed
30% of the signal transition time to prevent reflections and a severe impedance
discontinuity. For applications with receivers without internal termination, the external
termination resistor must be located at the far end (last receiver) of the interconnect.
G ZT R2
Stub
Length
R1
All receivers located between the generator and the final receiver must be non-
terminating receiver(s). Multiple terminating receivers would present a low impedance
load to the generator which would violate the total load limit (see 4.4.3), and adversely
attenuate the signal.
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G ZT R
G ZT R
Other standards and specifications using the electrical characteristics of the LVDS
interface circuit may require that specific interchange circuits be made failsafe to certain
fault conditions. Such fault conditions may include one or more of the following:
1) generator in power-off condition
2) receiver not connected with the generator
3) open-circuited interconnecting cable
4) short-circuited interconnecting cable
5) input signal to the load remaining within the transition region (±100 mV) for an
abnormal period of time (application dependent)
When detection of one or more of the above fault conditions is required by specified
applications, additional provisions are required in the load and the following items must
be determined and specified:
1) which interchange circuits require fault detection
2) what faults must be detected
3) what action must be taken when a fault is detected; the binary state that the
receiver assumes
4) what is done does not violate this Standard
The method of detection of fault conditions is application dependent and is therefore
not further specified as it is beyond the scope of this Standard.
The total load (ZL) including multiple receivers, failsafe provisions, and media
termination shall have a total resistance greater than or equal to 90 Ω and less or equal
to 132 Ω between its input points A' and B', shown in Figure 2. The receiver(s) shall not
require a differential input voltage of more than 100 mV in magnitude for all receiver(s)
to assume the intended binary state.
90 Ω ≤ ZL ≤ 132 Ω
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5 ENVIRONMENTAL CONSTRAINTS
A LVDS interface circuit conforming to this Standard will perform satisfactorily providing
that the following operational constraints are simultaneously satisfied:
a. For cable applications, the cable media meets the recommended cable
characteristics, the cable length is within that recommended for the applicable
data signaling rate indicated in Annex A, Section A.2 and the cable is properly
terminated.
b. For PC Board traces, the traces meets the recommended characteristics for
the applicable data signaling rate, and the trace is properly terminated.
c. The input voltage at the receiver (with respect to receiver circuit common) is
between 0 V and +2.4 V and either input (A' or B') terminal. The input voltage is
defined to be any uncompensated combination of generator-receiver common
potential difference, the generator offset voltage (VOS), and longitudinally coupled
peak noise voltage.
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6 CIRCUIT PROTECTION
The LVDS interface generator and receiver devices, under either the power-on or
power-off condition, complying to this Standard shall not be damaged under the
following conditions:
a. Generator open circuit.
b. Short-circuit across the balanced interconnecting media.
c. Short-circuit to common.
NOTE - Some integrated circuit manufacturers may impose additional
restrictions that may be required to meet this specification under the power-off
condition.
Proper operation of the LVDS interface circuits requires the presence of a signal
common path between the circuit commons of the equipment at each end of the
interconnection. The signal common interchange lead shall be connected to the circuit
common which shall be connected to protective ground by any one of the following
methods, shown in Figure 20 and Figure 21, as required by specific application.
The same configuration need not be used at both ends of an interconnection; however,
care should be exercised to prevent establishment of ground loops carrying high
currents.
The circuit common of the equipment is connected to protective ground, at one point
only, by a 100 Ω, ±20%, resistor with a power dissipation rating of 0.5 W. An additional
provision may be made for the resistor to be bypassed with a strap to connect circuit
common and protective ground directly together when specific installation conditions
necessitate.
NOTE - Under certain ground fault conditions in configuration "A", high ground
currents may cause the resistor to fail; therefore, a provision shall be made for
inspection and replacement of the resistor.
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Optional Strap
100 Ω SC
0.5 W
GWG
Legend:
GWG = Green wire ground of power system
SC = Signal common interchange circuit
Figure 20 - Optional grounding arrangements - configuration "A"
SC
GWG
Legend:
GWG = Green wire ground of power system
SC = Signal common interchange circuit
Figure 21 - Optional grounding arrangements - configuration "B"
Some interface applications may require the use of shielded balanced interconnecting
media for EMI or other purposes. When employed, the shield shall be connected only
to frame ground at either or both ends depending on the specific application. The
means of connection of the shield and any associated connector are beyond the scope
of this Standard.
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_____________________________________________________________________
ANNEX A (informative)
_____________________________________________________________________
(This annex is not a formal part of the attached TIA/EIA Recommended Standard, but is
included for information purposes only.)
The following section provides further information to Section 4.3 and is additional
guidance concerning operational constraints imposed by the cable media parameters of
length and termination.
Generally, if more than one signal transmission line is required for an interface, twisted
pairs are necessary to balance coupling reactance between individual conductors of
adjacent pairs and thus reduce crosstalk.
A.1.1 Length
The length of the cable separating the generator and the load is based on a maximum
loop resistance of 32 Ω, and a corresponding 80 mV loss of the signal.
The following examples given take only the DC effects into account in determining the
maximum cable length. This would pertain to low speed operation only. The AC
effects will limit the maximum cable length before the DC resistance for high speed
applications. See section A.2.
For the following cables gauges, the corresponding maximum length for a 50 mV signal
loss is:
Longer lengths are possible, if the voltage attenuation is allowed to decrease the
minimum generator differential output voltage to the maximum receiver threshold
voltage (250 mV to 100 mV) for a 150 mV voltage attenuation or -7.9 db. For the
following cables gauges, the corresponding maximum length at a 150 mV signal loss is:
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The following characteristics apply to common parallel interface cable (as used for
TIA/EIA-613, and other I/O interface standards) consisting of 25 twisted pairs
surrounded by an overall shield:
Braid Shield braided 36 AWG, tinned copper with 80% minimum coverage, in
electrical contact with the aluminum surface of the foil shield
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The following characteristics apply to a common Category 5 serial interface cable (as
used for TIA/EIA-422-B, and other I/O interface standards) consisting of 4 unshielded
twisted pairs surrounded by an overall jacket:
The characteristic impedance of twisted pair cable is a function of frequency, wire size
and type as well as the kind of insulating materials employed. For example, the
characteristic impedance of average 28 AWG, copper conductor, plastic insulated
twisted pair cable, to a 50 MHz sine wave will be on the order of 110 Ω.
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The maximum permissible length of cable separating the generator and the load is a
function of data signaling rate and is influenced by the tolerable signal distortion, the
amount of longitudinally coupled noise and common potential differences introduced
between the generator and the load circuit commons as well as by cable balance.
Increasing the physical separation and the interconnecting cable length between the
generator and the load interface points increases exposure to common-mode noise,
signal distortion, and the effects of cable imbalance. Accordingly, users are advised to
restrict cable length to a minimum, consistent with the generator to load physical
separation requirements.
To determine the maximum data signaling rate for a particular cable length the following
calculations / testing is recommended. First, the maximum DCR of the cable length
(loop resistance) should be calculated, then the resulting signal attenuation should be
calculated at the load. The voltage at the load must be greater than the receiver
thresholds of 100 mV. For a conservative design, a maximum attenuation of 50 mV is
recommended. Next eye patterns are recommended to determine the amount of jitter
at the load at the application data signaling rate and comparing that to system
requirements. Typically maximum allowable jitters tolerances range from 5% to 20%
depending upon actual system requirements. This testing should be done in the actual
application if possible, or in a test system that models the actual application as close as
possible. Parameters that should be taken in account include: balanced interconnect
media characteristics, termination, protocol and coding scheme, and worst case data
patterns (pseudo random for example). The generator / receiver manufacturers and
also the media manufacturers should provide additional guidance in predicting data
signaling rate versus cable length curves for a particular generator / receiver and a
particular media as this relationship is very dependent upon the actual characteristics of
the selected devices and media.
When generators are supplying symmetrical signals to clock leads, the period of the
clock, rather than the unit interval of the clock waveform, shall be used to determine the
maximum cable lengths (e.g., though the clock rate is twice the data rate, the same
maximum cable length limits apply).
With co-directional (same direction as data) timing, there are minimal problems with
proper clocking of the data bits since the difference between data and clock edges is
mostly the result of generator and receiver skew and not the transmission line. With
contra-directional timing, the user is advised that generator and receiver skew are not
the only items to be taken into account. The cable delay and skew must also be
considered. In both cases the clock should transition as close to the center of the data
bit as possible.
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ANNEX B (informative)
The LVDS interface circuit is not intended for direct inter-operation with other interface
electrical characteristics such as TIA/EIA-422-B, TIA/EIA-485-A, TIA/EIA-612, ITU-T
(Formerly CCITT) Recommendation V.11, emitter coupled logic (ECL) or PECL.
Under certain conditions, inter-operation with circuits of some of the above interfaces
may be possible but may require modification in the interface or within the equipment,
or may require limitations on certain parameters (such as common-mode range);
therefore, satisfactory operation is not assured, and additional provisions not specified
herein may be required.
Any balanced receiver device that guarantees and input range of at least 0V to +2.4V,
and thresholds of 200 mV or less may directly inter-operate with the generator specified
by this Standard and total noise is less than 50 mV.
The balanced receiver specified by this Standard may inter-operate with other balanced
generators specified by other standards along as the balanced generator does not
violate the maximum receiver input voltage range, and develops a differential voltage of
at least 100 mV, and not greater than 600 mV. Inter-operation with generators that
provide a greater differential voltage may also be possible with the use of an
attenuating circuit. The actual arrangement of such circuits is beyond the scope of this
annex.
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Voa
SWITCHING
INPUT A 49.9 Ω
G Vt VOS
SQUARE
WAVE 49.9 Ω
Vob
B
C
= Measured Parameter
Voa
Vob
GND
∆ | Vt |
| Vt |
0 V Differential
∆ | VOS |
VOS
GND
This Standard features very similar DC electrical specifications to the IEEE 1596.3
standard titled: SCI-LVDS Low Voltage Differential Signals Specifications and Packet
Encoding. Direct inter-operation should be possible at certain data signaling rates
without the use of intermediate circuitry. This Standard specifies generic electrical
characteristics of low voltage differential signaling interface circuits for general purpose
applications.
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Power dissipation is greatly reduced within the generator circuits compared to other
differential standards which specify a voltage-mode generator. The current-mode
generator can produce less spike current during transitions compared to a voltage-
mode generator. As data signaling rate increases, this component becomes more
critical. This allows for the generator to operate into the 300 MHz region without the
use of special integrated circuit packages or heat sinks. The load signal is specified
between 250 mV and 450 mV typically with a 100 Ω load, with creates a small loop
current of only 2.5 to 4.5 mA compared to the minimum 20 mA loop current for a
differential TIA/EIA-422-B generator. Since the load current component in also
reduced, this allows for highly integrated generator / receiver devices to be offered in
one package or integrated with other VLSI controller integrated circuits.
IEEE 1596.3 SCI-LVDS Low Voltage Differential Signals Specifications and Packet
Encoding
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