L9942

Integrated stepper motor driver for bipolar stepper motors

with microstepping and programmable current profile

Features
■ Two full bridges for max. 1.3 A load
(RDSON = 500 m)
■ Programmable current waveform with look-up
table: 9 entries with 5 bit resolution
■ Current regulation by integrated PWM
controller and internal current sensing
■ Programmable stepping mode: full, half, mini
and microstepping PowerSSO24
■ Programmable slew rate for EMC and power
dissipation optimization
■ Programmable Fast-, Slow-, Mixed- and Auto-
Decay Mode
■ Full-scale current programmable with 3 bit
Description
resolution The L9942 is an integrated stepper motor driver
■ Programmable stall detection for bipolar stepper motors with microstepping and
■ Step clock input for reduced µController programmable current profile look-up-table to
requirements allow a flexible adaptation of the stepper motor
characteristics and intended operating conditions.
■ Very low current consumption in standby mode
It is possible to use different current profiles
IS < 3 µA, typ. Tj  85 °C
depending on target criteria: audible noise,
■ All outputs short circuit protected with vibrations, rotation speed or torque. The decay
openload, overload current, temperature mode used in PWM-current control circuit can be
warning and thermal shutdown programmed to slow-, fast-, mixed-and auto-
■ The PWM signal of the internal PWM controller decay. In autodecay mode device will use slow
is available as digital output. decay mode if the current for the next step will
■ All parameters are guaranteed for 3 V < Vcc < increase and the fast decay or mixed decay mode
5.3 V and for 7 V < Vs < 20 V if the current will decrease. The programmable
stall detection is useful in case of head lamp
leveling and bending light application, by
Applications preventing to run the motor too long time in stall
Stepper motor driver for bipolar stepper motors in for position alignment. If a stall is detected, the
automotive applications like light levelling, alignment process is closed and the noise is
Bending light and Throttle control. minimized.

Table 1. Device summary

Order code Junction temp. range, C Package Packing

L9942XP1 -40 to 150 PowerSSO24 Tube

L9942XP1TR -40 to 150 PowerSSO24 Tape and reel

September 2013 Doc ID 11778 Rev 7 1/40

www.st.com 1
Contents L9942

Contents

1 Block diagram and pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Dual power supply: VS and VCC ..........................................9
2.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 PWM current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.3 Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.4 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.5 Outputs: Qxn (x = A; B n = 1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.6 PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Functional description of the logic with SPI . . . . . . . . . . . . . . . . . . . . . 21

4.1 Motor stepping clock input (STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 PWM output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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L9942 Contents

4.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Serial data in (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Serial data out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6 Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7 Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8 Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.1 Fault condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.2 SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.3 PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Logic with SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.6 STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Step clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Load current control and detection of overcurrent (shortages at outputs) 33

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 11778 Rev 7 3/40

List of tables L9942

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Outputs: Qxn (x = A; B n =1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. PWM control (see Figure 4 and Figure 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. DI timing (see Figure 11 and Figure 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 23. Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. Output: DO timing (see Figure 12 and Figure 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 25. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 26. STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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L9942 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Thermal data of the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. VS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Logic to set load current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Switching on minimum time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. SPI and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Reference generation for PWM control (switch on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Reference generation for PWM control (decay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 11778 Rev 7 5/40

Block diagram and pin information L9942

1 Block diagram and pin information

Figure 1. Block diagram

VBAT
ReversePolarityProtection
VCC Note: value of capacitor has
CP VS to be choosen carefully to
limit the VS voltage below
Oscillator Charge absolute maximum ratings in
Pump
QA1 case of an unexpected
STEP Diagnostic
freewheeling condition (e.g.
TSD, POR)
Gate-Driver
EN &

Phase Counter+Current Profile

PWM-Controller
QA2
SPI + Register + Logic

PWM Current DAC

PWM
μC

DO
Stepper
⇓

Motor
DI
QB1
CLK Gate-Driver
&
PWM-Controller
CSN Diagnostic
QB2
Biasing U/I-
Converter

GND RREF
GNDP

GND

Figure 2. Pin connection (top view)

PGND 1 24 PGND
Power SSO24
QA1 2 23 QA2

VS 3 22 VS

CLK 4 21 EN

DI 5 20 RREF

19 VCC
CSN 6 Exposed
DO 7 Pad 18 TEST

PWM 8 17 GND

STEP 9 16 CP

VS 10 15 VS

QB1 11 14 QB2

PGND 12 13 PGND

All pins with the same name must be externally connected!

All pins PGND are internally connected to the heat slug.

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L9942 Block diagram and pin information

Table 2. Pin description

Pin Symbol Function

1, 12, 13, Power ground: All pins PGND are internally connected to the heat slug.
PGND
24 Important: All pins of PGND must be externally connected!
Power supply voltage (external reverse protection required): For EMI
3, 10, 15,
VS reason a ceramic capacitor as close as possible to PGND is recommended.
22
Important: All pins of VS must be externally connected!
Fullbridge-outputs An: The output is built by a high-side and a low-side
switch, which are internally connected. The output stage of both switches is
QA1,QA
2, 23 a power DMOS transistor. Each driver has an internal reverse diode (bulk-
2
drain-diode: highside driver from output to VS, low-side driver from PGND to
output). This output is overcurrent protected.
Fullbridge-outputs Bn: The output is built by a highside and a low-side
switch, which are internally connected. The output stage of both switches is
QB1,QB
11, 14 a power DMOS transistor. Each driver has an internal reverse diode (bulk-
2
drain-diode: highside driver from output to VS, low-side driver from PGND to
output). This output is overcurrent protected.
SPI clock input: The input requires CMOS logic levels. The CLK input has
4 CLK
a pull-down current. It controls the internal shift register of the SPI.
Serial data input: The input requires CMOS logic levels. The DI input has a
pull-down current. It receives serial data from the microcontroller. The data
5 DI
is a 16bit control word and the most significant bit (MSB, bit 0) is transferred
first.
Chip Select Not input The input requires CMOS logic levels. The CSN
6 CSN input has a pull-up current. The serial data transfer between device and
micro controller is enabled by pulling the input CSN to low level.
SPI data output: The diagnosis data is available via the SPI and it is a
7 DO tristate-output. The output is CMOS compatible will remain highly resistive,
if the chip is not selected by the input CSN (CSN = high)
PWM output This CMOS compatible output reflects the current duty cycle
of the internal PWM controller of bridge A. It is an high resistance output
8 PWM
until VCC has reached minimum voltage ore can switched off via the SPI
command.
Step clock input: The input requires CMOS logic levels. The STEP input
has a pull-down current. It is clock of up and down counter of control
9 STEP
register 0. Rising edge starts new PWM cycle to drive motor in next
position.
Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be
16 CP
connected to this pin to buffer the charge-pump voltage.
Ground: Reference potential besides power ground e.g. for reference
17 GND
resistor RREF. From this pin exist a resistive path via substrate to PGND.
Test input The TEST input has a pull-down current. Pin used for production
18 TEST
test only. In the application it must be connected to GND.
Logic supply voltage: For this input a ceramic capacitor as close as
19 VCC
possible to GND is recommended.

Doc ID 11778 Rev 7 7/40

Block diagram and pin information L9942

Table 2. Pin description (continued)

Pin Symbol Function

Reference Resistor The reference resistor is used to generate a

temperature stable reference current used for current control and internal
20 RREF oscillator. At this output a voltage of about 1.28V is present. The resistor
should be chosen that a current of about 200uA will flow through the
resistor.
Enable input: The input requires CMOS logic levels. The EN input has a
pull-down resistor. In standby-mode outputs will be switched off and all
21 EN
registers will be cleared. If EN is set to a logic high level then the device will
enter the active mode.

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L9942 Device description

2 Device description

2.1 Dual power supply: VS and VCC

The power supply voltage VS supplies the half bridges. An internal charge-pump is used to
drive the highside switches. The logic supply voltage VCC (stabilized) is used for the logic
part and the SPI of the device. Due to the independent logic supply voltage the control and
status information will not be lost, if there are temporary spikes or glitches on the power
supply voltage. In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.60 V,
typical) the circuit is initialized by an internally generated power-on-reset (POR). If the
voltage VCC decreases under the minimum threshold (VPOR ON = 2.3 V, typical), the outputs
are switched to tristate (high impedance) and the internal registers are cleared.

2.2 Standby mode

The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to
a logic high level. All latched data will be cleared and the inputs and outputs are switched to
high impedance. In the standby mode the current at VS (VCC) is less than 3 µA (1 µA) for
CSN = high (DO in tristate). If EN is set to a logic high level then the device will enter the
active mode. In the active mode the charge pump and the supervisor functions are
activated.

2.3 Diagnostic functions

All diagnostic functions (overload/-current, open load, power supply over-/undervoltage,
temperature warning and thermal shutdown) are internally filtered (tGL = 32 µs, typical) and
the condition has to be valid for a minimum time before the corresponding status bit in the
status registers will be set. The filters are used to improve the noise immunity of the device.
Open load and temperature warning function are intended for information purpose and will
not change the state of the bridge drivers. On contrary, the overload/-current and thermal
shutdown condition will disable the corresponding driver (overload/-current) or all drivers
(thermal shutdown), respectively. The microcontroller has to clear the status bit to reactivate
the bridge driver.

2.4 Overvoltage and undervoltage detection

If the power supply voltage Vs rises above the overvoltage threshold VSOV OFF (typical
21 V), an overvoltage condition is detected. Programmable by SPI (OVW) the outputs are
switched to high impedance state (default after reset) or the overvoltage bit is set without
switching the outputs to high impedance. When the voltage Vs drops below the under-
voltage threshold VSUV OFF, the outputs are switched to high impedance state to avoid the
operation of the power devices without sufficient gate driving voltage (increased power
dissipation). Error condition is latched and the microcontroller needs to clear the status bits
to reactivate the drivers.

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Device description L9942

2.5 Temperature warning and thermal shutdown

If junction temperature rises above Tj TW a temperature warning flag is set which is
detectable via the SPI. If junction temperature increases above the second threshold Tj SD,
the thermal shutdown bit will be set and power DMOS transistors of all output stages are
switched off to protect the device. In order to reactivate the output stages the junction
temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be
cleared by the microcontroller.

2.6 Inductive loads

Each half bridge is built by an internally connected highside and a low-side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven without external free-wheeling diodes. In order to reduce the power dissipation during
free-wheeling condition the PWM controller will switch-on the output transistor parallel to the
freewheeling diode (synchronous rectification).

2.7 Cross-current protection

The four half-brides of the device are cross-current protected by an internal delay time
depending on the programmed slew rate. If one driver (LS or HS) is turned-off then
activation of the other driver of the same half bridge will be automatically delayed by the
cross-current protection time.

2.8 PWM current regulation

An internal current monitor output of each high-side and low-side transistor sources a
current image which has a fixed ratio of the instantaneous load current. This current images
are compared with the current limit in PWM control. Range of limit can reach from
programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC
(register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current
profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 current profiles
are moved in register1 for DAC Phase A and B. Number of profile depends on phase
counter reading and direction bit in register0 (Figure 7). The bridges are switched on until
the load current sensed at HS switch exceeds the limit. Load current comparator signal is
used to detect open load or overcurrent condition also.

2.9 Decay modes

During off-time the device will use one of several decay modes programmable by SPI
(Figure 4 top). In slow decay mode HS switches are activated after cross current protection
time for synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast
decay opposite half bridge will switched on after cross current protection time, that is same
like change in the direction. For mixed decay the duration of fast decay period before slow
decay can be set to a fixed time (Figure 4 detail B continuous line) or is triggered by under-
run of the load current limit (Figure 4 detail B dashed line), that can be detected at LS
switch. The special mode where the actual phase counter value is taken into account to
select the decay mode is called auto decay (e.g. in Figure 3 Micro Stepping DIR=1). If the
absolute value of the current limit is higher as during step before then PWM control uses

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L9942 Device description

slow decay mode always. Otherwise one of the fast decay modes is automatic selected for a
quick decrease of the load current and so it obtains new lower target value.

2.10 Overcurrent detection

The overcurrent detection circuit monitors the load current in each activated output stage. In
HS stage it is in function after detection of current limit during PWM cycle and in LS stage it
works permanently. If the load current exceeds the overcurrent detection threshold for at
least tISC = 4 µs, the overcurrent flag is set and the corresponding driver is switched off to
reduce the power dissipation and to protect the integrated circuit. Error condition is latched
and the microcontroller needs to clear the status bits to reactivate the drivers.

2.11 Open load detection

The open load detection monitors the activity time of the PWM controller and is available for
each phase. If the limit of load current is below around 100mA then open load condition is
detectable. Open load bit for a bridge is set in the register6 if this low current limit can't
reached after at least 15 consecutive PWM cycles.

Table 3. Truth table

DC2 DC1 DC0 I4 I3 I2 I1 I0 max. IOL

0 0 0 0 x x x x 46mA
0 0 1 0 x x x x 68mA
0 1 0 0 0 x x x 52mA
0 1 1 0 0 x x x 81mA
1 0 0 0 0 0 x x 53mA
1 0 1 0 0 0 x x 78mA
1 1 0 0 0 0 0 1 37mA
1 1 1 0 0 0 0 1 44mA

Truth table shows possible profiles for active open load detection. Maximum threshold IOL is
shown in left column if x bits are 1 (see also Figure 7). Lowest possible limit is e.g. 3.1 mA
for DC2=DC1=DC0=0 and it is set only I0=1.

2.12 Stepping modes

One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32
microsteps.
Mode is set up in register 0 and it defines increment size of phase counter. Phase counter
value defines address of corresponding current profile. Stepping modes with typical profile
values can see in Figure 3 (e.g. also so called 'Two Phase On' shown in dashed line).

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Device description L9942

Figure 3. Stepping modes

Full-Stepping Mode: DIR=0 Full-Stepping Mode: DIR=1
0 8 16 24 Phase Counter 24 16 8 0

Current Driver A Current Driver A

0 8 0 8 Address of Current 0 8 0 8
Profile Entry

Current Driver B

Current Driver B
8 0 8 0 Address of Current 8 0 8 0
Profile Entry

STEP Signal STEP Signal

Half-Stepping Mode: DIR=0 Half-Stepping Mode: DIR=1

0 4 8 12 16 20 24 28 Phase Counter 0 28 24 20 16 12 8 4

Current Driver A Driver Current A

0 4 8 4 0 4 8 4 Address of Current 0 4 8 4 0 4 8 4
Profile Entry

Current Driver B Driver Current B

8 4 0 4 8 4 0 4 Address of Current 8 4 0 4 8 4 0 4
Profile Entry

STEP Signal STEP Signal

Mini-Stepping Mode: DIR=0 Mini-Stepping Mode: DIR=1

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
Phase Counter
Current Driver A
Current Driver A

0 2 4 6 8 6 4 2 0 2 4 6 8 6 4 2 Adress of Current 0 2 4 6 8 6 4 2 0 2 4 6 8 6 4 2
Profile Entry

Current Driver B Current Driver B

8 6 4 2 0 2 4 6 8 6 4 2 0 2 4 6 Adress of Current 8 6 4 2 0 2 4 6 8 6 4 2 0 2 4 6
Profile Entry

STEP Signal STEP Signal

Micro Stepping Mode: DIR=0 (e.g auto decay) Micro Stepping Mode: DIR=1 (e.g. auto decay)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Current Driver A Current Driver A

Slow Decay Mixed Decay Slow Decay Mixed Decay
Mode Mode Mode Mode
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 Adress of Current 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Profile Entry Mixed Decay
Slow Decay Mixed Decay Slow Decay
Mode Mode Mode Mode

Mixed Decay Slow Decay Slow Decay

Mode Mixed Decay
Mode Current Driver B Current Driver B Mode
Mode
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 Adress of Current 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Slow Decay Mixed Decay Profile Entry
Slow Decay Mixed Decay
Mode Mode Mode Mode

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L9942 Device description

2.13 Decay modes

Figure 4. Decay modes
Load
Current
ON SLOW FAST MIXED
DECAY DECAY DECAY

VS VS

on on

A on

VS VS VS
B
on on on on

on on

Time

Internal PWM_CLK

Detail A: SWITCH ON AND SLOW DECAY register0

Load
Current
fast decay

ON DM2 DM1 DM0 MODE

T FT TCC SLOW DECAY
0 0 0 slow
Step
Limit
fast decay

HS VS
Fast decay is caused by OFF OFF

TB current through internal

TCC diodes during cross current OFF OFF

Time protection time.

TFT Filter time for the purpose of switch off delay in on mode is set by FT register6
TCC Cross current protection time is set by SR1 SR0 register0
TB Blank time of load current comparator TB=TCC

Detail B: register0
MIXED DECAY DM2 DM1 DM0 MODE CURVE
X 0 1 T MD1
X 1 0 T MD2
X 1 1 T mc
Load Load
Current TFT Current
TCC TCC SLOW DECAY TCC SLOW DECAY
Step after current
Limit FAST with delay
undershoot DECAY
LS
FAST
DECAY T MDx= TMD1
> TCC
Tmc T mc = T FT + 2TCC T MDx
or T MD2
Time Time
TFT Filter time for purpose of delay when decay mode has to change after limit under-run
TMD When limit is reached so fast decay duration time is set by DM1 DM2 register0

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Electrical specifications L9942

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings
Symbol Parameter Value Unit

DC supply voltage -0.3 to 28 V

VS
single pulse tmax < 400 ms 40 V

VCC Stabilized supply voltage, logic supply -0.3 to 5.5 V

VDI,VDO, Digital input / output voltage

VCLK VCSN, -0.3 to VCC + 0.3 V
VSTEP VEN

VRREF Current reference resistor -0.3 to VCC + 0.3 V

VCP Charge pump output -0.3 to VS + 11 V

VQxn (x=A;B n=1;2) output voltage -0.3 to VS + 0.3 V

IQxn (x=A;B n=1;2) output current 2.5 A

Warning: Leaving the limitation of any of these values may cause an

irreversible damage of the integrated circuit!

3.2 ESD protection

Table 5. ESD protection
Parameter Value Unit

All pins 2 (1) kV

output pins: Qxn (x=A;B n=1;2) 4(2) kV
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A
2. HBM with all unzapped pins grounded

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L9942 Electrical specifications

3.3 Thermal data

Table 6. Operating junction temperature
Symbol Parameter Value Unit

Tj Operating junction temperature -40 to 150 °C

Table 7. Temperature warning and thermal shutdown

Symbol Parameter Min. Typ. Max. Unit

Temperature warning
TjTW ON threshold junction Tj increasing - - 150 °C
temperature
Temperature warning
TjTW OFF threshold junction - 130 - - °C
temperature
Thermal shutdown threshold
TjSD ON - - - 170 °C
junction temperature
Thermal shutdown threshold
TjSD OFF - 150 - - °C
junction temperature
TjSD HYS Thermal shutdown hysteresis - - 5 - K

Figure 5. Thermal data of the package

Note:
1s 1 signal layer
2s2p 2 signal layers 2 internal planes

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Electrical specifications L9942

3.4 Electrical characteristics

VS = 7 to 20 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, IREF = -200 µA, unless otherwise
specified. The voltages are referred to GND and currents are assumed positive, when the
current flows into the pin.

3.4.1 Supply

Table 8. Supply
Symbol Parameter Test condition Min. Typ. Max. Unit

VS DC supply current in active VS = 13.5 V, EN=VCC outputs

- 7 20 mA
mode floating
IS VS = 13.5 V, TEST, Tj = -40 °C
- 3 10
VS quiescent supply current EN = 0V outputs to 25 °C µA
floating Tj = 125 °C - 6 20
VCC = 5.0 V EN=VCC,
- 1 3 mA
DI=CLK=STEP=0V
VCC DC supply current in VCC = 5.0 V TEST;
ICC
active mode EN = 0 V; CSN = Tj = -40 °C
- 1 3 µA
VCC no clocks to 25 °C
outputs floating
CSN=VCC no
clocks outputs Tj = 125 °C - 2 6 µA
ICC VCC quiescent supply current floating
VS = 13.5 V, VCC = Tj = -40 °C
- 4 13
5.0 V to 25 °C
TEST; EN=0 V µA
CSN=VCC no
IS + ICC Sum quiescent supply current Tj = 125 °C - 8 26
clocks outputs
floating
EN = 5 V, CSN=CLK=0V DO
tsetPOR (1) VCC on set up time changes from high ohmic to logic 2 - - µs
level LOW
1. This parameter is guaranteed by design.

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L9942 Electrical specifications

3.4.2 Over- and undervoltage detection

Table 9. Over- and undervoltage detection

Symbol Parameter Test condition Min. Typ. Max. Unit

VSUV ON VS UV-threshold voltage VS increasing - - 6.90 V

VSUV OFF VS UV-threshold voltage VS decreasing 4.8 - - V
VSUV hyst VS UV-hysteresis VSUV ON -VSUV OFF - 0.3 - V
VSOV OFF VS OV-threshold voltage VS increasing - 21 25 V
VSOV ON VS OV-threshold voltage VS decreasing 18.5 20 - V
VSOV hyst VS OV-hysteresis VSOV OFF -VSOV ON - 0.5 - V
VPOR OFF Power-off-reset threshold VCC increasing - 2.6 2.9 V
VPOR ON Power-on-reset threshold VCC decreasing 2.00 2.3 - V
VPOR hyst Power-on-reset hysteresis VPOR OFF -VPOR ON - 0.11 - V

Figure 6. VS monitoring
Register 7 Register 7
UV OV

1 1

0 0
VS VS
VSUV OFF VSUV ON VSOV ON VSOV OFF

3.4.3 Reference current output

Table 10. Reference current output

Symbol Parameter Test condition Min. Typ. Max. Unit

VREF Reference voltage range IREF = -200 A 1.05 1.25 1.45 V

Reference current
IREFshorted register6 bit7 RERR = 1 - - -250 A
threshold shorted pin REF
Reference current
IREFopen register6 bit7 RERR = 1 -150 - - A
threshold open pin REF

The device works properly without the external resistor at pin REF. In this case it doesn't
have to fulfill all specified parameters.

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Electrical specifications L9942

3.4.4 Charge pump output

Table 11. Charge pump output

Symbol Parameter Test condition Min. Typ. Max. Unit

VS=7 V 11 - 20 V
ICP= -100 A, all
VCP Charge pump output voltage VS=13.5 V switches off at 20 - 35 V
Qxn
VS=20 V 30 - 40 V

The ripple of voltage at CP can suppressed using a capacity of e.g.100 nF.

3.4.5 Outputs: Qxn (x = A; B n = 1; 2)

The comparator, which is monitoring current image of HS, is working during ON cycle of
PWM control. If load current is higher as set value then the signal ILIMIT is generated and
after filter time the bridge is switched off. Test mode gets access to signal ILIMIT and
threshold of current can be measured.

Table 12. Outputs: Qxn (x = A; B n =1; 2)

Symbol Parameter Test condition Min. Typ. Max. Unit
VS = 13.5 V, Tj = 25 °C,
- 500 700 m
IQxn = -1.0 A
VS = 13.5 V, Tj = 125 °C,
RDSON HS On-resistance Qxn to VS - 750 1000 m
IQxn = -1.0 A
VS = 7.0 V, Tj = 25 °C,
- 550 750 m
IQxn = -1.0 A
VS = 13.5 V, Tj = 25 °C,
- 500 700 m
IQxn = + 1.0 A
On-resistance Qxn to VS = 13.5 V, Tj = 125 °C,
RDSON LS - 750 1000 m
PGND IQxn = + 1.0 A
VS = 7.0 V, Tj = 25 °C,
- 550 750 m
IQxn = + 1.0 A
Output overcurrent test mode exclusive of filter
|IQxnOC | 1.6 2 - A
limitation to VS or PGND time 4µs (Chapter 2.10)
Bits: DC2 DC1 DC0=000 60 95 130
Bits: DC2 DC1 DC0=001 100 140 180
Bits: DC2 DC1 DC0=010 180 230 280
Value of output current to
supply VS (so called full Bits: DC2 DC1 DC0=011 300 360 420
IQxnFS_HS mA
scale value)1 sourcing Bits: DC2 DC1 DC0=100 485 550 615
from HS switch
Bits: DC2 DC1 DC0=101 720 810 900
Bits: DC2 DC1 DC0=110 1000 1150 1300
Bits: DC2 DC1 DC0=111 1200 1350 1500
Accuracy of micro steps
IQxnLIM_HS - MIN(1) - MAX(1) mA
current limit
1. MIN= 0.92 · IQxnLIM – 0.02 · |IQxnFS_HS |; MAX= 1.08 · IQxnLIM + 0.02 · |IQxnFS_HS |

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L9942 Electrical specifications

Note: Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1.
Output current limit IQxnLIM is product of full scale current |IQxnFS_ | (bits DC2 DC1 DC0) and
value of DAC Phase A/B (bits I4 I3 I2 I1 I0) in register1.
Values of DAC Phase A and B can read out and depends on set up done before:
1. direction DIR, stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0 and
2. value of corresponding current profile (for address of current profile entry see also
Figure 3).

Figure 7. Logic to set load current limit

UP/Down Register 0
Count by PhaseCounter Decay Mode Slew Rate StepMode
1,2,4,8 P4 P3 P2 P1 P0 DM2 DM1 DM0 SR1 SR0 ST1 ST0 DIR

STEP
0 0 0

0 1 2 3 0 1 2 3 0 1 2 3
A2 A1 A0
MUX MUX MUX

A3 A2 A1 A0 Address Calculation
Phase A Phase B
A3=0 A3=1 A3=0 A3=1
Adr A[3..0] Adr neg(A[3..0]) Adr neg(A[3..0]) Adr A[3..0]

Current-Profile Table
stored in register2, ...6 5

9
5 Register 1
I4 I3 I2 I1 I0 Profile 8 DAC Scale DAC Phase B DAC Phase A

DI DC2 DC1 DC0 I4 I3 I2 I1 I0 I4 I3 I2 I1 I0

5
I4 I3 I2 I1 I0 Profile 7 QA1
5 I QA1LIM
I4 I3 I2 I1 I0 Profile 6 1000
5 bit DAC
LIMIT B
5 bit DAC
I LIMIT A I Qx1LIM
5
Phase B Phase A
I4 I3 I2 I1 I0 Profile 5
I REF I MAX QA2
5 DAC
REF
I4 I3 I2 I1 I0 Profile 4 Full Scale I QB1LIM
5 1000
I4 I3 I2 I1 I0 Profile 3
5
I4 I3 I2 I1 I0 Profile 2 QB1
5 IQA2LIM
I4 I3 I2 I1 I0 Profile 1
1000
5
I Qx2LIM
I4 I3 I2 I1 I0 Profile 0
QB2
IQB2LIM
1000

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Electrical specifications L9942

3.4.6 PWM control

Table 13. PWM control (see Figure 4 and Figure 7)

Symbol Parameter Test condition Min. Typ. Max. Unit

Bit: FRE= 1 - 20.8 - kHz

fPWM (1) Frequency of PWM cycles
Bit: FRE= 0 - 31.3 - kHz
Bits: DM1 DM0= 0 1 - 4 - µs
TMD(1) Mixed decay switch off delay time
Bits: DM1 DM0= 1 0 - 8 - µs
Bit: FILTER= 0 - 1.5 - µs
TFT(1) Glitch filter delay time
Bit: FILTER= 1 - 2.5 - µs
Bits: SR1 SR0= 0 0 - 0.5 - µs

Tcc (1) Cross current protection time Blank Bits: SR1 SR0= 0 1 - 1 - µs
TB (1) time of comparator Bits: SR1 SR0= 1 0 - 2 - µs
Bits: SR1 SR0= 1 1 - 4 - µs
Bits: SR1 SR0= 0 0 - 13 - V/µs
Slew rate (dV/dt 30 % - 70 %) @HS Bits: SR1 SR0= 0 1 - 13 - V/µs
VSR switches on resistive load of 10 ,
VS = 13.5 V Bits: SR1 SR0= 1 0 - 6 - V/µs
Bits: SR1 SR0= 1 1 - 6 - V/µs
1. This parameter is guaranteed by design.
Time base is an internal trimmed oscillator of typical 2MHz and it has an accuracy of ±6 %.

Figure 8. Switching on minimum time

Load current T FT Filter time of current comparator

at Qxn T FT TCC
T CC Cross current protection time

T B Blank time of current comparator

Step limit e.g. T B = TCC = 1 us T FT = 1.5 us

T CC TB
Time

Internal PWM TPWM

clock
20 or 30 kHz on decay

TINT _2MHz

Pin PWM
(for bridge A)

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L9942 Functional description of the logic with SPI

4 Functional description of the logic with SPI

4.1 Motor stepping clock input (STEP)

Rising edge of signal STEP is latched. It is synchronized by internal clock. At next start of a
new PWM cycle the new values of output current limit are used to drive motor in next
position. Before start new motor step this signal has to be low for at least two internal clock
periods to reset latch.

4.2 PWM output (PWM)

This output reflects the current duty cycle of the internal PWM controller of bridge A. High
level indicates on state to increase current through load and low level is in off state so load
current decreases depending on chosen decay mode.

4.3 Serial peripheral interface (SPI)

This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can
be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0
and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an
internal error flag of the device which is a logical-or of all status bits in the Status Register
(reg 7) and in the current profile register 4 (reg 6). The microcontroller can poll the status of
the device without the need of a full SPI-communication cycle.

4.4 Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame.

4.5 Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register.
The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN
signal the contents of the shift register will be transferred to the selected data register. The
writing to the register is only enabled if exactly 16 bits are transmitted within one
communication frame (i.e. CSN low). If more or less clock pulses are counted within one
frame the complete frame will be ignored. This safety function is implemented to avoid an
activation of the output stages by a wrong communication frame.

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Functional description of the logic with SPI L9942

Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.

4.6 Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.

4.7 Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.

4.8 Data register

The device has eight data registers. The first three bits (bit 0 ... bit 2) at the DI-input are used
to select one of the input registers. All bits are first shifted into an input shift register. After
the rising edge of CSN the contents of the input shift register will be written to the selected
Input Data Register only if a frame of exact 16 data bits are detected. The selected register
will be transferred to DO during the current communication frame.

Figure 9. SPI and registers

DI

DO
CLK D
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A0 A1 A2

CSN CLK_ADR D A0 A1 A2
SPI-
INT_2MHz Controll
SEL_ERROR
POR SPI2REG

Phase Counter Decay Mode Slew Rate Step Mode

P4 P3 P2 P1 P0 DM2 DM1 DM0 SR1 SR0 ST1 ST0 DIR
Register 0
Read Only
DAC_Scale DAC Phase B DAC Phase A
Register 1 DC2 DC1 DC0 BI4 BI3 BI2 BI1 BI0 AI4 AI3 AI2 AI1 AI0

Current Profile 1 OV Test only Current Profile 0

Register 2 I4 I3 I2 I1 I0 OVW T1 T0 I4 I3 I2 I1 I0

Current Profile 3 PWM Counter PWM Current Profile 2

Register 3 I4 I3 I2 I1 I0 D1 D0 NPWM I4 I3 I2 I1 I0

Current Profile 5 PWM Counter Current Profile 4

Register 4 I4 I3 I2 I1 I0 D4 D3 D2 I4 I3 I2 I1 I0

Current Profile 7 PWM Counter Current Profile 6

Register 5 I4 I3 I2 I1 I0 D7 D6 D5 I4 I3 I2 I1 I0

Read-Only
PWM RREF Openload Current Profile 8
Register 6 CLR6 SST FT Freq ST Error Phase Phase I4 I3 I2 I1 I0
B A

Read-Only
Temperature VS Monitor Overcurrent
Register 7 CLR7
TSD TW OV(W) UV HSB2 HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1

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L9942 SPI - control and status registers

5 SPI - control and status registers

5.1 Register 0
Table 14. Register 0
Phase counter Decay mode Slew rate Step mode DIR
Bit
12 11 10 9 8 7 6 5 4 3 2 1 0

Access rw rw rw rw rw rw rw rw rw rw rw rw rw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name P4 P3 P2 P1 P0 DM2 DM1 DM0 SR1 SR0 ST1 ST0 DIR

The meaning of the different bits is as follows:

:

DIR This bit controls direction of motor movement. DIR=1 clockwise DIR=0 counter clockwise.

ST1 ST0 This bits controls step mode of motor movement (Figure 3).
00 Micro-stepping
01 Mini-stepping
10 Half-stepping
11 Full-stepping

SR1 SR0 This bit controls slew rate of bridge switches. See also parameter Table 13

DM2 DM1 DM0 This bits controls decay mode of output current (Figure 3).
000 Slow decay
001 Mixed decay, fast decay until TMD > 4 µs
010 Mixed decay, fast decay until TMD > 8 µs
011 Mixed decay, fast decay until current undershoot Tmc =TFT +TCC
100 Auto decay, fast decay without delay time
101 Auto decay, fast decay until TMD > 4 µs Auto decay uses mixed decay automatically
110 Auto decay, fast decay until TMD > 8 µs to reduce current for next step if required
(see Figure 3 down right).
Auto decay, fast decay until current
111
undershoot Tmc

P4 P3 P2 P1 P0 This bits control position of motor, e.g. 00000 step angle is 0°, 01111 step angle is 180 °.

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SPI - control and status registers L9942

5.2 Register 1
Table 15. Register 1
DAC scale DAC phase B DAC phase A
Bit
12 11 10 9 8 7 6 5 4 3 2 1 0

Access rw rw rw r r r r r r r r r r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name DC2 DC1 DC0 BI4 BI3 BI2 BI1 BI0 AI4 AI3 AI2 AI1 AI0

The meaning of the different bits is as follows:

These bits control DAC of

AI4 AI3 AI2 AI1 AI0
bridge A. Value depends on address and the value of corresponding
These bits control DAC of current profile.
BI4 BI3 BI2 BI1 BI0
bridge B.
These bits set full scale range
DC2 DC1 DC0 of limit, e.g. 000 for 100 mA or See also parameter Table 12.
111 for e.g. 1500 mA

5.3 Register 2
Table 16. Register 2
Current profile 1 OV Test only Current profile 0
Bit
12 11 10 9 8 7 6 5 4 3 2 1 0

Access rw rw rw rw rw rw rw rw rw rw rw rw rw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name I4 I3 I2 I1 I0 OVW T1 T0 I4 I3 I2 I1 I0

The meaning of the different bits is as follows:

:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Table 12
T1 T0 Should be programmed to 0. -
In case of an overvoltage event (V-SOV OFF) the outputs are
OVW = 0 switched to high impedance state and the Vs Monitor bit OV is -
set.
In case of an overvoltage event (V-SOV OFF) the Vs Monitor bit
OVW = 1 -
OV is set. The status of the outputs are unchanged.

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L9942 SPI - control and status registers

5.4 Register 3
Table 17. Register 3
Current profile 3 PWM counter PWM Current profile 2
Bit
12 11 10 9 8 7 6 5 4 3 2 1 0

Access rw rw rw rw rw rw rw rw rw rw rw rw rw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name I4 I3 I2 I1 I0 D1 D0 NPW M I4 I3 I2 I1 I0

The meaning of the different bits is as follows:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Table 12

These bits are for threshold value in counter of active time during
D1 D0 -
signal PWM.

This bit switches internal PWM signal of bridge A to pin PWM if it

NPWM -
is set to 0, otherwise pin is in high resistance status.

5.5 Register 4 and 5

Table 18. Register 4 and 5
Current profile 5 (7) PWM counter Current profile 4 (6)
Bit
12 11 10 9 8 7 6 5 4 3 2 1 0

Access rw rw rw rw rw rw rw rw rw rw rw rw rw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name I4 I3 I2 I1 I0 D4(7) D3(6) D2(5) I4 I3 I2 I1 I0

The meaning of the different bits is as follows:

These bits are loaded needed. in register1 DAC Phase A

I4 I3 I2 I1 I0 See also parameter Table 12
or B if needed.
D4 D3 D2 (register4) These bits are for threshold value in counter of active time
during signal PWM. LSB and next value are set in -
D7 D6 D5 (register5) register3 by D0 and D1.

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SPI - control and status registers L9942

5.6 Register 6
Table 19. Register 6
ST REF
CLR Filter Freq. ST Open load Current profile 8
(PWM) ERR
Bit 12 11 10 9 8 7 6 5 4 3 2 1 0
Access rw rw rw rw r r r r rw rw rw rw rw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
PWM RREF Phase Phase
Name CLR6 SST FT ST I4 I3 I2 I1 I0
Freq. Error B A

The meaning of the different bits is as follows:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed See also parameter Table 12
Phase B Phase A These bits indicate open load at bridges
RREF Error This bit indicates if reference current is OK (150 µA <IREF < 250 µA), then is RERR=0.
ST This bit indicates stall detection.
PWM Freq. This bit sets frequency of PWM cycle. FRE=1 frequency 20 kHz, FRE=0 frequency 30 kHz
FT This bit sets filter time in glitch filter. FT=0 TF =1.5 µs, FT=1 TF = 2.5 µs
SST This bit specifies output PWM to reflect same logical level like bit ST.
CLR6 This bit resets all read only bits to 0 in register 6.

5.7 Register 7
Table 20. Register 7
CLR Temperature VS monitor Overcurrent

Bit 12 11 10 9 8 7 6 5 4 3 2 1 0
Access rw r r r r r r r r r r r r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name CLR7 TSD TW OV(W) UV HSB2 HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1

The meaning of the different bits is as follows:

bit7 ... bit0 These bits indicate overcurrent in each low side or highside power transistor.
1 overcurrent failure I > 2 A
OV(W) UV These bits indicates failure at VS (See also parameter Table 9)
01 Voltage at pin VS is too low.
10 Voltage at pin VS is too high.
TSD TW These bits indicates temperature failure (See also parameter Table 7)
01 Only for information set at temperature warning threshold.
10 In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.
CLR7 This bit resets all bits to 0 in register 7.

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L9942 SPI - control and status registers

5.8 Auxiliary logic blocks

5.8.1 Fault condition

Logical level at pin D0 represents fault condition. It is valid from first high to low edge of
signal CLK up to transfer of data bit D12. Fault bit is an logical OR of:
Control and status register 6 bit 5 and 6 for open load, bit 7 reference current failure
(RERR) and
Control and status register 7 bit 0 to bit 7 for overcurrent, bit 8 and 9 failure at VS
(UV,OV) and
bit 10 and bit 11 during high temperature (TW,TSD)

5.8.2 SPI communication monitoring

At the rising edge of the CSN signal the contents of the shift register will be transferred to
the selected data register. A counter monitors proper SPI communication. It counts rising
edges at pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted
within one communication frame (i.e. CSN low). If more or less clock pulses are counted
within one frame the complete frame will be ignored. This safety function is implemented to
avoid an activation of the output stages by a wrong communication frame. SPI
communication can be checked by loading a command twice and then answer at pin DO
must be same.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.

5.8.3 PWM monitoring for stall detection

Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold.
The value in this set of bits determine the minimum time for current rise over one quadrant of
motor driving. D7-D0 is compared with the sum of the rise times over one quadrant. When
the sum is less than the value stored in D7-D0 the ST bit (register 6 bit 8) is set to a logic “1”.
The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after
power on when the SST bit (register 6, bit11) is reset to a logic “0”. If this bit is set to a
logical “1” then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection
without the need of reading register 6 through the SPI bus.

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Logic with SPI - electrical characteristics L9942

6 Logic with SPI - electrical characteristics

VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 A, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.

6.1 Inputs: CSN, CLK, STEP, EN and DI

Table 21. Inputs: CSN, CLK, STEP, EN and DI
Symbol Parameter Test condition Min. Typ. Max. Unit

Vin L input low level - 0.3*VCC 0.4*VCC - V

Vin H input high level - - 0.6*VCC 0.7*VCC V
Vin Hyst input hysteresis - - 0.1*VCC - V
ICSN in pull up current at input CSN VCSN = VCC -1.5 V, -50 -25 -10 µA
ICLK in pull down current at input CLK VCLK = 1.5 V 10 25 50 µA
IDI in pull down current at input DI VDI = 1.5 V 10 25 50 µA
ISTEP in pull down current at input STEP VSTEP = 1.5 V 10 25 50 µA
REN in resistance at input EN to GND VEN in = VCC 110 510 k
input capacitance at input CSN,
Cin (1) 0 V < VCC < 5.3 V - 10 15 pF
CLK, DI and PWM
1. Parameter guaranteed by design.

6.2 DI timing
Table 22. DI timing (see Figure 11 and Figure 13) (1)
Symbol Parameter Test condition Min. Typ. Max. Unit

tCLK Clock period VCC = 5 V 250 - - ns

tCLKH Clock high time VCC = 5 V 100 - - ns
tCLKL Clock low time VCC = 5 V 100 - - ns
CSN set up time, CSN low before
tset CSN VCC = 5 V 100 - - ns
rising edge of CLK
CLK set up time, CLK high before
tset CLK VCC = 5 V 100 - - ns
rising edge of CSN
tset DI DI set up time VCC = 5 V 50 - - ns
thold DI DI hold time VCC = 5 V 50 - - ns
Rise time of input signal DI, CLK,
tr in VCC = 5 V - - 25 ns
CSN
Fall time of input signal DI, CLK,
tf in VCC = 5 V - - 25 ns
CSN
1. DI timing parameters tested in production by a passed/failed test:
Tj=-40°C/+25°C: SPI communication @5MHz; Tj=+125°C: SPI communication @4.25MHz

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L9942 Logic with SPI - electrical characteristics

6.3 Outputs: DO, PWM

Table 23. Outputs: DO, PWM
Symbol Parameter Test condition Min. Typ. Max. Unit

VDOoutL
Output low level VCC = 5 V, ID = 2 mA - 0.2 0.4 V
VPWMoutL
VDOoutH VCC - VCC -
output high level VCC = 5 V, ID = -2 mA - V
VPWMoutH 0.4 0.2

VCSN = VCC,
IDOoutLK Tristate leakage current -10 - 10 µA
0 V < VDO < VCC
Register3bit5=1 (NPWM)
IPWMoutLK Tristate leakage current -10 - 10 µA
0 V < VPWM < VCC
VCSN = VCC,
Cout (1) Tristate input capacitance - 10 15 pF
0 V < VCC < 5.3 V

6.4 Output: DO timing

Table 24. Output: DO timing (see Figure 12 and Figure 13)
Symbol Parameter Test condition Min. Typ. Max. Unit

tr DO DO rise time CL = 100 pF, Iload = -1 mA - 50 100 ns

tf DO DO fall time CL = 100 pF, Iload = 1 mA - 50 100 ns
DO enable time from tristate to low CL = 100 pF, Iload = 1 mA pull-
ten DO tri L - 50 250 ns
level up load to VCC
DO disable time from low level to CL = 100 pF, Iload = 4 mA pull-
tdis DO L tri - 50 250 ns
tristate up load to VCC
DO enable time from tristate to CL = 100 pF, Iload = -1 mA pull-
ten DO tri H - 50 250 ns
high level down load to GND
DO disable time from high level to CL = 100 pF, Iload = -4 mA
tdis DO H tri - 50 250 ns
tristate pull-down load to GND
VDO < 0.3 VCC, VDO > 0.7
td DO DO delay time - 50 250 ns
VCC, CL = 100 pF

6.5 CSN timing

Table 25. CSN timing
Symbol Parameter Test condition Min. Typ. Max. Unit

Transfer of SPI-command to
tCSN_HI,min(1) CSN high time, active mode 2 - - µs
Input Register
1. Parameter guaranteed by design.

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Logic with SPI - electrical characteristics L9942

6.6 STEP timing

Table 26. STEP timing
Symbol Parameter Test condition Min. Typ. Max. Unit

tSTEPmin(1) STEP low or high time - 2 - - µs

1. Parameter guaranteed by design.

Figure 10. Transfer timing diagram

t
CSN_HI,min

CSN high to low: DO enabled

CSN
time

CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
time
DI: data will be accepted on the rising edge of CLK signal
actual data new data
DI A2 A1 A0 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1
time
DO: data will change on the falling edge of CLK signal
status information
DO D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
time
CSN low to high: actual data is fault bit
fault bit transfered to registers
Control and Status Register old data actual data
time

Figure 11. Input timing

0.8 VCC
CSN t CLK
0.2 VCC
t set CSN t CLKH t
set CLK

0.8 VCC
CLK
0.2 VCC
t set DI t hold DI t CL KL

0.8 VCC
DI Valid Valid
0.2 VCC

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L9942 Logic with SPI - electrical characteristics

Figure 12. SPI - DO valid data delay time and valid time

tf in t r in

0.8 VCC
CLK 0.5 VCC
0.2 VCC
t r DO

DO 0.8 VCC
(low to high)
0.2 VCC
td DO t f DO

DO 0.8 VCC
(high to low)
0.2 VCC

Figure 13. DO enable and disable time

tf in tr in

0 .8 V C C
C S N 50%
0 .2 V C C

D O 50%
p u ll - u p lo a d to V C C
C L = 10 0 pF ten t d is
D O tri L D O L tri

D O 50%
p u ll- d o w n lo a d t o G N D
C L = 10 0 pF
ten D O tri H t d is D O H tri

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Logic with SPI - electrical characteristics L9942

Figure 14. Timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transferred to D0

CSN

time

CLK

time

DI

time
DI: data is not accepted
D0
D0 0

time
D0: status information of data bit 0 (fault condition) will stay as long as CSN is low

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L9942 Appendix

7 Appendix

7.1 Stall detection

The L9942 contains logic blocks designed to detect a motor stall caused by excessive
mechanical load.During a motor stall condition the load current rises much faster than
during normal operation. The L9942 measures this time and compares it to a programmed
value.
This is done by summing the PWM on times for one full quadrant. For a full wave stepping
this is just one value (step 0). For microstepping this includes 8 separate values added
together, one for each step. This measurement is only done on phase A during the
quadrants where the current is increasing naturally (quadrants 1 and 3 of Figure 15); e.g.
stall detection is active during phase counter values 1 to 8 and 17 to 24 for DIR=0. During
the quadrants where the current is decreasing fast decay recirculation interferes with
accurate measurement of this time. If the sum of the PWM on time is less than a
programmed threshold stored in D0-D7, stall is detected and indicated as a logic “1” in the
stall (ST) bit found in register 6 bit 8 (Figure 15 bottom). If bit 11 of register 6 is set to logical
“1” then the ST bit is mirrored to the PWM pin providing detection externally.The register
values DT7-DT0 store the threshold value in 16us intervals. These bits can be found
interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7).
Care should be taken when deciding the threshold timing. Motor current slew rates are
dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor
as well as the motor and the inductance. Be sure to set your threshold well away from what
can be seen in normal operation at any temperature.

7.2 Step clock input

The Step clock input allows to run one device in micro-step mode, or several devices
simultaneously with cost effective 8 bit µController. In case of the L9942, the SPI
communication link provides only the settings for motor operation mode. Motor commutation
as high duty process is outsourced to a parallel driven pin. Without this step clock input, the
SPI command would also have to clock the motor, leading to a high SPI speed. For full
micro-step operation or simultaneous motor drive, an 8 bit µController could be rapidly
overloaded.

7.3 Load current control and detection of overcurrent (shortages

at outputs)
The L9942 controls load current in the two full bridges by using a pulls with modulation
(PWM) regulator. The mirrored output current of active HS switch is compared with a
programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if
current has exceeded the programmed limit value. A second comparator of the related LS
switch uses the mirrored load current to detect an overcurrent to ground during ON state of
bridges (e.g. in Figure 16 LSA2 and LSB1). The event of shortage from output to supply
voltage VS is detectable, but short current between outputs is limited through PWM
controller and so an overcurrent failure will not occur.
Load currents decrease more or less fast during OFF state of bridges depending on
selected decay mode. Slow decay mode is released by activating the HS switches of the

Doc ID 11778 Rev 7 33/40

Appendix L9942

bridge and current comparator has as new reference the overcurrent limit. A shortage to
ground can be detected, but not between the outputs.
Is it recommended to use the different fast decay modes too, especially in period if the load
current has to reduce from step to step. The duration of fast decay can set by fixed time ore
that it depends on the comparator signal utilizing the second current mirror at LS switch.
There can be monitored the undershoot of bridge current during OFF state.
Fast decay can be seen as switching the bridge in opposite direction, if it is compared to ON
state before. The load current control at HS switch is not used, but the comparator is still
active. The reference value is changed to overcurrent limit and a shortage to ground or now
between the outputs too will result in a signal. The internal filter time of at least 4 us will
inhibit the signal in many applications. Then you can use the mode “auto decay without any
delay time“ (On Section 5.1 mode 100). On page 12 you can find in the lower part of
Figure 3 the phase counter values, when fast decay as only part of mixed decay is used and
the shortages can be detected during a longer time. After this it is signalized in register 7 as
overcurrent in HS switch (e.g. in Figure 17 HSA1).

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L9942 Appendix

Figure 15. Stall detection

Load Current Rising During High Speed
Counter value is above threshold value.

PWM activ detection Stall

Register 5 Register 4 Reg3
Time
Threshold 16us * bit7 bit6 bit5 bit7 bit6 bit5 bit7 bit6
D7 D6 D5 D4 D3 D2 D1 D0

PWM activ detection PWM activ detection

Time

Stall Stall
Threshold Threshold
PWM activ PWM activ
counter counter

No
Stall Signal

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Activ Current Driver A

sampling and
threshold
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 Adress of Current 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Profile Entry
Activ Current Driver A
sampling and
threshold

Current Driver B Current Driver B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 Adress of Current 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Profile Entry

STEP Signal

Micro Stepping Mode: DIR=0 Micro Stepping Mode: DIR=1

Load Current Rising During Low Speed or Stall

PWM activ detection Counter value is below threshold value.

PWM activ detection PWM activ detection

Time PWM activ PWM activ

counter counter
Stall Stall
Threshold Threshold

Stall Signal Stall Signal

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Activ Current Driver A

sampling and
threshold
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 Adress of Current 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Profile Entry
Activ Current Driver A
sampling and
threshold

Current Driver B Current Driver B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 Adress of Current 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Profile Entry

STEP Signal

Micro Stepping Mode: DIR=0 Micro Stepping Mode: DIR=1

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Appendix L9942

Figure 16. Reference generation for PWM control (switch on)

1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 3
UP/Down Register 0 (e.g. during micro stepping to value 2) .
Count by PhaseCounter 1 Decay Mode Slew Rate StepMode DIR
0 0 0 0 1 DM2 DM1 DM0 SR1 SR0 0 0
1,2,4,8 0
STEP

0 0 0

0 1 2 3 0 1 2 3 0 1 2 3

A2 A1 A0
MUX MUX MUX

Address Calculation A3 A2 A1 A0

Phase A Phase B
Adr
A3=0
A[3..0] Adr
A3=1
neg(A[3..0]) Adr
A3=0
neg(A[3..0])
A3=1
Adr A[3..0]
PWM Control With HS Current Monitoring
Overcurrent Detection At LS Switch
Current-Profile Table
stored in register2, ...6
9
5
1 1 1 1 1 Profile 8
5 Phase Counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

1 1 1 1 0 Profile 7
Current Driver A
5
1 1 1 0 1 Profile 6
5 Adress of Current 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
1 1 0 1 0 Profile 5 Profile Entry
Phase A
5
1 0 1 1 0 Profile 4
5
1 0 0 0 1 Profile 3
5
0 1 1 0 0 Profile 2 Current Driver B
Adress of Current 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
5 Profile Entry
0 0 1 1 0 Profile 1 Phase B
5
0 0 0 0 0 Profile 0 STEP Signal

Register 1
HS Current
DAC Scale DAC Phase B DAC Phase A Monitoring
0 0 0
DI 1 1 1 1 0 0 0 1 1 0 (Load control)
95 mA 100mA * 30/31 = 91.9mA 100mA * 6/31 = 18.4mA LIMIT HSA1 - HS1 on
IQA1LIM
+
2mA 1000 QA1
I LIMIT B I LIMIT A
5 bit DAC 5 bit DAC
Phase B Phase A
2mA -
I REF I MAX
DAC +
REF -
Full Scale
200 uA
- IA
-
+ +
2mA QB1
-
LS Current
2mA -
Monitoring OC LSB1
-
+ LS1 on +
2mA QA2
(Overcurrentl) -

IB 2mA
- -
+ OC LSA2
LS2 on
+
-
-

LIMIT HSB2 -
IQA2LIM
HS2on -
+
LS Current
+
HS Current 2mA 1000 QB2 Monitoring
-
Monitoring (Overcurrent)
2mA
(Load control) -
+
-

-
+

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L9942 Appendix

Figure 17. Reference generation for PWM control (decay)

1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 1.2
UP/Down Register 0 (e.g. during micro stepping to value 2) .
PhaseCounter 1 Decay Mode Slew Rate StepMode DIR
Count by
1,2,4,8 0 0 0 0 1 DM2 DM1 DM0 SR1 SR0 0 0
0
STEP

0 0 0
Auto Decay
0 1 2 3 0 1 2 3 0 1 2 3

A2 A1 A0
MUX MUX MUX Mixed Decay
Fast and Slow
Address Calculation A3 A2 A1 A0 Slow Decay Decay
Phase A Phase B
A3=0 A3=1 A3=0 A3=1
Adr A[3..0] Adr neg(A[3..0]) Adr neg(A[3..0]) Adr A[3..0]

Current-Profile Table
stored in register2, ...6
9
5
1 1 1 1 1 Profile 8
5 Phase Counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

1 1 1 1 0 Profile 7
Current Driver A
5
1 1 1 0 1 Profile 6
5 Adress of Current 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
1 1 0 1 0 Profile 5 Profile Entry
Phase A
5
1 0 1 1 0 Profile 4
5
1 0 0 0 1 Profile 3
5
0 1 1 0 0 Profile 2 Current Driver B
Adress of Current 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
5 Profile Entry
0 0 1 1 0 Profile 1 Phase B
5
0 0 0 0 0 Profile 0 STEP Signal

Register 1
HS Current
DAC Scale DAC Phase B DAC Phase A Monitoring
0 0 0
DI 1 1 1 1 0 0 0 1 1 0 (Overcurrent)
95 mA 95mA * 30/31 = 91.9mA 100mA * 6/31 = 18.4mA OC HSA1 - HS1 on
+

I LIMIT B 2mA QA1

5 bit DAC 5 bit DAC
I LIMIT A
Phase B Phase A
2mA -
I REF I MAX +
REF DAC
Full Scale -
200 uA
Slow IA
OC -
HS Current HSB1 -
+ IQB1
HS1 on
+ Decay
Monitoring 2mA 1000 QB1
-

(Overcurrent) 2mA -
OC HSB1 - HS2 on
+
+
2mA QA2
-

Fast IB 2mA
- -
+ Decay +

-
-
HS Current
- - Monitoring
+
+
QB2 (Overcurrent)
LS Current 2mA
-

Monitoring 2mA - LS2on

(Load Control) +
-

LIMIT LSB2 -
+

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Package information L9942

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 18. PowerSSO24 mechanical data and package dimensions

mm inch
Dim.
Min. Typ. Max. Min. Typ. Max.
A 2.45 0.0965
OUTLINE AND
A2 2.15 2.35 0.084 0.0925 MECHANICAL DATA
a1 0 0.10 0 0.003
b 0.33 0.51 0.013 0.020
c 0.23 0.32 0.009 0.012
D (1) 10.10 10.50 0.398 0.413
E (1) 7.40 7.60 0.291 0.299
e 0.80 0.031
e3 8.80 0.346
F 2.30 0.090
G 0.10 0.004
G1 0.06 0.002
H 10.10 10.50 0.398 0.413
h 0.40 0.016
k 0˚ (min.), 8˚ (max.)
L 0.55 0.85 0.0217 0.0335
O 1.20 0.047
Q 0.80 0.031
S 2.90 0.114
T 3.65 0.143
U 1.0 0.039
N 10˚ (max)
X 4.10 4.70 0.161 0.185
6.50 7.10 0.256 0.279
Y
4.90(4) 5.50(4) 0.192(4) 0.216(4)
(1) “D and E1” do not include mold flash or protusions. PowerSSO24
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads. (Exposed pad down)
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
(4) Variation for small window leadframe option.

7412818 I

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L9942 Revision history

9 Revision history

Table 27. Document revision history

Date Revision Changes

10-Nov-2005 1 Initial release.

Feature list updated.
04-May-2006 2
Part numbers updated.
Feature list updated.
21-Sep-2006 3
Table 21 on page 28 updated.
Updated the order codes (see Table 1: Device summary on page 1).
09-Jul-2007 4
Changed the status from Preliminary data to Datasheet.
Updated the following tables: 2, 9, 14, 15, 16, 17, 18, 19 and 20.
02-Feb-2009 5 Updated the following chapters: 2.4, 5.1, 5.2, 5.3, 5.4, 5.5, 5.6 and
5.7.
Updated Figure 18: PowerSSO24 mechanical data and package
15-May-2009 6
dimensions on page 38.
19-Sep-2013 7 Updated Disclaimer.

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 L9942

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