DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

September 1986
Revised July 2001

DM7474
Dual Positive-Edge-Triggered D-Type Flip-Flops
with Preset, Clear and Complementary Outputs
General Description transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
This device contains two independent positive-edge-trig- HIGH without affecting the outputs as long as the data
gered D-type flip-flops with complementary outputs. The setup and hold times are not violated. A LOW logic level on
information on the D input is accepted by the flip-flops on the preset or clear inputs will set or reset the outputs
the positive going edge of the clock pulse. The triggering regardless of the logic levels of the other inputs.
occurs at a voltage level and is not directly related to the

Ordering Code:
Order Number Package Number Package Description
DM7474M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM7474N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram Function Table

Inputs Outputs
PR CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H H
(Note 1) (Note 1)
H H H H L
H H L L H
H H L X Q0 Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
= Positive-going transition of the clock.
Q0 = The output logic level of Q before the indicated input conditions were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.

2001 Fairchild Semiconductor Corporation DS006526 www.fairchildsemi.com

DM7474
Absolute Maximum Ratings(Note 2)
Note 2: The Absolute Maximum Ratings are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 5.5V
Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0C to +70C The Recommended Operating Conditions table will define the conditions
for actual device operation.
Storage Temperature Range 65C to +150 C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current 0.4 mA
IOL LOW Level Output Current 16 mA
fCLK Clock Frequency (Note 4) 0 15 MHz
tW Pulse Width Clock HIGH 30
(Note 4) Clock LOW 37
ns
Clear LOW 30
Preset LOW 30
tSU Input Setup Time (Note 3)(Note 4) 20 ns
tH Input Hold Time (Note 3)(Note 4) 5 ns
TA Free Air Operating Temperature 0 70 C
Note 3: The symbol () indicates the rising edge of the clock pulse is used for reference.
Note 4: TA = 25C and V CC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 5)
VI Input Clamp Voltage VCC = Min, II = 12 mA 1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.4 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.2 0.4 V
Output Voltage VIH = Min, VIL = Max
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
IIH HIGH Level VCC = Max D 40
Input Current VI = 2.4V Clock 80
A
Clear 120
Preset 40
IIL LOW Level VCC = Max D 1.6
Input Current VI = 0.4V Clock 3.2
mA
(Note 8) Clear 3.2
Preset 1.6
IOS Short Circuit Output Current VCC = Max (Note 6) 18 55 mA
ICC Supply Current VCC = Max (Note 7) 17 30 mA
Note 5: All typicals are at VCC = 5V, TA = 25C.
Note 6: Not more than one output should be shorted at a time.
Note 7: With all outputs open, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Note 8: Clear is tested with preset HIGH and preset is tested with clear HIGH.

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 DM7474
Switching Characteristics
at VCC = 5V and TA = 25C
From (Input) RL = 400, CL = 15 pF
Symbol Parameter Units
To (Output) Min Max
fMAX Maximum Clock
15 MHz
Frequency

tPHL Propagation Delay Time Preset to Q

40 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time Preset to Q
25 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time Clear to Q
40 ns
HIGH-to-LOW Level Output

tPLH Propagation Delay Time Clear to Q

25 ns
LOW-to-HIGH Level Output

tPHL Propagation Delay Time Clock to Q or Q

40 ns
HIGH-to-LOW Level Output

tPLH Propagation Delay Time Clock to Q or Q

25 ns
LOW-to-HIGH Level Output

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DM7474
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

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 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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