Cmos

DATASHEET
OKI
M82C55A-2V
OTHER SYMBOLS:
RGB ELEKTRONIKA AGACIAK CIACIEK

SPÓŁKA JAWNA
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51-162 Wrocław www.rgbelektronika.pl
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E2O0020-27-X3
This version: Jan. 1998

¡ Semiconductor
¡ Semiconductor MSM82C55A-2RS/GS/VJS
Previous version: Aug. 1996
MSM82C55A-2RS/GS/VJS
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
GENERAL DESCRIPTION
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high
speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best
fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU.
This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are
TTL interface compatible.
FEATURES
• High speed and low power consumption due to 3m silicon gate CMOS technology
• 3 V to 6 V single power supply
• Full static operation
• Programmable 24-bit I/O ports
• Bidirectional bus operation (Port A)
• Bit set/reset function (Port C)
• TTL compatible
• Compatible with 8255A-5
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)
1/26
CIRCUIT CONFIGURATION
8
VCC
8 8
Group A
GND Port A PA0 - PA7
(8)
8
Group A
Control
4 4
Group A
Port C
(High Order PC4 - PC7
4 Bits)
Internal Bus Line

8 Data 8
D 0 - D7 Bus
Buffer
4 4
Group B
Port C PC0 - PC3
(Low Order
8 4 Bits)
RD Group B
Read/ Control
WR
Write 8 8
Control Group B
RESET
Logic Port B PB0 - PB7
CS (8)
A0
A1
2/26
PIN CONFIGURATION (TOP VIEW)

40 pin Plastic DIP
PA3 1 40 PA4
PA2 2 39 PA5
PA1 3 38 PA6
PA0 4 37 PA7
RD 5 36 WR
CS 6 35 RESET
GND 7 34 D0
A1 8 33 D1
A0 9 32 D2
PC7 10 31 D3
PC6 11 30 D4
PC5 12 29 D5
PC4 13 28 D6
PC0 14 27 D7
PC1 15 26 VCC
44 pin Plastic QFP 25
PC2 16 PB7
PC3 17 24 PB6
43 PA0
42 PA1
41 PA2
40 PA3
38 PA4
37 PA5
36 PA6
35 PA7
34 WR
39 VCC
44 RD
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3
CS 1 33 RESET
GND 2 32 D0
A1 3 31 D1
A0 4 30 D2.
PC7 5 29 D3
PC6 6 28 D4
PC5 7 27 D5
PC4 8 26 D6
PC0 9 25 D7
PC1 10 24 VCC
PC2 11 23 PB7
44 pin Plastic QFJ
PB0 14
PB1 15
PB2 16
17
PB3 18
PB4 19
PB5 20
PB6 21
NC 22
NC 12
PC3 13
5 PA0
4 PA1
3 PA2
2 PA3
44 PA4
43 PA5
42 PA6
41 PA7
40 WR
VCC
6 RD
1 NC
CS 7 39 RESET
GND 8 38 D0
A1 9 37 D1
A0 10 36 D2.
PC7 11 35 D3
NC 12 34 NC
PC6 13 33 D4
PC5 14 32 D5
PC4 15 31 D6
PC0 16 30 D7
PC1 17 29 VCC
PB0 20
PB1 21
PB2 22
NC 23
PB3 24
PB4 25
PB5 26
PB6 27
PB7 28
PC2 18
PC3 19
3/26
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter Symbol Conditions Unit
MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS
Supply Voltage VCC Ta = 25°C –0.5 to +7 V
Input Voltage VIN with respect –0.5 to VCC +0.5 V
Output Voltage VOUT to GND –0.5 to VCC +0.5 V
Storage Temperature TSTG — –55 to +150 °C
Power Dissipation PD Ta = 25°C 1.0 0.7 1.0 W
OPERATING RANGE
Parameter Symbol Range Unit

Supply Voltage VCC 3 to 6 V
Operating Temperature Top –40 to 85 °C
RECOMMENDED OPERATING RANGE
Parameter Symbol Min. Typ. Max. Unit

Supply Voltage VCC 4.5 5 5.5 V
Operating Temperature Top –40 +25 +85 °C
"L" Input Voltage VIL –0.3 — +0.8 V
"H" Input Voltage VIH 2.2 — VCC + 0.3 V
DC CHARACTERISTICS
MSM82C55A-2
Parameter Symbol Conditions Unit
Min. Typ. Max.
"L" Output Voltage VOL IOL = 2.5 mA — — 0.4 V
IOH = –40 mA 4.2 — — V
"H" Output Voltage VOH
IOH = –2.5 mA 3.7 — — V
Input Leak Current ILI 0 £ VIN £ VCC VCC = 4.5 V to 5.5 V –1 — 1 mA
Output Leak Current ILO 0 £ VOUT £ VCC Ta = –40°C to +85°C –10 — 10 mA
(CL = 0 pF)
Supply Current CS ≥ VCC –0.2 V
ICCS VIH ≥ VCC –0.2 V — 0.1 10 mA
(Standby)
VIL £ 0.2 V
Average Supply I/O Wire Cycle

Current (Active) ICC 82C55A-2 — — 8 mA
...8 MHzCPU Timing
4/26
AC CHARACTERISTICS
(VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C)
MSM82C55A-2
Parameter Symbol Unit Remarks
Min. Max.
Setup Time of Address to the Falling Edge of RD tAR 20 — ns
Hold Time of Address to the Rising Edge of RD tRA 0 — ns
RD Pulse Width tRR 100 — ns
Delay Time from the Falling Edge of RD to the Output of
tRD — 120 ns
Defined Data
Delay Time from the Rising Edge of RD to the Floating of
tDF 10 75 ns
Data Bus
Time from the Rising Edge of RD or WR to the Next Falling
tRV 200 — ns
Edge of RD or WR
Setup Time of Address before the Falling Edge of WR tAW 0 — ns
Hold Time of Address after the Rising Edge of WR tWA 20 — ns
WR Pulse Width tWW 150 — ns
Setup Time of Bus Data before the Rising Edge of WR tDW 50 — ns
Hold Time of Bus Data after the Rising Edge of WR tWD 30 — ns
Delay Time from the rising Edge of WR to the Output of
tWB — 200 ns
Defined Data
Setup Time of Port Data before the Falling Edge of RD tIR 20 — ns
Hold Time of Port Data after the Rising Edge of RD tHR 10 — ns
ACK Pulse Width tAK 100 — ns Load
STB Pulse Width tST 100 — ns 150 pF
Setup Time of Port Data before the rising Edge of STB tPS 20 — ns
Hold Time of Port Bus Data after the rising Edge of STB tPH 50 — ns
Delay Time from the Falling Edge of ACK to the Output of
tAD — 150 ns
Defined Data
Delay Time from the Rising Edge of ACK to the Floating of
tKD 20 250 ns
Port (Port A in Mode 2)
Delay Time from the Rising Edge of WR to the Falling Edge of
tWOB — 150 ns
OBF
Delay Time from the Falling Edge of ACK to the Rising Edge of
tAOB — 150 ns
OBF
Delay Time from the Falling Edge of STB to the Rising Edge of
tSIB — 150 ns
IBF
Delay Time from the Rising Edge of RD to the Falling Edge of
tRIB — 150 ns
IBF
Delay Time from the the Falling Edge of RD to the Falling Edge
tRIT — 200 ns
of INTR
Delay Time from the Rising Edge of STB to the Rising Edge of
tSIT — 150 ns
INTR
Delay Time from the Rising Edge of ACK to the Rising Edge of
tAIT — 150 ns
INTR
Delay Time from the Falling Edge of WR to the Falling Edge of
tWIT — 250 ns
INTR
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
5/26
TIMING DIAGRAM
Basic Input Operation (Mode 0)
tRR
RD
tIR tHR
Port Input
tAR tRA
CS, A1, A0
D7 - D0
tRD tDF
Basic Output Operation (Mode 0)
tWW
WR
tDW tWD
D 7 - D0
tAW tWA
CS, A1, A0
Port Output
tWB
Strobe Input Operation (Mode 1)
tST
STB
tSIB
IBF
tSIT tRIB
INTR tRIT
RD
tPH
Port Input
tPS
6/26
Strobe Output Operation (Mode 1)
WR
tAOB
OBF
tWOB
INTR
tWIT
ACK
tAK tAIT
Port Output
tWB
Bidirectional Bus Operation (Mode 2)
WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB
tSIB
IBF tAD tKD
tPS
Port A
tPH tRIB
RD
7/26
OUTPUT CHARACTERISTICS (REFERENCE VALUE)
1 Output "H" Voltage (VOH) vs. Output Current (IOH)
5
Output "H" Voltage VOH (V)
4 Ta = –40 to + 85°C
VCC = 5.0 V
3
0 –1 –2 –3 –4 –5
Output Current IOH (mA)
2 Output "L" Voltage (VOL) vs. Output Current (IOL)
5
Output "L" Voltage VOL (V)
2
VCC = 5.0 V
1 Ta = –40 to +85°C
0 1 2 3 4 5
Output Current IOL (mA)
Note: The direction of flowing into the device is taken as positive for the output current.
8/26
PIN DESCRIPTION
Pin No. Item Input/Output Function
These are three-state 8-bit bidirectional buses used to write and

D 7 - D0 Bidirectional Input and read data upon receipt of the WR and RD signals from CPU and also
Data Bus Output used when control words and bit set/reset data are transferred from
CPU to MSM82C55A-2.
This signal is used to reset the control register and all internal
registers when it is in high level. At this time, ports are all made into
RESET Reset Input Input the input mode (high impedance status).
all port latches are cleared to 0.
and all ports groups are set to mode 0.
When the CS is in low level, data transmission is enabled with CPU.

CS Chip Select Input When it is in high level, the data bus is made into the high impedance
Input status where no write nor read operation is performed. Internal
registers hold their previous status, however.
When RD is in low level, data is transferred from MSM82C55A-2 to

RD Read Input Input
CPU.
When WR is in low level, data or control words are transferred from

WR Write Input Input
CPU to MSM82C55A-2.
By combination of A0 and A1, either one is selected from among

A0 , A 1 Port Select Input Input port A, port B, port C, and control register. These pins are usually
(Address) connected to low order 2 bits of the address bus.
These are universal 8-bit I/O ports. The direction of inputs/ outputs
Input and can be determined by writing a control word. Especially, port A can
PA7 - PA0 Port A
Output be used as a bidirectional port when it is set to mode 2.
Input and These are universal 8-bit I/O ports. The direction of inputs/outputs
PB7 - PB0 Port B
Output ports can be determined by writing a control word.
These are universal 8-bit I/O ports. The direction of inputs/outputs
can be determined by writing a control word as 2 ports with 4 bits
Input and
PC7 - PC0 Port C each. When port A or port B is used in mode 1 or mode 2 (port A
Output
only), they become control pins. Especially, when port C is used as
an output port, each bit can set/reset independently.
VCC – – +5V power supply.
GND – – GND
9/26
BASIC FUNCTIONAL DESCRIPTION
Group A and Group B
When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each.
Group A: Port A (8 bits) and high order 4 bits of port C (PC7~PC4)

Group B: Port B (8 bits) and low order 4 bits of port C (PC3~PC0)
Mode 0, 1, 2
There are 3 types of modes to be set by grouping as follows:
Mode 0: Basic input operation/output operation (Available for both groups A and B)
Mode 1: Strobe input operation/output operation (Available for both groups A and B)
Mode 2: Bidirectional bus operation (Available for group A only)
When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal
for operation ports (port A for group A and port B for group B) of their respective groups.
Port A, B, C
The internal structure of 3 ports is as follows:
Port A: One 8-bit data output latch/buffer and one 8-bit data input latch
Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer
Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input)
Single bit set/reset function for port C

When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to
turn to low level) any one of 8 bits individually without affecting other bits.
10/26
OPERATIONAL DESCRIPTION
Control Logic
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table
below:
Operaiton A1 A0 CS WR RD Operation
0 0 0 1 0 Port A Æ Data Bus
Input 0 1 0 1 0 Port B Æ Data Bus
1 0 0 1 0 Port C Æ Data Bus
0 0 0 0 1 Data Bus Æ Port A
Output 0 1 0 0 1 Data Bus Æ Port B
1 0 0 0 1 Data Bus Æ Port C
Control 1 1 0 0 1 Data Bus Æ Control Register
1 1 0 1 0 Illegal Condition
Others
¥ ¥ 1 ¥ ¥ Data bus is in the high impedance status.
Setting of Control Word
The control register is composed of 7-bit latch circuit and 1-bit flag as shown below.
Group A Control Bits Group B Control Bits
D7 D6 D5 D4 D3 D2 D1 D0
Definition of input/ 0 = Output

output of low order 1 = Input
4 bits of port C.
output of 8 bits of 1 = Input
port B.
Mode definition of 0 = Mode 0
group B. 1 = Mode 1
output of high order 1 = Input
4 bits of port C.
output of 8 bits of 1 = Input
port A.
Mode definition of group A.
D6 D5 Mode
Control word Identification flag 0 0 Mode 0
Be sure to set 1 for the control word 0 1 Mode 1
to define a mode and input/output.
1 ¥ Mode 2
When set to 0, it becomes
the control word for bit set/
reset.
11/26
Precaution for Mode Selection
The output registers for ports A and C are cleared to f each time data is written in the command
register and the mode is changed, but the port B state is undefined.
Bit Set/Reset Function
When port C is defined as output port, it is possible to set (set output to 1) or reset (set output
to 0) any one of 8 bits without affecting other bits as shown below.
D7 D6 D5 D4 D3 D2 D1 D0
Definition of set/reset 0 = Reset

for a desired bit. 1 = Set
Definition of bit wanted

to be set or reset.
Port C D3 D2 D1
PC0 0 0 0
Dont's Care PC1 0 0 1
PC2 0 1 0
Control word Identification flag PC3 0 1 1
Be sure to set to 0 for bit set/reset PC4 1 0 0
When set to 1, it becomes the control PC5 1 0 1
word to define a mode and input/output. PC6 1 1 0
PC7 1 1 1
Interrupt Control Function
When the MSM82C55A-2 is used in mode 1 or mode 2, the interrupt signal for the CPU is
provided. The interrupt request signal is output from port C. When the internal flip-flop INTE
is set beforehand at this time, the desired interrupt request signal is output. When it is reset
beforehand, however, the interrupt request signal is not output. The set/reset of the internal
flip-flop is made by the bit set/reset operation for port C virtually.
Bit set Æ INTE is set Æ Interrupt allowed

Bit reset Æ INTE is reset Æ Interrupt inhibited
Operational Description by Mode
1. Mode 0 (Basic input/output operation)

Mode 0 makes the MSM82C55A-2 operate as a basic input port or output port. No control
signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as
two-8-bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/
outputs. The inputs are not latched, but the outputs are.
12/26
Control Word Group A Group B

Type High Order 4 Bits Low Order 4 Bits
Port A Port B
D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 of Port C of Port C
1 1 0 0 0 0 0 0 0 Output Output Output Output
2 1 0 0 0 0 0 0 1 Output Output Output Input
3 1 0 0 0 0 0 1 0 Output Output Input Output
4 1 0 0 0 0 0 1 1 Output Output Input Input
5 1 0 0 0 1 0 0 0 Output Input Output Output
6 1 0 0 0 1 0 0 1 Output Input Output Input
7 1 0 0 0 1 0 1 0 Output Input Input Ouput
8 1 0 0 0 1 0 1 1 Output Input Input Input
9 1 0 0 1 0 0 0 0 Input Output Output Output
10 1 0 0 1 0 0 0 1 Input Output Output Input
11 1 0 0 1 0 0 1 0 Input Output Input Output
12 1 0 0 1 0 0 1 1 Input Output Input Input
13 1 0 0 1 1 0 0 0 Input Input Output Output
14 1 0 0 1 1 0 0 1 Input Input Output Input
15 1 0 0 1 1 0 1 0 Input Input Input Output
16 1 0 0 1 1 0 1 1 Input Input Input Input
Notes: When used in mode 0 for both groups A and B
2. Mode 1 (Strobe input/output operation)

In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB (Strobe input)

When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)

This is the response signal for the STB. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of STB
and to low level at the rising edge of RD.
INTR (Interrupt request output)

This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge
of the RD when the INTE is set.
INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the
bit for PC2 is set.
Following is a description of the output operation of mode 1.
13/26
OBF (Output buffer full flag output)

This signal when turned to low level indicates that data is written to the specified port upon
receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of
the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)

This signal when turned to low level indicates that the terminal has received data.

This is the signal used to interrupt the CPU when a terminal receives data from the CPU via
the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the
internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK
(OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set.
INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the
bit for PC2 is set.
Mode 1 Input
(Group A) (Group B)
8 8
PA7 PB7
-
-
INTEA PA0 INTEB PB0
PC4 STBA PC2 STBB
PC5 IBFA PC1 IBFB
RD RD
PC3 INTRA PC0 INTRB
Note: Although belonging to group B, PC3 operates as the control signal of

group A functionally.
Mode 1 Output
(Group A) (Group B)
8 8
PA7 PB7
-
INTEA PA0 INTEB PB0
PC7 OBFA PC1 OBFB
PC6 ACKA PC2 ACKB
WR WR
PC3 INTRA PC0 INTRB
14/26
Port C Function Allocation in Mode 1

Combination of
Group A: Input Group A: Input Group A: Output Group A: Output
Input/Output
Group B: Input Group B: Output Group B: Input Group B: Output
Port C
PC0 INTRB INTRB INTRB INTRB
PC1 IBFB OBFB IBFB OBFB
PC2 STBB ACKB STBB ACKB
PC3 INTRA INTRA INTRA INTRA
PC4 STBA STBA I/O I/O
PC5 IBFA IBFA I/O I/O
PC6 I/O I/O ACKA ACKA
PC7 I/O I/O OBFA OBFA
Note: I/O is a bit not used as the control signal, but it is available as a port of mode 0.
Examples of the relation between the control words and pins when used in mode 1 are
shown below:
(a) When group A is mode 1 output and group B is mode 1 input.
D7 D6 D5 D4 D3 D2 D1 D0
Control Word 1 0 1 0 1/0 1 1 ¥
Selection of I/O As all of PC0 - PC3 bits

of PC4 and PC5 become a control pin
when not defined in this case, this bit is
as a control pin. "Don't Care".
1 = Input
0 = Output
8
PA7 - PA0
WR PC7 OBFA
PC6 ACKA
PC3 INTRA
PC4, PC5 2 I/O Group A: Mode 1 Output
8
Group B: Mode 1 Input
PB7 - PB0
PC2 STBB
RD PC1 IBFB
PC0 INTRB
15/26
(b) When group A is mode 1 input and group B is mode 1 output.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0 1 0 ¥
Selection of I/O of PC6 and PC7

when not defined as a control pin.
1 = Input
0 = Output
8
PA7 - PA0
RD PC4 STBA
PC5 IBFA
PC3 INTRA
PC6, PC7 2
I/O Group A: Mode 1 Input
8
Group B: Mode 1 Output
PB7 - PB0
PC1 OBFB
WR PC2 ACKB
PC0 INTRB
3. Mode 2 (Strobe bidirectional bus I/O operation)

In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This
operation is akin to a combination between input and output operations. Port C waits for
the control signal in this case, too. Mode 2 is available only for group A, however.
Next, a description is made on mode 2.
OBF (Output buffer full flag output)

This signal when turned to low level indicates that data has been written to the internal
output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the
high impedance status and the data is not yet output to the outside. This signal turns to low
level at the rising edge of the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)

When a low level signal is input to this pin, the high impedance status of port A is cleared,
the buffer is enabled, and the data written to the internal output latch is output to port A.
When the input returns to high level, port A is made into the high impedance status.
STB (Strobe input)

When this signal turns to low level, the data output to the port from the pin is fetched into
the internal input latch. The data is output to the data bus upon receipt of the RD signal from
the CPU, but it remains in the high impedance status until then.
IBF (Input buffer full flag output)

This signal when turned to high level indicates that data from the pin has been fetched into
the input latch. This signal turns to high level at the falling edge of the STB and low level
at the rising edge of the RD.
16/26

This signal is used to interrupt the CPU and its operation in the same as in mode 1. There
are two INTE flip-flops internally available for input and output to select either interrupt
of input or output operation. The INTE1 is used to control the interrupt request for output
operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt
request for the input operation and it can be set by the bit set for PC4.
Mode 2 I/O Operation
PC3 INTRA
PA7 8
-
PA0
PC7 OBFA
INTE1 PC6 ACKA
WR
RD INTE2 PC4 STBA
PC5 IBFA
Port C Function Allocation in Mode 2
Port C Function
PC0
PC1 Confirmed to the Group B Mode
PC2
PC3 INTRA
PC4 STBA
PC5 IBFA
PC6 ACKA
PC7 OBFA
Following is an example of the relation between the control word and the pin when used in
mode 2.
When input in mode 2 for group A and in mode 1 for group B.
17/26
D7 D6 D5 D4 D3 D2 D1 D0
1 1 ¥ ¥ ¥ 1 1 ¥
As all of 8 bits of port C become

control pins in this case, D3 and
D0 bits are treated as "Don't Care".
No I/O specification is required for mode 2,

since it is a bidirectional operation.
This bit is therefore treated as "Don't Care".
When group A is set to mode 2, this bit is treated

as "Don't Care".
PC3 INTRA
8
PA7 - PA0
PC7 OBFA
PC6 ACKA
PC4 STBA Group A: Mode 2
PC5 IBFA Group B: Mode 1 Input
8
RD PB7 - PB0
PC2 STBB
WR PC1 IBFB
PC0 INTRB
18/26
4. When Group A is Different in Mode from Group B
Group A and group B can be used by setting them in different modes each other at the same
time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined
as a control pin in port C to both input and output as port which operates in mode 0 at the
3rd and 0th bits of the control word.
(Mode combinations that define no control bit at port C)
Port C
Group A Group B
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Mode 1
1 Mode 0 I/O I/O IBFA STBA INTRA I/O I/O I/O
input
Mode 0
2 Mode 0 OBFA ACKA I/O I/O INTRA I/O I/O I/O
Output
Mode 1
3 Mode 0 I/O I/O I/O I/O I/O STBB IBFB INTRB
Input
Mode 1 I/O I/O I/O I/O I/O ACKB OBFB INTRB
4 Mode 0
Output
Mode 1 Mode 1
5 I/O I/O IBFA STBA INTRA STBB IBFB INTRB
Input Input
Mode 1 Mode 1
6 I/O I/O IBFA STBA INTRA ACKB OBFB INTRB
Input Output
Mode 1 Mode 1
7 OBFA ACKA I/O I/O INTRA STBB IBFB INTRB
Output Input
Mode 1 Mode 1
8 OBFA ACKA I/O I/O INTRA ACKB OBFB INTRB
Output Output
9 Mode 2 Mode 0 OBFA ACKA IBFA STBA INTRA I/O I/O I/O
Controlled at the 3rd bit (D3) of Controlled at the 0th bit (D0) of
the Control Word the Control Word
When the I/O bit is set to input in this case, it is possible to access data by the normal port
C read operation.
When set to output, PC7-PC4 bits can be accessed by the bit set/reset function only.
Meanwhile, 3 bits from PC2 to PC0 can be accessed by normal write operation.
The bit set/reset function can be used for all of PC3-PC0 bits. Note that the status of port C
varies according to the combination of modes like this.
19/26
5. Port C Status Read
When port C is used for the control signal, that is, in either mode 1 or mode 2, each control
signal and bus status signal can be read out by reading the content of port C.
The status read out is as follows:
Status Read on the Data Bus

Group A Group B
D7 D6 D5 D4 D3 D2 D1 D0
Mode 1
1 Mode 0 I/O I/O IBFA INTEA INTRA I/O I/O I/O
Input
Mode 1
2 Mode 0 OBFA INTEA I/O I/O INTRA I/O I/O I/O
Output
Mode 1
3 Mode 0 I/O I/O I/O I/O I/O INTEB IBFB INTRB
Input
Mode 1 I/O I/O I/O I/O I/O INTEB OBFB INTRB
4 Mode 0
Output
Mode 1 Mode 1
5 I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Input Input
Mode 1 Mode 1
6 I/O I/O IBFA INTEA INTRA INTEB OBFB INTRB
Input Output
Mode 1 Mode 1
7 OBFA INTEA I/O I/O INTRA INTEB IBFB INTRB
Output Input
Mode 1 Mode 1
8 OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
Output Output
9 Mode 2 Mode 0 OBFA INTE1 IBFA INTE2 INTRA I/O I/O I/O
Mode 1
10 Mode 2 OBFA INTE1 IBFA INTE2 INTRA INTEB IBFB INTRB
Input
Mode 1 OBFA INTE1 IBFA INTE2 INTRA INTEB OBFB INTRB
11 Mode 2
Output
6. Reset of MSM82C55A-2
Be sure to keep the RESET signal at power ON in the high level at least for 50 ms.
Subsequently, it becomes the input mode at a high level pulse above 500 ns.
Note: Comparison of MSM82C55A-5 and MSM82C55A-2
MSM82C55A-5
After a write command is executed to the command register, the internal latch is cleared in
PORTA PORTC. For instance, 00H is output at the beginning of a write command when
the output port is assigned. However, if PORTB is not cleared at this time, PORTB is
unstable. In other words, PORTB only outputs ineffective data (unstable value according
to the device) during the period from after a write command is executed till the first data
is written to PORTB.
MSM82C55A-2
After a write command is executed to the command register, the internal latch is cleared in
All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command
when the output port is assigned.
20/26
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.
High-speed device (New) Low-speed device (Old) Remarks

M80C85AH M80C85A/M80C85A-2 8bit MPU
M80C86A-10 M80C86A/M80C86A-2 16bit MPU
M80C88A-10 M80C88A/M80C88A-2 8bit MPU
M82C84A-2 M82C84A/M82C84A-5 Clock generator
M81C55-5 M81C55 RAM.I/O, timer
M82C37B-5 M82C37A/M82C37A-5 DMA controller
M82C51A-2 M82C51A USART
M82C53-2 M82C53-5 Timer
M82C55A-2 M82C55A-5 PPI
21/26
Differences between MSM82C55A-5 and MSM82C55A-2
1) Manufacturing Process
These devices use a 3 m Si-Gate CMOS process technology.
The MSM82C55A-2 is about 7% smaller in chip size than the MSM82C55A-5 as the MSM82C55A-
2 changed its output characteristics.
2) Function
Item MSM82C55A-5 MSM82C55A-2

Internal latch during writing into Only ports A and C are cleared. All ports are cleared.
the command register Port B is not cleared.
The above function has been improved to remove bugs and other logics are not different between
the two devices.
3) Electrical Characteristics
3-1) DC Characteristics
Parameter Symbol MSM82C55A-5 MSM82C55A-2

0.45 V 0.40 V
''L'' Output Voltage VOL
(IOL = +2.5 mA) (IOL = +2.5 mA)
2.4 V 3.7 V
''H'' Output Voltage VOH (IOH = -400 mA) (IOH = -2.5 mA)
5 mA maximum 8 mA maximum
Average Operating Current ICC (I/O Cycle = 1 ms) (I/O Cycle = 375 ns)
As shown above, the DC characteristics of the MSM82C55A-2 satisfies the DC characteristics of the
MSM82C55A-5.
3-2) AC Characteristics
Address Hold Time for RD Rising tRA 20 ns minimum 0 ns minimum
RD Pulse Width tRR 300 ns minimum 100 ns minimum

Difined Data Output Delay Time tRD 200 ns maximum 120 ns maximum
From RD Falling
Data Floating Delay Time From RD Rising tRF 100 ns maximum 75 ns maximum
RD/WR Recovery Time tRV 850 ns minimum 200 ns minimum
22/26
Address Hold Time for WR Rising tWA 30 ns minimum 20 ns minimum
WR Pulse Width tWW 300 ns minimum 150 ns minimum
Data Setup Time for WR Rising tDW 1000 ns minimum 50 ns minimum
Data Hold Time for WR Rising tWD 40 ns minimum 30 ns minimum
Defined Data Output Time

tWB 350 ns maximum 200 ns maximum
From WR Rising
Port Data Hold Time for RD Rising tHR 20 ns minimum 10 ns minimum
ACK Pulse Width tAK 300 ns minimum 100 ns minimum

STB Pulse Width tST 300 ns minimum 100 ns minimum
Port Data Hold Time for STB Falling tPH 180 ns minimum 50 ns minimum
ACK Falling to Defined Data Output tAD 300 ns maximum 150 ns maximum
WR Falling to OBF Falling Delay Time tWOB 650 ns maximum 150 ns maximum
ACK Falling to OBF Rising Delay Time tAOB 350 ns maximum 150 ns maximum
STB Falling to IBF Rising Delay Time tSIB 300 ns maximum 150 ns maximum
RD Rising to IBF Falling Delay Time tRIB 300 ns maximum 150 ns maximum
RD Falling to INTR Falling Delay Time tRIT 400 ns maximum 200 ns maximum
STB Rising to INTR Rising Delay Time tSIT 300 ns maximum 150 ns maximum
ACK Rising to INTR Rising Delay Time tAIT 350 ns maximum 150 ns maximum
WR Falling to INTR Falling Delay Time tWIT 850 ns minimum 250 ns maximum
As shown above, the MSM82C55A-2 satisfies the characteristics of the MSM82C55A-5.
23/26
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material Epoxy resin

Lead frame material 42 alloy
Pin treatment Solder plating
Solder plate thickness 5 mm or more
Package weight (g) 6.10 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/26
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish

Lead frame material Cu alloy
25/26
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish

Lead frame material 42 alloy
26/26

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DATASHEET

RGB ELEKTRONIKA AGACIAK CIACIEK

Jana Dlugosza 2-6 Street

Buy this product at RGB AUTOMATYKA BUY ∠

This version: Jan. 1998

Internal Bus Line

PIN CONFIGURATION (TOP VIEW)

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Range Unit

RECOMMENDED OPERATING RANGE

Parameter Symbol Min. Typ. Max. Unit

Average Supply I/O Wire Cycle

Basic Input Operation (Mode 0)

Basic Output Operation (Mode 0)

Strobe Input Operation (Mode 1)

Strobe Output Operation (Mode 1)

Bidirectional Bus Operation (Mode 2)

OUTPUT CHARACTERISTICS (REFERENCE VALUE)

1 Output "H" Voltage (VOH) vs. Output Current (IOH)

2 Output "L" Voltage (VOL) vs. Output Current (IOL)

Pin No. Item Input/Output Function

These are three-state 8-bit bidirectional buses used to write and

When the CS is in low level, data transmission is enabled with CPU.

When RD is in low level, data is transferred from MSM82C55A-2 to

When WR is in low level, data or control words are transferred from

By combination of A0 and A1, either one is selected from among

BASIC FUNCTIONAL DESCRIPTION

Group A and Group B

Group A: Port A (8 bits) and high order 4 bits of port C (PC7~PC4)

Single bit set/reset function for port C

Setting of Control Word

Group A Control Bits Group B Control Bits

Definition of input/ 0 = Output

Precaution for Mode Selection

Bit Set/Reset Function

Definition of set/reset 0 = Reset

Definition of bit wanted

Interrupt Control Function

Bit set Æ INTE is set Æ Interrupt allowed

Operational Description by Mode

1. Mode 0 (Basic input/output operation)

Control Word Group A Group B

2. Mode 1 (Strobe input/output operation)

STB (Strobe input)

IBF (Input buffer full flag output)

INTR (Interrupt request output)

OBF (Output buffer full flag output)

ACK (Acknowledge input)

INTR (Interrupt request output)

PC4 STBA PC2 STBB

PC5 IBFA PC1 IBFB

Note: Although belonging to group B, PC3 operates as the control signal of

INTEA PA0 INTEB PB0

PC7 OBFA PC1 OBFB

PC6 ACKA PC2 ACKB

Port C Function Allocation in Mode 1

(a) When group A is mode 1 output and group B is mode 1 input.

Selection of I/O As all of PC0 - PC3 bits