Secure Authentication Starter Kit

Evaluates: DS28E01/DS28CN01/DS2460
General Description Features
The secure authentication starter kit is a highly program- S Complete Development System for Applications
mable hardware/software system for development, lab Using Maxim SHA-1 Products
testing, and demonstration of embedded applications S Starter Kit Board Includes Maxim’s DS2460,
that use Maxim’s SHA-1-based secure authentication DS2482-100, DS28CN01, and DS28E01 Devices for
products. The system supports multiple options for dem- Rapid Development
onstrating and developing both host SHA-1 computa-
S Other and Future Maxim SHA-1 Authenticators
tion and associated host communication with Maxim’s
1-WireM and I2C-based SHA-1 slave ICs. Multiple options Supported Through Expansion Ports
are supported for host SHA-1 computation development S Embedded Host Development Options Supported
including fixed function processing with the Maxim with PIC18F4550 µC and Xilinx XC3S400A FPGA
DS2460, microcontroller(FC)-based with a Microchip S PC Connectivity with RS-232 and USB 2.0
PIC18F4550, and a Maxim-developed SHA-1 Verilog
S JTAG Connector Mates to Xilinx Platform Cables
implementation (DSSHA1) used in conjunction with
Through a Single Ribbon Cable
a Xilinx SpartanM-3A XC3S400A FPGA. Development
capabilities for the host interface to Maxim’s SHA-1 S 120-Pin Expansion Port for FPGA
slaves are similarly supported with multiple options S In-Circuit Debugger Port for PIC18F4550
including the Maxim DS2482-100 I2C-to-1-Wire line
S 40-Pin Expansion Port for PIC18F4550 Periphery
driver, software generation of 1-Wire waveforms with the
PIC18F4550, and a Verilog implementation (DS1WM) S Extension Ports for I2C and 1-Wire Bus
with the Xilinx FPGA. The EV kit can be used alone or S Jumper Configurable for µC or FPGA as I2C
controlled with a PC over RS-232 or USB interfaces. Master
Microcontroller software can be installed and tested
S Jumper Configurable for µC, FPGA, DS2482-100,
through an in-circuit debugger port. A JTAG port allows
or External 1-Wire Bus Master
changing the FPGA programming through standard
Xilinx development tools. With its expansion ports (40 S Six General-Purpose Pushbuttons and Indicator
pins for the microcontroller, 120 pins for the FPGA), the LEDs
board can be the development platform for complex S LED Indicators for Power and FPGA Load Done
designs. S Free Evaluation Software Available by NDA
The free software/firmware is available by request at
https://support.maximintegrated.com/1-Wire. Ordering Information
PART TYPE
DSAUTHSK# Secure Authentication Starter Kit
#Denotes a RoHS-compliant device that may include lead(Pb)
that is exempt under the RoHS requirements.

1-Wire is a registered trademark of Maxim Integrated

Products, Inc.
Spartan is a registered trademark of Xilinix, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5894; Rev 0; 6/11
Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Component List
LOCATION
ITEM TYPE DESIGNATOR LABEL DESCRIPTION
(SEE FIGURE 1)
PCB — — — PCB: Secure Authentication Starter Kit#, REV A
POWER SUPPLY
Red LED
LED D9 — B7
LNJ208R8ARA
2.1mm barrel socket
Connector J14 — A6
PJ-002A-SMT
Jumper JP9 USB, JACK A6/A7, B6/B7 3 pins
Normally open
Pushbutton SW8 RESET POWER B5
7914J-1-000E
TP5 TIP A7 Inner contact of J14 (positive)
TP6 RING A6 Outer contact of J14 (negative)
TP7 5V B7 Raw 5V power rail
TP8 — B6/C6 Filtered 3.3V power rail before R47
TP9 — B6 Filtered 3.3V power rail
TP10 — C6 Filtered 1.2V power rail before R49
Test Point TP11 — C6 Filtered 1.2V power rail
TP14 GND I1
TP15 GND B7
TP16 GND H7
Access to local ground
TP17 GND I4
TP18 GND C2
TP19 GND C7
Step-down DC-DC converter (10 TDFN-EP*)
U24, U25 — B6, C6
Maxim MAX1556AETB+
IC Triple voltage monitor and sequencer
U26 — B5 (20 TQFN-EP*)
Maxim MAX16028TP+
SYSTEM CLOCK
Single Schmitt-trigger inverter
U21, U23 E2
74VHC1G14DF
IC
16MHz oscillator
U22 E2/F2
Fox Electronics FXO-HC536R-16
PIC MICRO
Green LED
LED D1, D2 — B1
LNJ308G8TRA
Mini USB, female
J1 — A4/A5
DX3R005HN2E700
DB9 connector
J2 — A1, A2, A3
5788797-1
Connector
5-pin header, ICD port
J3 — B3/B4
4-102972-0
2 x 20-pin header
J4 — D2–D5
PEC20DAAN
Jumper JP4 uP-OW E6 2 pins

2   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Component List (continued)

LOCATION
ITEM TYPE DESIGNATOR LABEL DESCRIPTION
(SEE FIGURE 1)
SW1 RB4 MICRO B1 Normally open
Pushbutton
SW2 RB5 MICRO B1/C1 7914J-1-000E
RS-232 drivers/receivers (16 TSSOP)
U2 — B2/B3
Maxim MAX232ACUE+
IC
Microcontroller
U5 — C3
PIC18F4550T-I/PT
FPGA
D3, D4 — E1
Green LED
D5 — D1
LNJ308G8TRA
LED D6 — C1
Blue LED
D7 — F1
LTST-C191TBKT
2mm spaced pin header, 2 x 7 pins
J5 — E5/F5
87759-1450
Connector J6 BANK 3 I4–I7
0.1-mil spaced pin header, 2 x 20 pins
J7 BANK 0 I1–I4
PEC20DAAN
J8 BANK 1 F1–I1
2 x 3 pins
Jumper Block JB1 — G3
9-146252-0-01
JP1 — F3/G3 3 pins
Jumper
JP6 FPGA E6 2 pins
SW3 BANK 0 FPGA E1/F1
SW4 BANK 1 FPGA E1
Normally open
Pushbutton SW5 BANK 2 FPGA D1
7914J-1-000E
SW6 BANK 3 FPGA C1
SW7 RESET F4
Spartan-3A FPGA
U10 — G2/G3, H2/H3
XC3S400A-4FTG256C
Gate
U11 — F4
NC7SV08P5X
IC
PROM for FPGA
U12 — E4/F4
XCF04SVOG20C
G5, D5/E5, D6/ Dual-level translator (8 TDFN-EP*)
U17, U19 —
E6 Maxim MAX3394EETA+T
PIC/FPGA BRIDGE
Test Point TP1 RA6 C2 Signal input pin of U3
U1 — D2
Three-state bus buffer/line driver
U3 — C2
74VHC1G125DF
U4, U9 — E3
IC Octal transparent latch
U6 — E3/F3
74LCX573DTG
Low-voltage CMOS octal transceiver
U7 — E3/F3, E4/F4
MC74LCX245DTR2G

Maxim Integrated   3

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Component List (continued)

LOCATION
ITEM TYPE DESIGNATOR LABEL DESCRIPTION
(SEE FIGURE 1)
Single Schmitt-trigger inverter
IC U8 — C2
74VHC1G14DF
I2C
Connector J9 — G7/H7 I2C expansion port
JP2 — G5 Select SCL source for I2C slaves
JP3 — F5 Select SDA source for I2C slaves
Jumper
Enable 1-Wire extra strong pullup from
JP8 2482 F6
DS2482-100
TP2 SCL H7 SCL line of I2C bus
Test Point
TP3 SDA I7 SDA line of I2C bus
Single-channel 1-Wire master (8 SO)
U13 — F7
Maxim DS2482S-100+
1Kbit I2C/SMBus EEPROM with SHA-1 engine
U14 — F6 (8 FSOP)
IC Maxim DS28CN01U-A00+
SHA-1 coprocessor with EEPROM (8 SO)
U15 — F6
Maxim DS2460S+
12-bit I2C voltage-output DAC (6 SOT23)
U16 — F5/F6
Maxim MAX5812MEUT
1-Wire
J10 VPUP E5 1-Wire pullup resistor
RJ11 1-Wire port
J11 — D7/E7
5520250-3
Connector
J12 — F7/G7 1-Wire expansion port
TO-92 1-Wire socket
J13 — F7
801-93-036-10-012000
2 x 3 pins
JP5 — E5/F5, E6/F6
9-146252-0-03
Jumper JP7 — E7 2 pins
JP10 — C5 3 pins
JP11 — C5 3 pins
TP4 OW D7 Data line of 1-Wire bus
Test Point TP12 VPUP D6 1-Wire VPUP before R52
TP13 VPUP D7 1-Wire VPUP
ESD protection diode with resistors (6 TSOC)
U18 — D6
Maxim DS9503P+
IC 1Kb protected 1-Wire EEPROM with SHA-1
U20 — E7 engine (6 TSOC)
Maxim DS28E01P-100+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.

4   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Figure 1. Secure Authentication Starter Kit Circuit Board with Reference Grid

Maxim Integrated   5

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

5V DC (BARREL JACK) USB RS-232 ICD EXPANSION 1-Wire

J14 J1 J2 J3 J4 RPUP (RJ11)
J10 4 J11
2 2 2 5 5
40
2

5V 5V PIC JP5 5V 1-Wire

POWER 1-Wire 3
3.3V MICRO 3.3V
SUPPLY SECTION J12
1.2V SECTION

1-Wire
3
DAC J13
5V 16MHz 5V
PIC/FPGA
3.3V SYSTEM 3.3V
BRIDGE
CLOCK JP2, JP3 5V
I 2C
2
SECTION
2
2
3.3V
FPGA
1.2V
SECTION

40 40 40 14 4

J6 J7 J8 J5 J9
EXPANSION EXPANSION EXPANSION JTAG I 2C

Figure 2. Secure Authentication Starter Kit Block Diagram

Detailed Description of Hardware power line of the USB port (J1). See Table 1 for J14 pin
assignments. Jumper JP9 must be installed according to
Figure 1 shows the starter kit with an overlaid grid to the available power source. See the Setting the Jumpers
provide a quick reference for component location on the section for details. Various test points give access to the
board. The block diagram in Figure 2 shows the circuit 5V input and the 3.3V and 1.2V rails. TP8/TP9 and TP10/
with all connectors and ports. Subsequent sections dis- TP11 connect to 10mI resistors in the 3.3V and 1.2V rail
cuss the individual blocks, explain the necessary jumper to allow measuring the load current. A voltage measure-
settings, and give further references on additional appli- ment of 10mV corresponds to a current load of 1mA.
cations of the board.
Power-Supply Section Table 1. J14 Pin Assignments
The power-supply section contains three integrated cir- PIN SIGNAL NAME ALIAS
cuits: U24, U25, and U26. U24 and U25 are step-down 1 POWER TIP
DC-DC converters that generate 3.3V and 1.2V from
2 GND RING
the 5V input voltage. U26 monitors and sequences the
3 GND RING
power lines and issues a reset pulse on power-on, when
the 3.3V or 1.2V rail fails, or when the RESET POWER 4 POWER TIP
button (SW8) is pressed (user reset). The red LED (D9) Note: J14 has no printed pin 1 marker. Pin 1 is to the left
is on if the 5V power is available. Power is supplied either of TP5. The pin numbering is counterclockwise. Warning:
Incorrect voltage applied to J14 can result in damage to
from an external 5V Q5% source connected to J14 or the the board.

6   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Table 2. J1 USB Port Pin Assignments Table 5. J4 Expansion Port Pin

PIN SIGNAL NAME Assignments
1 VBUS PIN SIGNAL NAME PIN SIGNAL NAME
2 USB DM 1 GND 2 OWSP
3 USB DP 3 3V 4 RA2
4 NC 5 OW 6 RST
5–9 GND 7 5V 8 RB7
Note: J1 has no printed pin 1 marker. Pin 5 is above the right 9 GND 10 RB6
side of FB1. The pin numbering is descending left to right.
11 RB5 12 RB4
Pins 6–9 are the outer part of the USB socket and connect to
GND. 13 RB3 14 RB2
15 SCL 16 SDA
Table 3. J2 RS-232 Port Pin Assignments 17 RD7 18 RD6
PIN SIGNAL NAME PIC PIN 19 RD5 20 RD4
1, 4, 6, 9 NC — 21 RC7 22 RC6
2 T1OUT\ TX 23 USBP 24 USBM
3 R1IN RX 25 RD3 26 RD2
5 GND — 27 RD1 28 RD0
7 R2IN RA3 29 RC2 30 RC1
8 T2OUT\ RA2 31 RC0 32 RA6
33 RE2 34 RE1
Note: J2 has no printed pin 1 marker. Pin 1 is on the left side.
The pin numbering is ascending left to right with pins 1 to 5 35 RE0 36 RA5
in the front row (accessible) and pins 6–9 in the rear row (not 37 RA4 38 RA3
accessible). 39 CLKA 40 GND

Table 4. J3 ICD Port Pin Assignments

PIC Micro Section
PIN SIGNAL NAME The PIC micro section contains two integrated circuits,
1 RSTZ the dual-channel RS-232 driver/receiver U2 and the
2 5V microcontroller U5. Both U2 and U5 operate on the 5V
3 GND supply. U2 makes the microcontroller accessible though
4 PGD a RS-232 port J2. The USB port J1 directly connects
5 PGC to the microcontroller. The ICD port J3 can be used
to operate the microcontroller under the control of an
Note: J3 has no printed pin 1 marker. Pin 1 is labeled RSTZ. in-circuit debugger. The expansion port J4 allows con-
The pin numbering is ascending left to right.
necting external circuitry to the microcontroller. See
Tables 2–5 for J1–J4 pin assignments. There are two
System Clock Section pushbuttons (SW1, SW2) and two green LEDs (D1, D2)
The system clock section contains three integrated for user input and feedback. Their function depends on
circuits: U21, U22, and U23. The clock source is U22, the software loaded into the microcontroller. The only
a 16MHz silicon oscillator. U21 and U23 are Schmitt- jumper in the PIC micro section is JP4. It is relevant
trigger inverters used as line drivers. U21, which is pow- when the microcontroller functions as 1-Wire master. JP4
ered from the 5V supply, delivers a 5V clock signal to the must be installed if the software-controlled 1-Wire power-
PIC micro. U23 delivers a 3.3V clock signal to the FPGA. delivery feature “strong pullup” is used. See the Setting
U22 and U23 operate on the 3.3V supply. There are no the Jumpers section for details. There are no direct test
direct test points for the clock signal. The 5V clock can points in the PIC micro section, however, several signals
be probed at pin 39 of J4. can be probed at J4.

Maxim Integrated   7

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

FPGA Section through SW7, independent of the power-on reset. The

The FPGA section contains five integrated circuits: U10, FPGA requires both 1.2V and 3.3V for operation. U11
U11, U12, U17, and U19. U10 and U12 are the FPGA runs on 3.3V. U17 needs 3.3V and 5V. U19 operates with
and the associated JTAG PROM. U17 and U19 are 3.3V on the FPGA side and the user-selectable VPUP
level translators that allow the 3.3V FPGA to communi- (JP10, JP11) on the 1-Wire side. The FPGA section has
cate with the 5V I2C and 1-Wire section. The dual-input a JTAG port J5 and three expansion ports, J6, J7, and
AND gate U11 implements a manual reset of the FPGA J8. See Tables 6–9 for the respective pin assignments.
Besides the RESET button (SW7), the FPGA section
has four more pushbuttons (SW3–SW6) and four green
Table 6. J5 JTAG Port Pin Assignments LEDs (D3–D6) for user input and feedback. Their func-
PIN SIGNAL NAME PIN SIGNAL NAME tion depends on the software loaded into the FPGA.
1 GND 2 3V The blue LED D7 reports the state of the FPGA’s DONE
3 GND 4 TMS signal. The LED is on if DONE is high. The FPGA section
5 GND 6 TCK includes three jumpers: JP1, JB1, and JP6. JP1 relates to
the FPGA suspend mode, which can be enabled to save
7 GND 8 TDO
power. JB1 controls whether the FPGA loads its configu-
9 GND 10 TDI
ration from U12 (normal operation) or from the JTAG port
11 GND 12 NC (during program development). JP6 is relevant when the
13 GND 14 NC FPGA functions as 1-Wire master. JP6 must be installed
Note: J5 has no printed pin 1 marker. Pin 1 is on bottom if the software-controlled 1-Wire power-delivery feature
right side of J5, and pin 2 is at the bottom left side. The odd “strong pullup” is used. See the Setting the Jumpers
numbers are on the right side ascending from bottom up. The section for details. There are no direct test points in the
even numbers are on the left side, ascending from bottom up.
FPGA section.

Table 7. J6 Bank 3 Expansion Port Pin Assignments

CONNECTOR PIN FPGA PIN SIGNAL NAME CONNECTOR PIN FPGA PIN SIGNAL NAME
1 — GND 2 — 5V
3 — 3V 4 C2 BANK3 IO2
5 C1 BANK3 IO1 6 D1 BANK3 IO4
7 E3 BANK3 IO3 8 E2 BANK3 IO6
9 F3 BANK3 IO5 10 E1 BANK3 IO8
11 H5 BANK3 IO7 12 F1 BANK3 IO10
13 G4 BANK3 IO9 14 G3 BANK3 IO12
15 J6 BANK3 IO11 16 G1 BANK3 IO14
17 H3 BANK3 IO13 18 G2 BANK3 IO16
19 H1 BANK3 IO15 20 H4 BANK3 IO18
21 J2 BANK3 IO17 22 J4 BANK3 IO20
23 J1 BANK3 IO19 24 K1 BANK3 IO22
25 K3 BANK3 IO21 26 L3 BANK3 IO24
27 J3 BANK3 IO23 28 L1 BANK3 IO26
29 L2 BANK3 IO25 30 K4 BANK3 IO28
31 M1 BANK3 IO27 32 L4 BANK3 IO30
33 M3 BANK3 IO29 34 M4 BANK3 IO32
35 N1 BANK3 IO31 36 N3 BANK3 IO34
37 N2 BANK3 IO33 38 P1 BANK3 IO35
39 — GND 40 — GND

8   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Table 8. J7 Bank 0 Expansion Port Pin Assignments

CONNECTOR PIN FPGA PIN SIGNAL NAME CONNECTOR PIN FPGA PIN SIGNAL NAME
1 — GND 2 — 5V
3 — 3V 4 C4 BANK0 IO2
5 A14 BANK0 IO1 6 B14 BANK0 IO4
7 A13 BANK0 IO3 8 D13 BANK0 IO6
9 C13 BANK0 IO5 10 C12 BANK0 IO8
11 A12 BANK0 IO7 12 D11 BANK0 IO10
13 B12 BANK0 IO9 14 C11 BANK0 IO12
15 A11 BANK0 IO11 16 D10 BANK0 IO14
17 A10 BANK0 IO13 18 E10 BANK0 IO16
19 A9 BANK0 IO15 20 D9 BANK0 IO18
21 C9 BANK0 IO17 22 C8 BANK0 IO20
23 A8 BANK0 IO19 24 E7 BANK0 IO22
25 B8 BANK0 IO21 26 D8 BANK0 IO24
27 A7 BANK0 IO23 28 D7 BANK0 IO26
29 C7 BANK0 IO25 30 C6 BANK0 IO28
31 A6 BANK0 IO27 32 C5 BANK0 IO30
33 B6 BANK0 IO29 34 D4 BANK3 IO37
35 A5 BANK0 IO31 36 B4 BANK0 IO32
37 C16 BANK1 IO36 38 D3 BANK3 IO36
39 — GND 40 — GND

Table 9. J8 Bank 1 Expansion Port Pin Assignments

CONNECTOR PIN FPGA PIN SIGNAL NAME CONNECTOR PIN FPGA PIN SIGNAL NAME
1 — GND 2 — 5V
3 — 3V 4 N13 BANK1 IO2
5 N14 BANK1 IO1 6 N16 BANK1 IO4
7 R15 BANK1 IO3 8 M13 BANK1 IO6
9 M14 BANK1 IO5 10 L13 BANK1 IO8
11 K13 BANK1 IO7 12 M15 BANK1 IO10
13 M16 BANK1 IO9 14 L14 BANK1 IO12
15 L16 BANK1 IO11 16 K15 BANK1 IO14
17 J13 BANK1 IO13 18 K16 BANK1 IO16
19 J14 BANK1 IO15 20 J16 BANK1 IO18
21 H15 BANK1 IO17 22 H16 BANK1 IO20
23 H13 BANK1 IO19 24 G16 BANK1 IO22
25 H14 BANK1 IO21 26 G14 BANK1 IO24
27 G13 BANK1 IO23 28 F16 BANK1 IO26
29 F15 BANK1 IO25 30 E16 BANK1 IO28
31 F14 BANK1 IO27 32 E14 BANK1 IO30
33 F13 BANK1 IO29 34 D16 BANK1 IO32
35 D15 BANK1 IO31 36 E13 BANK1 IO34
37 D14 BANK1 IO33 38 C15 BANK1 IO35
39 — GND 40 — GND

Maxim Integrated   9

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

PIC/FPGA Bridge Section I2C Section

The PIC/FPGA bridge section contains seven integrated The I²C section contains four integrated circuits: U13–
circuits: U1, U3, U4, and U6–U9. U6 and U7 transfer U16. U13 is a 1-Wire master, which can be selected by
and level-translate address and data signals between JP5 to communicate with 1-Wire devices on or external to
the PIC and the FPGA. U1, U3, U8, and U9 level-convert the board. U14 is a 1Kb I2C/SMBus EEPROM with SHA-1
control signals from the PIC to U6, U7 and the FPGA from engine and U15 is a SHA-1 coprocessor. These are the
5V to 3.3V levels. U4 level-converts a feedback signal of typical I2C devices to be evaluated with this board. U16
the FPGA from 3.3V to 5V. Besides U4, which runs on is the DAC to generate the adjustable 1-Wire pullup volt-
5V, the other integrated circuits of the PIC/FPGA bridge age. J9 is intended for connecting a small circuit board
operate on 3.3V. The only test point in the bridge is TP1, with an I2C slave. See Table 10 for the pin assignments.
which allows access to the signals that controls write The I2C section includes the jumpers JP2, JP3, and JP8.
access to the FPGA. JP2 and JP3 must be populated with one jumper each to
select either the PIC micro or the FPGA as I2C master.
Table 10. J9 I2C Expansion Port Pin JP8 is relevant when the DS2482-100 functions as 1-Wire
Assignments master. JP8 should be installed if the software-controlled
1-Wire power-delivery feature “strong pullup” is used.
PIN SIGNAL NAME See the Setting the Jumpers section for details. The I2C
1 5V section has two test points (TP2, TP3) that allow monitor-
2 SCL ing the activity on SCL and SDA.
3 SDA
1-Wire Section
4 GND
The 1-Wire section contains two integrated circuits:
U18 and U20. U18 is an ESD protection device, which
Table 11. J10 RPUP Socket Pin protects the 1-Wire section from ESD hits that could be
Assignments introduced at J11, J12, or J13. U20 is a 1Kb protected
1-Wire EEPROM with SHA-1 engine, which can be put on
PIN SIGNAL NAME
the 1-Wire bus using JP7. Special attention is necessary
1 VPUP for J10. Because the R37 position is not populated, it is
2 OW necessary to install a pullup resistor to the 1-Wire bus
across the terminals of J10. The typical pullup resistor
Table 12. J11 RJ11 Port Pin Assignments value is 2.2kΩ. The resistor must not be installed when
using the DS2482-100 as 1-Wire master. J11 allows con-
PIN SIGNAL NAME
necting DS1402 1-Wire network cables to the 1-Wire bus.
1 5V
It can also be used to access U20 from the outside, pro-
2 GND vided that the terminals of J10 are open, and no jumper
3 OW (DATA) is installed at JP5. J12 is intended for connecting a small
4 OW RTN circuit board with a 1-Wire slave. A 1-Wire slave in a
5 NC TO-92 or PR-35 package can directly be inserted at J13.
6 NC See Tables 11–14 for the respective pin assignments.
Besides JP7, the 1-Wire section includes the jumpers
Note: J11 has no printed pin 1 marker. Pin 1 is at the bottom.
The pin numbering is ascending from bottom to top. JP5, JP10, and JP11. JP5 must be populated with one

Table 13. J12 1-Wire Expansion Port Pin Table 14. J13 TO-92 Socket Pin
Assignments Assignments
PIN SIGNAL NAME PIN SIGNAL NAME
1 GND 1 GND
2 3V 2 OW
3 OW 3 GND

10   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

jumper to select either the PIC micro, or the FPGA or the points: TP4, TP12, and TP13. TP4 allows monitoring the
DS2482-100 as 1-Wire master. JP10 must be populated activity on the 1-Wire bus. TP12 and TP13 connect to a
to select the 1-Wire pullup voltage, which is typically 5V 10mI resistor in the VPUP path, which allows measuring
or 3.3V. JP11 is intended to select a user-programmable the load current. A voltage measurement of 10mV cor-
pullup voltage, which is controlled by U16, a digital-to- responds to a current load of 1mA.
analog converter in the I2C section. As a factory setting,
the JP11 location is not populated and the FIXED VPUP Setting the Jumpers
selection is hardwired by means of a short (R51). To
Power Supply
use adjustable VPUP, R51 must be removed and JP11
Jumpers must be installed according to the available
must be populated. For more details see the Setting
power source. See Figure 3.
the Jumpers section. The 1-Wire section has three test
FPGA Suspend Mode
The suspend mode, if enabled, reduces power consump-
USB JACK tion (Figure 4). Refer to XAPP480 for more information.

JP9 FPGA Initialization

In master-serial mode, the FPGA loads its configuration
USB (J1) SUPPLY from U12 (PROM). This setting is used for normal opera-
tion. In JTAG mode, the FPGA loads its configuration
from the JTAG interface J5. This setting is used for FPGA
USB JACK
program development. Configurations with only one
JP9
jumper (M0 or M2) installed are not valid. See Figure 5.
I2C Master Selection
EXTERNAL (J14) SUPPLY
Both jumpers must be installed as shown in Figure 6,
either to select the PIC or the FPGA.
Figure 3. JP9, Power Source Selection

JP1 JP1
JP3 JP3
3V 3V

PIC PIC
SUSPEND SUSPEND

SDA SDA
GND GND

FPGA FPGA
SUSPEND DISABLED SUSPEND ENABLED

Figure 4. JP1, Suspend Mode Selection

PIC PIC

M0 JB1 M0 JB1
SCL SCL

FPGA FPGA

JP2 JP2
M2 M2 PIC IS SELECTED FPGA IS SELECTED
MASTER SERIAL MODE JTAG MODE

Figure 5. JB1, FPGA Configuration Source Selection Figure 6. JP2, JP3, I2C Master Selection

Maxim Integrated   11

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

1-Wire Master Selection DS28E01 Access

With the DS2482-100 or an external master, the resistor To access the DS28E01, the jumper must be installed.
at J10 must be removed. See Figure 7. See Figure 10.
1-Wire Pullup Voltage Selection Adjustable 1-Wire Pullup Voltage
JP10 defines the 1-Wire pullup voltage unless adjustable JP11 is not factory installed. To use JP11, R51 must be
pullup voltage is selected. See Figure 8 for details. removed. See Figure 11.
1-Wire Strong Pullup Enable
Strong pullup must be enabled when using the PIC or
uP-OW
FPGA to operate 1-Wire slaves that temporarily enter a JP4
high-power mode. The DS2482-100 has a built-in strong
pullup, therefore, the strong pullup enable is optional.
See Figure 9.
FPGA
JP6

2482
JP8

STRONG PULLUP IS ENABLED FOR PIC AND FPGA

JP5 JP5
PIC IS SELECTED FPGA IS SELECTED Figure 9. JP4, JP6, JP8, 1-Wire Strong Pullup Enable

JP7 JP7

DS28E01 DS28E01
CONNECTED DISCONNECTED
JP5 JP5
DS2482-100 IS SELECTED EXTERNAL MASTER
Figure 10. JP7, DS28E01 Access
Figure 7. JP5, 1-Wire Master Selection

5V 5V FIXED FIXED

VPUP VPUP

3V 3V ADJ ADJ

JP11 JP11
JP10 JP10 FIXED VPUP ADJUSTABLE VPUP
VPUP = 5V VPUP = 3.3V

Figure 8. JP10, 1-Wire Pullup Voltage preselection Figure 11. JP11, Fixed vs. Adjustable 1-Wire Pullup Selection

12   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Supported Configurations Additional Applications of the

The challenge and response authentication can be Secure Authentication Starter Kit
implemented relying solely on the PIC or the FPGA. The
Using the PIC with RS-232
PIC can communicate to the FPGA by means of a 6-bit
A standard female DB9 connector (J2), along with a
address bus, 8-bit data bus, and control lines. This way
line transceiver/receiver (U2), provides an RS-232 serial
firmware in the PIC can offload some functions to the
connection to the demonstration board. This serial con-
FPGA. The FPGA can contain the DS1WM synthesizable
nection can be used by the programmer to develop
1-Wire bus master, the DSSHA1 processor together with
communication with WindowsM, LinuxM, and Mac OSM
the user’s FPGA design to create a custom security solu-
operating systems or other types of serial-capable host
tion. The SHA-1 computation can be performed by PIC
systems. This is one of the more traditional and usually
software, the FPGA (DSSHA1), or the DS2460 SHA-1
simpler ways of establishing communication to a serial-
coprocessor. The 1-Wire bus can be driven directly, i.e.,
capable host system. An additional advantage the serial
from the PIC, the FPGA (DS1WM), or the DS2482-100.
port provides is that most computers contain a terminal
The I2C bus can be driven by the PIC through its built-
program that supports communication to a serial port.
in I2C port or by the FPGA (I2CM). Table 15 shows the
In doing so, the developer can write his firmware in the
possible combinations supported by the secure authen-
PIC as to not need any software installed on computers
tication starter kit.
across many operating systems.

Table 15. Configurations Overview

HOST SHA-1 COMPUTATION BUS INTERFACE PATH TARGET SLAVE DEVICE
1-Wire
Software code (PIC) Direct
PIC Software code (PIC) DS28E01 (1-Wire)
or
alone I2C By DS2482-100
DS2460 (PIC I2C port)
(PIC I2C port) Direct DS28CN01 (I2C)
1-Wire
Software code (PIC) Software code (PIC)
PIC or or Direct
DS28E01 (1-Wire)
with DSSHA1 (Verilog, FPGA) DS1WM
FPGA or (VHDL/Verilog, FPGA)
DS2460 (PIC I2C port)
I2C By DS2482-100
(PIC I2C port) Direct DS28CN01 (I2C)
1-Wire
PicoBlaze™ ASM code PicoBlaze ASM code
(FPGA) (FPGA)
Direct
FPGA or or DS28E01 (1-Wire)
alone DSSHA1 (Verilog, FPGA) DS1WM
or (VHDL/Verilog, FPGA)
DS2460 (FPGA I2CM*) I2C By DS2482-100
I2CM* (VHDL, FPGA) Direct DS28CN01 (I2C)
*I2CM is in development.
Note: The board hardware supports all permutations indicated in Table 15. Some combinations are of more interest than others.
The example implementation in bold indicates PIC alone with SHA-1 computation in software using the I2C port of the PIC to com-
municate directly to the DS28CN01.

Windows is a registered trademark of Microsoft Corp.

Linux is a registered trademark of Linus Torvalds.
Mac OS is a registered trademark of Apple Inc.
PicoBlaze is a trademark of Xilinx, Inc.

Maxim Integrated   13

Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Using PIC with USB Port Changing the FPGA Configuration

In addition to the USB port (J1) being able to supply The Xilinx Spartan-3A FPGA is to be configured by the
power to the board, the USB port also connects to the JTAG port (J5). The JTAG port supports the HW-USB-II-G
PIC. The USB port can be used to develop USB-based (Platform Cable USB II) or other Xilinx cables to program
applications intended to interface with Windows OS, the FPGA directly or to program the available XCF04S
Linux, Mac OS, or other types of USB-capable host JTAG PROM. A 14-position, 2mm ribbon cable can be
systems. This is meant to be an alternative to using the connected from the HW-USB-II-G to the JTAG port.
serial connection and can be essential in today’s market The free software to perform the programming is inte-
as serial cable host systems continue to diminish and grated with the Xilinx ISEM WebPACKM software called
USB-capable host systems increases. Additionally, it is iMPACT. Refer to the Xilinx website for more information.
possible to develop a USB functional bootloader inside Figure 12 shows the actual JTAG chain. The FPGA or the
the PIC to provide field firmware updates as needed by JTAG PROM can be directly loaded in the chain. When
a company’s customer base. using the JTAG PROM, the user also needs to install
both jumpers located at JB1 for the FPGA to actually get
Debugging and Updating the PIC Firmware
loaded.
The PIC microcontroller can be debugged and updated
with firmware by the ICD port (J3). The ICD port supports
Microchip’s MPLABM ICD 3 In-Circuit Debugger with a
J5
PC that contains the MPLAB IDE software. By using this
U10 U12
ICD port, the programmer can load development code, 3.3V 2
set break points, step through code to verify correct TDO 8 FPGA JTAG PROM
operation, and test/erase firmware. TDI 10 TDI TDO TDI TDO
TMS 4
TMS TCK TMS TCK
TCK 6
GND

Figure 12. JTAG Chain Topology

MPLAB is a registered trademark of Microchip Technology Inc.

ISE and WebPACK are registered trademarks of Xilinx, Inc.

14   Maxim Integrated

 Secure Authentication Starter Kit
Evaluates: DS28E01/DS28CN01/DS2460

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/11 Initial release —

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licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.

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