DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

March 1989
Revised March 2000

DM9374
7-Segment Decoder/Driver/Latch
with Constant Current Sink Outputs
General Description
The DM74 is a 7-segment decoder driver incorporating
input latches and output circuits to directly drive common
anode LED displays.

Ordering Code:
Order Number Package Number Package Description
DM9374N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Logic Symbol

VCC = Pin 16
GND = Pin 8

Pin Descriptions
Pin
Description
Names
A0–A3 Address (Data Inputs)
LE Latch Enable Input (Active LOW)
RBI Ripple Blanking Input (Active LOW)
RBO Ripple Blanking as Output (Active LOW)
as Input (Active LOW)
a –g Constant Current Outputs (Active LOW)

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DM9374
Truth Table
Binary Inputs Outputs
Display
State LE RBI A3 A2 A1 A0 a b c d e f g RBO
— H (Note 1) X X X X STABLE H Stable
0 L L L L L L H H H H H H H L Blank
0 L H L L L L L L L L L L H H 0
1 L X L L L H H L L H H H H H 1

2 L X L L H L L L H L L H L H 2
3 L X L L H H L L L L H H L H 3
4 L X L H L L H L L H H L L H 4
5 L X L H L H L H L L H L L H 5

6 L X L H H L L H L L L L L H 6
7 L X L H H H L L L H H H H H 7
8 L X H L L L L L L L L L L H 8
9 L X H L L H L L L L H L L H 9
10 L X H L H L H H H H H H L H —

11 L X H L H H L H H L L L L H E
12 L X H H L L H L L H L L L H H
13 L X H H L H H H H L L L H H L
14 L X H H H L L L H H L L L H P
15 L X H H H H H H H H H H H H BLANK
X X X X X X X H H H H H H H L (Note 2) BLANK
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: The RBI will blank the display only if a binary zero is stored in the latches.
Note 2: RBO used as an input overrides all other input conditions.

Numerical Designations

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 DM9374
Functional Description
The DM9374 is a 7-segment decoder/driver with latches on eliminated. It also allows low strobing rates to be used with-
the address inputs and active LOW constant current out- out display flicker.
puts to drive LEDs directly. This device accepts a 4-bit Another DM9374 feature is the reduced loading on the
binary code and produces output drive to the appropriate data inputs when the Latch Enable is HIGH (only 10 µA
segments of the 7-segment display. It has a decode format typ). This allows many DM9374s to be driven from a MOS
which produces numeric codes “0” through “9” and other device in multiplex mode without the need for drivers on
codes. the data lines. The DM9374 also provides automatic blank-
Latches on the four data inputs are controlled by an active ing of the leading and/or trailing-edge zeroes in a multidigit
LOW Latch Enable, LE. When LE is LOW, the state of the decimal number, resulting in an easily readable decimal
outputs is determined by the input data. When LE goes display conforming to normal writing practice. In an 8-digit
HIGH, the last data present at the inputs is stored in the mixed integer fraction decimal representation, using the
latches and the outputs remain stable. The LE pulse width automatic blanking capability 0060.0300 would be dis-
necessary to accept and store data is typically 50 ns, which played as 60.03. Leading-edge zero suppression is
allows data to be strobed into the DM9374 at normal TTL obtained by connecting the Ripple Blanking Output (RBO)
speeds. This feature means that data can be routed of a decoder to the Ripple Blanking Input (RBI) of the next
directly from high speed counters and frequency dividers lower stage device. The most significant decoder stage
into the display without slowing down the system clock or should have the RIB input grounded; and since suppres-
providing intermediate data storage. sion of the least significant integer zero in a number is not
The latch/decoder combination is a simple system which usually desired, the RBI input of this decoder stage should
drives LED displays with multiplexed data inputs from MOS be left open. A similar procedure for the fractional part of a
time clocks, DVMs, calculator chips, etc. Data inputs are display will provide automatic suppression of trailing-edge
multiplexed while the displays are in static mode. This low- zeroes. The RBO terminal of the decoder can be OR-tied
ers component and insertion costs, since several circuits— with a modulating signal via an isolating buffer to achieve
seven resistors per display, strobe drivers, a separate dis- duration intensity modulation. A suitable signal can be gen-
play voltage source, and clock failure detect circuits—tradi- erated for this purpose by forming a variable frequency
tionally found in multiplexed display systems are multivibrator with a cross coupled pair of TTL or DTL gates.

Logic Diagram

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DM9374
Applications
It is possible with common anode 7-segment LED displays can maintain approximately 15 mA with as little as 0.5V
and constant current sink decoder drivers to save substan- across the output device. By using a separate power
tial amounts of power by carefully choosing operating source (VS, Figure 1) for the LEDs, which is set to the LED
points on display supply voltage. First, examine the power VF plus the offset voltage of the driver, as much as 280 mW
used in the normal display driving method where the dis- can be saved per digit. i.e.,
play and decoder driver are both operated from a +5.0V
VS = VF (Max) + Voffset
regulated supply (VCC = VS).
= 2.0V + 0.5V
The power dissipated by the LED and the driver outputs is
(VCC x Iseg x n Segments). The total power dissipated with = 2.5V
a 15 mA LED displaying an eight (8) would be: PT= 2.5V x 14 mA (from Figure 6) x 7
PTOT = 5.0V x 15 mA x 7 = 245 mW
= 525 mW These figures show that using a separate supply to drive
Of this 525 mW, the power actually required to drive the the LEDs can offer significant display power savings. In
LED is dependent on the VF drop of each segment. Most battery powered equipment, two rechargeable nickel-cad-
mium cells in series would be sufficient to drive the display,
GaAsP LEDs exhibit either a 1.7V or a 3.4V forward volt-
while four such cells would be needed to operate the logic
age drop. Therefore, the required total power for seven
units.
segments would be:
Another method to save power is to apply intensity modula-
P(1.7) = 1.7V x 15 mA x 7
tion to the displays (Figure 2). It is well known that LED dis-
= 178.5 mW plays are more efficient when operated in pulse mode.
P(3.4)= 3.4V x 15 mA x 7 There are two reasons: one, the quantum efficiency of the
LED material is better; secondly the eye tends to peak
= 357 mW
detect. Typically a 20% off duty cycle to displays (GaAsP)
The remaining power is dissipated by the driver outputs will produce the same brightness as operating under dc
which are maintaining the 15 mA constant current required conditions.
by the LEDs. Most of this power is wasted, since the driver

FIGURE 1. Separate Supply for LED Displays

All Inverters are DTL 9936 or Open Collector TTL 7405

FIGURE 2. Intensity Control by RBO Pulse Duty Cycle

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 DM9374
Low Power, Low Cost Display Power Sources—In small Full Wave Center Tapped Rectifier Circuit
line operated systems using TTL/MSI and LED or incan- Transformer rms current = 1.2 x dc current required
descent displays, a significant portion of the total dc power
Therefore, the removal of a large portion of the filtered dc
is consumed to drive the displays. Since it is irrelevant
current requirement (display power) substantially reduces
whether displays are driven from unfiltered dc or pulsed dc
the transformer loading.
(at fast rates), a dual power system can be used that
makes better utilization of transformer rms ratings. The There are two basic approaches. First (Figure 3) is the
system utilizes a full wave rectified but unsmoothed dc volt- direct full wave rectified unregulated supply to power the
age to provide the displays with 120 Hz pulsed power while displays. The '74 decoder driver constant current feature
the reset of the system is driven by a conventional dc maintains the specified segment current after the LED
power circuit. The frequency of 120 Hz is high enough to diode drop and 0.5V saturation voltage has been reached
avoid display flicker problems. The main advantages of this (≅2.2V). Care must be exercised not to exceed the '74
system are: power ratings and the maximum voltage that the decoder
driver sees in both the “on” and “off” modes.
• Reduced transformer rating
The second approach (Figure 4) uses a 3-terminal voltage
• Much smaller smoothing capacitor
regulator such as the 7805 to provide dc pulsed power to
• Increased LED light output due to pulsed operation the display with the peak dc voltage limited to +5.0V. This
With the standard capacitor filter circuit, the rms current approach allows easier system thermal management by
(full wave) loading of the transformer is approximately heat sinking the regulator rather than the display or display
twice the dc output. Most commercial transformer manu- drivers. When this power source is used with an intensity
facturers rate transformers with capacitive input filters as modulation scheme or with a multiplexed display system,
follows: the frequencies must be chosen such that they do not beat
Full Wave Bridge Rectifier Circuit with the 120 Hz full wave rectified power frequency.
Transformer rms current = 1.8 x dc current required

FIGURE 3. Direct Unregulated Display Supply

FIGURE 4. Pulsed Regulated Display Supply

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DM9374
Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 5.5V Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VOUT Output Voltage Applied OFF 10 V
ON (Figure 5)
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current, a–g, VOUT = 5.5V 250 µA
IOL LOW Level Output Current, a–g, VOL = 3.0V 12 18 mA
TA Free Air Operating Temperature 0 70 °C
tS (H) Setup Time HIGH or LOW 75
ns
tS (L) An to LE 30
tH (H) Hold Time HIGH or LOW 0
ns
tH (L) An to LE 0
tW (L) LE Pulse Width LOW 85 ns

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 4)
VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V
VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max 2.4 3.4 V
VOL LOW Level Output Voltage VCC = Min, IOL = Max, VIH = Min 0.2 0.4 V
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA
IOS Short Circuit Output Current VCC = Max (Note 5) −18 −57 mA
ICCH Supply Current VCC = Max, VIN = 0V,
50 mA
VOUT = 3.0V
Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time.

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 DM9374
Switching Characteristics
VCC = +5.0V, TA = +25°C
CL = 15 pF
Symbol Parameter RL = 1 kΩ Units
Min Max
tPLH Propagation Delay 140
ns
tPHL An to a–g 140
tPLH Propagation Delay 140
ns
tPHL LE to a–g 140

Typical Performance Characteristics

FIGURE 5. Output Voltage Safe Operating Area FIGURE 6. Typical Constant Segment Current
Versus Output Voltage

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DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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