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GATE SOLVED PAPER

Instrumentation Engineering
Analog electronics

Copyright © By NODIA & COMPANY

Information contained in this book has been obtained by authors, from sources believes to be reliable. However,
neither Nodia nor its authors guarantee the accuracy or completeness of any information herein, and Nodia nor its
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Ph : +91 - 141 - 2101150
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 GATE SOLVED PAPER - IN
ANALOG ELECTRONICS

YEAR 2012 ONE MARK

Q. 1 The i -v characteristics of the diode in the circuit given below are :

v - 0.7 A v $ 0.7 V
i = * 500
0 A, v < 0.7 V
The current in the circuit is

. i n
c o
(A) 10 mA

a .
(B) 9.3 mA

i
(C) 6.67 mA (D) 6.2 mA

YEAR 2012
o d TWO MARKS

Q. 2

.n
The voltage gain Av of the circuit shown below is

w
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©

(A) Av . 200 (B) Av . 100

(C) Av . 20 (D) Av . 10

Q. 3 The circuit shown is a

GATE SOLVED PAPER - IN ANALOG ELECTRONICS

(A) low pass filter with f 3 dB = 1 rad/s

^R1 + R2h C

(B) high pass filter with f 3 dB = 1 rad/s

R1 C

(C) low pass filter with f 3 dB = 1 rad/s

R1 C

(D) high pass filter with f 3 dB = 1 rad/s

^R1 + R2h C

YEAR 2011 ONE MARK

n
Q. 4 The amplifier shown below has a voltage gain of - 2.5 , an input resistance of

. i
10 kW, and a lower 3-dB cut-off frequency of 20 Hz. Which one of the following

o
statements is TRUE when the emitter resistance RE is doubled ?

. c
i a
o d
.n
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w
(A) Magnitude of voltage gain will decrease
(B) Input resistance will decrease

w
(C) Collector bias current will increase

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(D) Lower 3-dB cut-off frequency will increase

YEAR 2011 TWO MARKS

Q. 5 Assuming base-emitter voltage of 0.7 V and b = 99 of transistor Q1 , the output

voltage Vo in the ideal opamp circuit shown below is

(A) - 1 V (B) - 1/3.3 V

(C) 0 V (D) 2 V
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 6 Assuming zener diode D1 has current-voltage characteristics as shown below of

the right and forward voltage drop of diode D2 is 0.7 V, the voltage Vo in the
circuit shown below is

(A) 3.7 V (B) 2.7 V

(C) 2.2 V (D) 0 V

Q. 7 The value of Vo of the series regulator shown below is

. in
c o
a .
i
od
(A) 24 V (B) 28 V
(C) 30 V (D) 32 V

.n
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Q. 8 The ideal opamp based circuit shown below acts as a

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©

(A) low-pass filter (B) high-pass filter

(C) band-pass filter (D) band-reject filter

Common Data For Questions 9 and 10 :

M1 , M2 and M 3 in the circuit shown below are matched N-channel enhancement
mode MOSFETs operating in saturation mode, forward voltage drop of each
diode is 0.7 V, reverse leakage current of each diode is negligible and the opamp
is ideal.
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 9 The current Is in the circuit is

(A) - 1 mA (B) 0.5 mA
(C) 1 mA (D) 2 mA

n
For the computed value of current Is , the output voltage Vo is

i
Q. 10

.
(A) 1.2 V (B) 0.7 V

o
(C) 0.2 V (D) - 0.7 V

c
i a.
YEAR 2010 ONE MARK

d
Q. 11 In the ideal op-amp circuit given in the adjoining figure, the value of R f is varied

o
from 1 kW to 100 kW. The gain G = bV0 l will

.n
Vi

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(A) remain constant at + 1
(C) vary as (R f /10, 000)
(B) remain constant at - 1
(D) vary as (1 + R f /10, 000)

YEAR 2010 TWO MARKS

Q. 12 The matched transistors Q1 and Q2 shown in the adjoining figure have b = 100.
Assuming the base-emitter voltages to be 0.7 V, the collector-emitter voltage V2
of the transistors Q2 is

(A) 33.9 V (B) 27.8 V

(C) 16.2 V (D) 0.7 V
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 13 An active filter is shown in the adjoining figure. The dc gain and the 3 dB cut-off
frequency of the filter respectively, are, nearly

R1 = 15.9kW, R2 = 159 kW, C1 = 1.0nF

(A) 40 dB, 3,14 kHz (B) 40 dB, 1.00 kHz
(C) 20 dB, 6.28 kHz (D) 20 dB, 1.00 kHz

Common Data For Questions 14 and 15 :

A differential amplifier is constructed using an ideal op-amp as shown in the

in
adjoining figure. The values of R1 and R2 are 47 kW and 470kW respectively.

o.
. c
i a
o d
. n
w
w
Q. 14 The input impedances seen looking into the terminals V1 and V2 with respect to
ground, respectively are

w
(A) 47 kW 43 kW (B) 47 kW and 47 kW

©
(C) 47 kW and 51 kW (D) 517 kW and 517 kW

Q. 15 V1 and V2 are connected to voltage sources having an open circuit of + 1V each

and internal resistances of 13 kW and 3 kW respectively. The output voltage V0 is
(A) 0 V (B) 0.15 V
(C) 1.5 V (D) 10 V

YEAR 2009 ONE MARK

Q. 16 The circuit shown in the figure is

GATE SOLVED PAPER - IN ANALOG ELECTRONICS

(A) an all-pass filter (B) a band-pass filter

(C) a high-pass filter (D) a low-pass filter

YEAR 2009 TWO MARKS

Q. 17 In the circuit shown, the Zener diode has ideal characteristics and a breakdown
voltage of 3.2 V. The output voltage V0 for an input voltage Vi =+ 1V is closed to

. i n
o
(A) - 10 V (B) - 6.6 V

c
(C) - 5 V (D) - 3.2 V

a .
i
Q. 18 The input resistance of the circuit shown in the figure assuming an ideal op-amp,
is

o d
.n
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(A) R/3 (B) 2R/3
(C) R (D) 4R/3

Q. 19 In the circuit shown in the figure, the switch S has been in Position 1 for a long
time. It is then moved to Position 2. Assume the Zener diodes to be idea. The
time delay between the switch moving to position 2 and the transition in the
output voltage V0 is

(A) 5.00 ms (B) 8.75 ms

(C) 10.00 ms (D) 13.75 ms
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Common Data For Questions 20 and 21 :

The figure shows a sample-and-hold circuit using a MOSFET as a switch. The
threshold voltage of the MOSFET as a switch. The threshold voltage of the
MOSFET is + 2 V. It has zero leakage current in the off state. Assume that the
capacitor is ideal.

Q. 20 The input voltage Vi ranges from - 5 V to + 5 V. Appropriate values of Vsub , of

Vg during hold are, respectively,
(A) + 12V $ + 7V and # - 3V (B) - 12V, $ + 3V, and # - 7V
(C) + 12V, $ + 3V and # - 7V (D) - 12V, $ + 7V, and # - 3V

Q. 21

. in
The circuit is used at a sampling rate of 1 kHz, with an A/D converter having a

o
conversion time of 200 ms. The op-amp has an input bias current of 10 nA. The

c
maximum hold error is
(A) 1 mV

a . (B) 2 mV

i
(C) 5 mV (D) 10 mV

o d
n
Common Data For Questions 22 and 23 :

.
The circuit shown in the figure uses three identical transistors with VBE = 0.7 V

w
and b = 100 . Given R1 = R2 = R 3 = 1kW, kT/qe = 25mV

w
.The collector current of transistor Q 3 is 2 mA.

w
©

Q. 22 The bias Voltage VB at the base of the transistor Q 3 is approximately

(A) - 9.3 V (B) - 10.0 V
(C) - 10.3 V (D) - 11.0 V

Q. 23 The small signal voltage gain of the circuit is

(A) - 20 (B) - 40
(C) 20 (D) 40
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

YEAR 2008 ONE MARK

Q. 24 For a single BJT common base amplifier

(A) Current gain as well as voltage gain can be greater than unity
(B) Current gain can be greater than unity but voltage gain is always < unity.
(C) Voltage gain can be greater than unity but current gain is always < unity
(D) Current gain as well as voltage gain is always less than unity.

Q. 25 In the circuit shown below, the ideality factor h of the diode is unity and the
voltage drop across it is 0.7 V. The dynamic resistance of the diode at room
temperature is approximately

. i n
o
(A) 15 W (B) 25 W

. c
(C) 50 W (D) 700 W

i a
An ideal op-amp has the characteristics of an ideal
Q. 26

d
(A) Voltage controlled voltage source (B) Voltage controlled current source

o
(C) Current controlled voltage sourec (D) Current controlled current source

.n
w
YEAR 2008 TWO MARKS

w
Q. 27 A differential amplifier shown below has a differential mode gain of 100 and a
CMRR of 40 dB. If V1 = 0.55 and V2 = 0.45 V, the output V0 is

w
©
(A) 10 V (B) 10.5 V
(C) 11 V (D) 15 V

Q. 28 The op-amp circuit shown below is that of a

(A) low-pass filter with a maximum gain of 1

(B) low-pass filter with a maximum, gain of 2
(C) high-pass filter with a maximum gain of 1
(D) high-pass filter with a maximum gain of 2
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 29 In the op-amp circuit shown below is that of Vin is gradually increased from - 10
V to + 10 V. Assuming that the output voltage Vout saturates at - 10 V and + 10
V, Vout will change from

(A) - 10V to + 10V when Vin =- 1V (B) - 10V to + 10V when Vin =+ 1V
(C) + 10V to - 10V when Vin =- 1V (D) + 10 V to - 10 V when Vin =+ 1 V

Q. 30 For the op-amp circuit shown below V0 is approximately equal to

. in
c o
a .
d i
n o
.
w
(A) - 10 V
w (B) - 5 V

w
(C) + 5 V (D) + 10 V

©
Q. 31 In the amplifier circuit shown below, assume VBE = 0.7 V and the b of the transistor
and the values of C1 and C2 are extremely high. If the amplifier is designed such
that at the quiescent point its VCE = VCC , When VCC is the power supply voltage,
2
its small signal voltage gain Vout will be
Vin
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

(A) 3.75 (B) 4.5

(C) 9 (D) 19

YEAR 2007 ONE MARK

Q. 32 When the light falls on the photodiode shown in the following circuit, the reverse
saturation current of the photodiode changes form 100 mA to 200 mA .

. i n
o
Assuming the op-amp to be ideal, the output voltage, Vout of the circuit.

c
(A) does not change (B) changes from 1 V to 2 V
(C) changes from 2 V to 1 V

a . (D) changes from - 1V to - 2 V

Q. 33

d i
A 555 astable multi-vibrator circuit is shown in the figure below :

o
.n
w
w
w
©
If RB is shorted, the waveform at VC is
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

YEAR 2007 TWO MARKS

Q. 34 Consider the linear circuit with and ideal op-amp shown in the figure below.

The Z-parameters of the two port feedback network are Z11 = Z22 = 11kW and
Z12 = Z21 = 1kW . The gain of the amplifier is
(A) + 110 (B) + 11
(C) - 1 (D) - 120

. in
Q. 35 A FET source follower is shown in the figure below :

c o
a .
d i
n o
.
w
The nature of feedback in the this circuit is

w
(A) positive current (B) negative current

w
(C) positive voltage (D) negative voltage

Q. 36
©
In the circuit shown below, VBE = 0.7 V

The b of the transistor and VCE are respectively

(A) 19 and 2.8 V (B) 19 and 4.7 V
(C) 38 and 2.8 V (D) 38 and 4.7 V
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 37 The figure shows a single op-amp differential amplifier circuit.

Which one of the following statements about the output is correct ?

(A) V0 # 95 mV (B) 95 m V < V0 # 98 mV
(C) 98 mV < V0 # 101 mV (D) V0 > 101 mV

i n
Q. 38 The three transistors in the circuit shown below are identical, with

.
VBE = 0.7 V and b = 100 .

c o
a .
d i
o
.n
The voltage Vc is
w
w
(A) 0.2 V (B) 2 V

w
(C) 7.4 V (D) 10 V

©
Q. 39 The input signal shown in the figure below is fed to a Schmitt trigger. The signal
has a square wave amplitude of 6 V p-p. It is corrupted by an additive by an
additive high frequency noise of amplitude 8V p-p.

Which one of the following is an appropriate choice for the upper and lower trip
points of the Schmitt trigger to recover a square wave of the same frequency from
the corrupted input signal Vi ?
(A) !8.0 V (B) !2.0 V
(C) !0.5 V (D) 0 V
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 40 Consider the circuit shown below

The correct frequency response of the circuit is

. in
c o
a .
d i
n o
.
w
w
w
Q. 41
©
In the circuit shown below the switch (S) is closed whenever the input voltage (
Vin ) is positive and open otherwise.

The circuit is a
(A) Low pass filter (B) Level shifter
(C) Modulator (D) Precision rectifier
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 42 Consider the triangular wave generator shown below.

Assume that the op-amps are idea and have !12 V power supply. If the input
is a !5V 50 Hz square wave of duty cycle 50%, the condition that results in a
triangular wave of peak to peak amplitude 5 V and frequency 50 Hz at the output
is
(A) RC = 1 (B) R = 1
C
(C) R
C
=5
R
. i
(D) C = 5
n
c o
Common Data For Questions 43, 44 and 45 :

a .
i
Consider the op-amp circuit shown in the figure below.

o d
.n
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Q. 43
©
If V1 = 0.2 V, V2 = 0.6 V and V0 =- 7 V , and the op-amp is ideal, the value of
R1 is
(A) 5 kW (B) 10 kW
(C) 15 kW (D) 20 kW

Q. 44 Let V1 = V2 = Vc sin2pft and R1 = 20 kW . The op-amp has a slew rate of 0.5 V/

ms with its other parameter being idea. The values of Vc and f for which the
amplifier output will have not distortion are, respectively
(A) 0.1 V and 300 kHz (B) 0.5 V and 300 kHz
(C) 0.1 V and 300 kHz (D) 0.5 V and 30 kHz

Q. 45 Let V1 = V2 = 0 and R1 = 20 kW . Assume that the op-amp is ideal except for a

non-zero input bias current. What is the value of R2 for the output voltage of the
op-amp to be zero ?
(A) 2.2 kW (B) 9.1 kW
(C) 20 kW (D) 100 kW
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

YEAR 2006 ONE MARK

Q. 46 If the value of the resistance R in the following figure is increased by 50%, then
voltage gain of the amplifier shown in the figure will change by.

(A) 50 % (B) 5%
(C) - 50 % (D) Negligible amount

Q. 47 When the switch S2 is closed the gain of the programmable gain amplifier shown
in the following figure is

. in
c o
a .
d i
n o
.
w
(A) 0.5
w (B) 2
(C) 4
w (D) 8

©
YEAR 2006 TWO MARKS

Q. 48 In the circuit shown in the following figure, the op-amp has input bias current
Ib < 10 nA , and input offset voltage Vio < 1. The maximum dc error in the output
voltage is

(A) 1.0 mV (B) 2.0 mV

(C) 2.5 mV (D) 3.0 mV
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 49 The potential difference between the input terminals of an op amp may be treated
to be nearly zero, if
(A) the two supply voltages are balanced
(B) The output voltage is not saturated
(C) the op-amp is used in a circuit having negative feedback
(D) there is a dc bias path between each of the input terminals and the circuit
ground

Q. 50 A dual op-amp instrumentation amplifier is shown below. The expression for the
output of the amplifier is given by.

. i n
c o
a .
d i
(A) v0 = c1 + R2 m (v2 - v1)
o (B) v0 = c1 + 2R2 m (v2 - v1)

.n
R1 R1

w
(C) v0 = 2R2 (v2 - v1) (D) v0 = c1 + 2R1 m (v2 - v1)

w
R1 R2

w
©
Q. 51 An amplifier circuit is shown below. Assume that the transistor works in
active region. The low frequency small-signal parameters for the transistor are
gm = 20 mS, b 0 = 50, r 0 = 3, r b = 0 . What is the voltage gain, AV = ` v0 j , of the
vi
amplifier ?

(A) 0.967 (B) 0.976

(C) 0.983 (D) 0.998
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 52 The biasing circuit of a silicon transistor is shown below. If b = 80, then what is
VCE for the transistor ?

(A) - 6.08 V (B) 0.2 V

(C) 1.2 V (D) 6.08 V

Q. 53 An astable multi-vibrator circuit using a 555 IC is given in the following figure.

The frequency of oscillation is.

. in
c o
a .
d i
n o
.
w
w
w
(A) 20 kHz (B) 30 kHz
(C) 40 kHz (D) 45 kHz

©
Statement For Linked Answer Q. 54 and 55 :
In the Schmitt trigger circuit shown below, the Zener diodes have VZ (reverse
saturation voltage) = 6 V and VD (forward voltage drop) = 0.7 V.
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 54 If the circuit has the input lower trip point (LTP) = 0 V, then value of R1 is
R2
given as.
(A) 0.223 (B) 2.67
(C) 4.67 (D) 3

Q. 55 The input upper trip point (UTP) of the Schmitt trigger is

(A) 1.5 V (B) 2.1 V
(C) 2.42 V (D) 6.7 V

YEAR 2005 ONE MARK

Q. 56 The peak value of the output voltage V0 across the capacitor shown in the figure
for a 2230:9 transformer and a 230 V, 50 Hz, input assuming 0.7 V diode drop

n
and an ideal transformer, is

. i
c o
a .
d i
o
.n
(A) 12.73 (B) 11.33

w
(C) 7.6 (D) 9.0

w
w
Q. 57 In the circuit shown in the given figure the input voltage Vin (t) is given by 2
sin (100pt). For RL in the range 0.5 kW to 1.5 kW to 1.5 kW, the current through

©
RL is.

(A) + 2 sin (100pt) mA (B) - 2 sin (100pt) mA

(C) + 0.5 sin (100pt) mA (D) 1.5 sin (100pt) mA

YEAR 2005 TWO MARKS

Q. 58 The input-output charcteristic of a Schmidt trigger has a hysteresis band of

! 0.1 V . If the input voltage is 5 sin (100pt), the delay between the corresponding
zero cross-over points of the output and input signals is
(A) 6.37 ms (B) 0.02 ms
(C) 63.7 ms (D) 2.0 ms
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 59 In the circuit shown in the figure the input voltage Vi is a symmetrical saw-tooth
wave of average value zero, positive slope and peak-to-peak value 20 V. The
average value of the output, assuming an ideal operational amplifier with peak-
to-peak symmetrical swing of 30 V, is

(A) 5 V (B) 10 V
(C) - 5 V (D) 7.5 V

Q. 60 In the instrumentation amplifier shown in the figure if the switch SW is changed

form position A to B, the values of the amplifier gain G before and after changing
the switch respectively are

. in
c o
a .
d i
n o
.
w
w
(A) 45, 95
w (B) 50, 100

©
(C) 100, 200 (D) 90, 180

Q. 61 Figure shows a circuit which has a coil of resistance R and inductance L. At

resonance, the Q-factor of the coil is given by

(A) bV - V0 l (B) V0
V V

(C) bV - V0 l (D) V
V0 V0
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 62 For the circuit shown in the figure, IDSQ (in mA) and VGSQ (in V) are related
through 2 IDSQ = (4 + VGSQ) 2 .
The following data is given :
VDD = 15 V, R1 = 1.0 MW, R2 = 6.5 MW, RD = 2.0 kW, RS = 1.0 kW,
IDSS = 8 mA. The value of IDSQ, assuming the gate current is negligible, is
approximately equal to.

. i n
c o
.
(A) 5 mA (B) 2.0 nA

a
(C) 2.3 mA (D) 3.4 mA

Q. 63

d i
In the circuit shown in the figure, assuming ideal diose characteristics with zero

o
forward resistance and 0.7 V forward drop, the average value of V0 when the input

.n
waveform is as shown, is

w
w
w
©
(A) - 0.7 V (B) - 1.0 V
(C) - 2.0 V (D) - 2.7 V

Q. 64 For the RC circuit shown in the figure, the condition for obtaining an attenuation,
Vout Vin , of 1/3 at a frequency w rad/s is

(A) 3wCR 1 = 0 (B) 2wCR - 1 = 0

(C) 3wCR - 2 = 0 (D) wCR - 1 = 0
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Statement For Linked Answer Q. 65 and 66 :

Given figure shows a transistor circuit with feedback

Q. 65 In the circuit, in order to get V0 in the range of 0-30 V, the range of Vin is
(A) 0-30 V (B) 0.20 V
(C) 0-15 V (D) 1.10 V

in
Q. 66 If Vin is generated using an n -bit DA converter, the minimum value of n required,

.
so that the value of V0 can be set with in an accuracy of less than 20 mV is,

o
(A) 9 (B) 10

c
(C) 11 (D) 12

a .
YEAR 2004

d i ONE MARK

o
Q. 67 Assuming ideal diode characteristics, the input/output voltage relationship for

n
the circuit shown in Fig. is

.
w
w
w
©
(A) v0 (t) = vi (t), for all vi (t) (B) v0 (t) = vi (t), for vi (t) vR
= 0, otherwise
(C) v0 (t) = vi (t), for vi (t), for vi (t) < vR (D) v0 (t) = vi (t), for vi (t) > vR
= vR, otherwise = vR, otherwise
Q. 68 The output of the op-amp in the circuit of Fig. is

(A) 0 V (B) - 3 V
(C) + 1.5 V (D) + 3 V
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 69 The device shown in Fig is a

(A) Variac (B) Triac

(C) Quadrac (D) Diac

YEAR 2004 TWO MARKS

Q. 70 The parameters of the JEET in Fig. gm = 1 mA/V , rd = 15 kW Neglecting the

effect of the capacitor of A.C. analysis, the small signal A.C. voltage gain for the
circuit is.

. i n
c o
a .
d i
o
(A) - 30 (B) - 10

.n
(C) + 40 (D) + 60

w
Q. 71 The value of V0 in the circuit, shown in Fig. is

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w
©
(A) - 5 V (B) - 3 V
(C) + 3 V (D) + 5 V

Q. 72 The gain ` v0 j of the amplifier circuit shown in Fig. is

vi

(A) 8 (B) 4
(C) - 4 (D) 3RL
R
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 73 The output voltage v0 in the circuit in Fig. is

(A) R2 Vd (B) R2 Vd
R R1
(C) R2 V (D) R2 V
R1 d R (1 + d)
Q. 74 V1 and V2 are the input voltages of an instrumentation amplifier. The output of the
instrumentation amplifier is found to be 100 (V1 - V2) +10 - 4 (V1 + V2). The gain
and the common mode rejection ratio (CMRR) of the instrumentation amplifier
respectively are

in
(A) (50, 60 dB) (B) (50 120 dB)
(C) (100, 60 dB)

o.
(D) (100, 120 dB)

. c
Q. 75 The circuit in Fig. is a

i a
o d
. n
w
w
(A) Band-pass filter with lower cut-off wl = 1 and higher cut off w = 1
H
R1 C1 R2 C2

w
(B) Band-reject filter with lower cut-off w1 = 1
R1 C1
and higher cut off wH = 1
R2 C2

©
(C) Band-pass filter with lower cut-off wl = 1 and higher cut off wH = 1
R2 C2
1
R1 C1
(D) Band-reject filter with lower cut-off wl = and higher cut off
1 R2 C2
wH =
R1 C1

Q. 76 For the circuit shown in Fig. the diode D is ideal. The power dissipated by the
300 W resistor is

(A) 0.25 W (B) 0.50 W

(C) 0.75 W (D) 1.00 W
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 77 Fig (a) shows a Schwitt trigger circuit and Fig (b) the corresponding hysteresis
characteristics. The values of VTL and VTH are

(A) VTL =- 3.75,VTH =+ 3.75 V (B) VTL =- 1 V, VTH =+ 5 V

(C) VTL =- 5 V,VTH =+ 1 V

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(D) VTL =- 5 V, VTH =+ 5 V

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YEAR 2003

a . ONE MARK

Q. 78

d i
An integrator circuit is shown in Fig. The op-amp is of type 741 and has an input
offset current ios of 1 mA and R is 1 MW. If the input Vi is a 1 kHz square wave of

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1 V peak to peak, the output V0 , under steady state condition, will be.

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(A) A square wave of 1 V peak to peak
(B) A triangular wave of 1 V peak to peak
(C) Positive supply voltage + Vcc
(D) Negative supply voltage - Vcc

Q. 79 The output of an op-amp whose input is a 2.5 MHz square wave is shown in Fig.
The slew rate of the op-amp is

(A) 0.8 V/ms (B) 8.0 V/ms

(C) 20.0 V/ms (D) 40.0 V/ms
GATE SOLVED PAPER - IN ANALOG ELECTRONICS

Q. 80 The op-amp and the 1 mA current source in the circuit of Fig. are ideal. The
output of the op-amp is

(A) - 1.5 mA (B) - 1.5 V

(C) - 7.5 V (D) + 1.5 V

YEAR 2003 TWO MARKS

Q. 81 A forward-biased silicon diode when carry negligible current, has a voltage drop
of 0.64 V. When the current is 1 A it dissipates 1 W. The ON-resistance of the

in
diode is

.
(A) 0.36 W (B) 0.64 W

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(C) 0.72 W (D) 1.0 W

Q. 82

. c
A transistor amplifier circuit is shown in Fig. The quescent collector current,

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rounded off to first decimal, is

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(A) 2.6 mA (B) 2.3 mA
(C) 2.1 mA (D) 2.0 mA

Q. 83 The op-amp used in the inverting amplifier shown in Fig. has an equivalent input
offset voltage Vios of 5 mV. The output offset voltage is.

(A) 5 mV (B) 280 mV

(C) 285 mV (D) 560 mV
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Q. 84 In the circuit shown in Fig. the op-amps used are ideal. The output V0 is

(A) 3.0 V (B) 1.5 V

(C) 1.0 V (D) 0.5 V

Q. 85 A 50 W power amplifier has a rated output of 30 Vr.m.s and a voltage gain of 40

dB. It is connected to a 40 W loudspeaker having an internal resistance of 10W.

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Determine the maximum input voltage that can be given to the power amplifier

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so that neither the power amplifier nor the loudspeaker is overloaded.
(A) 40 V
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(B) 20 V

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(C) 0.4 V (D) 0.2 V

Q. 86

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The circuit shown in Fig. is that of a waveform generator. Assuming ideal devices

d
and !12 V supply, the output V0 is a

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(A) Triangular wave of period 120 ms and amplitude !6 V
(B) Square wave of period 60 ms and amplitude !6 V
(C) Square wave of period 120 ms and amplitude !6 V
(D) Square wave of period 60 ms and amplitude !12 V

Q. 87 The 5 V Zener diode in figure is ideal and the ammeter (A), of full-scale 1 mA,
has an internal resistance of 100W. The circuit shown, with terminal 1 positive,
functions as a

(A) 0 - 1 VDC voltmeter (B) 0 - 1 mA DC ammeter

(C) 0 - 6 VDC voltmeter (D) 0 - 5 VAC voltmeter
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YEAR 2002 TWO MARKS

Q. 88 A unity gain buffer amplifier has a bandwidth of 1 MHz . The output voltage of
the amplifier for an input of 2 V sinusoid of frequency 1 MHz will be
(A) 2 V (B) 2 2 V
(C) 2 V (D) 4 V
2 2
Q. 89 An amplifier of gain 10, with a gain-bandwidth product of 1 MHz and slew rate
of 0.1 V/ms is fed with a 10 kHz symmetrical square wave of ! 1 V amplitude. Its
output will be
(A) ! 10 V amplitude square wave (B) ! 2.5 V amplitude square wave
(C) ! 10 V amplitude triangular wave (D) ! 2.5 V amplitude triangular wave

YEAR 2001 ONE MARK

Q. 90 A sample and hold circuit has two buffers, one at the input and the other at the
output. The primary requirements for the buffers are
(A) The input buffer should have high slew rate and the output buffer should

in
have low bias current

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(B) the input buffer should have low bias current and the output buffer should

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have high slew rate

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(C) both the buffers should have low bias currents

a
(D) both the buffers should have high slew rate

Q. 91

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A twisted pair of wires is used for connecting the signal source with the

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instrumentation amplifier, as it helps reducing

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(A) the effect of external interference

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(B) the error due to bias currents in the amplifier

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(C) the loading of the source by the amplifier

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(D) the common mode voltage

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YEAR 2001 TWO MARKS

Q. 92 For an input V ^ t h = 5 - 2 sin ^100 pt h - cos ^200 pt h the output of a full-wave

rectifier average is
(A) 2 (B) 4
(C) 5 (D) 8

Q. 93 In figure, input offset voltage of the operational amplifier is 2 mV . The output

DC error voltage is
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(A) 0 mV (B) 2 mV
(C) 11 mV (D) 22 mV

YEAR 2000 ONE MARK

Q. 94 An op-amp with a slew rate of 1 mVs has been used to build an amplifier of gain
+ 10 . If the input to the amplifier is a sinusoidal voltage with peak amplitude of
1 V , the maximum allowable frequency of the input signal for undistorted output
is
(A) 830 Hz (B) 15.92 kHz
(C) 31.84 kHz (D) 1.0 MHz

Q. 95 For a sinusoidal input of 50 V amplitude, the circuit shown in figure can be used
as

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(A) regulated DC power supply (B) square-wave generator

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(C) half-wave rectifier (D) full-wave rectifier

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Q. 96 In the DC millivoltmeter circuit shown in figure, the input voltage for full scale

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deflection is

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(A) 10 V (B) 1 V
(C) 100 mV (D) 10 mV

YEAR 2000 TWO MARKS

Q. 97 If both the junctions of a transistor are forward biased, it will be in

(A) saturation mode (B) active mode
(C) cut-ff mod (D) inversion mode

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ANSWER KEY
ANALOG ELECTRONICS
1 2 3 4 5 6 7 8 9 10
(D) (D) (B) (A) (C) (C) (C) (A) (B) (A)
11 12 13 14 15 16 17 18 19 20
(A) (B) (D) (C) (B) (A) (B) (A) (B) (D)
21 22 23 24 25 26 27 28 29 30
(C) (A) (C) (C) (B) (A) (B) (D) (D) (B)
31 32 33 34 35 36 37 38 39 40
(C) (B) (A) (D) (D) (A) (B) (C) (B) (C)
41 42 43 44 45 46 47 48 49 50
(D) (B) (B) (C) (B) (D) (B) (D) (C) (A)
51 52 53 54 55 56 57 58 59 60
(A) (B) (C) (C) (C) (B) (A) (A) (D) (C)

in
61 62 63 64 65 66 67 68 69 70

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(B) (D) (B) (D) (D) (C) (D) (A) (B) (B)

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71 72 73 74 75 76 77 78 79 80

c
a.
(A) (A) (B) (D) (A) (C) (D) (D) (D) (B)

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81 82 83 84 85 86 87 88 89 90

d
(A) (B) (C) (B) (D) (C) (C) (C) (D) (A)

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91 92 93 94 95 96 97

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(A) (C) (B) (B) (B) (D) (A)

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