Use of Spread Spectrum Time Domain Reflectometry

to Estimate State of Health of Power Converters

M. Sultana Nasrin and Faisal H. Khan

Power Engineering and Automation Research Lab (PEARL)
Dept. of Electrical and Computer Engineering
University of Utah
Salt Lake City, USA
[email protected], [email protected]

Abstract— A new online measurement and analysis method MOSFETs, IGBTs, BJTs are some of the primarily affected
has been presented in this paper to identify the state of health of components in power converters due to aging. Components
power converter circuits. Using spread spectrum time domain with degraded electrical characteristics eventually cause
reflectometry (SSTDR), impedance in the various current paths secondary and tertiary effects that can accelerate the aging
inside the converter as well as any fault can be identified without
process in a circuit having multiple control loops. Aging can
interrupting the circuit’s normal operation. Multiple sets of test
data have been generated while the SSTDR process is applied to degrade individual component’s performance as well as the
each of the components i.e. the power MOSFETs, the dc bus overall circuit’s efficiency and reliability.
capacitor and the load. These obtained test data are analyzed to
show how these test results are consistent with the impedances in II. AGING FACTORS AND STATE OF THE ART SOLUTIONS
various current paths. An impedance matrix was formed for a MOSFETs and electrolytic capacitors are known to be the
non-aged converter and a corresponding matrix using SSTDR two major components responsible for converter failure, and
data was formed as well. The matrices could be formed for any they have significantly higher failure rate than other
power converter, and the impedance matrix for the non-aged
components used in power converters. From the failure survey
converter could be considered as a “Reference matrix” for
comparison purpose. By comparing these two matrices, the
of two different types of switched mode power supplies, 60%
variation in path impedances due to aging could be determined. and 72% power supply failures are due to electrolytic
This research aims to identify the measurable quantities to capacitor breakdown and 31% of the total failure occurs due to
characterize the aging process, their origins of these quantities the failure of semiconductor switches [1], [2]. Degradation
and propose convenient methods to measure them. and failure of these components may be due to long time
operation under normal operating condition or due to short
Keywords-Reflectometry, Time Domain Reflectometry (TDR), time operation under extreme stress condition i.e. high
Spread Spectrum Time Domain Reflectometry (SSTDR), ambient temperature, high voltage, reverse bias and high
Equivalent Series Resistance (ESR), ON – state resistance
ripple current.
I. INTRODUCTION Electrical stress at the gate area was implemented in [3][4]
Power converters are widely used in industrial by applying high voltage at gate terminal and the
manufacturing processes, and the uninterrupted operation of corresponding impacts were studied. Here it was found that
those converters is critical. In addition, power converters are the threshold voltage increases with aging. An increase in
becoming a part of the residential power system because of the threshold voltage directly corresponds to an increase in
widespread adoption of grid-tied PV inverters. The switching time. Threshold voltage deviation is generally
overstressed conditions i.e. over voltage, over current or occurred due to the degradation in gate oxide region and the
switching impulses could permanently damage various interface of gate oxide and semiconductor region. The
components in a power converter. In addition, the degradation rate depends on the thickness of the gate oxide.
functionality and performance of a power converter degrades
The ON – state resistance is found to be the most
with time, and the degradation rate depends on several
significant aging factor in power MOSFETs [5], and two
associated factors such as any overload, ambient temperature,
aging measurement techniques for power MOSFETs have
connected load types, radiation, and so on. Power converters
been presented in [6]. During the first test, the drain current
are periodically replaced in an industrial process, but without
was increased from 3A to 15A and the device fails to turn off
identifying the remaining life of the aged converter. Therefore,
when the gate voltage reaches to zero. This phenomenon
effectiveness and utilization factor of power converters could
indicates the loss of gate control, and the ON – state resistance
be greatly enhanced if the power converters’ state of health
(RDS) exhibits a sudden drop due to elevated drain current.
could be identified with certain accuracy. Electrolytic
Therefore, higher RDS is consistent with aging and a sudden
capacitors are mostly affected, and switching devices such as

978-1-4244- 9373-9/12/$26.00 ©2012 IEEE

drop in the value of RDS is the indicator of the loss of gate Time domain reflectometry (TDR) method was identified as a
control. According to the second method of aging presented in potential method to identify small anomalies in the test cable
[6], the failure occurred as a result of increased resistance due to it’s large bandwidth [23]. TDR was used in [24] to
inside the device. As a result, the drain current dropped and measure the parasitic parameters on printed circuit boards
the transistor failed to switch. Degradation at the contact area (PCB). In addition, TDR was used in [25], [26] to detect two
of bonding wire – metallization is reflected in the MOSFET interconnect failure: solder joint cracking and solder pad
ON – stare resistance (RDS). RDS increases due to the separation. The method of extracting series resistance of
degradation at metallization and at the contact area of bonding capacitors is presented in [27] using TDR. The major
wire – metallization [7]. Reference [8] also concluded that RDS limitation of TDR is the higher cost compared to other
increases due to thermal aging of MOSFET. Reference [9] techniques and inability to use in live networks. In order to
described a technique of using ON – state resistance of the overcome the limitations of TDR, SSTDR was used to
device to find out the junction temperature. Die solder estimate the state of health of power MOSFETs in this paper.
degradation is observed in reference [10][11] by applying SSTDR is a combination of TDR and spread spectrum
thermal stress to the device, and the RDS increased due to the method. A high frequency PN signal is sent down to the wire
degradation. and the incident and reflected signals are correlated in SSTDR
technique. The location of the various peaks in the correlation
[12] presents the effect of high temperature gate bias
(HTGB) stress on large area (0.56 cm2) SiC power MOSFETs indicates the location of impedance discontinuities such as
with voltage and current ratings of 1200V and 67A open circuits, short circuits, and arcs (intermittent shorts).
respectively. This analysis showed that if the device is being Unlike TDR technology, SSTDR can identify small
operated under high temperature with high stress at gate, it will intermittent faults in cable and it can be used in a live network.
eventually have higher/lower threshold voltage depending on Due to aging, the equivalent series resistance (ESR) of
the type of stress and types of MOSFET (n channel or p capacitor increases [28] and the equivalent capacitance
channel). Reference [13] explains how threshold voltage, decreases i.e. impedance is being changed. In case of
transconductance, and collector-emitter ON voltage could be
MOSFETs, the channel “ON – state resistance” (RDS) is
used to identify aging of IGBTs. There are several real time
increased due to aging. Therefore, reflectometry method can
methods to estimate the state of health of power converters
[14]-[17]. However, they are suitable for detection of be used to identify these gradual changes in a power converter
degradation of a specific component in the converter. SSTDR by comparing these values with the reference values consistent
can be applied in an energized circuit and it can generate real with a non-aged (new) converter.
time data depending on the impedance discontinuity between
IV. EXPERIMENTAL RESULTS
the test points. It is possible to estimate the overall health state
of converter using the data generated by SSTDR hardware. A test circuit was built to identify the variation in
MOSFET’s ON – state resistance (RDS) as a function of aging,
III. PROPOSED METHODOLOGY and the schematic shown in Figure 1 was used for this purpose.
Most of the conventional techniques estimate components’ The other key objective of this test was to verify if the SSTDR
aging by measuring individual components while they are technique can identify this RDS variation. Five MOSFETs (M1
disconnected from the circuit. Even they are characterized in – M5) having different aging levels were used for this
measurement. These MOSFETs were aged using accelerated
real time; results applicable to individual components are not
stress in a controlled environment, and five FDP 3672 N-
suitable to predict the overall converter reliability. In order to channel power trench MOSFETs were used for this test. The
eliminate this limitation, spread spectrum time domain case temperature was stabilized between 110°C~120°C during
reflectometry (SSTDR) could be used to obtain several this accelerated aging process. M5 was used as the reference
parameters of the individual components as well as the MOSFET as zero stress was applied to it.
converter circuit. Reflectometry is conventionally used for
locating wiring faults, and several novel solutions using
reflectometry could locate the fault with a greater precision
[18]-[22]. Using reflectometry, a high frequency electrical
signal is sent down the wire and it reflects from any
impedance discontinuity. The reflection co-efficient gives a
measure of how much signal is returned and is given by ρ.
ρ= (i)

Where Z0 is defined as the characteristic impedance of the

transmission medium and Zt is the impedance of the Figure 1. Test schematic to identify the RDS variation of aged MOSFETs
terminating end of the transmission line. The time or phase using SSTDR system.
delay between the incident and reflected signals provides the
Figure 2(a) demonstrates how the MOSFETs RDS varies
distance to the fault, and the observed magnitude of the
with the level of aging. This RDS measurement was done using
reflection co-efficient provides the impedance at discontinuity. a data acquisition system. For a VGS of 5V, RDS will vary from
50 mΩ to 55 mΩ after 3 hours of accelerated aging. This impedances between these two nodes. The equivalent circuits
variation is reflected in the SSTDR measurement as well. The of these current paths are shown in Figures 4 and 5.
relationship between the correlated output and the level of
aging has been summarized in Figure 2(b). Apparently, the The internal resistances of diodes D1, D2, D3 and D4 are
SSTDR method can identify the variation in RDS at different considered as equal for simplicity. Here, RD is the diodes’
aging conditions. internal resistance, RS is the source’s internal resistance, ESR is
the equivalent series resistance of the DC bus capacitor, and
Once the MOSFET characterization was performed, the RDS1, RDS2, RDS3, RDS4 are the ON – state resistances of
SSTDR signal was applied to a power converter circuit shown MOSFETs S1, S2, S3, S4 respectively. The frequency of
in Figure 3. The key objective of this test was to observe the applied PN signal in SSTDR method is 24 MHz ~ 96 MHz.
correlated outputs across various components. There are four The MOSFET capacitances were neglected in calculating the
test points in this circuit (Figure 3). SSTDR technique was equivalent path impedances as the capacitive impedances are
applied in different combinations to map these four test points. very high at 24 MHz ~ 96 MHz compared to MOSFET ON –
A 3.53 V (RMS), 60 Hz AC voltage was applied to the circuit, resistances. The ON – resistances will be dominant when they
and the load resistor RL was 10 Ω. are in parallel with MOSFET capacitances during the circuit’s
65
operating mode. ESR is always in parallel to the series
combination of two diode resistances and the source resistance.
ON resistance (mohm)

If S1 and S2 are activated, the equivalent path impedance

60
between test points 1 and 2 is the parallel combination of the
two branches shown in Figure 4(b). As RDS1<<(Req+RL+RDS2),
55
the equivalent path impedance can be approximated as RDS1
shown in Figure 4(c). When S3 and S4 are activated, the
50 equivalent path impedance between test nodes 1 and 2 is the
series combination of Req and RDS4 (Figure 5). Similarly, the
45
0 10 20 30 40 50 60 70 80
path impedance between 1 and 3 will be RDS3 or the series
Level of aging(%) combination of RDS2 and Req.
(a)
4 The equivalent path impedance between nodes 1 and 4 is
-1.42 x 10
always Req (Figure 6), and the equivalent path impedances
-1.44 between nodes 2 and 3 are “RDS1 + Req + RDS2” or “RDS3 + Req
Correlated output

-1.46 + RDS4” (Figure 7). All the equivalent path impedances

between the test pairs have been derived. The SSTDR
-1.48
hardware will generate different values of correlated outputs
-1.5 depending on the path impedances. In addition, there may be
-1.52 few data points which will not give any consistent results
during the switching transition of the power MOSFETs. A
-1.54
0 10 20 30 40 50 60 70 80 similar MOSFET with a DC voltage applied at the gate
Level of aging (%)
terminal was tested in a DC chopper circuit to estimate the
(b)
steady state RDS. The correlated output was “-23516”. There is
Figure 3. The variation in RDS as a function of aging. There is a significant
increase in RDS once the MOSFET is subjected to stress. a) RDS was
a discrepancy in SSTDR data generated for similar MOSFETs
calculated using the data acquisition system, b) correlated output as a in different circuit. SSTDR data were generated in steady state
function of RDS was measured using the SSTDR setup. condition for H – bridge converter to find out the reason of the
discrepancy. All the SSTDR data (steady state operation and 60
Hz operation) and corresponding path impedances were given
in Table 1. The steady state data are consistent with the data
generated in a DC chopper circuit. Proper synchronization is
required between the SSTDR hardware and the switching pulse
generator to obtain accurate results.

Figure 3. Schematic of the AC-AC converter used to test the

effectiveness of the SSTDR system.

A 30 foot cable was connected between the SSTDR

hardware and any node pairs. When SSTDR was applied
between test points 1 and 2, different values of correlated (a) (b) (c)
output were found. This is due to the presence of different path Figure 4. Equivalent path impedances between test nodes 1 and 2 when
S1 and S2 are activated.
 V. MATRIX ANALYSIS
An impedance matrix was built from the single phase AC –
AC converter shown in Figure 8. For i=1-4 and j=1-4, Xij
represents correlated output between any two test points among
the four different nodes. Xij = -1 (normalized value) for i=j
because it would be a short circuit. Therefore, all the diagonal
elements of this matrix is “-1”. From the previous discussion,
there exist two impedance matrices for two different operating
states of the converter. X12 – X13 represent the correlated output
across upper side MOSFETs (S1 and S3), and X14 represents
(a) (b) (c)
the correlated output across the dc bus capacitor. In the same
Figure 5. Equivalent path impedances between test nodes 1 and 2 when S3 way X42 – X43 represent the correlated output across lower side
and S4 are activated. MOSFETs (S2 and S4).
The experimental values of the ON – resistances during
steady state condition, the capacitor ESR, and the load
impedance are given in Table 2. Using these values, the
equivalent path impedances for each test pairs were calculated
using simulations in PSIM software. The reference impedance
matrix was formed using these calculated values shown in
Figure 9. The corresponding SSTDR matrix using steady state
data was formed shown in Figure 10.
The values of matrices shown in Figure 9 and 10 will
(a) (b) (c) eventually be changed as the converter ages. These variations
Figure 6. Equivalent path impedances between test nodes 1 and 4 for both could be incremental for normal aging or substantial for any
switching states. failure. This matrix could be formed for any power converter,
and a “Reference matrix” could be constructed from a non-
aged power converter for comparison purpose. For example, if
MOSFET S1 is aged, it’s ON – resistance may increase to 50
mΩ, and these path impedances should be impacted
accordingly. Using this new assumed value of RDS1 while other
values remaining unchanged, a PSIM simulation was
performed to calculate the path impedances. A matrix was
formed using these path impedances and it is clearly
observable that only few matrix elements changed due to aging
of S1 (Figure 11). In this case, second row and second column
are affected only during the state when S1 and S2 are activated
and no changes were found during the state when S3 and S4
Figure 7. Equivalent path impedances between test nodes 2 and 3 for both are activated. Therefore, it is possible to determine the aged
switching states. component by observing the matrix elements. The location of
the elements indicates which component is aged and the value
Table 1. Experimental correlated output across various current paths in the of the elements indicates how much the component is aged.
non-aged AC-AC converter. The test set up of experiments is shown in Figure 12.

Correlated output
Test
Path impedance Steady A=
points
60 Hz state
RDS1 -13700 -23016
1 and 2 Figure 8. Impedance matrix.
Req + RDS4 -10942 -19347
Table 2. Experimental values of MOSFET ON – resistances,
RDS3 -13415 -22821
capacitor ESR and load resistance
1 and 3
Req + RDS2 -12101 -20635
Name of the Corresponding
RDS4 -13178 -23057 components resistance
2 and 4 S1 37.78 mΩ
Req + RDS1 -10505 -19232

RDS2 -12319 -22865 S2 37.28 mΩ

3 and 4
Req + RDS3 -10212 -20287 S3 33.67 mΩ

RDS1 + Req + RDS2 -7367 -19372 S4 39.17 mΩ

2 and 3
RDS3 + Req + RDS4 -5960 -19912 C 33 mΩ

1 and 4 Req -16601 -21173 RL 10 Ω

 When S1, S2 are “ON” and S3, S4 are “OFF” matrix. This matrix could be formed for any power converter,
0 37.6397 68.962 31.854 and a “Reference matrix” could be constructed from a non-
Reference A
37.6397 0 106.11 69.247 aged power converter for comparison purpose. By comparing
68.962 106.11 0 37.1435 these two matrices, it is possible to identify the impedance
31.854 69.247 37.1435 0 variation in various current paths due to aging and predict the
relative state of health of the converter.
When S1, S2 are “OFF” and S3, S4 are “ON”
0 70.6178 33.558 31.854
70.6178 0 103.707 39.019
Reference A
33.558 103.707 0 65.1981
31.854 39.019 65.1981 0

Figure 9: Reference Impedance matrix.

When S1, S2 are “ON” and S3, S4 are “OFF”

23706 23016 20635 21173

23016 23706 19372 19232
Reference A
20635 19372 23706 22865 (a)
21173 19232 22865 23706

When S1, S2 are “OFF” and S3, S4 are “ON”

23706 19347 22821 21173

19347 23706 19912 23057
Reference A
22821 19912 23706 20287
21173 23057 20287 23706

Figure 10: Matrix formed by SSTDR generated data in steady state

condition.

When S1, S2 are “ON” and S3, S4 are “OFF” (b)

Only S1 aged [Assuming RDS4 = 50 mΩ],

0 49.754 68.962 31.854

49.754 0 117.824 81.873
A
68.962 117.824 0 37.1435
31.854 81.873 37.1435 0

When S1, S2 are “OFF” and S3, S4 are “ON”

Only S1 aged [Assuming RDS4 = 50 mΩ],

0 70.6178 33.558 31.854

70.6178 0 103.707 39.019
A (c)
33.558 103.707 0 65.1981
31.854 39.019 65.1981 0 Figure 12. Experimental set up. (a) Test set up when SSTDR is applied
to a MOSFET in a chopper circuit, (b) Test set up when SSTDR is
Figure 11: Impedance matrix assuming S1 is aged. The impedances applied to different components of an AC-AC converter, (c) AC-AC
that are changed due to aging of S1 indicated as red marked. converter under test.
REFERENCES
VI. CONCLUSIONS [1] U.S. Dept. of Defense, Reliability Prediction of Electronic Equipment,
This paper presented a non-intrusive measurement and Military Handbook 217F, Feb. 28, 1995.
computation technique to estimate the state of health of power [2] A. Layhani, P. Venet, G. Grellet, and P. J. Viverge, “Failure prediction
converters. SSTDR was applied in a single phase AC-AC of electrolytic capacitors during operation of a switchmode power
supply,” IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1199–1207,
converter between different test point pairs and corresponding Nov. 1998.
correlated output for different path impedances were obtained. [3] Sankalita Saha, Jose. R. Celaya, Vladislav Vashchenko, Shompa
The proposed method involves a new technique to identify the Mahiuddin and Kai. F. Goebel; “Accelerated Aging with Electrical
variation in the path impedance in a non-interfering manner, Overstress and Prognostics for Power MOSFETs”; Energytech, 2011
and this paper shows the feasibility of using SSTDR method to IEEE.
identify the aging of power MOSFETs and other components. [4] J. Celaya, P. Wysocki, V. Vashchenko, S. Saha, and K. Goebel,
In addition, the test results suggest that this technique could be “Accelerated aging system for prognostics of power semiconductor
devices,” in AUTOTESTCON, 2010 IEEE, 2010, pp. 1 –6.
used to identify the aging of the entire power converter once
numerical computation is performed with the impedance
[5] Dupont, L., Lefebvre, S., Bouaroudj, M., Khatir, Z., Faugieres, J. C., [17] Dawei Xiang; Li Ran; Tavner, P.; Shaoyong Yang; Bryant, A.; Mawby,
Emorine, F.; “Ageing Test Results of low voltage MOSFET Modules for P.; “Monitoring solder fatigue in a power module using the rise of case-
Electrical Vehicles”; Power Electronics and Applications, 2007 above-ambient temperature”; Energy Conversion Congress and
European Conference. Exposition (ECCE), 2010; pp. 955-962.
[6] Jose R. Celaya, Nishad Patil, Sankalita Saha, Phil Wyscoki and Kai [18] Chet Lo,, and Furse, C., “Noise Domain Reflectometry for Locating
Goebel; “Towards Accelerated Aging Methodologies and Health Wiring Faults”; IEEE Transactions on Electromagnetic Compatibility,
Management of Power MOSFETs”; Annual Conference of the vol. 47, no. 1, pp. 97-104, February 2005.
Prognostics and Health Management Society 2009. [19] Tsai, P., Chet Lo, You Chung Chung, Furse, C., “Mixed-signal
[7] Azoui, T. ; Tounsi, P. ; Dupuy, Ph. ; Dorkel, J.M. ; Martineau, D.; reflectometer for location of faults on aging wiring”; Sensors Journal,
“Numerical and experimental results correlation during power MOSFET IEEE, vol 5, Issue 6, pp. 1479-1482, December 2005.
ageing”; 13th International Conference on Thermal, Mechanical and [20] Chirag R. Sharma; Furse C., Reid R. Harrison, “Low Power STDR
Multi-Physics Simulation and Experiments in Microelectronics and Sensor for Locationg Faults in Aging Aircraft Wiring”; Sensors Journal,
Microsystems (EuroSimE), 2012. IEEE, vol 7, Issue 1, pp. 43-50, January 2007.
[8] Yeoh Lai Seng; “Characterization of Intermetallic Growth for Gold [21] Peiman Amini; Furse, C.; B. Farhang-Boroujeny; “Filterbank
Bonding and Copper Bonding on Aluminum Metallization in Power Multicarrier Reflectometry for Cognitive Live Wire Testing”; Sensors
Transistors”; Electronics Packaging Technology Conference, 2007. Journal, IEEE, vol 9, Issue 12, pp. 1831-1837, December 2009
[9] Dimosthenis C. Katsis; and Jacobus Daniel van Wyk; “Void-Induced [22] Smith, P.; Furse, C.; Gunther, J.; “Analysis of spread spectrum time
Thermal Impedance in Power Semiconductor Modules: Some Transient domain reflectometry for wire fault location”; Sensors Journal, IEEE;
Temperature Effects”; IEEE Transaction on Industry Applications, Issue 6 Volume 5; pp 1469 -1478.
Volume 39, No. 5, September/October 2003.
[23] Furse C., You Chung Chung; Chet Lo; Praveen Pendayala; “A Critical
[10] Celaya, J.R. ; Saxena, A. ; Vashchenko, V. ; Saha, S. ; Goebel, K.; Comparison of Reflectometry Methods for Location of Wiring Faults”;
“Prognostics of power MOSFET”; 23rd International Symposium on Smart Structures and Systems, vol 2, Issue 1, pp. 25-46, 2006.
Power Semiconductor Devices and ICs (ISPSD), 2011.
[24] S. Hashino, T. Shimizu; “Characterization of Parasitic Impedance in a
[11] Celaya, J.R.; Saxena, A. ; Kulkarni, C.S. ; Saha, S. ; Goebel, K.; Power Electronics Circuit Board using TDR”; Power Electronics
“Prognostics approach for power MOSFET under thermal-stress aging”; Conference (IPEC), 2010 International; pp 900 – 905.
Annual Proceedings on Reliability and Maintainability Symposium
(RAMS), 2012. [25] Daeil Kwon ; Azarian, M.H. ; Pecht, M. ; “Identification of interconnect
failure mechanisms using RF impedance analysis”; IEEE workshop on
[12] Green, R. ; Lelis, A. ; Habersat, D. ; “Application of reliability test Signal Propagation on Interconnects, 2009; pp. 1-4.
standards to SiC Power MOSFETs”; Reliability Physics Symposium
(IRPS), 2011 IEEE International. [26] Yudong Lu; Bin Yao; Ming Wan; Jingdong Feng; “Time domain
reflectometry technique for detecting the degradation of solder
[13] Patil, N. ; Das, D. ; Goebel, K. ; Pecht, M. ; “Identification of failure joints”; 9th International Conference on Reliability, Maintainability and
precursor parameters for Insulated Gate Bipolar Transistors (IGBTs)”; Safety (ICRMS), 2011; pp. 395 – 397.
International Conference on Prognostics and Health Management, 2008.
PHM 2008; pp. 1-5. [27] Wang, Y. ; Cheung, K.P. ; Choi, R. ; Brown, G.A. ; Lee, B.-
H. ; “Accurate Series-Resistance Extraction From Capacitor Using Time
[14] Wiesinger, T.; Ertl, H.; “A Novel Real Time Monitoring Unit for PWM Domain Reflectometry”; IEEE Electron Device Letters, April 2007;
Converter Electrolytic Capacitors”; Power Electronics Specialists Issue 4; Volume 28; pp. 279 – 281.
Conference, 2008; pp. 523-528.
[28] K. P. Venet, F. Perisse, M. H. El-Husseini, and G. Rojat, “Realization of
[15] Franke, U.; Kruemmer, R.; Petzoldt, J.; “Online diagnostics and a smart electrolytic capacitor circuit,” IEEE Ind. Appl. Magazine, vol. 8,
condition monitoring in voltage source inverters”; European Conference no. 1, pp. 16–20, 2002.
on Power Electronics and Applications, 2005.
[16] Anderson, J.M.; Cox, R.W.; Noppakunkajorn, J.; “An On-Line Fault
Diagnosis Method for Power Electronic Drives”; Electric Ship
Technologies Symposium (ESTS), 2011 IEEE ; pp. 492-497.