19-3179; Rev 3; 3/05

KIT
ATION
EVALU BLE
AVA ILA

17-Output LED Driver/GPO with

Intensity Control and Hot-Insertion Protection
General Description Features

MAX6964
The MAX6964 I2C-compatible serial interfaced periph- ♦ 400kbps, 2-Wire Serial Interface, 5.5V Tolerant
eral provides microprocessors with 17 output ports. ♦ 2V to 3.6V Operation
Each output is an open-drain current-sinking output ♦ Overall 8-Bit PWM LED Intensity Control
rated at 50mA and 7V. The outputs are capable of dri- Global 16-Step Intensity Control
ving LEDs, or providing logic outputs with external Plus Individual 16-Step Intensity Controls
resistive pullup up to 7V. ♦ Two-Phase LED Blinking
Eight-bit PWM current control is also integrated. Four of ♦ High Port Output Current—Each Port 50mA (max)
the bits are global control and apply to all LED outputs ♦ RST Input Clears the Serial Interface and
to provide coarse adjustment of current from fully off to Restores Power-Up Default State
fully on with 14 intensity steps. Additionally, each output ♦ Supports Hot Insertion
has an individual 4-bit control, which further divides the ♦ Outputs are 7V-Rated Open Drain
globally set current into 16 more steps. Alternatively,
♦ Low Standby Current (1.2µA (typ), 3.3µA (max))
the current control can be configured as a single 8-bit
control that sets all outputs at once. ♦ Small 4mm x 4mm, 0.8mm High Thin QFN Package
♦ -40°C to +125°C Temperature Range
Each output has independent blink timing with two blink
phases. LEDs can be individually set to be either on or
off during either blink phase, or to ignore the blink con- Ordering Information
trol. The blink period is controlled by an external clock PIN-
(up to 1kHz) on BLINK or by a register. The BLINK PART TEMP RANGE PKG CODE
PACKAGE
input can also be used as a logic control to turn the
LEDs on and off, or as a general-purpose input (GPI). 24 Thin QFN
MAX6964ATG -40°C to +125°C 4mm x 4mm T2444-4
The MAX6964 supports hot insertion. The SDA, SCL, x 0.8mm
RST, BLINK, and the slave address input ADO remain
high impedance in power-down (V+ = 0V) with up to 6V MAX6964AEG -40°C to +125°C 24 QSOP —
asserted upon them. The output ports remain high
impedance with up to 8V asserted upon them.
Pin Configurations
The MAX6964 is controlled through a 2-wire I 2 C
serial interface, and can be configured to one of four
BLINK

TOP VIEW
O15

O14

O13

O12

O11

I2C addresses.
18 17 16 15 14 13
Applications SCL 19 12 O10
LCD Backlights Keypad Backlights
SDA 20 11 O9
LED Status Indication RGB LED Drivers
V+ 21 10 O8

O16 22
MAX6964 9 GND

Typical Application Circuit at end of data sheet. RST 23 8 O7

AD0 24 7 O6
1 2 3 4 5 6
O0

O1

O2

O3

O4

O5

QFN
Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGS
MAX6964

Voltage (with respect to GND) Continuous Power Dissipation (TA = +70°C)

V+ .............................................................................-0.3V to +4V 24-Pin QSOP (derate 9.5mW/°C over +70°C)..............761mW
SCL, SDA, AD0, BLINK, RST ...................................-0.3V to +6V 24-Pin QFN (derate 20.8mW/°C over +70°C) ............1666mW
O0–O16 ....................................................................-0.3V to +8V Operating Temperature Range .........................-40°C to +125°C
DC Current on O0 to O16 ...................................................55mA Junction Temperature ......................................................+150°C
DC Current on SDA.............................................................10mA Storage Temperature Range .............................-65°C to +150°C
Maximum GND Current ....................................................350mA Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage V+ 2.0 3.6 V
Output Load External Supply
VEXT 0 7 V
Voltage

SCL and SDA at V+; other TA = +25°C 1.2 2.3

Standby Current
I+ digital inputs at V+ or GND; TA = -40°C to +85°C 2.6 µA
(Interface Idle, PWM Disabled)
PWM intensity control disabled TA = TMIN to TMAX 3.3
SCL and SDA at V+; other TA = +25°C 8.5 15.1
Supply Current
I+ digital inputs at V+ or GND; TA = -40°C to +85°C 16.5 µA
(Interface Idle, PWM Enabled)
PWM intensity control disabled TA = TMIN to TMAX 17.2
Supply Current fSCL = 400kHz; other digital TA = +25°C 50 95.3
(Interface Running, PWM I+ inputs at V+ or GND; PWM TA = -40°C to +85°C 99.2 µA
Disabled) intensity control enabled TA = TMIN to TMAX 102.4
Supply Current fSCL = 400kHz; other digital TA = +25°C 57 110.2
(Interface Running, PWM I+ inputs at V+ or GND; PWM TA = -40°C to +85°C 117.4 µA
Enabled) intensity control enabled TA = TMIN to TMAX 122.1
Input High Voltage 0.7 x
VIH V
SDA, SCL, AD0, BLINK, RST V+
Input Low Voltage 0.3 x
VIL V
SDA, SCL, AD0, BLINK, RST V+
Input Leakage Current
IIH, IIL 0 ≤ input voltage ≤ 5.5V -0.2 +0.2 µA
SDA, SCL, AD0, BLINK, RST
Input Capacitance
8 pF
SDA, SCL, AD0, BLINK, RST

2 _______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
ELECTRICAL CHARACTERISTICS (continued)

MAX6964
(Typical Operating Circuit, V+ = 2V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA= + 25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TA = +25°C 0.15 0.26
V+ = 2V, ISINK = 20mA TA = -40°C to +85°C 0.3 V
TA = TMIN to TMAX 0.32
TA = +25°C 0.13 0.23
Output Low Voltage
VOL V+ = 2.5V, ISINK = 20mA TA = -40°C to +85°C 0.26 V
O0–O16
TA = TMIN to TMAX 0.28
TA = +25°C 0.12 0.23
V+ = 3.3V, ISINK = 20mA TA = -40°C to +85°C 0.24 V
TA = TMIN to TMAX 0.26
Output Low-Voltage SDA VOLSDA ISINK = 6mA 0.4 V
PWM Clock Frequency fPWM 32 kHz

TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Serial Clock Frequency fSCL 400 kHz
Bus Free Time Between a STOP and a START
tBUF 1.3 µs
Condition
Hold Time, Repeated START Condition tHD, STA 0.6 µs
Repeated START Condition Setup Time tSU, STA 0.6 µs
STOP Condition Setup Time tSU, STO 0.6 µs
Data Hold Time tHD, DAT (Note 2) 0.9 µs
Data Setup Time tSU, DAT 180 ns
SCL Clock Low Period tLOW 1.3 µs
SCL Clock High Period tHIGH 0.7 µs
20 +
Rise Time of Both SDA and SCL Signals, Receiving tR (Notes 3, 4) 300 ns
0.1Cb
20 +
Fall Time of Both SDA and SCL Signals, Receiving tF (Notes 3, 4) 300 ns
0.1Cb
20 +
Fall Time of SDA Transmitting tF.TX (Notes 3, 5) 250 ns
0.1Cb
Pulse Width of Spike Suppressed tSP (Note 6) 50 ns

_______________________________________________________________________________________ 3
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
TIMING CHARACTERISTICS (continued)
MAX6964

(Typical Operating Circuit, V+ = 2V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capacitive Load for Each Bus Line Cb (Note 3) 400 pF
RST Pulse Width tW 1 ns
Output Data Valid tDV Figure 10 5 ns

Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD.
Note 5: ISINK ≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE (PWM DISABLED; fSCL = 400kHz) (PWM ENABLED; fSCL = 400kHz)
10 70 MAX6964 toc02 70

MAX6964 toc03
MAX6964 toc01

V+ = 3.6V 65
9 PWM ENABLED 60 60
8 55
V+ = 3.6V
STANDBY CURRENT (µA)

SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

7 50 50
V+ = 3.6V
45
6 40 40 V+ = 2.7V
5 V+ = 2V V+ = 2.7V 35
V+ = 2.7V PWM ENABLED 30 30
4 V+ = 2V
PWM ENABLED V+ = 3.6V 25
3 PWM 20 V+ = 2V 20
V+ = 2V V+ = 2.7V
2 PWM DISABLED PWM DISABLED DISABLED 15
10 10
1 5
0 0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

PORT OUTPUT LOW VOLTAGE WITH 50mA PORT OUTPUT LOW VOLTAGE WITH 20mA PWM CLOCK FREQUENCY
LOAD CURRENT vs. TEMPERATURE LOAD CURRENT vs. TEMPERATURE vs. TEMPERATURE
0.6 0.6 1.050
MAX6964 toc05
MAX6964 toc04

MAX6964 toc06

ALL OUTPUTS LOADED

PORT OUTPUT LOW VOLTAGE VOL (V)
PORT OUTPUT LOW VOLTAGE VOL (V)

0.5 0.5 1.025 V+ = 3.6V

PWM CLOCK FREQUENCY (kHz)

V+ = 2.7V
0.4 V+ = 2V 0.4 1.000

0.3 0.3 V+ = 2V 0.975

V+ = 2.7V V+ = 2V

0.2 V+ = 3.6V 0.2 0.950

0.1 0.1 V+ = 3.6V 0.925

V+ = 2.7V
NORMALIZED TO V+ = 3.3V, TA = 25°C
0 0 0.900
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

4 _______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection

MAX6964
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)

SCOPE SHOT OF OUTPUT PORTS SCOPE SHOT OF OUTPUT PORTS SINK CURRENT vs. VOL
MAX6964 toc07 MAX6964 toc08
0.35

MAX6964 toc09
MASTER INTENSITY SET TO 14/15 MASTER INTENSITY SET TO 1/15 ONLY ONE OUTPUT LOADED
OUTPUT 1, OUTPUT 1 0.30
V+ = 2V
2V/div 2V/div
OUTPUT 1 INDIVIDUAL INTENSITY 0.25
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16 SET TO 1/16
0.20

VOL (V)
V+ = 2.7V
V+ = 3.3V
0.15
OUTPUT 2, OUTPUT 2 V+ = 3.6V
2V/div 2V/div 0.10
OUTPUT 2 INDIVIDUAL INTENSITY OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 14/15 SET TO 15/16 0.05

0
2ms/div 2ms/div 0 10 20 30 40 50
SINK CURRENT (mA)

Pin Description
PIN
NAME FUNCTION
QSOP QFN
1, 4–11, 13–20 1–8, 10–17, 22 O0-O16 Output Ports. Open-drain outputs rated at 7V, 50mA.
Reset Input. Active low clears the 2-wire interface and puts the device in the
2 23 RST
same condition as power-up reset.
Address Input. Sets device slave address. Connect to either GND, V+, SCL, or
3 24 AD0
SDA to give 4 logic combinations. See Table 1.
12 9 GND Ground. Do not sink more than 350mA into the GND pin.
21 18 BLINK Input Port. Configurable as blink control or general-purpose input.
22 19 SCL I2C-Compatible Serial Clock Input
23 20 SDA I2C-Compatible Serial Data I/O
24 21 V+ Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor.
— Pad Exposed Pad Exposed pad on package underside. Connect to GND.

_______________________________________________________________________________________ 5
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Functional Overview BLINK input) and/or software control (the blink flip flag
MAX6964

in the configuration register) (Table 4).

The MAX6964 is a general-purpose output (GPO)
peripheral that provides 17 output ports, O0–O16, con- The 17th output, O16, is controlled through 2 bits in the
trolled through an I2C-compatible serial interface. All configuration register, which provide the same static or
outputs sink loads up to 50mA connected to external blink control as the other 16 outputs (Table 4).
supplies up to 7V, independent of the MAX6964’s sup- The logic level of the BLINK input may be read back
ply voltage. The MAX6964 is rated for a ground current through the blink status bit in the configuration register
of 350mA, allowing all 17 outputs to sink 20mA at the (Table 4). The BLINK input, therefore, may be used as
same time. Figure 1 shows the output structure of the a general-purpose logic input (GPI port) if the blink
MAX6964. The outputs default to logic high (high function is not required.
impedance unless external pullup resistors are used)
on power-up. PWM Intensity Control
The MAX6964 includes an internal oscillator, nominally
Output Control and LED Blinking 32kHz, to generate PWM timing for LED intensity con-
The two blink phase 0 registers set the output logic lev- trol. PWM intensity control can be enabled on an out-
els of the 16 outputs O0–O15 (Table 6). These registers put-by-output basis, allowing the MAX6964 to provide
control the port outputs if the blink function is disabled. any mix of PWM LED drives and glitch-free logic out-
A duplicate pair of registers, the blink phase 1 regis- puts (Table 8). PWM can be disabled entirely, in which
ters, are also used if the blink function is enabled case all outputs are static and the MAX6964 operating
(Table 7). In blink mode, the outputs can be flipped current is lowest because the internal oscillator is
between using the blink phase 0 registers, and the turned off.
blink phase 1 registers using hardware control (the
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 11 and 12).
The 4-bit master control provides 16 levels of overall
OUTPUT intensity control, which applies to all PWM-enabled out-
PORT puts. The master control sets the maximum pulse width
REGISTER from 1/15 to 15/15 of the PWM time period. The individ-
DATA FROM D Q OUTPUT PORT
SHIFT REGISTER
ual settings comprise a 4-bit number, further reducing
REGISTER DATA I/O PIN
FF the duty cycle to be from 1/16 to 15/16 of the time win-
dow set by the master control.
WRITE PULSE CK Q Q2
For applications requiring the same PWM setting for all
GND output ports, a single global PWM control can be used
instead of all the individual controls to simplify the con-
trol software and provide 240 steps of intensity control
(Tables 8 and 11).

Figure 1. Simplified Schematic of I/O Ports

SDA

tSU,STA tBUF
tSU,DAT tHD,STA
tLOW
tHD,DAT tSU,STO

SCL tHIGH

tHD,STA
tR tF

START CONDITION REPEATED START CONDITION STOP START

CONDITION CONDITION

Figure 2. 2-Wire Serial Interface Timing Details

6 _______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
User RAM Serial Interface

MAX6964
The MAX6964 includes 2 register bytes, which are
available as general-user RAM (Table 2). These bytes Serial Addressing
are reset to the value 0xFF on power-up and when the The MAX6964 operates as a slave that sends and
RST input is taken low (Table 3). receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
Standby Mode serial clock line (SCL) to achieve bidirectional commu-
When the serial interface is idle and the PWM intensity nication between master(s) and slave(s). A master (typ-
control is unused, the MAX6964 automatically enters ically a microcontroller) initiates all data transfers to and
standby mode. If the PWM intensity control is used, the from the MAX6964 and generates the SCL clock that
operating current is slightly higher because the internal synchronizes the data transfer (Figure 2).
PWM oscillator is running. When the serial interface is The MAX6964 SDA line operates as both an input and
active, the operating current also increases because an open-drain output. A pullup resistor, typically 4.7kΩ,
the MAX6964, like all I2C slaves, has to monitor every is required on SDA. The MAX6964 SCL line operates
transmission. only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
SDA has an open-drain SCL output.
SCL
Each transmission consists of a START condition
S P (Figure 3) sent by a master, followed by the MAX6964
START STOP 7-bit slave address plus R/W bit, a register address
CONDITION CONDITION
byte, 1 or more data bytes, and finally a STOP condi-
Figure 3. Start and Stop Conditions tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
SDA not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
SCL
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
DATA LINE STABLE; CHANGE OF DATA
STOP (P) condition by transitioning SDA from low to
DATA VALID ALLOWED high while SCL is high. The bus is then free for another
transmission (Figure 3).
Figure 4. Bit Transfer Bit Transfer
One data bit is transferred during each clock pulse.
CLOCK PULSE The data on SDA must remain stable while SCL is high
START
CONDITION FOR ACKNOWLEDGE (Figure 4).
SCL 1 2 8 9 Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
SDA BY
TRANSMITTER
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
SDA BY requires 9 bits. The master generates the 9th clock
RECEIVER S
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
Figure 5. Acknowledge

SDA A6 1 0 0 A2 0 0 R/W ACK

MSB LSB
SCL

Figure 6. Slave Address

_______________________________________________________________________________________ 7
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 1. MAX6964 Address Map
MAX6964

DEVICE ADDRESS
PIN AD0
A6 A5 A4 A3 A2 A1 A0
SCL 1 1 0 0 0 0 0
SDA 1 1 0 0 1 0 0
GND 0 1 0 0 0 0 0
V+ 0 1 0 0 1 0 0

Table 2. Register Address Map

ADDRESS CODE AUTOINCREMENT
REGISTER
(hex) ADDRESS
Blink phase 0 outputs O7–O0 0x02 0x03
Blink phase 0 outputs O15–O8 0x03 0x02
User RAM0 0x06 0x07
User RAM1 0x07 0x06
Blink phase 1 outputs O7–O0 0x0A 0x0B
Blink phase 1 outputs O15–O8 0x0B 0x0A
Master and global/O16 intensity 0x0E —
Configuration 0x0F —
Outputs intensity O1, O0 0x10 0x11
Outputs intensity O3, O2 0x11 0x12
Outputs intensity O5, O4 0x12 0x13
Outputs intensity O7, O6 0x13 0x14
Outputs intensity O9, O8 0x14 0x15
Outputs intensity O11, O10 0x15 0x16
Outputs intensity O13, O12 0x16 0x17
Outputs intensity O15, O14 0x17 0x10

during the high period of the clock pulse. When the four possible slave addresses (Table 1), and therefore
master is transmitting to the MAX6964, the device gen- a maximum of four MAX6964 devices can be controlled
erates the acknowledge bit because the MAX6964 is independently from the same interface.
the recipient. When the MAX6964 is transmitting to the
master, the master generates the acknowledge bit Message Format for Writing the MAX6964
A write to the MAX6964 comprises the transmission of
because the master is the recipient.
the MAX6964’s slave address with the R/W bit set to
Slave Address zero, followed by at least 1 byte of information. The first
The MAX6964 has a 7-bit long slave address (Figure 6). byte of information is the command byte. The command
The eighth bit following the 7-bit slave address is the byte determines which register of the MAX6964 is to be
R/W bit. The R/W bit is low for a write command, high written to by the next byte, if received (Table 2). If a
for a read command. STOP condition is detected after the command byte is
The second (A5), third (A4), fourth (A3), sixth (A1), and received, then the MAX6964 takes no further action
last (A0) bits of the MAX6964 slave address are always beyond storing the command byte.
1, 0, 0, 0, and 0. Slave address bits A6 and A2 are Any bytes received after the command byte are data
selected by the address input AD0. AD0 can be con- bytes. The first data byte goes into the internal register of
nected to GND, V+, SDA, or SCL. The MAX6964 has the MAX6964 selected by the command byte (Figure 8).

8 _______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection

MAX6964
COMMAND BYTE IS STORED ON RECEIPT OF
D15 D14 D13 D12 D11 D10 D9 D8
STOP CONDITION
ACKNOWLEDGE FROM MAX6964

S SLAVE ADDRESS 0 A COMMAND BYTE A P

R/W ACKNOWLEDGE FROM MAX6964

Figure 7. Command Byte Received

ACKNOWLEDGE FROM MAX6964 ACKNOWLEDGE FROM MAX6964

HOW COMMAND BYTE AND DATA BYTE MAP INTO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MAX6964's REGISTERS
ACKNOWLEDGE FROM MAX6964

S SLAVE ADDRESS 0 A COMMAND BYTE A DATA BYTE A P

1
R/W BYTE
AUTOINCREMENT MEMORY ADDRESS

Figure 8. Command and Single Data Byte Received

ACKNOWLEDGE FROM MAX6964 ACKNOWLEDGE FROM MAX6964

HOW COMMAND BYTE AND DATA BYTE MAP INTO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MAX6964's REGISTERS
ACKNOWLEDGE FROM MAX6964

S SLAVE ADDRESS 0 A COMMAND BYTE A DATA BYTE A P

N
R/W BYTE
AUTOINCREMENT MEMORY ADDRESS

Figure 9. n Data Bytes Received

WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)

SCL 1 2 3 4 5 6 7 8 9
SLAVE ADDRESS COMMAND BYTE
SDA S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A MSB DATA1 LSB A MSB DATA2 LSB A P

START CONDITION R/W ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE STOP
CONDITION
O7–O0 DATA1 VALID
tDV
O15– O8 DATA2 VALID
tDV

Figure 10. Write Timing Diagram

If multiple data bytes are transmitted before a STOP con- Message Format for Reading
dition is detected, these bytes are generally stored in The MAX6964 is read using the MAX6964’s internally
subsequent MAX6964 internal registers because the stored command byte as an address pointer the same
command byte address autoincrements (Table 2). A way the stored command byte is used as an address
diagram of a write to the output ports registers (blink pointer for a write. The pointer autoincrements after
phase 0 registers or blink phase 1 registers) is given in each data byte is read using the same rules as for a
Figure 10. write (Table 2). Thus, a read is initiated by first configur-

_______________________________________________________________________________________ 9
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
ing the MAX6964’s command byte by performing a BLINK input) and software control (the blink flip flag B
MAX6964

write (Figure 7). The master can now read n consecu- in the configuration register) (Table 4).
tive bytes from the MAX6964 with the first data byte The blink function can be used for LED effects by pro-
being read from the register addressed by the initial- gramming different display patterns in the two sets of
ized command byte. When performing read-after-write output port registers, and using the software or hard-
verification, remember to reset the command byte’s ware controls to flip between the patterns.
address because the stored command byte address
has been autoincremented after the write (Table 2). If the blink phase 1 registers are written with 0xFF, then
the BLINK input can be used as a hardware disable to,
Operation with Multiple Masters for example, instantly turn off an LED pattern pro-
If the MAX6964 is operated on a 2-wire interface with grammed into the blink phase 0 registers. This tech-
multiple masters, a master reading the MAX6964 should nique can be further extended by driving the BLINK
use a repeated start between the write, which sets the input with a PWM signal to modulate the LED current to
MAX6964’s address pointer, and the read(s) that takes provide fading effects.
the data from the location(s) (Table 2). This is because it The blink mode is enabled by setting the blink enable
is possible for master 2 to take over the bus after master flag E in the configuration register (Table 4). When blink
1 has set up the MAX6964’s address pointer but before mode is enabled, the state of the blink flip flag and
master 1 has read the data. If master 2 subsequently BLINK input are EXORed to set the phase, and the out-
changes the MAX6964’s address pointer, then master puts are set by either the blink phase 0 registers or the
1’s delayed read can be from an unexpected location. blink phase 1 registers (Figure 11, Table 5).
Command Address Autoincrementing The blink mode is disabled by clearing the blink enable
The command address stored in the MAX6964 circu- flag E in the configuration register (Table 4). When blink
lates around grouped register functions after each data mode is disabled, the state of the blink flip flag is
byte is written or read (Table 2). ignored, and the blink phase 0 registers alone control
Device Reset the outputs.
The reset input RST is an active-low input. When taken The logic status of BLINK is made available as the read-
low, RST clears any transaction to or from the MAX6964 only blink status flag blink in the configuration register
on the serial interface and configures the internal regis- (Table 4). This flag allows BLINK to be used as an extra
ters to the same state as a power-up reset (Table 3). general-purpose input (GPI) in applications not using the
The MAX6964 then waits for a START condition on the blink function. When BLINK is going to be used as a GPI,
serial interface. blink mode should be disabled by clearing the blink
enable flag E in the configuration register (Table 4).
Detailed Description
Blink Phase Registers
Initial Power-Up When the blink function is disabled, the two blink phase
On power-up, and whenever the RST input is pulled 0 registers set the logic levels of the 16 outputs (O0
low, all control registers are reset and the MAX6964 through O15) (Table 6). A duplicate pair of registers
enters standby mode (Table 3). Power-up status makes called the blink phase 1 registers are also used if the
all outputs logic high (high impedance if external pullup blink function is enabled (Table 7). A logic high sets the
resistors are not fitted) and disables both the PWM appropriate output high impedance, while a logic low
oscillator and blink functionality. The RST input can be makes the port go low.
used as a hardware shutdown input, which effectively
turns off any LED (or other) loads and puts the device Reading a blink phase register reads the value stored
into its lowest power condition. in the register, not the actual port condition. The port
output itself may or may not be at a valid logic level,
Configuration Register depending on the external load connected.
The configuration register is used to configure the PWM The 17th output, O16, is controlled through 2 bits in the
intensity mode and blink behavior, operate the O16 out- configuration register, which provide the same static or
put, and read back the BLINK input logic level (Table 4). blink control as the other 16 output ports.
Blink Mode
In blink mode, the outputs can be flipped between
using either the blink phase 0 registers or the blink
phase 1 registers. Flip control is both hardware (the

10 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 3. Power-Up Configuration

MAX6964
ADDRESS REGISTER DATA
REGISTER FUNCTION POWER-UP CONDITION CODE
(hex)
D7 D6 D5 D4 D3 D2 D1 D0
Blink phase 0 outputs O7–O0 High-impedance outputs 0x02 1 1 1 1 1 1 1 1
Blink phase 0 outputs O15–O8 High-impedance outputs 0x03 1 1 1 1 1 1 1 1
User RAM0 0xFF 0x06 1 1 1 1 1 1 1 1
User RAM1 0xFF 0x07 1 1 1 1 1 1 1 1
Blink phase 1 outputs O7–O0 High-impedance outputs 0x0A 1 1 1 1 1 1 1 1
Blink phase 1 outputs O15–O8 High-impedance outputs 0x0B 1 1 1 1 1 1 1 1
Master and global/O16 PWM oscillator is disabled;
0x0E 0 0 0 0 1 1 1 1
intensity O16 is static logic output

O16 is high-impedance output;

Configuration blink is disabled; 0x0F 0 0 1 1 0 1 0 0
global intensity is enabled
Outputs intensity O1, O0 O1, O0 are static logic outputs 0x10 1 1 1 1 1 1 1 1
Outputs intensity O3, O2 O3, O2 are static logic outputs 0x11 1 1 1 1 1 1 1 1
Outputs intensity O5, O4 O5, O4 are static logic outputs 0x12 1 1 1 1 1 1 1 1
Outputs intensity O7, O6 O7, O6 are static logic outputs 0x13 1 1 1 1 1 1 1 1
Outputs intensity O9, O8 O9, O8 are static logic outputs 0x14 1 1 1 1 1 1 1 1
Outputs intensity O11, O10 O11, O10 are static logic outputs 0x15 1 1 1 1 1 1 1 1
Outputs intensity O13, O12 O13, O12 are static logic outputs 0x16 1 1 1 1 1 1 1 1
Outputs intensity O15, O14 O15, O14 are static logic outputs 0x17 1 1 1 1 1 1 1 1

Table 4. Configuration Register

ADDRESS REGISTER DATA
REGISTER CODE
(hex)
D7 D6 D5 D4 D3 D2 D1 D0

R/W
BLINK FLIP
INTENSITY
GLOBAL
OUTPUT

ENABLE
STATUS
BLINK

BLINK
O16

CONFIGURATION
0

Write device configuration 0 0x0F X X

BLINK O1 O0 G B E
Read back device configuration 1 0 0
Disable blink — X X X X X X X 0
Enable blink — X X X X X X X 1
— X X X X X X 0 1
Flip blink register (see text)
— X X X X X X 1 1
X = Don’t care.

______________________________________________________________________________________ 11
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 4. Configuration Register (continued)
MAX6964

ADDRESS REGISTER DATA

REGISTER CODE
(hex)
D7 D6 D5 D4 D3 D2 D1 D0

R/W

BLINK FLIP
INTENSITY
GLOBAL
OUTPUT

ENABLE
STATUS
BLINK

BLINK
O16
CONFIGURATION

0
Write device configuration 0 X X
BLINK O1 O0 G B E
Read back device configuration 1 0 0
Disable global intensity control—intensity
is set by registers 0x10–0x17 for ports O0
— X X X X X 0 X X
through O15 when configured as outputs,
and by D3–D0 of register 0x0E for output

Enable global intensity control—intensity

for all ports configured as outputs is set — X X X X X 1 X X
by D3–D0 of register 0x0E 0x0F
O16 output is low (blink is disabled) — X X X 0 0 X X 0
O16 output is high impedance (blink is
— X X X 1 0 X X 0
disabled)
O16 output is low during blink phase 0 — X X X 0 0 X X 1
O16 output is high impedance during
— X X X 1 0 X X 1
blink phase 0
O16 output is low during blink phase 1 — X X 0 X 0 X X 1
O16 output is high impedance during
— X X 1 X 0 X X 1
blink phase 1
Read back BLINK input pin status;
1 X 0 X X X X X X
input is low
Read back BLINK input pin status;
1 X 1 X X X X X X
input is high

X = Don’t care.

Table 5. Blink Controls

BLINK ENABLE BLINK FLIP BLINK FLIP FLAG
BLINK INPUT BLINK OUTPUT REGISTERS
FLAG FLAG EXOR
PIN FUNCTION USED
E B BLINK INPUT PIN
0 X X X Disabled Blink phase 0
0 0 0 Blink phase 0
0 1 1 Blink phase 1
1 Enabled
1 0 1 Blink phase 1
1 1 0 Blink phase 0
X = Don’t care.

12 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 6. Blink Phase 0 Registers

MAX6964
ADDRESS REGISTER DATA
REGISTER R/W CODE
(hex)
D7 D6 D5 D4 D3 D2 D1 D0
Write outputs O7–O0 phase 0 0
0x02 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Read back outputs O7–O0 phase 0 1
Write outputs O15–O8 phase 0 0
0x03 OP15 OP14 OP13 OP12 OP11 OP10 OP9 OP8
Read back outputs O15–O8 phase 0 1

Table 7. Blink Phase 1 Registers

ADDRESS REGISTER DATA
REGISTER R/W CODE
(hex)
D7 D6 D5 D4 D3 D2 D1 D0
Write outputs O7–O0 phase 1 0
0x0A OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Read back outputs O7–O0 phase 1 1
Write outputs O15–O8 phase 1 0
0x0B OP15 OP14 OP13 OP12 OP11 OP10 OP9 OP8
Read back outputs O15–O8 phase 1 1

Table 8. PWM Application Scenarios

APPLICATION RECOMMENDED CONFIGURATION
Set the master and global intensity register 0x0E to any value from 0x00 to 0x0F.
All outputs static without PWM The global intensity G bit in the configuration register is don't care.
The output intensity registers 0x10 through 0x17 are don't care.

Set the master and global intensity register 0x0E to any value from 0x10 to 0xFF.
Clear global intensity G bit to zero in the configuration register to disable global
A mix of static and PWM outputs, with PWM
intensity control.
outputs using different PWM settings
For the static outputs, set the output intensity value to 0xF.
For the PWM outputs, set the output intensity value in the range 0x0 to 0xE.
A mix of static and PWM outputs, with PWM As above. Global intensity control cannot be used with a mix of static and PWM
outputs all using the same PWM setting outputs, so write the individual intensity registers with the same PWM value.
Set the master and global intensity register 0x0E to any value from 0x10 to 0xFF.
Set global intensity G bit to 1 in the configuration register to enable global intensity
All outputs PWM using the same PWM
control.
setting
The master and global intensity register 0x0E is the only intensity register used.
The output intensity registers 0x10 through 0x17 are don't care.

______________________________________________________________________________________ 13
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
PWM Intensity Control master intensity. The individual controls provide 16
MAX6964

The MAX6964 includes an internal oscillator, nominally intensity settings from 1/16 through 16/16 (Table 12).
32kHz, to generate PWM timing for LED intensity control Figures 16, 17, and 18 show examples of individual
or other applications such as PWM trim DACs. PWM can intensity control settings. The highest value an individ-
be disabled entirely for all the outputs. In this case, all ual or global setting can be set to is 16/16. This setting
outputs are static and the MAX6964 operating current is forces the output to ignore the master control, and fol-
lowest because the internal PWM oscillator is turned off. low the logic level set by the appropriate blink phase
The MAX6964 can be configured to provide any combi- register bit. The output becomes a glitch-free static out-
nation of PWM outputs and glitch-free logic outputs. put with no PWM.
Each PWM output has an individual 4-bit intensity con-
trol (Table 12). When all outputs are to be used with the Using PWM Intensity Controls with Blink Disabled
same PWM setting, the outputs can be controlled When blink is disabled (Table 5), the blink phase 0 regis-
together instead using the global intensity control ters specify each output’s logic level during the PWM on-
(Table 11). Table 8 shows how to set up the MAX6964 time (Table 6). The effect of setting an output’s blink
to suit a particular application. phase 0 register bit to zero or 1 is shown in Table 9. With
its output bit set to zero, an LED can be controlled with 16
PWM Timing intensity settings from 1/16th duty through fully on, but
The PWM control uses a 240-step PWM period, divided cannot be turned fully off using the PWM intensity control.
into 15 master intensity timeslots. Each master intensity With its output bit set to 1, an LED can be controlled with
timeslot is divided further into 16 PWM cycles (Figure 12). 16 intensity settings from fully off through 15/16th duty.
The master intensity operates as a gate, allowing the indi- Using PWM Intensity Controls with Blink Enabled
vidual output settings to be enabled from 1 to 15 timeslots When blink is enabled (Table 5), the blink phase 0 regis-
per PWM period (Figures 13, 14, and 15) (Table 11). ters and blink phase 1 registers specify each output’s
Each output’s individual 4-bit intensity control only logic level during the PWM on-time during the respective
operates during the number of timeslots gated by the blink phases (Tables 6 and 7). The effect of setting an
output’s blink phase x register bit to 0 or 1 is shown in
Table 10. LEDs can be flipped between either directly on
BLINK ENABLE FLAG E and off, or between a variety of high/low PWM intensities.
BLINK FLIP FLAG B Global/O16 Intensity Control
The 4 bits used for output O16’s PWM individual inten-
sity setting also double as the global intensity control
(Table 11). Global intensity simplifies the PWM settings
BLINK PHASE when the application requires them all to be the same,
BLINK INPUT REGISTERS
such as for backlight applications, by replacing the 17
individual settings with one setting. Global intensity is
Figure 11. BLINK Logic

ONE PWM PERIOD IS 240 CYCLES OF THE 32kHz PWM

OSCILLATOR; A PWM PERIOD CONTAINS 15 MASTER
INTENSITY TIMESLOTS

14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2

15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2

EACH MASTER INTENSITY

TIMESLOT CONTAINS 16
PWM CYCLES

Figure 12. PWM Timing

14 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
enabled with the global intensity flag G in the configu- up to 8V asserted on them. The MAX6964 can therefore

MAX6964
ration register (Table 4). When global PWM control is be used in hot-swap applications.
used, the 4 bits of master intensity and 4 bits of global
intensity effectively combine to provide an 8-bit, 240- Output Level Translation
step intensity control applying to all outputs. The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
It is not possible to apply global PWM control to a sub- than the MAX6964 supply. An external pullup resistor
set of the ports, and use the others as logic outputs. To can be used on any output to convert the high-imped-
mix static logic outputs and PWM outputs, individual ance logic-high condition to a positive voltage level.
PWM control must be selected (Table 8). The resistor can be connected to any voltage up to 7V.
Applications Information For interfacing CMOS inputs, a pullup resistor value of
220kΩ is a good starting point. Use a lower resistance
Hot Insertion to improve noise immunity, in applications where power
The RST input, BLINK input, and serial interface SDA, consumption is less critical, or where a faster rise time
SCL, AD0 remain high impedance with up to 6V assert- is needed for a given capacitive load.
ed on them when the MAX6964 is powered down (V+ =
0V). Ouptut ports O0–O16 remain high impedance with Driving LED Loads
When driving LEDs, a resistor in series with the LED
must be used to limit the LED current to no more than
14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 50mA. Choose the resistor value according to the fol-
.
lowing formula:
RLED = (VSUPPLY - VLED - VOL) / ILED
Figure 13. Master Set to 1/15
where:
.

RLED is the resistance of the resistor in series with the

14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2
LED (Ω).
.

VSUPPLY is the supply voltage used to drive the LED (V).

Figure 14. Master Set to 14/15 VLED is the forward voltage of the LED (V).
VOL is the output low voltage of the MAX6964 when
.

sinking ILED (V).

14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2
ILED is the desired operating current of the LED (A).
.

Figure 15. Master Set to 15/15

MASTER INTENSITY TIMESLOT NEXT MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 16. Individual (or Global) Set to 1/16

MASTER INTENSITY TIMESLOT NEXT MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 17. Individual (or Global) Set to 15/16

MASTER INTENSITY TIMESLOT CONTROL IS IGNORED

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 18. Individual (or Global) Set to 16/16

______________________________________________________________________________________ 15
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
For example, to operate a 2.2V red LED at 14mA from a
MAX6964

2V TO 3.6V
5V supply, RLED = (5 - 2.2 - 0.25) / 0.014 = 182Ω.
5V
Driving Load Currents Higher than 50mA 0.047µF
The MAX6964 can be used to drive loads drawing
more than 50mA, like relays and high-current white V+ O0
LEDs, by paralleling outputs. Use at least one output µC
O1
per 50mA of load current; for example, a 6V 330mW SDA SDA O2 MMTBT4148
relay draws 55mA and needs two paralleled outputs to O3
SCL SCL
drive it. Ensure that the paralleled outputs chosen are O4
I/O BLINK
controlled by the same blink phase register, i.e., select O5
outputs from the O0 through O7 range, or the O8 I/O RST O6
through O15 range. This way, the paralleled outputs MAX6964 O7
are turned on and off together. Do not use output O16 O8
as part of a load-sharing design. O16 cannot be AD0 O9
switched at the same time as any of the other outputs O10
because it is controlled by a different register. O11
The MAX6964 must be protected from the negative O12
voltage transient generated when switching off induc- O13
tive loads, such as relays, by connecting a reverse- O14
biased diode across the inductive load (Figure 19). The GND O15
peak current through the diode is the inductive load’s
operating current.
Figure 19. Diode-Protected Switching Inductive Load

Table 9. PWM Intensity Settings (Blink Disabled)

OUTPUT PWM DUTY CYCLE LED BEHAVIOR WHEN PWM DUTY CYCLE LED BEHAVIOR WHEN
(OR OUTPUT BLINK PHASE 0 OUTPUT BLINK PHASE 0 OUTPUT BLINK PHASE 0 OUTPUT BLINK PHASE 0
GLOBAL) REGISTER BIT = 0 REGISTER BIT = 0 REGISTER = 1 REGISTER BIT = 1
INTENSITY (LED IS ON WHEN (LED IS ON WHEN
SETTING OUTPUT IS LOW) OUTPUT IS LOW)
LOW TIME HIGH TIME LOW TIME HIGH TIME
0x0 1/16 15/16 Lowest PWM intensity 15/16 1/16 Highest PWM intensity
0x1 2/16 14/16 14/16 2/16
0x2 3/16 13/16 13/16 3/16
0x3 4/16 12/16 12/16 4/16
Increasing PWM intensity 

Increasing PWM intensity

0x4 5/16 11/16 11/16 5/16

0x5 6/16 10/16 10/16 6/16
0x6 7/16 9/16 9/16 7/16
0x7 8/16 8/16 8/16 8/16
0x8 9/16 7/16 7/16 9/16
0x9 10/16 6/16 6/16 10/16
0xA 11/16 5/16 5/16 11/16
0xB 12/16 4/16 4/16 12/16
0xC 13/16 3/16 3/16 13/16
0xD 14/16 2/16 2/16 14/16
0xE 15/16 1/16 Highest PWM intensity 1/16 15/16 Lowest PWM intensity
Full intensity, no PWM Static high Static high
0xF Static low Static low LED off continuously
(LED on continuously) impedance impedance

16 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 10. PWM Intensity Settings (Blink Enabled)

MAX6964
EXAMPLES OF LED BLINK BEHAVIOR
PWM DUTY CYCLE PWM DUTY CYCLE (LED IS ON WHEN OUTPUT IS LOW)
OUTPUT OUTPUT BLINK OUTPUT BLINK
(OR PHASE X PHASE X
GLOBAL) REGISTER BIT = 0 REGISTER = 1 BLINK PHASE 0 BLINK PHASE 0
INTENSITY REGISTER BIT = 0 REGISTER BIT = 1
SETTING BLINK PHASE 1 BLINK PHASE 1
LOW HIGH LOW HIGH REGISTER BIT = 1 REGISTER BIT = 0
TIME TIME TIME TIME
0x0 1/16 15/16 15/16 1/16
0x1 2/16 14/16 14/16 2/16
0x2 3/16 13/16 13/16 3/16
Phase 0: LED on at low intensity Phase 0: LED on at high intensity
0x3 4/16 12/16 12/16 4/16
Phase 1: LED on at high intensity Phase 1: LED on at low intensity
0x4 5/16 11/16 11/16 5/16
0x5 6/16 10/16 10/16 6/16
0x6 7/16 9/16 9/16 7/16
0x7 8/16 8/16 8/16 8/16 Output is half intensity during both blink phases
0x8 9/16 7/16 7/16 9/16
0x9 10/16 6/16 6/16 10/16
0xA 11/16 5/16 5/16 11/16
Phase 0: LED on at high intensity Phase 0: LED on at low intensity
0xB 12/16 4/16 4/16 12/16
Phase 1: LED on at low intensity Phase 1: LED on at high intensity
0xC 13/16 3/16 3/16 13/16
0xD 14/16 2/16 2/16 14/16
0xE 15/16 1/16 1/16 15/16
Static high Static high Phase 0: LED on continuously Phase 0: LED off continuously
0xF Static low Static low
impedance impedance Phase 1: LED off continuously Phase 1: LED on continuously

Power-Supply Considerations
The MAX6964 operates with a power-supply voltage of
2V to 3.6V. Bypass the power supply to GND with at
least 0.047µF as close to the device as possible. For
the QFN version, connect the underside exposed pad
to GND.

______________________________________________________________________________________ 17
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 11. Master, O16 Intensity Register
MAX6964

ADDRESS REGISTER DATA

REGISTER CODE
R/W (hex)
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
MASTER AND GLOBAL INTENSITY
MASTER INTENSITY O16 INTENSITY
Write master and global intensity 0
M3 M2 M1 M0 G3 G2 G1 G0
Read back master and global intensity 1
Master intensity duty cycle is 0/15 (off);
internal oscillator is disabled; — 0 0 0 0 — — — —
all outputs will be static with no PWM
Master intensity duty cycle is 1/15 — 0 0 0 1 — — — —
Master intensity duty cycle is 2/15 — 0 0 1 0 — — — —
Master intensity duty cycle is 3/15 — 0 0 1 1 — — — —
— — — — — — — — — —
Master intensity duty cycle is 13/15 — 0X0E 1 1 0 1 — — — —
Master intensity duty cycle is 14/15 — 1 1 1 0 — — — —
Master intensity duty cycle is 15/15 (full) — 1 1 1 1 — — — —

O/16 intensity duty cycle is 1/16 — — — — — 0 0 0 0

O/16 intensity duty cycle is 2/16 — — — — — 0 0 0 1
O/16 intensity duty cycle is 3/16 — — — — — 0 0 1 0
— — — — — — — — — —
O/16 intensity duty cycle is 14/16 — — — — — 1 1 0 1
O/16 intensity duty cycle is 15/16 — — — — — 1 1 1 0
O/16 intensity duty cycle is 16/16
— — — — — 1 1 1 1
(static output, no PWM)

18 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 12. Output Intensity Registers

MAX6964
ADDRESS REGISTER DATA
REGISTER CODE
R/W (hex)
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
OUTPUTS O1, O0 INTENSITY
OUTPUT O1 INTENSITY OUTPUT O0 INTENSITY
Write output O1, O0 intensity 0
O1I3 O1I2 O1I1 O1I0 O0I3 O0I2 O0I1 O0I0
Read back output O1, O0 intensity 1
Output O1 intensity duty cycle is 1/16 — 0 0 0 0 — — — —
Output O1 intensity duty cycle is 2/16 — 0 0 0 1 — — — —
Output O1 intensity duty cycle is 3/16 — 0 0 1 0 — — — —
— — — — — — — — — —
Output O1 intensity duty cycle is 14/16 — 1 1 0 1 — — — —
Output O1 intensity duty cycle is 15/16 — 1 1 1 0 — — — —
Output O1 intensity duty cycle is 16/16 0X10
— 1 1 1 1 — — — —
(static logic level, no PWM)

Output O0 intensity duty cycle is 1/16 — — — — — 0 0 0 0

Output O0 intensity duty cycle is 2/16 — — — — — 0 0 0 1
Output O0 intensity duty cycle is 3/16 — — — — — 0 0 1 0
— — — — — — — — — —
Output O0 intensity duty cycle is 14/16 — — — — — 1 1 0 1
Output O0 intensity duty cycle is 15/16 — — — — — 1 1 1 0
Output O0 intensity duty cycle is 16/16
— — — — — 1 1 1 1
(static logic level, no PWM)

MSB LSB MSB LSB

OUTPUTS O3, O2 INTENSITY
OUTPUT O3 INTENSITY OUTPUT O2 INTENSITY
0x11
Write output O3, O2 intensity 0
O3I3 O3I2 O3I1 O3I0 O2I3 O2I2 O2I1 O2I0
Read back output O3, O2 intensity 1

MSB LSB MSB LSB

OUTPUTS O5, O4 INTENSITY
OUTPUT O5 INTENSITY OUTPUT O4 INTENSITY
0x12
Write output O5, O4 intensity 0
O5I3 O5I2 O5I1 O5I0 O4I3 O4I2 O4I1 O4I0
Read back output O5, O4 intensity 1

MSB LSB MSB LSB

OUTPUTS O7, O6 INTENSITY
OUTPUT O7 INTENSITY OUTPUT O6 INTENSITY
0x13
Write output O7, O6 intensity 0
O7I3 O7I2 O7I1 O7I0 O6I3 O6I2 O6I1 O6I0
Read back output O7, O6 intensity 1

______________________________________________________________________________________ 19
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Table 12. Output Intensity Registers (continued)
MAX6964

ADDRESS REGISTER DATA

REGISTER CODE
R/W (hex)
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
OUTPUTS O9, O8 INTENSITY
OUTPUT O9 INTENSITY OUTPUT O8 INTENSITY
0x14
Write output O9, O8 intensity 0
O9I3 O9I2 O9I1 O9I0 O8I3 O8I2 O8I1 O8I0
Read back output O9, O8 intensity 1

MSB LSB MSB LSB

OUTPUTS O11, O10 INTENSITY
OUTPUT O11 INTENSITY OUTPUT O10 INTENSITY
0x15
Write output O11, O10 intensity 0
O11I3 O11I2 O11I1 O11I0 O10I3 O10I2 O10I1 O10I0
Read back output O11, O10 intensity 1

MSB LSB MSB LSB

OUTPUTS O13, O12 INTENSITY
OUTPUT O13 INTENSITY OUTPUT O12 INTENSITY
0x16
Write output O13, O12 intensity 0
O13I3 O13I2 O13I1 O13I0 O12I3 O12I2 O12I1 O12I0
Read back output O13, O12 intensity 1

MSB LSB MSB LSB

OUTPUTS O15, O14 INTENSITY
OUTPUT O15 INTENSITY OUTPUT O14 INTENSITY
0x17
Write output O15, O14 intensity 0
O15I3 O15I2 O15I1 O15I0 O14I3 O14I2 O14I1 O14I0
Read back output O15, O14 intensity 1

OUTPUT O16 INTENSITY See master, 016 register (Table 11).

20 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Typical Application Circuit

MAX6964
7V

3.3V

0.047µF

V+ O0
µC
O1
SDA SDA O2
SCL SCL O3
O4
I/O BLINK
O5
I/O RST O6
O7
MAX6964 O8
AD0 O9
O10
O11
O12 RELAY
O13
5V 3.3V 6V RELAY
O14
O15
GND O16 RELAY

OUTPUT

OUTPUT

Pin Configurations (continued) Chip Information

TRANSISTOR COUNT: 25,991
TOP VIEW PROCESS: BiCMOS
O16 1 24 V+

RST 2 23 SDA

ADO 3 22 SCL

O0 4 21 BLINK

O1 5 MAX6964AEG 20 O15

O2 6 19 O14

O3 7 18 O13

O4 8 17 O12

O5 9 16 O11

O6 10 15 O10

O7 11 14 O9

GND 12 13 O8

QSOP

______________________________________________________________________________________ 21
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Package Information
MAX6964

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055 F 1

22 ______________________________________________________________________________________
 17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
Package Information (continued)

MAX6964
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

24L QFN THIN.EPS

PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
21-0139 E 2

PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
21-0139 E 2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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