Synthesizer for RF Personal Communications

LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency

September 1996

LMX2335/LMX2336/LMX2337
PLLatinum TM Dual Frequency Synthesizer
for RF Personal Communications
LMX2335 1.1 GHz/1.1 GHz Features
LMX2336 2.0 GHz/1.1 GHz Y 2.7V to 5.5V operation
Y Low current consumption
LMX2337 550 MHz/550 MHz Y Selectable powerdown mode:
ICC e 1 mA (typ)
General Description Y Dual modulus prescaler: 64/65 or 128/129
The LMX2335, LMX2336 and LMX2337 are monolithic, inte- Y Selectable charge pump TRI-STATEÉ mode
grated dual frequency synthesizers, including two high fre- Y Selectable charge pump current levels
quency prescalers, and are designed for applications requir- Y Selectable FastlockTM mode
ing two RF phase-lock loops. They are fabricated using Na-
tional’s ABiC IV silicon BiCMOS process.
The LMX2335/36/37 contains two dual modulus prescal-
Applications
Y Cellular telephone systems (AMPS, ETACS, RCR-27)
ers. A 64/65 or a 128/129 prescaler can be selected for
each RF synthesizer. A second reference divider chain is
Y Cordless telephone systems
included in the IC for improved system noise. (DECT, ISM , PHS, CT-1 a )
LMX2335/36/37, which employ a digital phase locked loop Y Personal Communication Systems
technique, combined with a high quality reference oscillator (DCS-1800, PCN-1900)
and loop filters, provide the tuning voltages for voltage con- Y Dual Mode PCS phones
trolled oscillators to generate very stable low noise RF local Y CATV
oscillator signals. Y Other wireless communication systems
Serial data is transferred into the LMX2335/36/37 via a
three wire interface (Data, Enable, Clock). Supply voltage
can range from 2.7V to 5.5V. The LMX2335/36/37 feature
very low current consumption; LMX2335/37 b10 mA at 3V,
LMX2336 b13 mA at 3V. The LMX2335/37 are available in
both a JEDEC SO and TSSOP 16-pin surface mount plastic
package. The LMX2336 is available in a TSSOP 20-pin sur-
face mount plastic package.

Functional Block Diagram

TL/W/12332 – 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

FastlockTM , MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.

C1996 National Semiconductor Corporation TL/W/12332 RRD-B30M96/Printed in U. S. A. http://www.national.com

 Connection Diagrams
LMX2335/LMX2337 LMX2336

TL/W/12332–2
Order Number LMX2335M/LMX2335TM or
LMX2337M/LMX2337TM TL/W/12332 – 16
NS Package Number M16A and MTC16 Order Number LMX2336TM
NS Package Number MTC20

Pin Description
Pin No. Pin No. Pin
I/O Description
2335/37 2336 Name
1 1 VCC1 Power supply voltage input for RF1 analog and RF1 digital circuits. Input may range
from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as
close as possible to this pin and be connected directly to the ground plane.
2 2 Vp1 Power supply for RF1 charge pump. Must be t VCC.
3 3 Do1 O RF1 charge pump output. For connection to a loop filter for driving the input of an
external VCO.
4 4 GND LMX2335/37: Ground for RF1 analog and RF1 digital circuits. LMX2336: Ground for
RF digital circuitry.
5 5 fIN 1 I First RF prescaler input. Small signal input from the VCO.
X 6 fIN 1 I RF1 prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is
optional with loss of some sensitivity.
X 7 GND Ground for RF1 analog circuitry.
6 8 OSCin I Oscillator input. The input has a VCC/2 input threshold and can be driven from an
external CMOS or TTL logic gate.
7 9 OSCout O Oscillator output.
8 10 FoLD O Multiplexed output of the programmable or reference dividers, lock detect signals and
Fastlock mode. CMOS output (see Programmable Modes).
9 11 Clock I High impedance CMOS Clock input. Data for the various latches is clocked in on the
rising edge, into the 20-bit shift register.
10 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits.
High impedance CMOS input.
11 13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the
shift registers is loaded into one of the 4 appropriate latches (control bit dependent).
X 14 GND Ground for RF2 analog circuitry.
X 15 fIN 2 I RF2 prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is
optional with loss of some sensitivity.
12 16 fIN 2 I RF2 prescaler input. Small signal input from the VCO.
13 17 GND LMX2335/37: Ground for RF2 analog, RF2 digital, MICROWIRETM , FoLD and
Oscillator circuits. LMX2336: Ground for RF2 digital, MICROWIRETM , FoLD and
Oscillator circuits.
14 18 Do 2 O RF2 charge pump output. For connection to a loop filter for driving the input of an
external VCO.
15 19 Vp2 Power supply for RF2 charge pump. Must be t VCC.
16 20 VCC2 Power supply voltage input for RF2 analog, RF2 digital, MICROWIRETM , FoLD and
Oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane.
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Block Diagram

TL/W/12332 – 17
LMX2335/37 Pin Ý x 8/10 w LMX2336 Pin Ý
Pin Name x FoLD
X signifies a function not available

Note 1: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase
detector, R-counter along with the OSCin buffer, MICROWIRE TM , and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same
voltage level.
Note 2: VP1 and VP2 can be run separately as long as VP t VCC.

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 Absolute Maximum Ratings (1, 2) Recommended Operating
If Military/Aerospace specified devices are required, Conditions
please contact the National Semiconductor Sales
Power Supply Voltage
Office/Distributors for availability and specifications.
VCC 2.7V to 5.5V
Power Supply Voltage VP VCC to a 5.5V
VCC b 0.3V to a 6.5V
Operating Temperature (TA) b 40§ C to a 85§ C
VP b 0.3V to a 6.5V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
Voltage on Any Pin the device may occur. Recommended Operating Conditions indicate condi-
with GND e 0V (VI) b 0.3V to VCC a 0.3V tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
Storage Temperature Range (TS) b 65§ C to a 150§ C
tions, see the Electrical Characteristics. The guaranteed specifications apply
Lead Temperature (solder 4 sec.) (TL) a 260§ C only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
rating k 2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected workstations.

Electrical Characteristics VCC e 5.0V, VP e 5.0V; TA e 25§ C, except as specified

Value
Symbol Parameter Conditions Units
Min Typ Max
ICC Power Supply LMX2335/37 VCC e 2.7V to 5.5V
10 15 mA
Current RF1 and RF2
ICC LMX2335/37 RF1 only 6 8 mA
ICC LMX2336
13 18 mA
RF1 and RF2
LMX2336 RF1 only 7 11 mA
fIN 1 Operating Frequency LMX2335 0.100 1.1 GHz
fIN 2 0.050 1.1 GHz
fIN1 LMX2336 0.200 2.0 GHz
fIN2 0.050 1.1 GHz
fIN 1 LMX2337 100 550 MHz
fIN 2 50 550 MHz
ICC-PWDN Powerdown Current LMX2335/2336 VCC e 5.5V 1 25
mA
LMX2337 100
fOSC Oscillator Frequency With resonator load on OSCout 5 20 MHz
fOSC No load on OSCout 5 40 MHz
fw Phase Detector Frequency 10 MHz
PfIN 1 and RF Input Sensitivity VCC e 3.0V, f l 100 MHz b 15 a4
PfIN 2
VCC e 5.0V, f l 100 MHz b 10 a4 dBm
VCC e 2.7 to 5.5V, f l 100 MHz b 10 0
VOSC Oscillator Sensitivity OSCin 0.5 VPP
VIH High-Level Input Voltage ** 0.8 VCC V
VIL Low-Level Input Voltage ** 0.2 VCC V
IIH High-Level Input Current VIH e VCC e 5.5V** b 1.0 1.0 mA
IIL Low-Level Input Current VIL e 0V, VCC e 5.5V** b 1.0 1.0 mA
IIH Oscillator Input Current VIH e VCC e 5.5V 100 mA
IIL Oscillator Input Current VIL e 0V, VCC e 5.5V b 100 mA
IDo-SOURCE Charge Pump Output Current VDo e VP/2, ICPo e LOW* b 1.25 mA
IDo-SINK VDo e VP/2, ICPo e LOW* 1.25 mA
IDo-SOURCE VDo e VP/2, ICPo e HIGH* b 5.0 mA
IDo-SINK VDo e VP/2, ICPo e HIGH* 5.0 mA
IDo-TRI Charge Pump LMX2335 0.5V s VDo s VP b 0.5V b 5.0 5.0 nA
TRI-STATE Current LMX2336 T e 25§ C
IDo-TRI Charge Pump LMX2337 0.5V s VDo s VP b 0.5V
g5 nA
TRI-STATE Current T e 25§ C

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Electrical Characteristics VCC e 5.0V, VP e 5.0V; TA e 25§ C, except as specified (Continued)
Value
Symbol Parameter Conditions Units
Min Typ Max
VOH High-Level Output Voltage IOH e b500 mA VCC b 0.4 V
VOL Low-Level Output Voltage IOL e 500 mA 0.4 V
tCS Data to Clock Set Up Time See Data Input Timing 50 ns
tCH Data to Clock Hold Time See Data Input Timing 10 ns
tCWH Clock Pulse Width High See Data Input Timing 50 ns
tCWL Clock Pulse Width Low See Data Input Timing 50 ns
tES Clock to Load Enable Set Up Time See Data Input Timing 50 ns
tEW Load Enable Pulse Width See Data Input Timing 50 ns
*See PROGRAMMABLE MODES for ICPo description.
**Clock, Data and LE does not include fIN1, fIN2 and OSCin.

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 Typical Performance Characteristics (Continued)

ICC vs VCC ICC vs VCC

LMX2335/37 LMX2336

TL/W/12332–19 TL/W/12332 – 20

Charge Pump Current vs Do Voltage Charge Pump Current vs Do Voltage

ICP e HIGH ICP e LOW

TL/W/12332–21 TL/W/12332 – 22

LMX2335/37 Input Impedance (for SO package) LMX2335/37 Input Impedance (for TSSOP package)
VCC e 2.7V to 5.5V, fIN e 50 MHz to 1.5 GHz LMX2336 Input Impedance
VCC e 2.7V to 5.5V, fIN e 50 MHz to 2.5 GHz

TL/W/12332–23
Marker 1 e 1 GHz, Real e 94, Imaginary e b 118 TL/W/12332 – 24
Marker 2 e 1.2 GHz, Real e 72, Imaginary e b 88 Marker 1 e 1 GHz, Real e 97, Imaginary e b 146
Marker 3 e 1.5 GHz, Real e 53, Imaginary e b 45 Marker 2 e 1.89 GHz, Real e 43, Imaginary e b 67
Marker 4 e 500 MHz, Real e 201, Imaginary e b 224 Marker 3 e 2.5 GHz, Real e 30, Imaginary e b 33
Marker 4 e 500 MHz, Real e 189, Imaginary e b 233

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Typical Performance Characteristics (Continued)

IDo TRI-STATE LMX2335/37 RF1 Sensitivity vs Frequency

vs Do Voltage

TL/W/12332 – 26
TL/W/12332 – 25

LMX2335/37 RF2 Sensitivity vs Frequency LMX2336 RF1 Sensitivity vs Frequency

TL/W/12332 – 27
TL/W/12332 – 28

LMX2336 RF2 Sensitivity vs Frequency Oscillator Input Sensitivity vs Frequency

TL/W/12332 – 30

TL/W/12332 – 29

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 Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermedi-
ate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data
stored in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the
Control Bits. The DATA is transferred into the counters as follows:

Control Bits DATA Location

C1 C2
0 0 RF2 R Counter
0 1 RF1 R Counter
1 0 RF2 N Counter
1 1 RF1 N Counter

TL/W/12332 – 1

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Functional Description (Continued)
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.

TL/W/12332 – 4

15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

Divide R R R R R R R R R R R R R R R
Ratio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
# # # # # # # # # # # # # # # #
32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable
reference divider.
Data is shifted in MSB first.

PROGRAMMABLE DIVIDER (N COUNTER)

Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial
data format is shown below.

TL/W/12332 – 5

7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)

Divide
N N N N N N N
Ratio
7 6 5 4 3 2 1
A
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
# # # # # # # #
127 1 1 1 1 1 1 1
Notes: Divide ratio: 0 to 127
BtA
AkP

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 Functional Description (Continued)
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)

Divide
N N N N N N N N N N N
Ratio
18 17 16 15 14 13 12 11 10 9 8
B
3 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 1 0 0
# # # # # # # # # # # #
2047 1 1 1 1 1 1 1 1 1 1 1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
BtA

PULSE SWALLOW FUNCTION

fVCO e [(P c B) a A] c fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 s A s P; A s B)
fOSC: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (P e 64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16 – R20 including the phase detector polarity, charge pump tristate
and the output of the FoLD pin. The prescaler and power down modes are selected with bits N19 and N20. The programmable
modes are shown in Table I. Truth table for the programmable modes and FoLD output are shown in Table II and Table III.
TABLE I. Programmable Modes

C1 C2 R16 R17 R18 R19 R20

RF2 Phase RF2 ICPo RF2 Do RF2 LD RF2 Fo
0 0
Detector Polarity TRI-STATE
0 1 RF1 Phase RF1 ICPo RF1 Do RF1 LD RF1 Fo
Detector Polarity TRI-STATE

C1 C2 N19 N20
RF2 Pwdn
1 0
Prescaler RF2
RF1 Pwdn
1 1
Prescaler RF1

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Functional Description (Continued)
TABLE II. Mode Select Truth Table
RF1 RF2
Phase Detector Polarity(3) Do TRI-STATE ICPo(1) Pwdn(2)
Prescaler Prescaler
0 Negative Normal Operation LOW 64/65 64/65 pwrd up
1 Positive TRI-STATE HIGH 128/129 128/129 pwrd dn
Note 1: The ICPo LOW current state e 1/4 c ICPo HIGH current.
Note 2: Activation of the RF2 PLL or RF1 PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs
(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program
mode is loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality
does not become disabled until both RF2 and RF1 powerdown bits are activated. The OSCin is connected to VCC through 100 kX resistor and the OSCout
goes HIGH when this condition exists. The MICROWIRE TM control register remains active and capable of loading and latching data during all of the
powerdown modes.
Note 3: PHASE DETECTOR POLARITY VCO Characteristics
Depending upon VCO characteristics, the R16 bits should be set
accordingly:
When VCO characteristics are positive like (1), R16 should be set
HIGH;
When VCO characteristics are negative like (2), R16 should be set
LOW.

TL/W/12332 – 7

TABLE III. The FoLD Output Truth Table

RF1 R[19] RF2 R[19] RF1 R[20] RF2 R[20] FoLD
(RF1 LD) (RF2 LD) (RF1 FO) (RF2 FO) Output State
0 0 0 0 Disabled (Note 1)
0 1 0 0 RF2 Lock Detect (Note 2)
1 0 0 0 RF1 Lock Detect (Note 2)
1 1 0 0 RF1/RF2 Lock Detect (Note 2)
X 0 0 1 RF2 Reference Divider Output
X 0 1 0 RF1 Reference Divider Output
X 1 0 1 RF2 Programmable Divider Output
X 1 1 0 RF1 Programmable Divider Output
0 0 1 1 Fastlock (Note 3)
0 1 1 1 For Internal use only
1 0 1 1 For Internal use only
1 1 1 1 Counter Reset (Note 4)
XÐdon’t care condition
Note 1: When the FoLD output is disabled it is actively pulled to a low logic state.
Note 2: Lock detect output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 3: The Fastlock mode utilized the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s Icpo magnitude bit Ý17 is selected HIGH (while the Ý19 and Ý20 mode bits are set for Fastlock).
Note 4: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in ‘‘close’’
alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth
acquisition upon powering up.

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 Functional Description (Continued)
SERIAL DATA INPUT TIMING

TL/W/12332 – 8
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with
amplitudes of 2.2V @ VCC e 2.7V and 2.6V @ VCC e 5.5V.

PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

TL/W/12332 – 9
Notes: Phase difference detection range: b 2q to a 2q
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.

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Typical Application Example

Operational Notes:
TL/W/12332 – 10
* VCO is assumed AC coupled.
** RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO
power level. fIN RF impedance ranges from 40X to 100X. fIN IF impedances are higher.
*** 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no
terminating resistor is required. OSCin may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure
below).
**** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling.

TL/W/12332 – 11

Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.

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 Application Information
A block diagram of the basic phase locked loop is shown in Figure 1.

TL/W/12332 – 12
FIGURE 1. Conventional PLL Architecture

Loop Gain Equations The 3rd order PLL Open Loop Gain can be calculated in
A linear control system model of the phase feedback for a terms of frequency, 0, the filter time contants T1 and T2,
PLL in the locked state is shown in Figure 2 . The open loop and the design constants Kw, KVCO, and N.
gain is the product of the phase comparator gain (Kw), the
# KVCO (1 a jw # T2) T1
À
b Kw
VCO gain (KVCO/s), and the loop filter gain Z(s) divided by G(s) # H(s) e # (4)
the gain of the feedback counter modulus (N). The passive Sej#w w2 C1 # N (1 a jw # T1) T2
loop filter configuration used is displayed in Figure 3 , while From equation 3 we can see that the phase term will be
the complex impedance of the filter is given in equation 2. dependent on the single pole and zero such that the phase
margin is determined in equation 5.
w(0) e tanb1 (0 # T2) btanb1 (0 # T1) a 180§ C (5)
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
wp shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
TL/W/12332–14 the loop). In a critically damped system, the amount of
FIGURE 2. PLL Linear Model phase margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison fre-
quency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
TL/W/12332–13 higher spur levels and wider loop filter conditions would ex-
FIGURE 3. Passive Loop Filter ist only during the initial lock-on phaseÐjust long enough to
reap the benefits of locking faster. The objective would be
Open to open up the loop bandwidth but not introduce any addi-
Hi K Z(s) KVCO
Loop e H(s) G(s) e e w (1) tional complications or compromises related to our original
gain He Ns
design criteria. We would ideally like to momentarily shift the
s(C2 # R2) a 1 curve Figure 4 over to a different cutoff frequency, illustrat-
Z(s) e (2)
S2 (C1 # C2 # R2) a sC1 a sC2 ed by dotted line, without affecting the relative open loop
The time constants which determine the pole and zero fre- gain and phase relationships. To maintain the same gain/
quencies of the filter transfer function can be defined as phase relationship at twice the original cutoff frequency,
other terms in the gain and phase equations 4 and 5 will
C1 # C2
T1 e R2 # (3a) have to compensate by the corresponding ‘‘1/w’’ or ‘‘1/w2’’
C1 a C2 factor. Examination of equations 3 and 5 indicates the
T2 e R2 # C2 (3b) damping resistor variable R2 could be chosen to compen-
sate with ‘‘w’’ terms for the phase margin. This implies that
another resistor of equal value to R2 will need to be
switched in parallel with R2 during the initial lock period. We
must also insure that the magnitude of the open loop gain,
H(s)G(s) is equal to zero at wp’ e 2 wp. KVCO, Kw, N, or the
net product of these terms can be changed by a factor of 4,
to counteract with w2 term present in the denominator of

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Application Information (Continued)
equation 3. The Kw term was chosen to complete the trans- second R2 resistor element to ground. The user calculates
formation because it can readily be switched between 1X the loop filter component values for the normal steady state
and 4X values. This is accomplished by increasing the considerations. The device configuration ensures that as
charge pump output current from 1 mA in the standard long as a second identical damping resistor is wired in ap-
mode to 4 mA in Fastlock. propriately, the loop will lock faster without any additional
stability considerations to account for. Once locked on the
Fastlock Circuit Implementation
correct frequency, the user can return the PLL to standard
A diagram of the Fastlock scheme as implemented in Na- low noise operation by sending a MICROWIRE instruction
tional Semiconductors LMX2335/36/37 PLL is shown in with the RF1 ICPo bit set low. This transition does not affect
Figure 5. When a new frequency is loaded, and the RF1 the charge on the loop filter capacitors and is enacted syn-
ICPo bit is set high, the charge pump circuit receives an input chronous with the charge pump output. This creates a near-
to deliver 4 times the normal current per unit phase error ly seamless change between Fastlock and standard mode.
while an open drain NMOS on chip device switches in a

TL/W/12332 – 15
FIGURE 4.Open Loop Response Bode Plot

TL/W/12332 – 18
FIGURE 5. Fastlock PLL Architecture

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 Physical Dimensions inches (millimeters) unless otherwise noted

JEDEC 16-Lead (0.150× Wide) Small Outline Molded Package (M)

Order Number LMX2335M or LMX2337M
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335MX or LMX2337MX
NS Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TM)

Order Number LMX2335TM or LMX2337TM
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335TMX or LMX2337TMX
NS Package Number MTC16

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LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency
Synthesizer for RF Personal Communications
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead (0.173× Wide) Thin Shrink Small Outline Package (TM)

Order Number LMX2336TM
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336TMX
NS Package Number MTC20

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