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CD4069UB
SCHS054D – NOVEMBER 1998 – REVISED FEBRUARY 2016

CD4069UB CMOS Hex Inverter

1 Features 3 Description
•
1 Standardized Symmetrical Output Characteristics The CD4069UB device consist of six CMOS inverter
circuits. These devices are intended for all general-
• Medium Speed Operation: –tPHL, tPLH = 30 ns at purpose inverter applications where the medium-
10 V (Typical) power TTL-drive and logic-level-conversion
• 100% Tested for Quiescent Current at 20 V capabilities of circuits such as the CD4009 and
• Maximum Input Current of 1 µA at 18 V Over Full CD4049 hex inverter and buffers are not required.
Package-Temperature Range, 100 nA at 18 V and
25°C Device Information(1)
PACKAGE
• Meets All Requirements of JEDEC Tentative PART NUMBER
(PINS)
BODY SIZE (NOM)
Standard No. 13B, Standard Specifications for CD4069UBE PDIP (14) 19.30 mm × 6.35 mm
Description of B Series CMOS Devices
CD4069UBF CDIP (14) 19.56 mm × 6.67 mm
CD4069UBM SOIC (14) 8.65 mm × 3.91 mm
2 Applications
CD4069UBNSR SO (14) 10.30 mm × 5.30 mm
• Logic Inversion
CD4069UBPW TSSOP (14) 5.00 mm × 4.40 mm
• Pulse Shaping
(1) For all available packages, see the orderable addendum at
• Oscillators the end of the data sheet.
• High-Input-Impedance Amplifiers
CD4069UB Functional Diagram

1 2
A G=A

3 4
B H=B

5 6
C I=C

9 8
D J=D

11 10
E K=E

13 12
F L=F

VDD = Pin 14
VSS = Pin 7

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4069UB
SCHS054D – NOVEMBER 1998 – REVISED FEBRUARY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description ................................................ 13
2 Applications ........................................................... 1 8.4 Device Functional Modes ....................................... 13
3 Description ............................................................. 1 9 Application and Implementation ........................ 14
4 Revision History..................................................... 2 9.1 Application Information .......................................... 14
9.2 Typical Application ................................................. 14
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 16
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 16
6.2 ESD Ratings ............................................................ 4 11.1 Layout Guidelines ................................................ 16
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example ................................................... 16
6.4 Thermal Information ................................................. 4 12 Device and Documentation Support ................. 17
6.5 Electrical Characteristics – Dynamic......................... 5 12.1 Device Support...................................................... 17
6.6 Electrical Characteristics – Static.............................. 5 12.2 Documentation Support ........................................ 17
6.7 Typical Characteristics .............................................. 8 12.3 Community Resource............................................ 17
7 Parameter Measurement Information .................. 9 12.4 Trademarks ........................................................... 17
12.5 Electrostatic Discharge Caution ............................ 17
8 Detailed Description ............................................ 13
12.6 Glossary ................................................................ 17
8.1 Overview ................................................................ 13
8.2 Functional Block Diagram ....................................... 13 13 Mechanical, Packaging, and Orderable
Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2003) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

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5 Pin Configuration and Functions

D, J, N, NS, and PW Packages

14-Pin PDIP, CDIP, SOIC, SO, and TSSOP
Top View

A 1 14 VDD
G=A 2 13 F
B 3 12 L=F
H=B 4 11 E
C 5 10 K=E
I=C 6 9 D
VSS 7 8 J=D

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A 1 I A input
B 3 I B input
C 5 I C input
D 9 I D input
E 11 I E input
F 13 I F input
G=A 2 O G output
H=B 4 O H output
I=C 6 O I output
J=D 8 O J output
K=E 10 O K output
L=F 12 O L output
VDD 14 — Positive supply
VSS 7 — Negative supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD DC supply-voltage (voltages referenced to VSS terminal) –0.5 20 V
VI Input voltage, all inputs –0.5 to VDD 0.5 V
IIK DC input current, any one input –10 10 mA
–55°C to 100°C 500
Power dissipation per package mW
PD 100°C to 125°C 12 200
Device dissipation per output transistor Full range (all package types) 100 mW
Lead temperature (2) 265 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) During soldering at distance 1/16 inch ± 1/32 inch (1.59 mm ± 0.79 mm) from case for 10 s maximum

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 3 18 V
TA Operating temperature –55 125 °C

6.4 Thermal Information

CD4069UB
THERMAL METRIC (1) D (SOIC) J (CDIP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 94.9 — 57.9 91.2 122.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.4 28.5 45.5 48.8 50.8 °C/W
RθJB Junction-to-board thermal resistance 49.2 — 37.7 50 63.8 °C/W
ψJT Junction-to-top characterization parameter 21.1 — 30.6 15 6.3 °C/W
ψJB Junction-to-board characterization parameter 48.9 — 37.6 49.6 63.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics – Dynamic

TA = 25°C; input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD (V) = 5 55 110
tPLH, tPHL Propagation delay time VDD (V) = 10 30 60 ns
VDD (V) = 15 25 50
VDD (V) = 5 100 200
tTHL, tTLH Transition time VDD (V) = 10 50 100 ns
VDD (V) = 15 40 80
CIN Input capacitance Any input 10 15 pF

6.6 Electrical Characteristics – Static

TA = 25°C; input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C 0.25
TA = –40°C 0.25
VIN = 0V or 5 V , VDD = 5 V TA = 25°C 0.01 0.25
TA = 85°C 7.5
TA = 125°C 7.5
TA = –55°C 0.5
TA = –40°C 0.5
VIN = 0 or 10 V, VDD = 10 V TA = 25°C 0.01 0.5
TA = 85°C 15
TA = 125°C 15
IDDmax Quiescent device current µA
TA = –55°C 1
TA = –40°C 1
VIN = 0 or 15 V, VDD = 15 V TA = 25°C 0.01 1
TA = 85°C 30
TA = 125°C 30
TA = –55°C 5
TA = –40°C 5
VIN = 0 or 20 V, VDD = 20 V TA = 25°C 0.02 5
TA = 85°C 150
TA = 125°C 150
TA = –55°C 0.64
TA = –40°C 0.61
VO = 0.4 V, VIN = 5 V,
TA = 25°C 0.51 1
VDD = 5 V
TA = 85°C 0.42
TA = 125°C 0.36
TA = –55°C 1.6
TA = –40°C 1.5
VO = 0.5 V, VIN = 10 V,
IOLmin Output low (sink) current TA = 25°C 1.3 2.6 mA
VDD = 10 V
TA = 85°C 1.1
TA = 125°C 0.9
TA = –55°C 4.2
TA = –40°C 4
VO = 1.5 V, VIN = 15 V,
TA = 25°C 3.4 6.8
VDD = 15 V
TA = 85°C 2.8
TA = 125°C 2.4

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Electrical Characteristics – Static (continued)

TA = 25°C; input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C –0.64
TA = –40°C –0.61
VO = 4.6 V, VIN = 0 V,
TA = 25°C –0.51 –1
VDD = 5 V
TA = 85°C –0.42
TA = 125°C –0..36
TA = –55°C –2
TA = –40°C –1.8
VO = 2.5 V, VIN = 0 V,
TA = 25°C –1.6 –3.2
VDD = 5 V
TA = 85°C –1.3
TA = 125°C –1.15
IOHmin Output high (source) current mA
TA = –55°C –1.6
TA = –40°C –1.5
VO = 9.5 V, VIN = 0 V,
TA = 25°C –1.3 –2.6
VDD = 10 V
TA = 85°C –1.1
TA = 125°C –0.9
TA = –55°C –4.2
TA = –40°C –4
VO = 13.5 V, VIN = 0 V,
TA = 25°C –3.4 –6.8
VDD = 15 V
TA = 85°C –2.8
TA = 125°C –2.4
TA = 25°C 0 0.05
VIN = 5 V, VDD = 5 V All other
0.05
temperatures
TA = 25°C 0 0.05
VOLmax Low-level output voltage VIN = 10 V, VDD = 10 V All other V
0.05
temperatures
TA = 25°C 0 0.05
VIN = 15 V, VDD = 15 V All other
0.05
temperatures
TA = 25°C 4.95 5
VIN = 0 V, VDD = 5 V All other
4.95
temperatures
TA = 25°C 9.95 10
VOHmin High-level output voltage VIN = 0 V, VDD = 10 V All other V
9.95
temperatures
TA = 25°C 14.95 15
VIN = 0 V, VDD = 15 V All other
14.95
temperatures
VO = 4.5 V, VDD = 5 V, all temperatures 1
VILmax Input low voltage VO = 9 V, VDD = 10 V, all temperatures 2 V
VO = 13.5 V, VDD = 15 V, all temperatures 2.5
VO = 0.5 V, VDD = 5 V, all temperatures 4
VIHmin Input high voltage VO = 1 V, VDD = 10 V, all temperatures 8 V
VO = 1.5 V, VDD = 15 V, all temperatures 12.5

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Electrical Characteristics – Static (continued)

TA = 25°C; input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C ±01
TA = –40°C ±01
IINmax Input current VIN = 0 V to 18 V, VDD = 18 V TA = 25°C ±10–5 ±1 µA
TA = 85°C ±1
TA = 125°C ±1

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6.7 Typical Characteristics

20 17.5
5 V at -55qC
17.5 15 5 V at 125qC
V IN VO 10 V at -55qC
15 10 V at 125qC
12.5 15 V at -55qC

Output Voltage (V)

Y Axis Title (Unit)

12.5 15 V at 125qC
10
10
7.5
7.5 5-V Min VDD
5-V Max VDD 5
5 10-V Min VDD
10-V Max VDD
2.5 15-V Min VDD 2.5
15-V Max VDD
0 0
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 2.5 5 7.5 10 12.5 15 17.5
Input Voltage (V) D033
Input Voltage (V) D034
Figure 1. Minimum and Maximum Voltage Transfer Figure 2. Typical Voltage Transfer Characteristics as a
Characteristics Function of Temperature
17.5 17.5 40
VDD = 5 V Gate-to-Source Voltage = 5 V
15 VDD = 10 V 15 35 Gate-to-Source Voltage = 10 V

Output Low (Sink) Current (mA)

VDD = 15 V Gate-to-Source Voltage = 15 V
IO at 5 V 30
12.5 12.5
Supply Current (mA)

IO at 10 V
Output Voltage (V)

IO at 15 V 25
10 10
20
7.5 7.5
15
5 5
10

2.5 2.5 5

0 0 0
0 2.5 5 7.5 10 12.5 15 17.5 0 5 10 15 20 25
Input Voltage (V) D035
Drain-to-Source Voltage (V) D001
Figure 3. Typical Current and Voltage Transfer Figure 4. Typical Output Low (Sink) Current Characteristics
Characteristics
20 0
Gate-to-Source Voltage = 5 V Gate-to-Source Voltage = -5 V
Gate-to-Source Voltage = 10 V
Output High (Source) Current (mA)

17.5 -5 Gate-to-Source Voltage = -10 V

Output Low (Sink) Current (mA)

Gate-to-Source Voltage = 15 V Gate-to-Source Voltage = -15 V

15 -10

12.5 -15

10 -20

7.5 -25

5 -30

2.5 -35

0 -40
0 5 10 15 20 25 -25 -20 -15 -10 -5 0
Drain-to-Source Voltage (V) D002
Drain-to-Source Voltage (V) D003
Figure 5. Minimum Output Low (Sink) Current Figure 6. Typical Output High (Source) Current
Characteristics Characteristics

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Typical Characteristics (continued)

0 120
Gate-to-Source Voltage = -5 V VDD = 5 V
VDD = 10 V
Output High (Source) Current (mA)

Gate-to-Source Voltage = -10 V

Gate-to-Source Voltage = -15 V 100 VDD = 15 V

Propagation Delay Time (ns)

-5
80

-10 60

40
-15
20

-20 0
-25 -20 -15 -10 -5 0 0 20 40 60 80 100 120 140 150
Drain-to-Source Voltage (V) D004
Load Capacitance (pF) D036
Figure 7. Minimum Output High (Source) Current Figure 8. Typical Propagation Delay Time vs Load
Characteristics Capacitance
140
CL = 15 pF
120 CL = 50 pF
Propagation Delay Time (ns)

100

80

60

40

20

0
0 5 10 15 20 25
Supply Voltage (V) D037
Figure 9. Typical Propagation Delay Time vs Supply Voltage

7 Parameter Measurement Information

VDD

VDD

p
G=A
1 (3, 5, 9, 11, 13) A G 2 (4, 6, 8, 10, 12)

VSS

Figure 10. Schematic Diagram of One of Six Identical Inverters

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Parameter Measurement Information (continued)

VDD

VDD
INPUTS

VSS

IDD

VSS

Figure 11. Quiescent Device Current Test Circuit

VDD

INPUTS OUTPUTS

VIH

+ DVM

±
VIL

VSS

Figure 12. Noise Immunity Test Circuit

VDD

INPUTS

VDD

VSS

VSS

Figure 13. Input Leakage Current Test Circuit

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Parameter Measurement Information (continued)

VDD

tr tf

1 14 90%
2 13 Input 50% VDD
Pulse Generator
3 12 10%
tr = tf = 20 ns
IN 4 11
5 10 tTHL tTLH
6 9
10
7 8 90%
Inverting
50% VDD
Output
OUT 10%

CL = 50 pF 200 k tPHL tPLH

Figure 14. Dynamic Electrical Characteristics Test Circuit and Waveform

1/6 CD4069

Rf

RS
XTAL

CS CT

Figure 15. Typical Crystal Oscillator Circuit

1/6 CD4069

IN OUT

Rf § 10 M

Figure 16. High-Input Impedance Amplifier

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Parameter Measurement Information (continued)

1/3 CD4069

CT
RS RT

Figure 17. Typical RC Oscillator Circuit

1/3 CD4069

RS
IN OUT

Rf

Upper Switching Point :

RS Rf VDD
VP u
Rf 2

Lower Switching Point :

R f RS VDD
VN u
Rf 2

R f ! RS

Figure 18. Input Pulse Shaping Circuit

VDD

0.1 F

I 500 F
10 kHz
100 kHz, 1 MHz

1 14
2 13
3 12

CL 4 CD4069UB 11
5 10
6 9
7 8

Figure 19. Dynamic Power Dissipation Test Circuit

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8 Detailed Description

8.1 Overview
The CD4069UB device has six inverter circuits. The recommended operating range is from 3 V to
18 V. The CD4069UB-series types are supplied in 14-pin hermetic dual-in-line ceramic packages (F3A suffix),
14-pin dual-in-line plastic packages (E suffix), 14-pin small-outline packages (M, MT, M96, and NSR suffixes),
and 14-pin thin shrink small-outline packages (PW and PWR suffixes).

8.2 Functional Block Diagram

1 2
A G=A

3 4
B H=B

5 6
C I=C

9 8
D J=D

11 10
E K=E

13 12
F L=F

VDD = Pin 14
VSS = Pin 7

8.3 Feature Description

CD4069UB has standardized symmetrical output characteristics and a wide operating voltage range from 3 V to
18 V with quiescent current tested at 20 V. This has a medium operation speed –tPHL, tPLH = 30 ns (typical) at
10 V. The operating temperature is from –55°C to 125°C. CB4069B meets all requirements of JEDEC tentative
standard No. 13B, Standard Specifications for Description of B Series CMOS Devices.

8.4 Device Functional Modes

Table 1 shows the functional modes for CD4069UB.

Table 1. Function Table

INPUT OUTPUT
A, B, C, D, E, F G, H, I, J, K, L
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CD4069UB device has a low input current of 1 µA at 18 V over full package-temperature range and 100 nA
at 18 V, 25°C. This device has a wide operating voltage range from 3 V to 18 V and used in high voltage
applications.

9.2 Typical Application

Vcc
C

Logic signal LED

Figure 20. CD4069UB Application

9.2.1 Design Requirements

The CD4069UB device is the industry's highest logic inverter operating at 18 V under recommended conditions.
The lower drive capabilities makes it suitable for driving light loads like LED and greatly reduces chances of
overshoots and undershoots.

9.2.2 Detailed Design Procedure

The recommended input conditions for Figure 20 includes rise time and fall time specifications (see Δt/ΔV in
Recommended Operating Conditions) and specified high and low levels (see VIH and VIL in Recommended
Operating Conditions). Inputs are not overvoltage tolerant and must be below VCC level because of the presence
of input clamp diodes to VCC.
The recommended output condition for the CD4069UB application includes specific load currents. Load currents
must be limited so as to not exceed the total power (continuous current through VCC or GND) for the device.
These limits are located in the Absolute Maximum Ratings. Outputs must not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curves

300 100k
Supply Voltage = 5 V

Power Dissipation Per Inverter(PW)

Supply Voltage = 10 V
250 Supply Voltage = 15 V
10k
Transition Time (ns)

200

150 1k

100
100 VDD = 5 V (CL = 50 pF)
50 VDD = 10 V (CL = 15 pF)
VDD = 10 V (CL = 50 pF)
VDD = 15 V (CL = 50 pF)
0 10
0 20 40 60 80 100 120 140 10 100 1k 10k 100k
Load Capacitance (pF) D010
Input Frequency (kHz) D038
Figure 21. Typical Transition Time vs Load Capacitance Figure 22. Typical Dynamic Power Dissipation vs
Frequency

5
Normalized Propagation Delay Time (ns)

0
2 4 6 8 10 12 14 16
Supply Voltage (V) D039
Figure 23. Variation of Normalized Propagation Delay Time (tPHL and tPLH) With Supply Voltage

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
TI recommends a 0.1-μF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-μF or 0.022-μF
capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as
close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs must never float.
In many cases, digital logic device functions or parts of these functions are unused (for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. This rule must be observed under all circumstances specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
See the application note, Implications of Slow or Floating CMOS Inputs (SCBA004), for more information on the
effects of floating inputs. The logic level must apply to any particular unused input depending on the function of
the device. Generally, they are tied to GND or VCC (whichever is convenient).

11.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004

12.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 1998–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: CD4069UB
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD4069UBE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4069UBE
(RoHS)
CD4069UBEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4069UBE
(RoHS)
CD4069UBF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4069UBF

CD4069UBF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4069UBF3A

CD4069UBM ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4069UBM
& no Sb/Br)
CD4069UBM96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4069UBM
& no Sb/Br)
CD4069UBMG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4069UBM
& no Sb/Br)
CD4069UBMT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4069UBM
& no Sb/Br)
CD4069UBNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4069UB
& no Sb/Br)
CD4069UBNSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4069UB
& no Sb/Br)
CD4069UBPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM069UB
& no Sb/Br)
CD4069UBPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM069UB
& no Sb/Br)
CD4069UBPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM069UB
& no Sb/Br)
CD4069UBPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM069UB
& no Sb/Br)
JM38510/17401BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
17401BCA
M38510/17401BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
17401BCA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4069UB, CD4069UB-MIL :

• Catalog: CD4069UB
• Military: CD4069UB-MIL

NOTE: Qualified Version Definitions:

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4069UBM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4069UBM96 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
CD4069UBMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4069UBNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4069UBPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4069UBPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Feb-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4069UBM96 SOIC D 14 2500 367.0 367.0 38.0
CD4069UBM96 SOIC D 14 2500 364.0 364.0 27.0
CD4069UBMT SOIC D 14 250 367.0 367.0 38.0
CD4069UBNSR SO NS 14 2000 367.0 367.0 38.0
CD4069UBPWR TSSOP PW 14 2000 367.0 367.0 35.0
CD4069UBPWR TSSOP PW 14 2000 364.0 364.0 27.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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