Section G6: Practical Op-Amps

So far, in our discussions of op-amps and op-amp circuits, weve been

treating them like ideal devices (remember: v+=v- and i+=i-=0?). Practical
op-amps do approach the behaviors of the ideal, but differ in some very
important respects. To effectively use the op-amp, it is essential that these
differences be understood and taken into account when designing or
implementing op-amp circuits. In this section, we will be defining and
describing the most significant characteristics of the practical device. These
parameters are detailed in tabular and/or graphical form in the
manufacturers specifications and should be consulted before the design
process is begun.

As an introduction, your author provides a tabular listing of some of the data

for the three op-amps, along with the characteristics of the ideal device.
Note that information on the data sheet is defined with respect to specified
operational conditions and that, if significant deviation is made from these
defined conditions, all bets may be off! Were going to discuss the modeling
of all of these characteristics in this section with the exception of bandwidth
and slew rate. The treatment of these two parameters will be deferred until
section H, when we discuss frequency response.

Table 9.1: Parameter values for op-amps

Ideal General- High- Low-
Device purpose speed noise
741 715 5534
Open-loop voltage gain, Go(V/V) 105 3x104 105
Output impedance, Zo() 0 75 75 0.3
Input impedance, Zin()
(open loop) 2x106 106 105
Offset current, Iio (nA) 0 20 250 300
Offset voltage, Vio (mV) 0 2 10 5
Bandwidth, BW (MHz) 1 65 10
Slew rate, SR (V/s) 0.7 100 13

Open-Loop Voltage Gain (Go)

Note: there is some discrepancy in your text as to the notation for

open loop gain. I will try to maintain consistency in these notes, but
if theres any question, please let me know!

The open-loop voltage gain (Go) of an op-amp is defined as the ratio of the
output voltage to the input voltage without feedback. This is a
dimensionless quantity that may be listed on a spec sheet in terms of volts
per millivolt (V/mV) or in decibels (dB), where

v out V v
Go = or G o = 20 log out (dB) .
v in mV v in

Modified Op-Amp Model

Figure 9.14, reproduced to the left below, illustrates a modified version of

the ideal op-amp model (The ideal op-amp model is repeated to the right
below for comparison purposes). In the figure on the left (the modified
version), everything inside the dashed box is internal to the device, with v+,
v-, and vout representing the connections for the non-inverting, inverting,
and output terminals.

As seen from the above figures, the first step in developing a practical model
is to remove the idealized behaviors of the input and output resistances, Rin
and Ro respectively, as well as incorporating the effect of the common mode
resistance, Rcm (Rcm for the ideal op-amp). The effect of Rcm is split
between the inverting and non-inverting terminals, for an equivalent of 2Rcm
in each path. Note that this is a strategy similar to the one we used in our
analysis of the common-mode operation of the differential amplifier. In this
case, if vd=v+-v-=0, the two legs are in parallel and we have
2Rcm||2Rcm=Rcm. The typical values of Ri, Ro and Go for the 741 op-amp are
listed in the table above as 2M, 75, and 105 V/mV, respectively. Your
author gives a representative value for the 741 common-mode resistance as
200M.

An op-amp circuit with a

single inverting input (vA),
fed through resistor RA, and
a single non-inverting input
(v1), fed through resistor
R1, is shown in Figure 9.15
and is given to the right. The resistor RF is the feedback resistor that
connects the op-amp output to the inverting input. Once again, the dashed
line indicates the separation of the op-amp model (inside the box) with
external parameters (components, measurements, etc.).

Input Offset Voltage (Vio)

For an ideal op-amp, if there is no applied input voltage(s), the difference

voltage (vd=v+-v-) is equal to zero and the output is also equal to zero. Not
surprisingly, this is not true for a practical device since it virtually impossible
to have perfect symmetry in the input stage circuitry. The input offset
voltage, Vio, is defined as the differential input voltage required to make the
output voltage exactly equal to zero. Vio is a small, but non-zero, value that
is defined on the spec sheet for the device (using the 741 again as an
example, Vio=2mV from the earlier table). A
technique for measuring Vio is shown in Figure 9.16
and is given to the right. By tying v+ and v- to
ground, the input voltage is forced to zero. Any
voltage measured at the output for a zero input is
known as the output dc offset voltage. The input
offset voltage may then be calculated by dividing
this measurement by the open-loop gain (Go) of the op-amp. Any non-zero
value of Vio is undesirable because, since the gain of the device is so large,
any offset is amplified and causes a larger dc error at the output.

The effect of the input offset

voltage may be incorporated into
our evolving op-amp model as
shown in Figure 9.17 and to the
right. If no internal offset
compensation is provided by the
op-amp, Figure 9.18 of your text
illustrates a method for canceling
out the effect of Vio using an
external balancing circuit at the inverting (Figure 9.18a) and non-inverting
(Figure 9.18b) input.

Input Bias Current (IBias)

The ideal op-amp draws no input current (i+=i-=0) due to an infinite input
impedance. For the practical device, the input impedance is finite and some
bias current does enter each input terminal. The input bias current, IBias, is
defined as the dc current into the input transistors (Q1 and Q2 of the 741
circuitry) and, according to your author, has a typical value of 2 A.
The bias current may be modeled as the two
current sinks labeled IB+ and IB-, as shown in Figure
9.19 and to the right. The values of these sinks are
independent of source impedance, but do have a
dependence on temperature. Your author defines
the input bias current as the average value of the
two current sinks, or

I B+ + I B
I Bias = , (Equation 9.40)
2

while the difference between the two sink values is known as the input
offset current, Iio,

I io = I B + I B . (Equation 9.41)

Both the input bias current and the input offset current are temperature
dependent. The temperature coefficient of each of these parameters is
defined as the ratio of the change in current to the change in temperature. A
typical value for the input bias current temperature coefficient is given
by your author as 10nA/oC, while that for the input offset current
temperature coefficient is 2nA/oC.

If we assume that the input offset

current is negligible by defining

I B+ = I B = I B , (Equation 9.42)

the input bias currents may be

incorporated into our op-amp
model as illustrated in Figure
9.20, reproduced to the right.

To analyze the model and determine the output

voltage caused by the input bias currents, we used
the circuit given in Figure 9.21a (to the right). In
this circuit, the inverting and non-inverting inputs
are tied to ground through resistances RA and R1,
respectively. The resistor RF again serves to provide
a feedback path between output and input.
The op-amp is replaced by the device model in Figure 9.21b (below and to
the left). Figure 9.21c (below and to the right) presents the first series of
simplifications to the equivalent circuit. Specifically, we are assuming

Vio is negligible and may be removed. This allows us to define the

equivalent resistances RA and R1, where

R A' = R A || 2Rcm and R1' = R1 || 2Rcm .

Ro is small enough that it may be neglected (replaced with a short

circuit); i.e., RF>>Ro and RL>>Ro. This allows us to remove the load
resistor, RL, and measure the output voltage directly as Govd.

The circuit is further simplified in Figure 9.21d (below and to the left) when
the series combination of voltage source and resistor is replaced with a
parallel combination of current source and resistor (the Norton equivalent).
The final (really, really) simplified circuit is given in Figure 9.21e (below and
to the right), where the parallel resistances RA and RF are combined into a
single equivalent resistance and the parallel current source-resistance
combinations [(IB-Govd/RF),RA||RF and IB, R1] have been replaced with
series voltage source-resistance combinations.
Using the final simplification of Figure 9.21e, your author states that we can
write a KVL to solve for the output voltage (remember that vout=Govd from
Figure 9.21c). After some serious voodoo (aka, algebra), he comes up with

Go R'1 (R' A || RF R'1 )I B (R' A +RF )

v out = G ov d = , (Equation 9.43)
(R' A +RF )(Ri n + R' A ) || (RF + R'1 ) + G o R'1 R' A

where (summarizing our earlier approximations and simplifications):

R' A = R A || 2Rcm ; R'1 = R1 || 2Rcm

. (Equation 9.44)
RF >> Ro ; RL >> Ro

For practical circuits, since the common-mode resistance is much larger than
any single (or equivalent) resistance applied to the inputs, we can make the
approximation that

R' A R A and R'1 R1 (Equation 9.45)

in Equation 9.43. If we further assume that Go is very large, the second term
in the denominator may be considered dominant. Your author states that,
with these simplifications, the output voltage may be expressed by

R
v out = 1 + F I B (R A || RF R1 ) . (Equation 9.46)
RA

In Equation 9.46, note that if R1 is selected to be equal to RA||RF, the output

voltage will be zero regardless of the value of IB. This implies that the dc
resistance from the positive source, +V, to ground should be equal the dc
resistance from the negative source, -V, to ground. This bias balance
constraint is used often in design. It is important in any design that both
the inverting and non-inverting terminals have a dc path to ground to reduce
the effects of the input bias current.

Common-Mode Rejection

The operational amplifier is normally operated in differential mode, i.e., to

amplify the difference between the two input voltages (v+ and v-). Ideally,
any common-mode voltage, a constant voltage that is added to each of the
two inputs, should not affect this difference and should not be propagated to
the output. However (big surprise), this constant value at the inputs does
affect the output in the practical case.
To calculate the common-mode
voltage gain, Gcm, a strategy similar
to that for the input offset voltage is
employed. The inverting and non-
inverting terminals of the op-amp are
again tied together, but now they are
tied to a common source, vcm. For an
ideal device the output would be zero,
but for a practical device, some output
voltage, vout, will be measured. The
common-mode voltage gain is simply the ratio of this measured output to
the applied input, as illustrated in the figure above. The definition of the
common-mode rejection ratio (CMRR) for the op-amp is the ratio of the
magnitude of the dc open loop gain, |Go|, to the magnitude of the common-
mode gain, |Gcm|. The CMRR may be expressed linearly or, more commonly,
as a dB value:

| Go | | Go |
CMRR = or CMRR = 20 log dB . (Equation 9.47)
| G cm | | G cm |

The CMRR for an ideal device would be infinity. It is desirable to have the
CMRR as high as possible, with typical values ranging from 80 to 100 dB.

Output Resistance

Because of the dependent source in the output circuit of the op-amp model,
we must use the strategy of applying a test voltage and calculating the
resulting current to determine the output resistance, where

v test
Rout = .
i test

The resulting circuit is shown to

the right (a modified version of
Figure 9.25a), where the input
bias current, the input offset
current, and the input offset
voltage have been ignored. All
independent sources (v1 and vA)
have also been grounded, so the
inverting and non-inverting
terminals are tied to ground
through RA and R1, respectively.
Figure 9.25b (below and left) is the same circuit as Figure 9.25a, just
redrawn to use a common ground (prove this to yourself!). Figure 9.25c
(below and right) is a simplified circuit, with the parallel resistor
combinations of RA, 2Rcm and R1, 2Rcm combined to form equivalent
resistances RA and R1:

R' A = R A || 2Rcm , R'1 = R1 || 2Rcm . (Equation 9.48)

If we make the assumption that RA <<

(R1+Rin) and Rin >> R1 (which is
completely valid since the input
impedance of the op-amp is so large)
the circuit of 9.25d, given to the right,
is our final result. The input differential
voltage, vd, may be found from this
circuit by using voltage division:

R' A v test
vd = . (Equation 9.49)
R' A +RF

To find the output resistance, we being by writing a KVL equation about the
output loop and then substitute the above expression for vd.

R' A v test
v test = i test Ro + G ov d = i test Ro + G o .
R' A + RF

Rearranging the above expression to collect the terms that contain vtest, we
obtain

G o R' A
i test Ro = v test 1 + . (Equation 9.50)
RF + R' A
The output resistance is then given by

Ro
R out = . (Equation 9.51)
G o R' A
1 +
RF + R' A

In most cases, Rcm is so large that RARA and R1R1. Equation 9.51 may be
further simplified by realizing that GoRA/(RF+RA) is the dominant term in the
denominator since it is >> 1, yielding

Ro R
Rout = 1 + F . (Equation 9.52)
Go RA

Power Supply Rejection Ratio

The power supply rejection ratio (PSRR) is a measure of the ability of the
op-amp to ignore any variations in the power supply voltage and is defined
as the ratio of the change in vout to the total change in the power supply
voltage. If, for example, the output stage of an amplification system draws a
current that varies, the supply voltage could also vary. This load-induced
change in supply voltage could then cause changes in the operation of any
other amplifiers that share the same supply. This is known as crosstalk, and
may lead to signal degradation and/or instability of the entire system. To
decrease any variation in supply voltage, the power supply for each group of
op-amps should be decoupled, or isolated, using capacitors, from those of
other groups to confine any interaction to a single group of devices. The
PSRR is usually specified in microvolts per volt (V/V) or in decibels (dB),
with typical values of about 30V/V ( -90.5dB).