Innovations in

Wafer Level Technology

A proven leader in Wafer Level Packaging technology
The demand for breakthrough performance in cost effective As die sizes and lithography nodes shrink, STATS ChipPAC is
solutions has driven integration technology to new levels of actively pushing the boundaries of traditional paradigms by
complexity in semiconductor package designs. The mobile pioneering a number of enabling integration technologies in
market is accelerating demand for more compact and com- wafer level packaging. STATS ChipPAC is an industry leader in
plex semiconductor packages that are challenging traditional providing a comprehensive platform of advanced wafer level
packaging technology in the areas of form factor, reliability solutions including Fan-out Wafer Level Packaging (FOWLP),
and performance, and integration is increasingly moving from Fan-in Wafer Level Packaging (FIWLP), Through Silicon
substrate-based package configurations to more complex wafer Via (TSV) and Integrated Passive Devices (IPD) for mobile
level package designs. handsets, smartphones, tablets and wearable devices.

A new paradigm in Wafer Level manufacturing: FlexLine

200mm Backgrinding and dicing FIWLP or FOWLP packages
A single (including 2.5D and 3D eWLB)
manufacturing
300mm Backgrinding and dicing module with
optimized
panel size
450mm Backgrinding and dicing

Si wafer backgrind
FlexLine is an innovative manufacturing approach that provides Backgrind (opt)
freedom from wafer diameter constraints, while enabling supply
chain simplification and significant cost reductions not possible Si wafer dicing
Laser marking
with a conventional manufacturing flow. This breakthrough
approach delivers unprecedented flexibility in producing both Reconstitution
Pkg singulation
fan-out wafer level packages (FOWLP) and fan-in wafer level
chip scale packages (WLCSP) on the same manufacturing line. Redistribution
Pkg pick and place
The FlexLine method is based on the advanced manufactur-
ing process for FOWLP technology known as embedded Wafer Ball drop / reflow
Level Ball Grid Array (eWLB). What is unique to the eWLB Ship in TnR
manufacturing process is the wafer reconstitution step where Panel probe
the incoming wafers are diced at the start of the process and
then the die are reconstituted into a uniform wafer or panel size.
The FlexLine process flow leverages the eWLB
Fan-Out package process
Leveraging the Fan-Out manufacturing process
By normalizing incoming wafer diameters to a uniform The FlexLine advantage is available in a wide range of wafer
processing size, the original wafer diameter no longer level packages.
dictates manufacturing or process capabilities. The FlexLine
method can seamlessly process any incoming silicon 3D
below
3D eWLB with Interposer 3D Face-to-Face (2S)
diameter without a change in equipment set or bill of 0.6mm

materials used in the packaging process. eWLB-PoP (1.5S)

Now one qualified manufacturing source can provide FIWLP

and FOWLP, including 2.5D and 3D eWLB, using the same
2.5D 2.5D/Extended eWLB
equipment, device structures, material sets and location.
And, as the FlexLine panel size increases, it effectively low-
ers the overhead processing cost per unit, and provides semi-
2D eWLL Flip Chip eWLB
conductor customers with a cost effective solution for current below
0.4mm eWLCSP
and future wafer level technologies.
Single chip Multi-chip
The FlexLine process has been qualified at advanced silicon
nodes down to 28nm, ball pitches down to 0.40mm and body
sizes as small as 2.5x2.5mm.

A new path for 3D integration: embedded Wafer Level BGA (eWLB)

3D
eWLB is a versatile platform for
2D, 2.5D and 3D integration
that delivers significant product 2.5D

advantages in terms of higher

input/output (I/O) and thinner profiles in a reliable, cost
2D
effective package. A powerful FOWLP technology, eWLB has
the design flexibility to accommodate an unlimited number of
interconnects and is unconstrained by die size. This enables Unique multi-die 2.5/3D integration
eWLB to deliver maximium connection density, improved with a quantum leap
electrical and thermal performance and smaller package in density and form factor
dimensions to meet the relentless form factor and performance
STATS ChipPAC offers the most comprehensive Fan-Out
requirements of the mobile market, and is now the preferred
portfolio in the industry:
packaging solution in smartphones, tablets and wearable
devices. Wide range of small die, large die, flip chip, stacked or
side-by-side multi-die and ultra-thin options
One of the first companies to ramp eWLB to high volume pro-
Body sizes: 2.2 x 2.2mm 14 x 14mm and expanding
duction, STATS ChipPAC is an industry leader in eWLB tech-
(package size dependent on die size)
nology, providing innovative package designs and an efficient
manufacturing process that is well-suited for a multitude of 2.5D eWLB interposer solutions (replaces stacked
complex and highly integrated solutions including 2.5D and package configurations or to enable 3D TSV)
3D integration, including Si partitioning. 3D System-in-Package (SiP) and Package-on-Package
STATS ChipPACs 2.5D and 3D solutions offer more cost (PoP) solutions include multiple embedded passives
effective and infrastructure-friendly alternatives to TSVs by and active components, face-to-back or face-to-face
achieving tighter line/spaces for a range of configurations that options, and single-sided, 1.5-sided and double-sided
deliver product advantages to customers in terms of higher PoP configurations (total stacked
performance, higher frequencies, higher bandwidth and thin- PoP height <1.0mm)
ner package profiles.
Fan-In WLP: Wafer Level Chip Scale Packages (WLCSP)
As a small, lightweight, high performance semiconductor
solution, WLCSP is a FIWLP technology that offers compelling
packaging solutions for cost and space constrained mobile
devices and new applications such as wearable technology.
WLCSP is a true Chip Scale Packaging (CSP) technology where
the package is the same size as the die, and the cost per pack-
age is primarily determined by the number of die per wafer
rather than the number of I/O per device.
STATS ChipPAC offers high performance WLCSP solutions
that provide significant package footprint reductions, lower
cost, improved electrical performance, and a relatively simpler
construction over conventional wirebond or interposer packaging
technologies.

The FlexLine advantage: encapsulated WLCSP (eWLCSP)

Utiliziing the FlexLine manufacturing sidewall
approach, STATS ChipPAC has developed
an innovative packaging technology called
encapsulated Wafer Level Chip Scale Package (eWLCSP).
eWLCSP offers significant structural advantages over
traditional WLCSP designs. As a bare die package, WLCSP
is regularly exposed to potential cracking, chipping and
handling issues that can occur before or during the SMT
assembly process. This is particularly true for advanced node
products where the die is very thin and dielectric layers are
extremely fragile.
eWLCSP is equivalent to a conventional WLCSP product
with the addition of a thin protective coating on the backside sidewall
and four sidewalls of the die, achieving increased durability
and reliability within the standard WLCSP size specification. Encapsulation offers sidewall
Standard WLCSP eWLCSP with sidewall
protection

FlexLine eWLCSP Cost Reductions

A product currently using a conventional WLCSP process can
Encapsulation offers a variety of advantages:
be converted to eWLCSP without any silicon design change
Light and mechanical protection required, regardless of the current silicon wafer diameter.
Alleviates die chipping The FlexLine method can reduce WLCSP costs by 15-30%
Enables more effective positioning on the printed when using the optimum design requirements for WLCSP
circuit board (PCB) devices. For example, using the FlexLine method, 200mm
Protects the silicon during socket insertion for test incoming wafers can be reconstituted into 300mm or larger
In addition, eWLCSP electrical performance is equivalent panel sizes, providing customers with the advantage of panel
to WLCSP with proven results in component level reliability size scaling--with further per-unit cost reductions as panel
(CLR), temperature cycle on board (TCoB) and drop test. sizes increase.
Integrated Passive Devices (IPD) Through Silicon Vias (TSV)
Passive devices such as resistors, STATS ChipPAC was one of the first OSAT providers to invest in
capacitors, inductors, filters and back-end of line (BEOL) manufacturing capabilities for 2.5D
baluns can consume 60-70% and 3D TSV technology. STATS ChipPACs BEOL services
of available space in a system, include chip-to-chip and chip-to-wafer assembly with stealth
subsystem or System-in-Package dicing and fine pitch micro-bump bonding down to 40um.
(SiP). One of the first companies STATS ChipPACs TSV capabilities also include 300mm mid-
in the industry to integrate and end of line (MEOL) processing capabilities in areas such as
fabricate passive devices at the silicon wafer level, STATS TSV formation and metallization, bumped wafer thinning, thin
ChipPAC is able to produce IPDs which are significantly small- wafer handling, 3D microbump bonding, wafer-level underfill
er, thinner and higher performing than standard discrete pas- and TSV assembly.
sive devices that are commercially available today. With this
To provide a bridge between todays 2D packaging solutions
knowledge and experience, STATS ChipPAC has been able to
and next-generation 3D technology, STATS ChipPAC also offers
embed passive devices in very close proximity to the active die,
TSV interposer processing and assembly. TSV interposers
providing significant performance, size reduction and device
provide flexibility for the integration of die from different
integration in System-in-Package (SiP) configurations that
technology nodes and deliver advantages in miniaturization,
address 2.5D and 3D integration requirements.
thermal performance and fine line/width spacing in a semi-
conductor package.

STATS ChipPACs WLP centers of excellence

Ichon, Korea
Shanghai, China SCK : 770K ft2 facility
SCC : 983K ft2 facility SCK2 : 212K ft2 facility

Singapore
Corporate Headquarters

Hsin-Chu Hsien, Taiwan

SCT : 218K ft2 facility
300mm Bumping, WLCSP,
Yishun, Singapore
Probe & Final Test
SCS : 808K ft2 facility
FlexLine, eWLB, eWLCSP,
WLCSP, IPD, Full Turnkey,
Probe & Final Test Woodlands, Singapore
SCH-WD : 51K ft2 facility Customer Support /Sales Office
R&D in Wafer Level Manufacturing Facility
technologies

To find out more about STATS ChipPACs Wafer Level technology offering,
visit us online at www.statschippac.com