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    Analog - RF VLSI Design (ECE 503) (Makeup) PDF

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    Rahul Pinnamaneni
    This document is an exam for an analog and RF VLSI design course. It contains 6 questions with multiple parts each related to analog and RF circuit design topics. Students are instructed to answer any 5 full questions from the exam, which covers concepts such as current sinks, op-amps, gain calculations, PLLs, and differential circuits.

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    © All Rights Reserved
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    Analog - RF VLSI Design (ECE 503) (Makeup) PDF

    Uploaded by

    Rahul Pinnamaneni
    411 views2 pages
    This document is an exam for an analog and RF VLSI design course. It contains 6 questions with multiple parts each related to analog and RF circuit design topics. Students are instructed to answer any 5 full questions from the exam, which covers concepts such as current sinks, op-amps, gain calculations, PLLs, and differential circuits.

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    Analog _ RF VLSI Design (ECE 503) (Makeup).pdf

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    This document is an exam for an analog and RF VLSI design course. It contains 6 questions with multiple parts each related to analog and RF circuit design topics. Students are instructed to answer any 5 full questions from the exam, which covers concepts such as current sinks, op-amps, gain calculations, PLLs, and differential circuits.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    411 views2 pages

    Analog - RF VLSI Design (ECE 503) (Makeup) PDF

    Uploaded by

    Rahul Pinnamaneni
    This document is an exam for an analog and RF VLSI design course. It contains 6 questions with multiple parts each related to analog and RF circuit design topics. Students are instructed to answer any 5 full questions from the exam, which covers concepts such as current sinks, op-amps, gain calculations, PLLs, and differential circuits.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Reg. No.

    MANIPAL INSTITUTE OF TECHNOLOGY


    Manipal University
    FIRST SEMESTER M.TECH (DEAC and MICRO) END SEMESTER EXAMINATION
    DECEMBER 2013
    SUBJECT: ANALOG AND RF VLSI DESIGN (ECE - 503)

    TIME: 3 HOURS MAX. MARKS: 50

    Instructions to candidates
    Answer ANY FIVE full questions.
    Missing data may be suitably assumed.
    1A.Find output resistance of the double cascode current sink designed to sink a current
    of 20 A. Given that VDD = - VSS = 2.5 V,VGS = 1.2 V, Vth = 0.83 V, W/L=10 m / 5
    m, n.Cox = 50 A/V2, = 0.06 V-1. Find the minimum voltage across the current
    sink.

    1B.Explain the channel length modulation.

    1C. Discuss the need for Layout with width correction for current mirror circuits.(4+3+3)

    2A.Explain the advantages of two-stage op-amp. Discuss the different two-stage op-amp
    topologies with their merits and demerits. Why op-amps having more than two stages
    are rarely used?

    2B. In a NMOS CD amplifier with a current sink load, all transistors have W/L=100 m/
    2 m.Given that Iref =100 A, = 0.1, Kn= 75 A/V2, Kp= 30 A/V2,rds-n = 128 k,
    rds-p= 192 k. Find Av, Rout.

    2C.Explain how a 3-MOSFET voltage divider circuit can be used to bias cascode current
    sink. (5+3+2)

    3A.Give the schematic circuit of NMOS common source amplifier with a current mirror
    active load. Assume all transistors have and
    , . Find the
    voltage gain and output resistance.

    3B.Define and explain the significance of following parameters with respect to MOS
    device: (i) (ii) (iii) (iv)

    3C.State why long channel devices are used in analog design? (5+4+1)
    4A.Calculate the small-signal voltage gain Av for NMOS (M1) CS stage with diode-
    connected PMOS load (M2). Given that (W/L)1= 50/0.5, (W/L)2 = 10/0.5, n = 2.5 p
    and Ids1 = Ids2 = 0.5 mA. Assume = 0.
    ECE - 503 Page 1 of 2
    4B. Derive the expression for small-signal voltage gain for the circuit shown in FIG. 4B
    assuming = = 0.

    4C.Explain how the differential operation can reduce the following: (i) effect of supply
    noise (ii) Effect of coupled noise from digital clock signal. (3+5+2)

    5A.Consider a NMOS CG amplifier with a passive resistive load . Derive the


    expression for following: (i) small-signal voltage gain (ii) input impedance (iii)
    output impedance considering with and without channel length effect. Give your
    comments.
    5B.With a schematic circuit, explain the working of basic operational transconductance
    amplifier circuit. (8+2)
    6A. Explain the basic PLL block diagram with necessary analog building blocks. Sketch
    and explain the different waveforms of PLL in locked condition.
    6B.Explain the use of following analog blocks: (i) Mixers (ii) RF synthesizers

    6C. Show that feed-forward path through in a CS stage introduces zero in the
    transfer function. (5+2+3)

    VDD

    RD
    Vo

    M1
    Vi

    M2

    FIG. 4B
    *********

    ECE - 503 Page 2 of 2

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