L9177

Peripheral on chip for low end engine control

Datasheet - production data

Serial driving
Output internally clamped to 45 V
Minimum guaranteed output current 1 A
(2 A during in-rush)
'!0'03

Ron 1.5 worst case (at Tj = 150 C)

PowerSO46
Stepper motor driver
Parallel driving
Features Minimum guaranteed output current
500 mA - full step
Supply voltage from 6 V to 18 V
Ron 2.6 worst case on the diagonal
Basic functionality guaranteed down to 3.9 V (at Tj = 150 C)
5 V regulator up to 300 mA with thermal O2 sensor heater
shutdown protection in current limitation
Parallel and serial driving
condition
Output internally clamped to 45 V
5 V tracking regulator up to 40 mA and short to
Minimum guaranteed output current 3 A
battery protection
Ron 0.5 worst case (at Tj = 150 C)
5 V standby regulator up to 2.5 mA
Protected high side driver
2 channels injectors drivers
100 mA min. current limitation threshold
Parallel and serial driving
Full diagnosis by SPI
Output internally clamped to 60 V
Injector driver: OL, STG, OC
Minimum overcurrent at 2.8 A
Relay and Lamp drivers: OL, STG, OC
Ron 0.6 worst case (at Tj = 150 C)
O2 sensor heater: OL, STG, OC
3 relay drivers
Tachometer: OL, STG, OC
2 with parallel and serial driving, 1 with
Stepper motor driver: OL, STG, STB, OC
serial driving
general diagnostic: over-temperature
Output internally clamped to 45 V
Minimum guaranteed output current 1 A Protection for STB, STG (for stepper motor
drivers and tracking regulator)
Ron 1.5 worst case (at Tj = 150 C)
Self configuring variable reluctance sensor
Tachometer driver
interface
Parallel and serial driving
K-line transceiver
Minimum guaranteed output current 25 mA
Ron 5 worst case (at Tj = 150 C) Microcontroller reset logic
Lamp driver Packaged in PowerSO46

Table 1. Device summary

Order code Package Packing

L9177 Tube
PowerSO46
L9177TR Tape and reel

November 2013 DocID17617 Rev 1 1/49

This is information on a product in full production. www.st.com
Contents L9177

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Latch-up test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2 Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Digital output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.5 5 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.7 5 V tracking voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.8 Standby regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.9 High side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.10 Injector driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.11 Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.12 Lamp driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.13 Tachometer driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.14 Stepper motor driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.15 O2 sensor heater driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.16 Variable reluctance sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5.17 K-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.18 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Chip working conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Chip bias current generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/49 DocID17617 Rev 1

L9177 Contents

4.3 Power up/down sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.1 Data in (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.2 Data out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.1 Voltage regulators thermal warning and shutdown . . . . . . . . . . . . . . . . 33
4.5.2 Overvoltage shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.3 Undervoltage shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.4 Low side on/off diagnosis (INJ, RLY's, TACH, O2H) . . . . . . . . . . . . . . . 34
4.5.5 Lamp driver on/off diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5.6 Stepper motor driver off diagnosis (EN signal high and output in high
impedance state) 36
4.5.7 Stepper motor driver on diagnosis (EN signal Low and output driven by
input commands) 36
4.5.8 VRS diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6 VRS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6.1 Function characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6.2 Auto-adaptative hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.6.3 Auto-adaptative time filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5 Low side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DocID17617 Rev 1 3/49

3
List of tables L9177

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Key electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Digital pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Digital output pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. VDD output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 12. Reset function electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. VDD_TRK output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. VDD_SB output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. HS_OUT output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. Injector driver electrical characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 17. Relay driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 18. Lamp driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 19. Tachometer driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 20. Stepper motor driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 21. O2 sensor heater driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 22. Variable reluctance sensor interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 24
Table 23. K-Line interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 24. SPI characteristics and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 25. L9177 outputs working conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 26. Data in (DIN) words content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 27. Data in command bits structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 28. Data in VRS hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 29. Data out (DOUT) words content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 30. Two bits diagnosis (normal drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 31. Three bits diagnosis (bridge stage). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 32. Peak voltage detector precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33. Hysteresis threshold precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 34. Values for IPx and INx current generators for each low side . . . . . . . . . . . . . . . . . . . . . . . 44
Table 35. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 36. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4/49 DocID17617 Rev 1

L9177 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Input threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Key block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. 5 V main regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. 5 V tracking regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. 5 V standby regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. High-side driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Low-side driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Low-side timing diagram (injectors, relays, lamp, tach, O2H). . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Stepper motor driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Stepper motor operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. VRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. K-line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. -SO loading for disable time measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. Current generator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21. L9177 under and over voltage time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. Low side driver diagnosis time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. Low side driver diagnosis I-V relationship. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 24. Lamp driver diagnosis time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 25. Stepper motor driver diagnosis time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. Stepper motor driver diagnosis I-V relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 27. VRS diagnosis I-V relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 28. VRS typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29. VRS interface structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 30. Auto-adaptive hysteresis block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 31. Hysteresis output voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 32. Input-output behavior of VRS interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 33. Auto-adaptative time filter behaviour 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 34. Auto-adaptative time filter behaviour 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 35. Low side drivers slew rate implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 36. Low side drivers slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 37. O2H low side driver slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 38. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 39. PowerSO46 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DocID17617 Rev 1 5/49

5
Description L9177

1 Description

L9177 is a device realized in ST BCD proprietary technology, able to provide the full set of
power supplies and signal preprocessing peripherals needed to control a 2 Cylinder internal
combustion Engine for Low End Application (e.g. small motorcycle, K-car, nautical engines,
etc.).
L9177 integrates a 5 V main voltage regulator, a 5 V 40 mA tracking regulator for sensor
supply and a 2.5 mA 5 V standby regulator.
The two channels injector drivers, the O2 sensor heater and two relay drivers can be
controlled both with parallel input and with SPI interface. One additional relay driver and the
lamp driver are controlled by SPI. The stepper motor driver is designed for a double winding
coil motor, used for engine idle speed control.
Low side drivers implement SR control to minimize emission.
A protected 50 mA high side driver is provided.
A Variable Reluctance Sensor interface allows the connection to a commercial magnetic
pick-up, allowing the indirect measurement of internal combustion engine crank angle. A K-
line (standard ISO-9141 compatible) is provided as data communication interface.
All functionalities are fully protected and provide complete diagnostics via a 24bit SPI
interface. An overall protection against over temperature is provided as well.
The device is available in PowerSO46, ST proprietary package for high power application.

6/49 DocID17617 Rev 1

L9177 Block diagram and pin description

2 Block diagram and pin description

2.1 Block diagram

Figure 1. Block diagram
6$$ 6$$?42+ 6$$?3" (3?/54

6"?
6REGULATORM!

6TRACKING6REG
M!

6ST BY6REGM!
3TANDBYMODE
+%9
/PERATINGMODE
(3SWITCHM!

2%3%4 2%3%4
).*%#4/2$2)6%2#(!..%,
).*
). $IAGNOSIS /VER CURRENT!
). /PEN,OAD 6#LAMP ).*
/VER CURRENT 2/.OHM
3HORTTO'.$ '.$?).*
62).
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62).
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DocID17617 Rev 1 7/49

48
Block diagram and pin description L9177

2.2 Pin description

Figure 2. Pin connection (top view)

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Table 2. Pin function

I/O
Pin # Pin name Description Class
type

1 GND Analog and power ground GND PWR

2 OUTB Output bridge 1 O PWR
3 OUTA Output bridge 1 O PWR
4 VB_1 Battery line to bridge1 I PWR
5 EN Logic input to enable stepper motor I SIGNAL
6 DIR Logic input to set stepper motor direction I SIGNAL
7 VDD_TRK Tracking voltage regulator output O PWR
8 REXT External resistor for precision current reference I SIGNAL
9 HS_OUT High side switch output O PWR
10 VRIN+ VRS positive differential input I SIGNAL
11 VRIN- VRS negative differential input I SIGNAL
12 VROUT VRS output O SIGNAL
13 O2H O2 sensor heater output O PWR

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L9177 Block diagram and pin description

Table 2. Pin function (continued)

I/O
Pin # Pin name Description Class
type

14 TACH Tachometer driver output O PWR

15 ILS_TACH Tachometer driver input I SIGNAL
16 GND_O2H O2 sensor heater ground GND PWR
17 INO2H O2 sensor heater input I SIGNAL
18 RESET Reset signal to the micro O SIGNAL
19 IN_REL2 Relay 2 parallel control input I SIGNAL
20 IN_REL1 Relay 1 parallel control input I SIGNAL
21 REL2 Relay 2 driver output O PWR
22 GND_P_1 Power ground relay 1-2 O PWR
23 REL1 Relay 1 driver output O PWR
24 REL3 Relay 3 driver output O SIGNAL
25 GND_P_2 Power ground for lamp GND PWR
26 LAMP Lamp driver output O PWR
27 SO SPI data out O SIGNAL
28 SI SPI data in I SIGNAL
29 SCK SPI serial clock I SIGNAL
30 CS SPI chip select I SIGNAL
31 KEY Key signal I SIGNAL
32 INJ1 Injector 1driver power output O PWR
33 IN1 Injector 1 driver input command I SIGNAL
34 GND_INJ1 Injector 1 ground GND PWR
35 GND_INJ2 Injector 2 ground GND PWR
36 IN2 Injector 2 driver input command I SIGNAL
37 INJ2 Injector 2 driver power output O PWR
38 KL_TX K-Line TX digital IN I SIGNAL
39 KL_RX K-Line RX digital OUT O SIGNAL
40 KL_LINE K-Line I/O PWR
41 VDD 5 V voltage regulator output O PWR
42 PWM Logic Input to set Stepper Motor Speed I SIGNAL
43 VDD_SB 5 V standby voltage regulator output O PWR
44 VB Battery line to bridge 2 I PWR
45 OUTD Output bridge 2 O PWR
46 OUTC Output bridge 2 O PWR

DocID17617 Rev 1 9/49

48
Electrical specifications L9177

3 Electrical specifications

3.1 Operating range

The device may not operate properly if maximum operating conditions are exceeded.

Table 3. Operating conditions

Symbol Parameter Value Unit

VB Supply voltage 6 to 18(1) V

I/O logic 0 to Vdd V
Stepper motor outputs -0.3 to Vb+ V
-0.3 to clamp
Low side V
voltage
1. Below 3.9 V the device is in a safety state (internal circuitries are on but all the outputs are off).

From 3.9 V to 5.5 V (cranck functionality)

Reset function; VDD > 3.3 V (rds-on state) IVDD=100mA; 3.3 V<VDD_TRK<VDD (rds-on state);
Low-sides, K-Line, H-Bridge OFF if Reset = 0; SPI not available, internal registers resetted if Reset = 0;
All Diagnosis disabled if Reset=0; VRS function limited (Vdiff max =1000mV).

From 5.5 V to 6 V (low battery)

All the functions are granted with the following degraded parameters; VDD5>4.510V; VDD Reset
function guaranteed, but no Reset asserted; Tracking error < 100 mV (Iload = 40 mA, rds-on state).

From 18 V to VB_off (load dump transient)

All the functions are granted with increased power dissipation and no reset is asserted during transient.

From VB_off to 40 V (internal circuitries are on but all the outputs are off)
The device is on in a safety state.

3.2 Absolute maximum ratings

Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.

Table 4. Absolute maximum ratings

Parameter Condition Min Max Unit

DC supply voltage pin VB/VB_1 -0.3 40 V

I/O low voltage pins(1) - -0.3 7 V
I/O low voltage digital
- -0.3 Vdd+0.3 V
pins(2)
I/O power pins(3) voltage
- -0.3 Clamp voltage V
range
TACH pin - -0.3 40 V
OUTA-D - -0.3 VB +0.3 V

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L9177 Electrical specifications

Table 4. Absolute maximum ratings (continued)

Parameter Condition Min Max Unit

To be protected with Rkey_ext to

limit sourced/sinked current to
KEY pin 5 mA in dc conditions and 20 mA -0.3 10 V
during transients
(ISO-pulses on battery line)
Max current |20 mA| to be limited
VRIN- / VRIN+ -0.3 Vdd + 0.3 V
with external resistors
VDD_TRK pin - -2 40 V
KL_LINE pin - -16 40 V
Maximum voltage shift PIN GND, GND_O2H, GND_P_1,2,
-0.3 0.3 V
between GND pins GND_INJ1,2, GNDA, GNDP
Injector drivers - 50 mJ
I/O power pins(3)
maximum energy (single O2 sensor heater - 60 mJ
pulse, max. current)
Relay/lamp drivers - 25 mJ
I/O power pins(3) Injector drivers - 18 mJ
maximum energy
O2 sensor heater - 22 mJ
(continuous pulse, max.
current, 36 million pulses
Relay/lamp drivers - 8 mJ
with T = 100 ms)
Static (room temperature, max
Reverse current through - 2.5
reverse diode voltage 1.5 V)
O2H output without A
supply voltage(4) Dynamic (guarantee by iso-pulse
- -
test immunity on application board)
Static (room temperature, max
Reverse current through - 2.2
reverse diode voltage 1.5 V)
INJx outputs without A
supply voltage(4) Dynamic (guarantee by iso-pulse
- -
test immunity on application board)
Static (room temperature, max
Reverse current through - 1.2
reverse diode voltage 1.5v)
LAMP output without A
supply voltage(4) Dynamic (guarantee by iso-pulse
- -
test immunity on application board)
Static (room temperature, max
Reverse current through - 1.5
reverse diode voltage 1.5 V)
RLYx outputs without A
supply voltage(4) Dynamic (guarantee by iso-pulse
- -
test immunity on application board)
Static (room temperature, max
Reverse current through - 0.5
reverse diode voltage 1.5 V)
TACH output without A
supply voltage(4) Dynamic (guarantee by iso-pulse
- -
test immunity on application board)
1. Pins are VDD, VDD_SB, REXT, DIR
2. Pins are CS, SCK, SI, SO, VROUT, RESET, PWM, EN, INO2H, ILS_TACH, IN, KL_TX, KL_RX
3. Pins are O2H, LAMP, INJ1-2, REL1-2-3
4. Reverse battery connection, parameter not tested for info only

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Electrical specifications L9177

Table 5. ESD protection

Item Condition Min Max Unit

All pins (1) HBM -2 2 kV

All pins MM -200 200 V
All pins CDM (values for corner pins in brackets) -500 / (-750) 500 / (750) V
Pins to connector (2) HBM -4 4 kV
1. Except:
OUTA-D, TACH, O2H, LAMP, INJ1-2, REL1-2-3 vs. GNDP1:-1 / 1 kV
OUTA-D, TACH, O2H, LAMP, INJ1-2, REL1-2-3 vs. GNDP2, GNDO2:-1.5 / 1.5 kV
2. Pins are OUTA-D, TACH, O2H, LAMP, INJ1-2, KEY, REL1-2-3,VB,KL_LINE, VDD_TRK all GND connected
together. The device is AEC-Q100 compliant.

3.3 Latch-up test

According to JEDEC 78 class 2 level A.

3.4 Temperature ranges and thermal data

Table 6. Temperature ranges and thermal data
Symbol Parameter Min Max Unit

Tamb Operating temperature (ECU environment) -40 125 C

Tj Operating junction temperature -40 150 C
Tstg Storage temperature -40 150 C
Tot Thermal shut-down temperature 155 200 C
OThys Thermal shut-down temperature hysteresis 10 C
RTh j-amb Thermal resistance junction-to-ambient(1) 16 C/W
RTh j-case Thermal resistance junction-to-case 2 C/W
1. with 2s2p PCB thermally enhanced.

3.5 Electrical characteristics

VB = 6 V to 18 V, Tamb = -40 C to 125 C.

3.5.1 Supply

Table 7. Supply electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

VB Operating supply voltage range - 6 - 18 V

VB_off Vbat switch off threshold voltage - 30 32 34 V
VB OVh Overvoltage threshold hysteresis - 0.5 - - V

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L9177 Electrical specifications

Table 7. Supply electrical characteristics (continued)

Symbol Parameter Condition Min Typ Max Unit

Undervoltage disable LOW

VB UVL - 3.5 3.7 3.9 V
threshold
Undervoltage threshold
VB UVh - 0.3 - 1 V
hysteresis
VB= 13 V, device
IVB(dis) Standby current - - 120 A
disabled, KEY<0.7 V
VB= 13 V, outputs
IVB Quiescent current - - 20 mA
floating
Vrext ASIC Bias reference Application note - 1.22 - V
fint_clk Internal clock reference Application note - 5.6 - MHz

3.5.2 Key

Table 8. Key electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

V_Key_L Input low threshold - 1.5 - - V

V_Key_H Input high threshold - - - 3.3 V
V_Key_Hyst Input voltage hysteresis - 0.5 - 1.8 V
R_Key Internal pull down - 50 150 300 k
T_key_deglitch Key input filter time Guaranteed by scan 26 - 40 s
Time from key rising
Maximum delay time from
T_key_delay edge to 20% VDD - - 200 s
Key to regulator enable
rising edge

Figure 3. Input threshold

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V 6?+EY?, 6?+EY?( V '!0'03

Figure 4. Key block diagram

'!0'03

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Electrical specifications L9177

3.5.3 Digital pins

Table 9. Digital pins characteristics

Symbol Parameter Condition Min Typ Max Unit

Vin_L Input level threshold low - 0.3*Vdd - - V

Vin_H Input level threshold high - - - 0.7*Vdd V
Vhin Input voltage hysteresis - 0.1 - - V
R_pull Internal pull-down/pull-up(1) - 50 150 250 k
I_pull_down Active pull-down - 10 - 100 A
1. Pins with pull-up: SI, SCK, CS, KL-TX;
Pins with pull-down: EN, PWM, ISL-TACH, INO2H, IN_REL1-2, IN1-2;
Pins with active pull-down: DIR.

3.5.4 Digital output pins

Table 10. Digital output pins characteristics

Symbol Parameter Condition Min Typ Max Unit

Output level low Isink = 2mA - - 0.4 V

Output level high Isource = 2mA(1) Vdd-0.5 - - V
1. Pins with open drain output: RESET, VROUT;
Pins with push-pull stage and tri-state condition: SDO

3.5.5 5 V voltage regulator

Table 11. VDD output electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Vdd Output voltage - 4.9 5 5.1 V

VB = 6 V to 18 V
Ln_vdd Line regulation -25 - 25 mV
Iload = 150 mA
VB = 13 V
Ld_vdd Load regulation -25 - 25 mV
Iload = 5 mA to 300 mA
Recovery from ISO pulse stimuli on
Vdd_OS Max overshoot - - 5.5 V
battery line (guaranteed by design)
Voltage slew-rate at power-
Vdd_SR Cload = 4.7 F 2 - 25 V/ms
on
Idd Load current - 5 - 300 mA
Idd_max Current limitation Output short to 4 V 350 - 600 mA
Short to ground current
Idd_STG Output shorted to GND 350 - 700 mA
limitation
Sin wave @ 1 kHz 1V pp VB = 13 V
PSRR Power supply rejection ratio 40 - - dB
Iload = 5 mA to 300 mA
VB - Vdd - Vdd dropout
Vdr5 VB = 5 V Iload = 300 mA 0.30 - 0.75 V
voltage

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L9177 Electrical specifications

Figure 5. 5 V main regulator block diagram

'!0'03

3.5.6 Reset

Table 12. Reset function electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

1 < Vdd< Vth_UV,

VUV_LO Output low voltage - - 0.6 V
Ireset = 2 mA
1 < Vdd < Vth_UV,
IUV_LO Reset current capability 2 - - mA
Vreset = 0.6 V
Ilk Leakage current VUV_reset = 4.5 V - - 1 A
Vdd under voltage low Vdd -
Vth_UV VB = 13.5 V 4.5 - V
threshold 150 mV
Vdd under voltage high Vdd -
Vth_UV Tht - 4.5 - V
threshold 50 mV
Vdd under voltage
Vth_UV HYS - 50 - - mV
hysteresis
Td_UV_ rst Power on UV reset delay - 17 22 30 ms
TfUV_reset UV reset filter Vdd< Vth_UV 25 50 75 s

Figure 6. Reset

'!0'03

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Electrical specifications L9177

3.5.7 5 V tracking voltage regulator

Table 13. VDD_TRK output electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

VB = 6 V,
DVddtrk Output voltage tracking error -15 - 15 mV
Itrk = 1 to 40 mA
Tracking output short circuit
Vshort - -2 - VB V
voltage range
Itrk_max Output current limitation Output short to 4 V 50 - 100 mA
Tracking output reverse current
Itrk_sb Output shorted to VB = 16 V - - 10 mA
(limited by the regulator)
Idd Load current - 1 - 40 mA
VB = 6 V to 18 V - Iload = 40
Ln_vdd_trk Line regulation -15 - 15 mV
mA
Ld_vdd_trk Load regulation VB = 13 V Iload = 1 to 40 mA -15 - 15 mV
Sin wave @ 1 kHz 1V pp
PSRR Power supply rejection ratio 40 - - dB
VB = 13 V Iload = 1 to 40 mA

Figure 7. 5 V tracking regulator block diagram

'!0'03

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L9177 Electrical specifications

3.5.8 Standby regulator

Table 14. VDD_SB output electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Vddsb Output voltage - 4.75 5 5.25 V

VB =6 V to 18 V
Ln_vsb Line regulation -25 - 25 mV
Iload = 1 mA
VB =13 V
Ld_vsb Load regulation -25 - 25 mV
Iload = 0.1 mA to 2.5 mA
Vdd_OS Max overshoot - - - 5.5 V
Idd Load current - 0.1 - 2.5 mA
Isb_max Current limitation Output short to 4 V 5 - 50 mA
Voltage slew-rate at
Vsb_SR Cload = 1 F 2 - 30 V/ms
power on
Sin wave @ 1 kHz 1V pp
Power supply rejection
PSRR VB = 13 V 40 - - dB
ratio
Iload = 0.1 to 1 mA

Figure 8. 5 V standby regulator block diagram

'!0'03

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48
Electrical specifications L9177

3.5.9 High side switch

Table 15. HS_OUT output electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Ron_hs Ron Ihs = 50 mA - - 14

Ihs_max Current limitation VB =13.5 V 100 - 400 mA

Figure 9. High-side driver block diagram

'!0'03

3.5.10 Injector driver

Table 16. Injector driver electrical characteristic

Symbol Parameter Condition Min Typ Max Unit

Imax Output current - - - 2.2 A

I_oc Overcurrent threshold - 2.8 - 5 A
VDS Output clamping voltage I = 2.2 A 55 - 65 V
Ron On resistance I = 2.2 A - - 0.6
Ilk_off Leakage current Vout = 18 V, diagnosis OFF - - 10 A
Ilk_on Leakage current Vout = 18 V, diagnosis ON - - 100 A
from CMD edge to 50%
ton-off Turn on-off delay - - 6 s
output variation
VOL Open load output voltage Driver in OFF condition 0.46*VDD 0.5*VDD 0.54*VDD V
Vdiagth_H(1) Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
Vdiagth_L (1) Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
1. Vdiagth_L<Vout<Vdiagth_H Open Load; Vout<Vdiagth_L Short to GND

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L9177 Electrical specifications

Figure 10. Low-side driver block diagram

'!0'03

Figure 11. Low-side timing diagram (injectors, relays, lamp, tach, O2H)
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'!0'03

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48
Electrical specifications L9177

3.5.11 Relay drivers

Table 17. Relay driver characteristics

Symbol Parameter Condition Min Typ Max Unit

Imax Output current - - - 1 A

I_oc Overcurrent threshold - 1.2 - 2.5 A
VDS Output clamping voltage I=1A 40 - 50 V
Ron On resistance I=1A - - 1.5
Ilk_off Leakage current Vout = 18 V, diagnosis OFF - - 10 A
Ilk_on Leakage current Vout = 18 V, diagnosis ON - - 100 A
From CMD (serial or
ton_off Turn on-off delay - - 6 s
parallel) rising edge
VOL Open load output voltage Driver in OFF condition 0.46*VDD 0.5*VDD 0.54*VDD V
Vdiagth_H(1) Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
Vdiagth_L(1) Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
1. Vdiagth_L<Vout<Vdiagth_H Open Load; Vout<Vdiagth_L Short to GND

3.5.12 Lamp driver

Table 18. Lamp driver characteristics

Symbol Parameter Condition Min Typ Max unit

ILI Linear current limitation - 2 - 4 A

Masked for lamp driver
Ioc Overcurrent threshold 1.2 - 2.4 A
during in-rush
tdgmsk Diagnosis masking time Guaranteed by scan 2 - 5 ms
VDS Output clamping voltage I = 200 mA 40 - 50 V
Ron On resistance I = 200 mA - - 1.5
Ilk_off Leakage current Vout = 18 V, diagnosis OFF - - 10 A
Ilk_on Leakage current Vout = 18 V, diagnosis ON - - 100 A
ton_off Turn on-off delay From SPI CS rising edge - - 6 s
VOL Open load output voltage Driver in OFF condition 0.46*VDD 0.5*VDD 0.54*VDD V
Vdiagth_H(1) Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
Vdiagth_L(1) Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
1. Vdiagth_L<Vout<Vdiagth_H Open Load; Vout<Vdiagth_L Short to GND

20/49 DocID17617 Rev 1

L9177 Electrical specifications

3.5.13 Tachometer driver

Table 19. Tachometer driver electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Ioc Overcurrent threshold - 100 - 500 mA

Ron On resistance I = 25 mA - - 5
Ilk_off Leakage current Vout = 18 V, diagnosis OFF - - 10 A
Ilk_on Leakage current Vout = 18 V, diagnosis ON - - 100 A
From CMD (serial or
ton_off Turn on-off delay - - 6 s
parallel) rising edge
VOL Open load output voltage driver in OFF condition 0.46*VDD 0.5*VDD 0.54*VDD V
(1)
Vdiagth_H Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
(1)
Vdiagth_L Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
1. Vdiagth_L<Vout<Vdiagth_H Open Load; Vout<Vdiagth_L Short to GND

3.5.14 Stepper motor driver

Table 20. Stepper motor driver electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Ioc Overcurrent threshold ON condition 0.85 - 2 A

Iout = 0.5 A,
RdsON On resistance HS+LS - - 2.6
Tj = 150 C, VB = 14 V
fstepper Working frequency Application note - - 20 kHz
OUTA short to OUTB;
OUTA_B_C_D output
Vout_off(1) OUTC short to OUTD; 0.44*VDD 0.5*VDD 0.54*VDD V
voltage
Stepper driver disable
Vdiagth_H Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
Vdiagth_L Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
IDSS_OUT Output leakage current Driver in OFF condition - - 10 A
tscvb Over current switch_off time Guaranteed by scan - - 25 s
trb Rise output time VB = 12 V, RI = 39 - - 15 s
tfb Fall output time VB = 12 V, RI = 39 - - 15 s
trb-a Rise output time Tamb = 25 C, - - 10 s
tfb-a Fall output time VB = 12 V, RI = 39 - - 10 s
tpHLb Turn-off in/out delay time - - 15 s
VB = 12 V, RI = 39
tpLHb Turn-off in/out delay time - - 15 s
Driver in OFF condition
Vreverse_HS Reverse HS diode drop - - 1.5 V
Iinjected = 0.5 A

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48
Electrical specifications L9177

Table 20. Stepper motor driver electrical characteristics (continued)

Symbol Parameter Condition Min Typ Max Unit

Driver in OFF condition

Vreverse_LS Reverse LS diode drop - - -1.5 V
ISourced = 0.5 A
1. VoutA >Vdiagth_H and VoutB<Vdiagth_L or VoutC>Vdiagth_H and VoutD<Vdiagth_L Open load
VoutA_B_C_D>Vdiagth_H Short to Battery
VoutA_B_C_D<Vdiagth_L Short to GND
VoutA <Vdiagth_H and VoutB>Vdiagth_Lor VoutC<Vdiagth_H and VoutD>Vdiagth_L No Fault

Figure 12. Stepper motor driver block diagram


#HANELISCONNECTEDTO6" 6"
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#HANELISCONNECTEDTO6"?


'!0'03

22/49 DocID17617 Rev 1

L9177 Electrical specifications

Figure 13. Stepper motor operations

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'!0'03

3.5.15 O2 sensor heater driver

Table 21. O2 sensor heater driver characteristics

Symbol Parameter Condition Min Typ Max Unit

RdsON On resistance Iout = 3 A - - 0.5

VC Output clamping voltage Iout = 3 A 40 - 50 V
Ilk_off Leakage current Vout = 18 V, diagnosis OFF - - 10 A
Ilk_on Leakage current Vout = 18 V, diagnosis ON - - 100 A
From CMD (serial or
ton_off Turn on-off delay - - 6 s
parallel) rising edge
VOL Open load output voltage Driver in OFF condition 0.46*VDD 0.5*VDD 0.54*VDD V
IOC Overcurrent threshold 3.8 - 5 A
Vdiagth_H(1) Diagnostic high threshold Driver in OFF condition 0.54*VDD 0.6*VDD 0.66*VDD V
Vdiagth_L(1) Diagnostic low threshold Driver in OFF condition 0.36*VDD 0.4*VDD 0.44*VDD V
1. Vdiagth_L<Vout<Vdiagth_H Open Load; Vout<Vdiagth_L Short to GND

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Electrical specifications L9177

3.5.16 Variable reluctance sensor interface

Table 22. Variable reluctance sensor interface electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

Input high to low

differential
VHTH threshold voltage at - -50 - 50 mV
VRIN+ and VRIN-
nodes
Common mode
VCM operating range at - 0 1.5 3 V
VRIN+ and VRIN-
Internal common
Vcm_internal Switch off hysteresis current 0.27*VDD 0.3*VDD 0.33*VDD V
mode voltage
Diagnostic high
Vdiagth_H(1) 0.67*VDD 0.75*VDD 0.82*VDD V
threshold Diagnostic voltage referred to
Diagnostic low VRIN- (see Figure 14)
Vdiagth_L(1) 0.18*VDD 0.2*VDD 0.22*VDD V
threshold
Current from VRIN- when
Idiag Diagnostic current 35 50 65 A
diagnostic on
Rinternal_ Internal common
Switch off hysteresis current 50 200 350 k
common mode resistor
IIB Input bias current VRIN+ = VRIN- = 1.5 V - - 2 A
Ileak Output leakage VROUT = 5 V - - 1 A
Input high clamping
VCLPH VRIN+ = |VRIN-| = 20 mA - 5 - V
voltage
Input low clamping
VCLPL VRIN+ = |VRIN-| = |20 mA| -1.5 - -0.3 V
voltage
tof Output fall time CLOAD = 20 pF, RLOAD = 5 k - - 300 ns
tof_1nf Output fall time CLOAD = 1nF - - 1.5 s
Output buffer low
VOUTL Isink = 2 mA - - 0.6 V
voltage
Output current
IOUTL Vout = 0.6 V 2 - - mA
capability
VRS INM = 0.5 V, INP applied to
tprop Propagation delay 1 V to make VRS OUT 0.1 0.45 0.8 s
commuted
1. if (VRIN- > Vdiagth_H) or (VRIN- < Vdiagth_L) then Fault is detected.

24/49 DocID17617 Rev 1

L9177 Electrical specifications

Figure 14. VRS block diagram

'!0'03

3.5.17 K-line

Table 23. K-Line interface electrical characteristics

Pin Symbol Parameter Test conditions Min. Typ. Max. Unit

Transmitter input
ITXsource - 10 - 100 A
source current
KL_TX
Transmitter input
ITXsink KL_TX = VDD - - 2.1 A
sink current
Transmitter output IsinkK_LINE = 35 mA,
VKoutL -1 - 1.5 V
low voltage KL_TX = Low
Receiver input high
VKinH - 0.7xVB - VB V
voltage
Receiver input low 0.35xV
K_LINE VKinL - -1 - V
voltage B
Receiver input
VKH - 0.05xVB - 0.3xVB V
hysteresis
Receiver leakage KL_LINE = VB,KL_TX =
IKleak - - 1 A
current High

DocID17617 Rev 1 25/49

48
Electrical specifications L9177

Table 23. K-Line interface electrical characteristics (continued)

Pin Symbol Parameter Test conditions Min. Typ. Max. Unit

Transmitter short KL_LINE = VB, KL_TX =

IKshort 60 - - mA
circuit current Low
Reverse battery or ENABLE = KEY = VB = 0 V,
IKrev - - 10 mA
GND loss current KL_LINE = -13.5
K_LINE
KLINE internal pull-
IKpull-up KL_TX = High 60 - 140 k
up
Under voltage KEY = High, KL_TX = Low,
IKuv - - 1 mA
current VB = 13.5 V, KL_LINE = -1 V
KL_RX output low
KL_RX VRXoutL Isink = 0.4 mA - - 0.4 V
voltage
KL_TX to Transmitter turn-on CKline = 10 nF,
Tp_HLT - - 5 s
K_LINE delay time RKline = 510
CKline = 10 nF,
K_LINE T_fT Transmitter fall time - - 10 s
RKline = 510
KL_LINE Receiver turn-on Cload = 20 pF,
TpR - - 4 s
to KL_RX delay time RPKL_Rx = 2 k
Cload = 20 pF,
T_fR Receiver fall time - - 2 s
RPKL_Rx = 2 k
KL_RX
Cload = 20 pF,
T_rR Receiver rise time - - 2 s
RPKL_Rx = 2 k
Max transmission
K_LINE fMax Operating Application note - - 60 kHz
frequency

Figure 15. K-line block diagram

'!0'03

26/49 DocID17617 Rev 1

L9177 Electrical specifications

3.5.18 SPI interface

Table 24. SPI characteristics and timings

Symbol Parameter Test conditions Min Typ Max Unit

SICin - - - 20 pF
Input capacitance
SCKCin - - - 20 pF
Clock inactive time before
tSCKCS - 100 - - ns
frame
tCSSO Access time See Figure 17 - - 500 ns
No Capacitor on SO,
tSOdis Output data (SO) disable time - - 500 ns
See Figure 16
Channels elect (CS) lead
tlead See Figure 17 500 - - ns
time
tSCKFSO Output valid time See Figure 17, @ fCLK = 5.4 MHz 60 - - ns
tSOCS Output data (SO) disable time No capacitor on SO, see Figure 17 - 500 ns
tSIsetup Input data (SI) set-up time See Figure 17, @ fCLK = 5.4 MHz 20 - - ns
tSIhold Input data (SI) hold time See Figure 17, @ fCLK = 5.4 MHz 20 - - ns
tSCK CLK period - 185 - - ns
Clock inactive time after
tCSCK - 600 - - ns
frame
tCSN CS de asserted time - 600 - - ns

Figure 16. -SO loading for disable time measurement

6
6##
6

K7 3/DIS 3/

3/ 6

K7
#3

'!0'03

Figure 17. SPI timing diagram

43/#3

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3/ 3/ 3/ 3/ 3/ 3/ 3/ 3/ 3/

!#!
'!0'03

DocID17617 Rev 1 27/49

48
Functional description L9177

4 Functional description

4.1 Chip working conditions

Table 25. L9177 outputs working conditions
Run Thermal
- Standby VB_OV VB_UV Reset Over current
mode warning

VDD_SB regulator ON ON ON ON ON Current limitation ON

OFF if linked with
VDD regulator OFF ON OFF OFF ON Current limitation VDD current
limitation
OFF if linked with
VDD_TRK regulator OFF ON OFF OFF ON Current limitation VDD_TRK
current limitation
Over current
All LS drivers OFF ON OFF OFF OFF ON
switch off
Diagnostics of all LS
OFF ON OFF OFF ON - ON
drivers
HS Driver OFF ON OFF OFF OFF Current limitation ON
Stepper Motor Over current
OFF ON OFF OFF OFF ON
Driver switch off
K-line Transceiver OFF ON OFF OFF OFF Current limitation ON
VRS OFF ON OFF OFF OFF - ON
SPI Default Default Default Default Default ON ON

28/49 DocID17617 Rev 1

L9177 Functional description

4.2 Chip bias current generation

The Internal current generator circuit is buffering internal band-gap voltage (1.2 V typ.) on a
high precision external resistor (10 k 1 %) and generates an accurate current reference
used to create all the chip bias currents.

Figure 18. Current generator block diagram

'!0'03

4.3 Power up/down sequences

Below figures show the power-on, power-off and time diagram behaviour of L9177.
VDD_SB (standby voltage) rises together with battery input, and in standby it is always
present if battery is present, no matter the KEY_IN status.
When the KEY_IN signal rises up and remains stable for at least T_key_deglitch (see
Table 8), the device goes in ON state, meaning that all voltage regulators and functions are
active.
Wake-up is an intermediate status between standby and on mode, with current consumption
higher than the standby one.
When Key_IN goes low, device goes in OFF mode but standby regulator remains ON.

DocID17617 Rev 1 29/49

48
Functional description L9177

Figure 19. Power-up sequence

6"

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34"9 7AKE?5P /N3TATE

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2%3%4 4$?56?RST
'!0'03

Figure 20. Power-down sequence

6"

6$$?3"

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6$$

2%3%4

'!0'03

Reset signal detects a VDD undervoltage longer than UV_Reset_Filter_time by going to low
level. When VDD recovers to normal level Reset signal returns to high level after
Power_On_UV_Reset_Delay time (td_UV_rst). The Reset signal resets all the internal SPI
registers.

4.4 SPI
SPI is a standard four wires interface, that communicates with a data word of 24 bits. By
means of SPI all the channels can be driven in serial way and diagnosis is sent out.Timing
of SPI's operations are reported in Figure 17. The input data (DIN) is read on the rising edge
of the SPI's clock (SCLK), in the same way the output data (DOUT) must be read by the
Microcontroller on the SCLK's rising edge.

4.4.1 Data in (DIN)

DIN command is used to turn On/Off internal channels which do not have Parallel Input
command, and to clear diagnostic latches.
DIN is decoded at the end of the frame if the integrity checks are passed.

30/49 DocID17617 Rev 1

L9177 Functional description

Table 26. Data in (DIN) words content

DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7

Mask LAMP_0 LAMP_1 VRS Diag VRS Hys0 VRS Hys1 VRS Hys2 0

DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15

INJ1_0 INJ1_1 INJ2_0 INJ2_1 O2H_0 O2H_1 RLY1_0 RLY1_1

DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23

RLY2_0 RLY2_1 RLY3_0 RLY3_1 TACH_0 TACH_1 Clear diag Parity

Data in structure (LSB first)

Mask bit is used to mask serial command for diagnosis only readings on DOUT:
0 - Read Diag. All DIN bits are ignored.
1 - Write. All DIN are transferred into the internal registers.
Command bits are used to control the output drivers: (INJ1-2, O2H, RLY1-2-3, LAMP
and TACH) as described in following table:

Table 27. Data in command bits structure

xxx_1 xxx_0 Description

1 0 Turn-off driver / parallel polarity 0

1 1 Turn-on driver / parallel polarity 1
0 X No change (the driver will maintain the previous condition)

VRS Diag bit is used active high to enable diagnostic phase of VRS block.
Programmable VRS Hysteresis: VRS hysteresis is programmable in 5 steps according
to Table 28: Data in VRS hysteresis.
Clear Diag, when set to 1 generates a request to clear those diagnostic flags which are
latched.
In addition odd parity bit (that is the last bit of the frame and includes in its calculation
the "Don't care" bits) is used for DIN word check together with falling clock edges
count.

Table 28. Data in VRS hysteresis

Hys 2 Hys 1 Hys 0 Description

0 0 0 Default hysteresis value

0 0 1 Hys VRS = 100 mV
0 1 0 Hys VRS = 200 mV
0 1 1 Hys VRS = 350 mV
1 0 0 Hys VRS = 650 mV
1 0 1 Hys VRS = 1000 mV
1 1 1 Not Valid (Hys doesn't change)

DocID17617 Rev 1 31/49

48
Functional description L9177

4.4.2 Data out

Status flag are sampled and sent out through DOUT pin at each R/W SPI operation. The
structure of the 24 bit word is described in Table 29. A three bits diagnosis is provided for
stepper motor driver, a two bit diagnosis for others drivers. VRS diagnosis is coded as '0'
means No Fault, while '1' means Fault. Over temperature warning is coded as '0' means No
Fault, while '1' means Fault.
The SPI default value is: all bits set to zero.

Table 29. Data out (DOUT) words content

DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7

INJ1 Diag0 INJ1 Diag1 INJ2 Diag0 INJ2 Diag1 O2H Diag0 O2H Diag1 RLY1 Diag0 RLY1 Diag1

DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15

RLY2 Diag0 RLY2 Diag1 RLY3 Diag0 RLY3 Diag1 LAMP Diag0 LAMP Diag1 TACH Diag0 TACH Diag1

DOUT16 DOUT17 DOUT18 DOUT19 DOUT20 DOUT21 DOUT22 DOUT23

Thermal
VRS Diag Brdg1 Diag0 Brdg1 Diag1 Brdg1 Diag2 Brdg2 Diag0 Brdg2 Diag1 Brdg2 Diag2
Warning

Data out structure

Table 30. Two bits diagnosis (normal drivers)

Bit 1 Bit 0 Fault

0 0 No Fault
0 1 Short to Ground (OFF)
1 0 Open Load (OFF)
1 1 Overcurrent (ON)

Table 31. Three bits diagnosis (bridge stage)

Bit 2 Bit 1 Bit 0 Fault

0 0 0 No Fault
0 0 1 Short to Ground (OFF)
1 0 1 Short to VBAT (OFF)
0 1 0 Open Load (OFF)
0 1 1 Overcurrent (ON)

32/49 DocID17617 Rev 1

L9177 Functional description

4.5 Diagnosis
L9177 provides a full set of diagnosis; deglitch timings listed below are digital, generated
from internal clock and their accuracy is guaranteed by scan patterns and clock
measurement.

4.5.1 Voltage regulators thermal warning and shutdown

The 5V linear voltage regulator/tracking regulator is shut down when the thermal shutdown
temperature is reached and also the regulator is in current limitation. The shutdown is
filtered with Tdcg filter of 30 s 25 %. As soon as the over temperature disappear the
regulator is switched on again. Over temperature flag without any latch is present via SPI.

4.5.2 Overvoltage shut down

If the VB_off voltage is reached after Tdgc filtering time of 30 s 25 % the L9177 enters a
safety state where main outputs are switched-off. Voltage regulators, all low side channels,
stepper motor driver and KLINE are switched off and reset is asserted. As soon as the
battery comes below VB_off minus VB_off_h the L9177 recover standard operation.

4.5.3 Undervoltage shut down

If the VB_UV voltage is reached after analog Tdgc 1 s 20 % filtering time the L9177
enters a safety state where main outputs are switched-off. Voltage regulators, all low side
channels, stepper motor driver and KLINE are switched off. As soon as the battery rises
above VB_UV plus the hysteresis the L9177 recovers normal operation.

Figure 21. L9177 under and over voltage time diagram

6" 6B?OFF 6B?OFF
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'!0'03

DocID17617 Rev 1 33/49

48
Functional description L9177

4.5.4 Low side on/off diagnosis (INJ, RLY's, TACH, O2H)

About low side channels OFF diagnosis, L9177 issues a masking filter Tmask after channel
turning off (falling edge of driving command) to avoid false fault detecting due to output
transition from low to high. Tmask is of 1 ms 25 % for all channels except for the relays, for
which Tmask is 3.5 ms 25 %. Once masking time expires a deglitch filter Tdgc_noise of
3.6 s 40 % for noise immunity is activated. A fault longer than deglitch time is latched. Off
state diagnostic fault can be overwritten by on state fault. Off state fault does not prevent the
driver to switch on. The latched fault is cleared on request.
During on-phase if an over current fault occurs the drivers enters in current limitation
condition for a digital filtering time Tdgc of 20 s 25 %,then it is switched OFF and the fault
is latched. The channel is turned ON again by input command transition. The latched fault is
cleared on request via SPI.
Over current fault has higher priority respect to OFF condition faults.

Figure 22. Low side driver diagnosis time diagram

'!0'03

34/49 DocID17617 Rev 1

L9177 Functional description

Figure 23. Low side driver diagnosis I-V relationship

'!0'03

4.5.5 Lamp driver on/off diagnosis

In OFF condition diagnosis is the same as Low side, with Tmask 3.5 ms 25 % and
Tdgc_noise 3.6 s 40 %, while in ON condition initial Inrush current is masked for
Tmask_rush of 45 ms 25 % then, if an over current fault occurs the drivers enters in current
limitation condition for a digital filtering time Tdgc of 20 s 25 %, then it is switched OFF
and the fault is latched. The channel is turned ON again by input command transition. The
latched fault is cleared on request via SPI. Over current fault has higher priority with respect
to OFF condition faults.

DocID17617 Rev 1 35/49

48
Functional description L9177

Figure 24. Lamp driver diagnosis time diagram

'!0'03

4.5.6 Stepper motor driver off diagnosis (EN signal high and output in high
impedance state)
In OFF condition Short to GND/Short to Vb or Open Load condition is continuously detected
through a deglitch filter of 125 s 25 %, after Tmask masking time of 1 ms 25 % to filter
ON/ OFF transition. To avoid false diagnostic due to motor residual movement, the stepper
has to be disabled at least 40 ms after the PWL signal has been disabled. A fault longer
than deglitch time is latched. Off state diagnostic fault can be overwritten by on state fault.
Off state fault does not prevent the stepper to switch on. The latched fault is cleared on
request.

4.5.7 Stepper motor driver on diagnosis (EN signal Low and output driven by
input commands)
In ON condition when over current fault is detected and validated after digital filtering time
Tdgc of 20 s 25 %, the bridge is turned OFF and the fault is latched. The bridge is turned
ON again by input command EN transition. The latched fault is cleared on request. Over
current fault has higher priority with respect to OFF condition faults. Each Bridge has
dedicated fault diagnosis detection coded by three bits.

36/49 DocID17617 Rev 1

L9177 Functional description

Figure 25. Stepper motor driver diagnosis time diagram

'!0'03

Figure 26. Stepper motor driver diagnosis I-V relationship

'!0'03

DocID17617 Rev 1 37/49

48
Functional description L9177

4.5.8 VRS diagnosis

VRS block enters diagnosis phase on request via SPI and then generates a Fault bit. If the
fault exceeds the Tdgc filter time of 30 s 20 %, it is latched. The latched fault is cleared on
request via SPI.

Figure 27. VRS diagnosis I-V relationship

'!0'03

4.6 VRS interface

4.6.1 Function characteristic

The flying wheel interface is an interface between the P and the flying wheel sensor: it
conditions signal coming from magnetic pick-up sensor or hall effect sensor and feeds the
digital signal to microcontroller that extracts flying wheel rotational position, angular speed
and acceleration.

Figure 28. VRS typical characteristics

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'!0'03

Figure 29. VRS interface structure

!UTOADAPTATIVE )NT?VRS !UTOADAPTATIVE

623VOLTAGE /UT?VRS
(YSTERESIS 4IMEFILTERINGBLOCK

'!0'03

38/49 DocID17617 Rev 1

L9177 Functional description

4.6.2 Auto-adaptative hysteresis

Input signals difference is obtained trough a full differential amplifier; its output, DV signal, is
fed to peak detection circuit and then to A/D converter implemented with 4 voltage
comparator (5 levels Pvi).Output of A/D is sent to Logic block (hysteresis selection Table 33)
that implements correlation function between Peak voltage and hysteresis value; hysteresis
value is used by square filtering circuit which conditions DV signal.

Figure 30. Auto-adaptive hysteresis block diagram

(YSTERESIS3QUARER#IRCUITAND
4EMPORAL&ILTERING

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623VOLTAGE
n
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(YSTERESIS
( 6ALUE

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'!0'03

Figure 31. Hysteresis output voltage level

(YSTERESISOUTPUT
VOLTAGEM6
(
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 06 06 06 06 1UANTIZEDPEAKDETECTOR

OUTPUTVOLTAGEM6 '!0'03

To the previous 5 levels PV = [0 PV1 PV2 PV3 PV4] correspond a set of 5 thresholds:
H = [HO HIH2 H3 H4]
The advised values for the previous defined vectors are:
PV = [0 PV1 PV2 PV3 PV4] = [0, 900, 1560, 2230, 2900] mV
H = [H0 H1 H2 H3 H4] = [100, 200, 350, 650, 1000] mV

DocID17617 Rev 1 39/49

48
Functional description L9177

Table 32. Peak voltage detector precision

Value
Pick voltage [PV] Unit
Min. Typ. Max.

PV1 850 900 950 mV

PV2 1452 1560 1638 mV
PV3 2118 2230 2341 mV
PV4 2755 2900 3045 mV

Table 33. Hysteresis threshold precision

Value
Pick voltage [PV] Unit
Min. Typ. Max.

H0 70 100 130 mV
HV1 140 200 220 mV
HV2 250 347 390 mV
HV3 490 644 720 mV
HV4 730 1000 1120 mV

Note: Hysteresis voltages are achieved injecting an hysteresis bias current on VRIN external
resistors (typ. 10 k each, see Figure 38 application circuit). Resulting HV voltage is
HV = I_hys*Rtyp. Changing the value of R would change in a linear mode the hysteresis
value.

Figure 32. Input-output behaviour of VRS interface

40/49 DocID17617 Rev 1

L9177 Functional description

4.6.3 Auto-adaptative time filter

This characteristic is useful to set the best internal filter time in function of the input signal
frequency.
Tfilter time is function of the duration of the previous period Tn according to following
formula:
Tfilter(n+1) = 1/32*Tn if Tn > Tfilter(n)
The filtering time purpose is filtering very short spikes.
The digital filtering time is applied to internal squared signal (int_vrs), obtained by voltage
comparators.
The output of time filtering block is out_vrs signal.
The filtering time Tfilter is applied to int_vrs signal in two different way:
Rising edge: if int_vrs high level lasts less than Tfilter out_vrs is not set to high level.
In absence of any spikes during input signal rising edge out_vrs signal is expected with
a delay of Tfilter time.
Falling edge: the falling edge of int_vrs is not delayed through time filtering block: after
falling edge for a time Tfilter any other transition on int_vrs signal is ignored
The initial value (Default) and maximum for Tfilter must be considered at RPM_min = 20 e.g.
Tmax filter = 180 s. The minimum available value is Tmin filter = 2.8 s.

Figure 33. Auto-adaptative time filter behaviour 1

6DIFF

6DIFFMAX

(YS
6DIFFMIN

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4N 
4N

4N  
4N 
4N
6OUT

4N 4N 4N 4N ;S=

20-
20-MAX

20-MIN

;S= '!0'03

DocID17617 Rev 1 41/49

48
Functional description L9177

Figure 34. Auto-adaptative time filter behaviour 2

6DIFF

6DIFFMAX


4N
(YS
6DIFFMIN

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&ILTER -ASK
4IME 4IME


4N 
4N

4N  
4N 
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6OUT

4N 4N 4N 4N ;S=

'!0'03

42/49 DocID17617 Rev 1

L9177 Low side drivers

5 Low side drivers

Low side drivers have a voltage slew rate control during switch-on/off phase to reduce
emissions.
The slew-rate control is achieved controlling the gate charging current and the behavior is
described in Figure 35 and Figure 36.

Figure 35. Low side drivers slew rate implementation

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Figure 36. Low side drivers slew rate

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'!0'03

DocID17617 Rev 1 43/49

48
Low side drivers L9177

At switch-on command the charging current is provided by current generator IP1 and is kept
constant until the output voltage is decreased of roughly 80% of typical battery level. At this
point the low side transistor is on and VLVT signal is set to logic 1 to connect IP2 current
generator in parallel with IP1, completing the gate charge curve and providing maximum
gate drive.
When the power transistor is switched-off the gate is discharged quickly using both IN1 and
IN2 currents; as soon as the output voltage reaches roughly 20 % of the nominal battery
voltage only IN1 is kept connected to complete the gate discharging.
In Table 34 the values for IPx and INx current generators are reported for each low side.
As an example Figure 37 shows the resulting slew rate, in typical conditions, of O2H low
side driver.

Table 34. Values for IPx and INx current generators for each low side
Low side IP1 IP2 IN1 IN2 Unit

O2H 243 81 253 337 A

INJ 174 23 180 124 A
RLYs 78 0 80 120 A
LAMP 78 0 62 119 A
TACH 22 0 21 25 A

Figure 37. O2H low side driver slew rate

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'!0'03

44/49 DocID17617 Rev 1

L9177 Application circuit

6 Application circuit

Figure 38. Application circuit

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'!0'03

DocID17617 Rev 1 45/49

48
Application circuit L9177

6.1 Bill of material

Table 35. Bill of material
Block Component Name Usage Min Typ Max Unit

Supply Capacitor C1VB_MAIN Bulk capacitor 220 F

Reverse polarization
Diode D1
protection diode
Key Resistor R_Key Current limiting resistor 20 k
Rext Resistor R_ext Pull-up resistor 10 1% k
Reset Resistor R_reset Pull-up resistor 1 k
C_Vdd value Output capacitor (Ceramic 4.7 60 F
Vdd Capacitor
C_Vdd ESR or Tantalum) 1.5
C_Vtrk value 2.2 100 F
Vdd_trk Capacitor Output capacitor
C_Vtrk ESR 10 100 m
C_Vdd_stby
1 10 F
value
Vdd_sby Capacitor Output capacitor
C_Vdd_stby
200 m
ESR
VRS Capacitor C_VRS+_in Filter Capacitor 100 pF
VRS Capacitor C_VRS-_in Filter Capacitor 100 pF
VRS Capacitor C_VRS+_out Filter Capacitor 470 pF
VRS Capacitor C_VRS-_out Filter Capacitor 470 pF
VRS Resistor R_VRS+ Current limiting resistor 10 k
VRS Resistor R_VRS- Current limiting resistor 10 k
VRS Capacitor CF_1 Filter Capacitor 470 pF
VRS Capacitor CF_2 Filter Capacitor 100 nF
VRS Resistor RF_1 Filter resistor 33 k
VRS Resistor RF_2 Filter resistor 33 k
VRS Resistor R_VROUT Pull-up resistor 10 k
K-Line Resistor RX pull-up Pull-up resistor 2 k
Stepper Capacitor OUTA EMI filter capacitor 10 nF
Stepper Capacitor OUTB EMI filter capacitor 10 nF
Stepper Capacitor OUTC EMI filter capacitor 10 nF
Stepper Capacitor OUTD EMI filter capacitor 10 nF

46/49 DocID17617 Rev 1

L9177 Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

Figure 39. PowerSO46 mechanical data and package dimensions

MM INCH
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'!0'03

DocID17617 Rev 1 47/49

48
Revision history L9177

8 Revision history

Table 36. Document revision history

Date Revision Changes

06-Nov-2013 1 Initial release.

48/49 DocID17617 Rev 1

L9177

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (ST) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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