PIC18F2450/4450 Data Sheet

PIC18F2450/4450
Data Sheet
28/40/44-Pin, High-Performance,
12 MIPS, Enhanced Flash,
USB Microcontrollers with
nanoWatt Technology
© 2006 Microchip Technology Inc. Advance Information DS39760A

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DS39760A-page ii Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450
28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash,
USB Microcontrollers with nanoWatt Technology
Universal Serial Bus Features: Peripheral Highlights:
• USB V2.0 Compliant • High-current sink/source: 25 mA/25 mA
• Low speed (1.5 Mb/s) and full speed (12 Mb/s) • Three external interrupts
• Supports control, interrupt, isochronous and • Three Timer modules (Timer0 to Timer2)
bulk transfers • Capture/Compare/PWM (CCP) module:
• Supports up to 32 endpoints (16 bidirectional) - Capture is 16-bit, max. resolution 5.2 ns
• 256-byte dual access RAM for USB - Compare is 16-bit, max. resolution 83.3 ns
• On-chip USB transceiver with on-chip voltage - PWM output: PWM resolution is 1 to 10-bit
regulator • Enhanced USART module:
• Interface for off-chip USB transceiver - LIN bus support
• 10-bit, up to 13-channel Analog-to-Digital Converter
Power-Managed Modes: module (A/D):
• Run: CPU on, peripherals on - Up to 100 ksps sampling rate
• Idle: CPU off, peripherals on - Programmable acquisition time
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 μA typical
Special Microcontroller Features:
• Sleep mode currents down to 0.1 μA typical • C compiler optimized architecture with optional
• Timer1 oscillator: 1.8 μA typical, 32 kHz, 2V extended instruction set
• Watchdog Timer: 2.1 μA typical • Flash memory retention: > 40 years
• Two-Speed Oscillator Start-up • Self-programmable under software control
• Priority levels for interrupts
Flexible Oscillator Structure: • 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
• Four Crystal modes, including High-Precision PLL
for USB - Programmable period from 4 ms to 131s
• Two External Clock modes, up to 48 MHz • Programmable Code Protection
• Internal 31 kHz oscillator • Single-Supply In-Circuit Serial Programming™
(ICSP™) via two pins
• Secondary oscillator using Timer1 @ 32 kHz
• In-Circuit Debug (ICD) via two pins
• Dual oscillator options allow microcontroller and
USB module to run at different clock speeds • Optional dedicated ICD/ICSP port
(44-pin TQFP devices only)
• Fail-Safe Clock Monitor:
• Wide operating voltage range (2.0V to 5.5V)
- Allows for safe shutdown if any clock stops
Program Memory Data

Memory 10-Bit A/D Timers
Device Flash # Single-Word I/O CCP EUSART
SRAM (ch) 8/16-Bit
(bytes) Instructions (bytes)
PIC18F2450 16K 8192 768* 23 10 1 1 1/2
PIC18F4450 16K 8192 768* 34 13 1 1 1/2
* Includes 256 bytes of dual access RAM used by USB module and shared with data memory.
© 2006 Microchip Technology Inc. Advance Information DS39760A-page 1

PIC18F2450/4450
Pin Diagrams
28-Pin SDIP, SOIC
MCLR/VPP/RE3 1 28 RB7/KBI3/PGD
RA0/AN0 2 27 RB6/KBI2/PGC
RA1/AN1 3 26 RB5/KBI1/PGM
RA2/AN2/VREF- 4 25 RB4/AN11/KBI0
RA3/AN3/VREF+ 5 24 RB3/AN9/VPO
PIC18F2450
RA4/T0CKI/RCV 6 23 RB2/AN8/INT2/VMO
RA5/AN4/HLVDIN 7 22 RB1/AN10/INT1
VSS 8 21 RB0/AN12/INT0
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/UOE 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/D+/VP
VUSB 14 15 RC4/D-/VM
28-Pin QFN
RB4/AN11/KBI0
MCLR/VPP/RE3
RB5/KBI1/PGM
RB7/KBI3/PGD
RB6/KBI2/PGC
RA1/AN1
RA0/AN0
28 27 26 25 24 23 22
RA2/AN2/VREF- 1 21 RB3/AN9/VPO
RA3/AN3/VREF+ 2 20 RB2/AN8/INT2/VMO
RA4/T0CKI/RCV 3 19 RB1/AN10/INT1
RA5/AN4/HLVDIN 4 PIC18F2450 18 RB0/AN12/INT0
VSS 5 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO/RA6 7 15 RC7/RX/DT
8 9 10 11 12 13 14
RC5/D+/VP
RC1/T1OSI/UOE
RC6/TX/CK
RC4/D-/VM
RC2/CCP1
RC0/T1OSO/T1CKI
VUSB
Note: Pinouts are subject to change.
DS39760A-page 2 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450
Pin Diagrams (Continued)
40-Pin PDIP
MCLR/VPP/RE3 1 40 RB7/KBI3/PGD
RA0/AN0 2 39 RB6/KBI2/PGC
RA1/AN1 3 38 RB5/KBI1/PGM
RA2/AN2/VREF- 4 37 RB4/AN11/KBI0
RA3/AN3/VREF+ 5 36 RB3/AN9/VPO
RA4/T0CKI/RCV 6 35 RB2/AN8/INT2/VMO
RA5/AN4/HLVDIN 7 34 RB1/AN10/INT1
PIC18F4450
RE0/AN5 8 33 RB0/AN12/INT0
RE1/AN6 9 32 VDD
RE2/AN7 10 31 VSS
VDD 11 30 RD7
VSS 12 29 RD6
OSC1/CLKI 13 28 RD5
OSC2/CLKO/RA6 14 27 RD4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/UOE 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/D+/VP
VUSB 18 23 RC4/D-/VM
RD0 19 22 RD3
RD1 20 21 RD2
44-Pin QFN
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RC2/CCP1
VUSB
RD3
RD2
RD1
RD0
41
40
39
37
36
35
34
42
44
43
38
RC7/RX/DT 1 33 OSC2/CLKO/RA6
RD4 2 32 OSC1/CLKI
RD5 3 31 VSS
RD6 4 30 AVSS
RD7 5 29 VDD
VSS 6 PIC18F4450 28 AVDD
AVDD 7 27 RE2/AN7
VDD 8 26 RE1/AN6
RB0/AN12/INT0 9 25 RE0/AN5
RB1/AN10/INT1 10 24 RA5/AN4/HLVDIN
RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/RCV
15
16
17
18
19
20
21
22
12
13
14
NC
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
RB4/AN11/KBI0
RB5/KBI1/PGM
RB3/AN9/VPO
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-

PIC18F2450/4450
Pin Diagrams (Continued)
44-Pin TQFP
RC1/T1OSI/UOE
NC/ICPORTS*
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RC2/CCP1
VUSB
RD3
RD2
RD1
RD0
41
40
39
37
36
35
34
42
44
43
38
RC7/RX/DT 1 33 NC/ICRST*/ICVPP*
RD4 2 32 RC0/T1OSO/T1CKI
RD5 3 31 OSC2/CLKO/RA6
RD6 4 30 OSC1/CLKI
RD7 5 29 VSS
VSS 6 PIC18F4450 28 VDD
VDD 7 27 RE2/AN7
RB2/AN8/INT2/VMO 10 24 RA5/AN4/HLVDIN
RB3/AN9/VPO 11 23 RA4/T0CKI/RCV
15
16
17
18
19
20
21
22
12
13
14
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
NC/ICDT*/ICPGD*
NC/ICCK*/ICPGC*
RB4/AN11/KBI0
RB5/KBI1/PGM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-

* Assignment of this feature is dependent on device configuration.

PIC18F2450/4450
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 33
4.0 Reset .......................................................................................................................................................................................... 41
5.0 Memory Organization ................................................................................................................................................................. 53
6.0 Flash Program Memory.............................................................................................................................................................. 73
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 83
8.0 Interrupts .................................................................................................................................................................................... 85
9.0 I/O Ports ..................................................................................................................................................................................... 99
10.0 Timer0 Module ......................................................................................................................................................................... 111
11.0 Timer1 Module ......................................................................................................................................................................... 115
12.0 Timer2 Module ......................................................................................................................................................................... 121
13.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 123
14.0 Universal Serial Bus (USB) ...................................................................................................................................................... 129
15.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 153
16.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 173
17.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 183
18.0 Special Features of the CPU.................................................................................................................................................... 189
19.0 Instruction Set Summary .......................................................................................................................................................... 211
20.0 Development Support............................................................................................................................................................... 261
21.0 Electrical Characteristics .......................................................................................................................................................... 265
22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 293
23.0 Packaging Information.............................................................................................................................................................. 295
Appendix A: Revision History............................................................................................................................................................. 303
Appendix B: Device Differences ........................................................................................................................................................ 303
Appendix C: Conversion Considerations ........................................................................................................................................... 304
Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................ 304
Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 305
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 305
Index ................................................................................................................................................................................................. 307
The Microchip Web Site ..................................................................................................................................................................... 315
Customer Change Notification Service .............................................................................................................................................. 315
Customer Support .............................................................................................................................................................................. 315
Reader Response .............................................................................................................................................................................. 316
PIC18F2450/4450 Product Identification System .............................................................................................................................. 317

PIC18F2450/4450
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PIC18F2450/4450
1.0 DEVICE OVERVIEW 1.1.3 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
This document contains device-specific information for
the following devices: All of the devices in the PIC18F2450/4450 family offer
twelve different oscillator options, allowing users a wide
• PIC18F2450 • PIC18F4450 range of choices in developing application hardware.
This family of devices offers the advantages of all PIC18 These include:
microcontrollers – namely, high computational • Four Crystal modes using crystals or ceramic
performance at an economical price – with the addition of resonators.
high endurance, Enhanced Flash program memory. In • Four External Clock modes, offering the option of
addition to these features, the PIC18F2450/4450 family using two pins (oscillator input and a divide-by-4
introduces design enhancements that make these micro- clock output) or one pin (oscillator input, with the
controllers a logical choice for many high-performance, second pin reassigned as general I/O).
power sensitive applications.
• An INTRC source (approximately 31 kHz, stable
over temperature and VDD). This option frees an
1.1 New Core Features oscillator pin for use as an additional general
purpose I/O.
1.1.1 nanoWatt TECHNOLOGY
• A Phase Lock Loop (PLL) frequency multiplier,
All of the devices in the PIC18F2450/4450 family available to both the High-Speed Crystal and
incorporate a range of features that can significantly External Oscillator modes, which allows a wide
reduce power consumption during operation. Key range of clock speeds from 4 MHz to 48 MHz.
items include: • Asynchronous dual clock operation, allowing the
• Alternate Run Modes: By clocking the controller USB module to run from a high-frequency
from the Timer1 source or the internal RC oscillator while the rest of the microcontroller is
oscillator, power consumption during code clocked from an internal low-power oscillator.
execution can be reduced by as much as 90%. The internal oscillator provides a stable reference
• Multiple Idle Modes: The controller can also run source that gives the family additional features for
with its CPU core disabled but the peripherals still robust operation:
active. In these states, power consumption can be
• Fail-Safe Clock Monitor: This option constantly
reduced even further, to as little as 4% of normal
monitors the main clock source against a
operation requirements.
reference signal provided by the internal
• On-the-Fly Mode Switching: The power- oscillator. If a clock failure occurs, the controller is
managed modes are invoked by user code during switched to the internal oscillator, allowing for
operation, allowing the user to incorporate power- continued low-speed operation or a safe
saving ideas into their application’s software application shutdown.
design.
• Two-Speed Start-up: This option allows the
• Low Consumption in Key Modules: The internal oscillator to serve as the clock source
power requirements for both Timer1 and the from Power-on Reset, or wake-up from Sleep
Watchdog Timer are minimized. See mode, until the primary clock source is available.
Section 21.0 “Electrical Characteristics” for
values.
1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2450/4450 family incorporate a
fully featured Universal Serial Bus communications
module that is compliant with the USB Specification
Revision 2.0. The module supports both low-speed and
full-speed communication for all supported data
transfer types. It also incorporates its own on-chip
transceiver and 3.3V regulator and supports the use of
external transceivers and voltage regulators.

PIC18F2450/4450
1.2 Other Special Features 1.3 Details on Individual Family
• Memory Endurance: The Enhanced Flash cells
Members
for program memory are rated to last for many Devices in the PIC18F2450/4450 family are available
thousands of erase/write cycles – up to 100,000. in 28-pin and 40/44-pin packages. Block diagrams for
• Self-Programmability: These devices can write the two groups are shown in Figure 1-1 and Figure 1-2.
to their own program memory spaces under The devices are differentiated from each other in the
internal software control. By using a bootloader following two ways:
routine, located in the protected Boot Block at the
top of program memory, it becomes possible to 1. A/D channels (10 for 28-pin devices, 13 for
create an application that can update itself in the 40/44-pin devices).
field. 2. I/O ports (3 bidirectional ports and 1 input only
• Extended Instruction Set: The PIC18F2450/ port on 28-pin devices, 5 bidirectional ports on
4450 family introduces an optional extension to 40/44-pin devices).
the PIC18 instruction set, which adds 8 new All other features for devices in this family are identical.
instructions and an Indexed These are summarized in Table 1-1.
Literal Offset Addressing mode. This extension,
The pinouts for all devices are listed in Table 1-2 and
enabled as a device configuration option, has
Table 1-3.
been specifically designed to optimize re-entrant
application code originally developed in high-level Like all Microchip PIC18 devices, members of the
languages such as C. PIC18F2450/4450 family are available as both standard
• Enhanced Addressable USART: This serial and low-voltage devices. Standard devices with
communication module is capable of standard Enhanced Flash memory, designated with an “F” in the
RS-232 operation and provides support for the LIN part number (such as PIC18F2450), accommodate an
bus protocol. Other enhancements include operating VDD range of 4.2V to 5.5V. Low-voltage parts,
Automatic Baud Rate Detection and a 16-bit Baud designated by “LF” (such as PIC18LF2450), function
Rate Generator for improved resolution. over an extended VDD range of 2.0V to 5.5V.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without waiting for a sampling period and
thus, reducing code overhead.
• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other micro-
controller features. Offered as an option in select
packages, this feature allows users to develop I/O
intensive applications while retaining the ability to
program and debug in the circuit.

PIC18F2450/4450
TABLE 1-1: DEVICE FEATURES
Features PIC18F2450 PIC18F4450
Operating Frequency DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 16384 16384
Program Memory (Instructions) 8192 8192
Data Memory (Bytes) 768 768
Interrupt Sources 13 13
I/O Ports Ports A, B, C, (E) Ports A, B, C, D, E
Timers 3 3
Capture/Compare/PWM Modules 1 1
Enhanced USART 1 1
Universal Serial Bus (USB) Module 1 1
10-bit Analog-to-Digital Module 10 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR, POR, BOR,
RESET Instruction, RESET Instruction,
Stack Full, Stack Full,
Stack Underflow (PWRT, OST), Stack Underflow (PWRT, OST),
MCLR (optional), MCLR (optional),
WDT WDT
Programmable Low-Voltage Detect Yes Yes
Programmable Brown-out Reset Yes Yes
Instruction Set 75 Instructions; 75 Instructions;
83 with Extended Instruction Set 83 with Extended Instruction Set
enabled enabled
Packages 28-pin PDIP 40-pin PDIP
28-pin SOIC 44-pin QFN
44-pin TQFP

PIC18F2450/4450
FIGURE 1-1: PIC18F2450 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21> PORTA
Data Latch RA0/AN0

inc/dec logic 8 8 RA1/AN1
Data Memory RA2/AN2/VREF-
(2 Kbytes) RA3/AN3/VREF+
PCLATU PCLATH
21 RA4/T0CKI/RCV
20 Address Latch RA5/AN4/HLVDIN
PCU PCH PCL OSC2/CLKO/RA6
Program Counter 12
Data Address<12>
31 Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
(24/32 Kbytes) FSR1
FSR2 12
Data Latch PORTB
RB0/AN12/INT0
inc/dec RB1/AN10/INT1
8 logic
Table Latch RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
ROM Latch Address RB5/KBI1/PGM
Instruction Bus <16> Decode RB6/KBI2/PGC
RB7/KBI3/PGD
IR
8
Instruction State Machine
Decode & Control Signals
Control
PRODH PRODL
PORTC
8 x 8 Multiply RC0/T1OSO/T1CKI
3 8 RC1/T1OSI/UOE
(2) Internal RC2/CCP1
OSC1 Power-up
Oscillator BITOP W
Timer 8 RC4/D-/VM
Block 8 8
OSC2(2) Oscillator RC5/D+/VP
INTRC Start-up Timer RC6/TX/CK
Oscillator Power-on 8 8 RC7/RX/DT
T1OSI
Reset
ALU<8>
T1OSO Watchdog
Timer
8
Single-Supply Brown-out
MCLR(1) Reset
Programming
In-Circuit Fail-Safe
VDD, VSS Debugger Clock Monitor
PORTE
USB Voltage Band Gap
VUSB
Regulator Reference
MCLR/VPP/RE3(1)
BOR ADC
HLVD Timer0 Timer1 Timer2
10-bit
CCP1 EUSART USB
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F2450/4450
FIGURE 1-2: PIC18F4450 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21> PORTA
RA0/AN0
Data Latch RA1/AN1
inc/dec logic 8 8
RA2/AN2/VREF-
Data Memory
RA3/AN3/VREF+
PCLATU PCLATH (2 Kbytes) RA4/T0CKI/RCV
21
Address Latch RA5/AN4/HLVDIN
20
PCU PCH PCL OSC2/CLKO/RA6
Program Counter 12
Data Address<12>
PORTB
31 Level Stack
RB0/AN12/INT0
Address Latch 4 12 4
RB1/AN10/INT1
BSR Access
Program Memory STKPTR FSR0 RB2/AN8/INT2/VMO
Bank
(24/32 Kbytes) FSR1 RB3/AN9/VPO
FSR2 12 RB4/AN11/KBI0
Data Latch
RB5/KBI1/PGM
RB6/KBI2/PGC
inc/dec
8 logic RB7/KBI3/PGD
Table Latch
Address PORTC
ROM Latch
Instruction Bus <16> Decode RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
IR RC2/CCP1
RC4/D-/VM
RC5/D+/VP
8 RC6/TX/CK
Instruction State Machine RC7/RX/DT
Decode & Control Signals
Control
PRODH PRODL
PORTD
8 x 8 Multiply
3 RD0
VDD, VSS 8
Internal RD1
Oscillator Power-up RD2
OSC1(2) Timer BITOP W
Block 8 8 8 RD3
OSC2(2) Oscillator RD4
INTRC RD5
Oscillator Start-up Timer
T1OSI 8 8 RD6
Power-on RD7
T1OSO Reset ALU<8>
Watchdog 8
ICPGC(3) Timer
Single-Supply
Programming Brown-out
ICPGD(3) PORTE
Reset
In-Circuit RE0/AN5
(3)
ICPORTS Debugger Fail-Safe RE1/AN6
Clock Monitor Band Gap RE2/AN7
ICRST(3)
Reference MCLR/VPP/RE3(1)
MCLR(1) USB Voltage
Regulator
VUSB
BOR
Timer0 Timer1 Timer2
HLVD
EUSART ADC
CCP1 USB
10-bit
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated
Packages Only)” for additional information.

PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name PDIP, Description
QFN Type Type
SOIC
MCLR/Vpp/RE3 1 26 Master Clear (input) or programming voltage (input).
MCLR I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP P Programming voltage input.
RE3 I ST Digital input.
OSC1/CLKI 9 6 Oscillator crystal or external clock input.
OSC1 I Analog Oscillator crystal input or external clock source input.
CLKI I Analog External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
CLKO O — In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
RA6 I/O TTL General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
QFN Type Type
SOIC
PORTA is a bidirectional I/O port.
RA0/AN0 2 27
RA0 I/O TTL Digital I/O.
AN0 I Analog Analog input 0.
RA1/AN1 3 28
RA2/AN2/VREF- 4 1
VREF- I Analog A/D reference voltage (low) input.
RA3/AN3/VREF+ 5 2
VREF+ I Analog A/D reference voltage (high) input.
RA4/T0CKI/RCV 6 3
RA4 I/O ST Digital I/O.
T0CKI I ST Timer0 external clock input.
RCV I TTL External USB transceiver RCV input.
RA5/AN4/HLVDIN 7 4
HLVDIN I Analog High/Low-Voltage Detect input.
RA6 — — — — See the OSC2/CLKO/RA6 pin.

PIC18F2450/4450
Pin Number
Pin Buffer
QFN Type Type
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0 21 18
RB0 I/O TTL Digital I/O.
INT0 I ST External interrupt 0.
RB1/AN10/INT1 22 19
RB2/AN8/INT2/VMO 23 20
VMO O — External USB transceiver VMO output.
RB3/AN9/VPO 24 21
VPO O — External USB transceiver VPO output.
RB4/AN11/KBI0 25 22
KBI0 I TTL Interrupt-on-change pin.
RB5/KBI1/PGM 26 23
PGM I/O ST Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC 27 24
PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD 28 25
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.

PIC18F2450/4450
Pin Number
Pin Buffer
QFN Type Type
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI 11 8
RC0 I/O ST Digital I/O.
T1OSO O — Timer1 oscillator output.
T1CKI I ST Timer1external clock input.
RC1/T1OSI/UOE 12 9
T1OSI I CMOS Timer1 oscillator input.
UOE — — External USB transceiver OE output.
RC2/CCP1 13 10
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output.
RC4/D-/VM 15 12
RC4 I TTL Digital input.
D- I/O — USB differential minus line (input/output).
VM I TTL External USB transceiver VM input.
RC5/D+/VP 16 13
D+ I/O — USB differential plus line (input/output).
VP O TTL External USB transceiver VP input.
RC6/TX/CK 17 14
TX O — EUSART asynchronous transmit.
CK I/O ST EUSART synchronous clock (see RX/DT).
RC7/RX/DT 18 15
RX I ST EUSART asynchronous receive.
DT I/O ST EUSART synchronous data (see TX/CK).
RE3 — — — — See MCLR/VPP/RE3 pin.
VUSB 14 11 O — Internal USB 3.3V voltage regulator.
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.

PIC18F2450/4450
TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS
Pin Number Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type
MCLR/Vpp/RE3 1 18 18 Master Clear (input) or programming voltage (input).
MCLR I ST Master Clear (Reset) input. This pin is an
active-low Reset to the device.
VPP P Programming voltage input.
RE3 I ST Digital input.
OSC1/CLKI 13 32 30 Oscillator crystal or external clock input.
OSC1 I Analog Oscillator crystal input or external clock source input.
CLKI I Analog External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O — In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
RA6 I/O TTL General purpose I/O pin.
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2450/4450
PORTA is a bidirectional I/O port.
RA0/AN0 2 19 19
RA1/AN1 3 20 20
RA2/AN2/VREF- 4 21 21
VREF- I Analog A/D reference voltage (low) input.
RA3/AN3/VREF+ 5 22 22
VREF+ I Analog A/D reference voltage (high) input.
RA4/T0CKI/RCV 6 23 23
RA4 I/O ST Digital I/O.
RCV I TTL External USB transceiver RCV input.
RA5/AN4/HLVDIN 7 24 24
HLVDIN I Analog High/Low-Voltage Detect input.
RA6 — — — — — See the OSC2/CLKO/RA6 pin.

PIC18F2450/4450
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/AN12/INT0 33 9 8
RB1/AN10/INT1 34 10 9
RB2/AN8/INT2/VMO 35 11 10
VMO O — External USB transceiver VMO output.
RB3/AN9/VPO 36 12 11
VPO O — External USB transceiver VPO output.
RB4/AN11/KBI0 37 14 14
RB5/KBI1/PGM 38 15 15
PGM I/O ST Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC 39 16 16
PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD 40 17 17
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.

PIC18F2450/4450
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI 15 34 32
T1OSO O — Timer1 oscillator output.
RC1/T1OSI/UOE 16 35 35
T1OSI I CMOS Timer1 oscillator input.
UOE O — External USB transceiver OE output.
RC2/CCP1 17 36 36
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output.
RC4/D-/VM 23 42 42
D- I/O — USB differential minus line (input/output).
VM I TTL External USB transceiver VM input.
RC5/D+/VP 24 43 43
D+ I/O — USB differential plus line (input/output).
VP I TTL External USB transceiver VP input.
RC6/TX/CK 25 44 44
TX O — EUSART asynchronous transmit.
CK I/O ST EUSART synchronous clock (see RX/DT).
RC7/RX/DT 26 1 1
RX I ST EUSART asynchronous receive.
DT I/O ST EUSART synchronous data (see TX/CK).

PIC18F2450/4450
PORTD is a bidirectional I/O port.
RD0 19 38 38 I/O ST Digital I/O.


PIC18F2450/4450
PORTE is a bidirectional I/O port.
RE0/AN5 8 25 25
RE0 I/O ST Digital I/O.
RE1/AN6 9 26 26
RE2/AN7 10 27 27
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins.
31
VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins.
28, 29
VUSB 18 37 37 O — Internal USB 3.3V voltage regulator output.
NC/ICCK/ICPGC(1) — — 12 No Connect or dedicated ICD/ICSP™ port clock.
ICCK I/O ST In-Circuit Debugger clock.
ICPGC I/O ST ICSP programming clock.
NC/ICDT/ICPGD(1) — — 13 No Connect or dedicated ICD/ICSP port clock.
ICDT I/O ST In-Circuit Debugger data.
ICPGD I/O ST ICSP programming data.
NC/ICRST/ICVPP(1) — — 33 No Connect or dedicated ICD/ICSP port Reset.
ICRST I — Master Clear (Reset) input.
ICVPP P — Programming voltage input.
NC/ICPORTS(1) — — 34 P — No Connect or 28-pin device emulation.
ICPORTS Enable 28-pin device emulation when connected
to VSS.
NC — 13 — — — No Connect.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
2.0 OSCILLATOR 2.2 Oscillator Types
CONFIGURATIONS PIC18F2450/4450 devices can be operated in twelve
distinct oscillator modes. In contrast with the non-USB
2.1 Overview PIC18 enhanced microcontrollers, four of these modes
involve the use of two oscillator types at once. Users
Devices in the PIC18F2450/4450 family incorporate a can program the FOSC3:FOSC0 Configuration bits to
different oscillator and microcontroller clock system select one of these modes:
than the non-USB PIC18F devices. The addition of the
USB module, with its unique requirements for a stable 1. XT Crystal/Resonator
clock source, make it necessary to provide a separate 2. XTPLLCrystal/Resonator with PLL enabled
clock source that is compliant with both USB low-speed 3. HS High-Speed Crystal/Resonator
and full-speed specifications. 4. HSPLLHigh-Speed Crystal/Resonator
To accommodate these requirements, PIC18F2450/ with PLL enabled
4450 devices include a new clock branch to provide a 5. EC External Clock with FOSC/4 output
48 MHz clock for full-speed USB operation. Since it is 6. ECIO External Clock with I/O on RA6
driven from the primary clock source, an additional
7. ECPLL External Clock with PLL enabled
system of prescalers and postscalers has been added
and FOSC/4 output on RA6
to accommodate a wide range of oscillator frequencies.
An overview of the oscillator structure is shown in 8. ECPIO External Clock with PLL enabled,
Figure 2-1. I/O on RA6
Other oscillator features used in PIC18 enhanced 9. INTHS Internal Oscillator used as
microcontrollers, such as the internal RC oscillator and microcontroller clock source, HS
clock switching, remain the same. They are discussed Oscillator used as USB clock source
later in this chapter. 10. INTXT Internal Oscillator used as
microcontroller clock source, XT
2.1.1 OSCILLATOR CONTROL Oscillator used as USB clock source
The operation of the oscillator in PIC18F2450/4450 11. INTIO Internal Oscillator used as
devices is controlled through two Configuration microcontroller clock source, EC
registers and two control registers. Configuration Oscillator used as USB clock source,
registers, CONFIG1L and CONFIG1H, select the digital I/O on RA6
oscillator mode and USB prescaler/postscaler options. 12. INTCKO Internal Oscillator used as
As Configuration bits, these are set when the device is microcontroller clock source, EC
programmed and left in that configuration until the Oscillator used as USB clock source,
device is reprogrammed. FOSC/4 output on RA6
The OSCCON register (Register 2-1) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.

PIC18F2450/4450
2.2.1 OSCILLATOR MODES AND however, the microcontroller core and other peripherals
USB OPERATION can be separately clocked from the secondary or internal
oscillators as before.
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In Because of the timing requirements imposed by USB,
previous PICmicro® devices, all core and peripheral an internal clock of either 6 MHz or 48 MHz is required
clocks were driven by a single oscillator source; the usual while the USB module is enabled. Fortunately, the
sources were primary, secondary or the internal microcontroller and other peripherals are not required
oscillator. With PIC18F2450/4450 devices, the primary to run at this clock speed when using the primary
oscillator becomes part of the USB module and cannot oscillator. There are numerous options to achieve the
be associated to any other clock source. Thus, the USB USB module clock requirement and still provide
module must be clocked from the primary clock source; flexibility for clocking the rest of the device from the
primary oscillator source. These are detailed in
Section 2.3 “Oscillator Settings for USB”.
FIGURE 2-1: PIC18F2450/4450 CLOCK DIAGRAM
PIC18F2450/4450
PLLDIV USB Clock Source

÷ 12
111
÷ 10 110 USBDIV
÷6
PLL Prescaler
101 (4 MHz Input Only)

÷5 0
MUX
Primary Oscillator 100 96 MHz ÷2 1

OSC2 ÷4 PLL
011
÷3
Sleep 010
÷2 FSEN
OSC1 001
÷1 000
HSPLL, ECPLL, 1
USB
XTPLL, ECPIO Peripheral
CPUDIV
÷6 ÷4 0
PLL Postscaler
11
÷4
CPUDIV 10
÷3
01
Oscillator Postscaler
÷4 ÷2
11 00
÷3
10 CPU
XT, HS, EC, ECIO
÷2 1
01
÷1
0 Primary
00 Clock IDLEN
FOSC3:FOSC0
Secondary Oscillator Peripherals
MUX
T1OSO
T1OSC
T1OSCEN
Enable
T1OSI Oscillator
OSCCON<6:4> Internal Oscillator
Clock
Control
Internal RC Oscillator
31.25 kHz
FOSC3:FOSC0 OSCCON<1:0>
Clock Source Option

for other Modules
WDT, PWRT, FSCM

and Two-Speed Start-up

PIC18F2450/4450
2.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 2-2: CAPACITOR SELECTION FOR
RESONATORS CRYSTAL OSCILLATOR
In HS, HSPLL, XT and XTPLL Oscillator modes, a Typical Capacitor Values
crystal or ceramic resonator is connected to the OSC1 Crystal Tested:
Osc Type
and OSC2 pins to establish oscillation. Figure 2-2 Freq
shows the pin connections. C1 C2
The oscillator design requires the use of a parallel cut XT 4 MHz 27 pF 27 pF

crystal. HS 4 MHz 27 pF 27 pF
Note: Use of a series cut crystal may give a fre- 8 MHz 22 pF 22 pF
quency out of the crystal manufacturer’s 20 MHz 15 pF 15 pF
specifications.
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
FIGURE 2-2: CRYSTAL/CERAMIC
below for basic start-up and operation. These values
RESONATOR OPERATION are not optimized.
(XT, HS OR HSPLL
Different capacitor values may be required to produce
CONFIGURATION)
acceptable oscillator operation. The user should test
C1(1) OSC1 the performance of the oscillator over the expected
VDD and temperature range for the application.
To
Internal See the notes following this table for additional
XTAL Logic
RF(3) information.
Sleep Crystals Used:
RS(2)
C2(1) PIC18FXXXX 4 MHz
OSC2
8 MHz
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2. 20 MHz
2: A series resistor (RS) may be required for AT
strip cut crystals.
Note 1: Higher capacitance increases the stability
3: RF varies with the oscillator mode chosen.
of oscillator but also increases the start-
up time.
TABLE 2-1: CAPACITOR SELECTION FOR 2: When operating below 3V VDD, or when
CERAMIC RESONATORS using certain ceramic resonators at any
voltage, it may be necessary to use the
Typical Capacitor Values Used: HS mode or switch to a crystal oscillator.
Mode Freq OSC1 OSC2 3: Since each resonator/crystal has its own
characteristics, the user should consult
XT 4.0 MHz 33 pF 33 pF the resonator/crystal manufacturer for
HS 8.0 MHz 27 pF 27 pF appropriate values of external
16.0 MHz 22 pF 22 pF components.
Capacitor values are for design guidance only. 4: Rs may be required to avoid overdriving
These capacitors were tested with the resonators crystals with low drive level specification.
listed below for basic start-up and operation. These 5: Always verify oscillator performance over
values are not optimized. the VDD and temperature range that is
Different capacitor values may be required to produce expected for the application.
acceptable oscillator operation. The user should test An internal postscaler allows users to select a clock
the performance of the oscillator over the expected frequency other than that of the crystal or resonator.
VDD and temperature range for the application. Frequency division is determined by the CPUDIV Con-
See the notes following Table 2-2 for additional figuration bits. Users may select a clock frequency of
information. the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.
Resonators Used:
An external clock may also be used when the micro-
4.0 MHz controller is in HS Oscillator mode. In this case, the
8.0 MHz OSC2/CLKO pin is left open (Figure 2-3).
16.0 MHz

PIC18F2450/4450
FIGURE 2-3: EXTERNAL CLOCK INPUT 2.2.4 PLL FREQUENCY MULTIPLIER
OPERATION (HS OSC PIC18F2450/4450 devices include a Phase Locked
CONFIGURATION) Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
OSC1 be used as a microcontroller clock source.
Clock from
Ext. System PIC18FXXXX The PLL is enabled in HSPLL, XTPLL, ECPLL and
(HS Mode) ECPIO Oscillator modes. It is designed to produce a
Open OSC2
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
2.2.3 EXTERNAL CLOCK INPUT PLL has a fixed frequency input and output, there are
The EC, ECIO, ECPLL and ECPIO Oscillator modes eight prescaling options to match the oscillator input
require an external clock source to be connected to the frequency to the PLL.
OSC1 pin. There is no oscillator start-up time required There is also a separate postscaler option for deriving
after a Power-on Reset or after an exit from Sleep the microcontroller clock from the PLL. This allows the
mode. USB peripheral and microcontroller to use the same
In the EC and ECPLL Oscillator modes, the oscillator oscillator input and still operate at different clock
frequency divided by 4 is available on the OSC2 pin. speeds. In contrast to the postscaler for XT, HS and EC
This signal may be used for test purposes or to modes, the available options are 1/2, 1/3, 1/4 and 1/6
synchronize other logic. Figure 2-4 shows the pin of the PLL output.
connections for the EC Oscillator mode. The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
FIGURE 2-4: EXTERNAL CLOCK The prescaler divides the oscillator input by up to 12 to
INPUT OPERATION produce the 4 MHz drive for the PLL. The XTPLL mode
(EC AND ECPLL can only use an input frequency of 4 MHz which drives
CONFIGURATION) the PLL directly.
OSC1/CLKI FIGURE 2-6: PLL BLOCK DIAGRAM

Clock from
Ext. System PIC18FXXXX
(HS MODE)
FOSC/4 OSC2/CLKO HS/EC/ECIO/XT Oscillator Enable
PLL Enable
(from CONFIG1H Register)
The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
OSC2
becomes an additional general purpose I/O pin. The I/O Phase
Oscillator FIN Comparator
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows and
OSC1 FOUT
the pin connections for the ECIO Oscillator mode. Prescaler
FIGURE 2-5: EXTERNAL CLOCK Loop

INPUT OPERATION Filter
(ECIO AND ECPIO
CONFIGURATION)
÷24 VCO
SYSCLK
MUX
Clock from OSC1/CLKI

Ext. System PIC18FXXXX
RA6 I/O (OSC2)
The internal postscaler for reducing clock frequency in

XT and HS modes is also available in EC and ECIO
modes.

PIC18F2450/4450
2.2.5 INTERNAL OSCILLATOR 2.3 Oscillator Settings for USB
The PIC18F2450/4450 devices include an internal RC When the PIC18F2450/4450 is used for USB
oscillator (INTRC) which provides a nominal 31 kHz out- connectivity, it must have either a 6 MHz or 48 MHz
put. INTRC is enabled if it is selected as the device clock clock for USB operation, depending on whether Low-
source; it is also enabled automatically when any of the Speed or Full-Speed mode is being used. This may
following are enabled: require some forethought in selecting an oscillator
• Power-up Timer frequency and programming the device.
• Fail-Safe Clock Monitor The full range of possible oscillator configurations
• Watchdog Timer compatible with USB operation is shown in Table 2-3.
• Two-Speed Start-up
2.3.1 LOW-SPEED OPERATION
These features are discussed in greater detail in
The USB clock for Low-Speed mode is derived from
Section 18.0 “Special Features of the CPU”.
the primary oscillator chain and not directly from the
PLL. It is divided by 4 to produce the actual 6 MHz
2.2.5.1 Internal Oscillator Modes
clock. Because of this, the microcontroller can only use
When the internal oscillator is used as the micro- a clock frequency of 24 MHz when the USB module is
controller clock source, one of the other oscillator active and the controller clock source is one of the
modes (External Clock or External Crystal/Resonator) primary oscillator modes (XT, HS or EC, with or without
must be used as the USB clock source. The choice of the PLL).
USB clock source is determined by the particular This restriction does not apply if the microcontroller
internal oscillator mode. clock source is the secondary oscillator or internal
There are four distinct modes available: oscillator.
1. INTHS mode: The USB clock is provided by the
2.3.2 RUNNING DIFFERENT USB AND
oscillator in HS mode.
MICROCONTROLLER CLOCKS
2. INTXT mode: The USB clock is provided by the
oscillator in XT mode. The USB module, in either mode, can run
asynchronously with respect to the microcontroller core
3. INTCKO mode: The USB clock is provided by an
and other peripherals. This means that applications can
external clock input on OSC1/CLKI; the OSC2/
use the primary oscillator for the USB clock while the
CLKO pin outputs FOSC/4.
microcontroller runs from a separate clock source at a
4. INTIO mode: The USB clock is provided by an lower speed. If it is necessary to run the entire
external clock input on OSC1/CLKI; the OSC2/ application from only one clock source, full-speed
CLKO pin functions as a digital I/O (RA6). operation provides a greater selection of microcontroller
Of these four modes, only INTIO mode frees up an clock frequencies.
additional pin (OSC2/CLKO/RA6) for port I/O use.

PIC18F2450/4450
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller
Frequency (PLLDIV2:PLLDIV0) (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) Clock Frequency
48 MHz N/A(1) EC, ECIO None (00) 48 MHz

÷2 (01) 24 MHz
÷3 (10) 16 MHz
÷4 (11) 12 MHz
48 MHz ÷12 (111) EC, ECIO None (00) 48 MHz
÷2 (01) 24 MHz
÷3 (10) 16 MHz
÷4 (11) 12 MHz
ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
40 MHz ÷10 (110) EC, ECIO None (00) 40 MHz
÷2 (01) 20 MHz
÷3 (10) 13.33 MHz
÷4 (11) 10 MHz
ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
24 MHz ÷6 (101) HS, EC, ECIO None (00) 24 MHz
÷2 (01) 12 MHz
÷3 (10) 8 MHz
÷4 (11) 6 MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
÷2 (01) 10 MHz
÷3 (10) 6.67 MHz
÷4 (11) 5 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
÷2 (01) 8 MHz
÷3 (10) 5.33 MHz
÷4 (11) 4 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.

PIC18F2450/4450
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)
Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller
Frequency (PLLDIV2:PLLDIV0) (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) Clock Frequency

÷2 (01) 6 MHz
÷3 (10) 4 MHz
÷4 (11) 3 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
÷2 (01) 4 MHz
÷3 (10) 2.67 MHz
÷4 (11) 2 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
4 MHz ÷1 (000) XT, HS, EC, ECIO None (00) 4 MHz
÷2 (01) 2 MHz
÷3 (10) 1.33 MHz
÷4 (11) 1 MHz
HSPLL, ECPLL, XTPLL, ÷2 (00) 48 MHz
ECPIO ÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.

PIC18F2450/4450
2.4 Clock Sources and Oscillator INTRC always remains the clock source for features
Switching such as the Watchdog Timer and the Fail-Safe Clock
Monitor.
Like previous PIC18 enhanced devices, the
The OSTS and T1RUN bits indicate which clock source
PIC18F2450/4450 family includes a feature that allows
is currently providing the device clock. The OSTS bit
the device clock source to be switched from the main
indicates that the Oscillator Start-up Timer has timed out
oscillator to an alternate low-frequency clock source.
and the primary clock is providing the device clock in
PIC18F2450/4450 devices offer two alternate clock
primary clock modes. The T1RUN bit (T1CON<6>) indi-
sources. When an alternate clock source is enabled,
cates when the Timer1 oscillator is providing the device
the various power-managed operating modes are
clock in secondary clock modes. In power-managed
available.
modes, only one of these three bits will be set at any
Essentially, there are three clock sources for these time. If none of these bits are set, the INTRC is providing
devices: the clock or the internal oscillator has just started and is
• Primary oscillators not yet stable.
• Secondary oscillators The IDLEN bit determines if the device goes into Sleep
• Internal oscillator mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes and The use of the flag and control bits in the OSCCON
the internal oscillator. The particular mode is defined by register is discussed in more detail in Section 3.0
the FOSC3:FOSC0 Configuration bits. The details of “Power-Managed Modes”.
these modes are covered earlier in this chapter.
Note 1: The Timer1 oscillator must be enabled to
The secondary oscillators are those external sources select the secondary clock source. The
not connected to the OSC1 or OSC2 pins. These Timer1 oscillator is enabled by setting the
sources may continue to operate even after the T1OSCEN bit in the Timer1 Control regis-
controller is placed in a power-managed mode. ter (T1CON<3>). If the Timer1 oscillator is
PIC18F2450/4450 devices offer the Timer1 oscillator not enabled, then any attempt to select a
as a secondary oscillator. This oscillator, in all power- secondary clock source will be ignored.
managed modes, is often the time base for functions 2: It is recommended that the Timer1
such as a Real-Time Clock. Most often, a 32.768 kHz oscillator be operating and stable prior to
watch crystal is connected between the RC0/T1OSO/ switching to it as the clock source; other-
T1CKI and RC1/T1OSI/UOE pins. Like the XT and HS wise, a very long delay may occur while
Oscillator mode circuits, loading capacitors are also the Timer1 oscillator starts.
connected from each pin to ground. The Timer1
oscillator is discussed in greater detail in Section 11.3 2.4.2 OSCILLATOR TRANSITIONS
“Timer1 Oscillator”.
PIC18F2450/4450 devices contain circuitry to prevent
In addition to being a primary clock source, the internal clock “glitches” when switching between clock sources.
oscillator is available as a power-managed mode A short pause in the device clock occurs during the
clock source. The INTRC source is also used as the clock switch. The length of this pause is the sum of two
clock source for several special features, such as the cycles of the old clock source and three to four cycles
WDT and Fail-Safe Clock Monitor. of the new clock source. This formula assumes that the
new clock source is stable.
2.4.1 OSCILLATOR CONTROL REGISTER
Clock transitions are discussed in greater detail in
The OSCCON register (Register 2-1) controls several Section 3.1.2 “Entering Power-Managed Modes”.
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 Configura-
tion bits), the secondary clock (Timer1 oscillator) and the
internal oscillator. The clock source changes immedi-
ately after one or more of the bits is written to, following
a brief clock transition interval. The SCS bits are cleared
on all forms of Reset.

PIC18F2450/4450
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 U-0 U-0 U-0 R(1) U-0 R/W-0 R/W-0
IDLEN — — — OSTS — SCS1 SCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 Unimplemented: Read as ‘0’
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator
01 = Timer1 oscillator
00 = Primary oscillator
Note 1: Depends on the state of the IESO Configuration bit.

PIC18F2450/4450
2.5 Effects of Power-Managed Modes Enabling any on-chip feature that will operate during
on the Various Clock Sources Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
When PRI_IDLE mode is selected, the designated Timer1 oscillator may be operating to support a Real-
primary oscillator continues to run without interruption. Time Clock. Other features may be operating that do
For all other power-managed modes, the oscillator not require a device clock source (i.e., PSP, INTn pins
using the OSC1 pin is disabled. Unless the USB and others). Peripherals that may add significant
module is enabled, the OSC1 pin (and OSC2 pin if current consumption are listed in Section 21.2 “DC
used by the oscillator) will stop oscillating. Characteristics: Power-Down and Supply Current”.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and 2.6 Power-up Delays
providing the device clock. The Timer1 oscillator may
Power-up delays are controlled by two timers, so that no
also run in all power-managed modes if required to
external Reset circuitry is required for most applications.
clock Timer1.
The delays ensure that the device is kept in Reset until
In internal oscillator modes (RC_RUN and RC_IDLE), the device power supply is stable under normal circum-
the internal oscillator provides the device clock source. stances and the primary clock is operating and stable.
The 31 kHz INTRC output can be used directly to For additional information on power-up delays, see
provide the clock and may be enabled to support various Section 4.5 “Device Reset Timers”.
special features regardless of the power-managed
The first timer is the Power-up Timer (PWRT), which
mode (see Section 18.2 “Watchdog Timer (WDT)”,
provides a fixed delay on power-up (parameter 33,
Section 18.3 “Two-Speed Start-up” and Section 18.4
Table 21-10). It is enabled by clearing (= 0) the
“Fail-Safe Clock Monitor” for more information on
PWRTEN Configuration bit.
WDT, Fail-Safe Clock Monitor and Two-Speed Start-up).
The second timer is the Oscillator Start-up Timer
Regardless of the Run or Idle mode selected, the USB
(OST), intended to keep the chip in Reset until the
clock source will continue to operate. If the device is
crystal oscillator is stable (XT and HS modes). The
operating from a crystal or resonator-based oscillator,
OST does this by counting 1024 oscillator cycles
that oscillator will continue to clock the USB module.
before allowing the oscillator to clock the device.
The core and all other modules will switch to the new
clock source. When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
If the Sleep mode is selected, all clock sources are
the HS mode OST delay, so the PLL can lock to the
stopped. Since all the transistor switching currents
incoming clock frequency.
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage There is a delay of interval, TCSD (parameter 38,
currents). Table 21-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
Sleep mode should never be invoked while the USB
concurrently with any other delays. This may be the
module is operating and connected. The only exception
only delay that occurs when any of the EC or internal
is when the device has been issued a “Suspend” com-
oscillator modes are used as the primary clock source.
mand over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.
TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin
INTCKO Floating, pulled by external clock At logic low (clock/4 output)
INTIO Floating, pulled by external clock Configured as PORTA, bit 6
ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent
voltage level voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F2450/4450
3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES
PIC18F2450/4450 devices offer a total of seven The SCS1:SCS0 bits allow the selection of one of three
operating modes for more efficient power clock sources for power-managed modes. They are:
management. These modes provide a variety of • The primary clock, as defined by the
options for selective power conservation in applications FOSC3:FOSC0 Configuration bits
where resources may be limited (i.e., battery-powered • The secondary clock (the Timer1 oscillator)
devices). • The internal oscillator (for RC modes)
There are three categories of power-managed modes:
3.1.2 ENTERING POWER-MANAGED
• Run modes
MODES
• Idle modes
• Sleep mode Switching from one power-managed mode to another
begins by loading the OSCCON register. The
These categories define which portions of the device SCS1:SCS0 bits select the clock source and determine
are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these
Idle modes may use any of the three available clock bits causes an immediate switch to the new clock
sources (primary, secondary or internal oscillator); the source, assuming that it is running. The switch may
Sleep mode does not use a clock source. also be subject to clock transition delays. These are
The power-managed modes include several power- discussed in Section 3.1.3 “Clock Transitions and
saving features offered on previous PICmicro® Status Indicators” and subsequent sections.
devices. One is the clock switching feature, offered in Entry to the power-managed Idle or Sleep modes is
other PIC18 devices, allowing the controller to use the triggered by the execution of a SLEEP instruction. The
Timer1 oscillator in place of the primary oscillator. Also actual mode that results depends on the status of the
included is the Sleep mode, offered by all PICmicro IDLEN bit.
devices, where all device clocks are stopped.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
3.1 Selecting Power-Managed Modes not always require setting all of these bits. Many
Selecting a power-managed mode requires two transitions may be done by changing the oscillator
decisions: if the CPU is to be clocked or not and the select bits, or changing the IDLEN bit, prior to issuing a
selection of a clock source. The IDLEN bit SLEEP instruction. If the IDLEN bit is already
(OSCCON<7>) controls CPU clocking, while the configured correctly, it may only be necessary to
SCS1:SCS0 bits (OSCCON<1:0>) select the clock perform a SLEEP instruction to switch to the desired
source. The individual modes, bit settings, clock sources mode.
and affected modules are summarized in Table 3-1.
TABLE 3-1: POWER-MANAGED MODES

OSCCON Bits Module Clocking
Mode Available Clock and Oscillator Source
IDLEN(1) SCS1:SCS0 CPU Peripherals
Sleep 0 N/A Off Off None – all clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes.
This is the normal full power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 oscillator
RC_RUN N/A 1x Clocked Clocked Internal oscillator(2)
PRI_IDLE 1 00 Off Clocked Primary – all oscillator modes
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 oscillator
RC_IDLE 1 1x Off Clocked Internal oscillator(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Clock is INTRC source.

PIC18F2450/4450
3.1.3 CLOCK TRANSITIONS AND 3.2.1 PRI_RUN MODE
STATUS INDICATORS The PRI_RUN mode is the normal, full power execution
The length of the transition between clock sources is mode of the microcontroller. This is also the default
the sum of two cycles of the old clock source and three mode upon a device Reset unless Two-Speed Start-up
to four cycles of the new clock source. This formula is enabled (see Section 18.3 “Two-Speed Start-up”
assumes that the new clock source is stable. for details). In this mode, the OSTS bit is set.
Two bits indicate the current clock source and its
3.2.2 SEC_RUN MODE
status. They are:
The SEC_RUN mode is the compatible mode to the
• OSTS (OSCCON<3>)
“clock switching” feature offered in other PIC18
• T1RUN (T1CON<6>) devices. In this mode, the CPU and peripherals are
In general, only one of these bits will be set while in a clocked from the Timer1 oscillator. This gives users the
given power-managed mode. When the OSTS bit is option of lower power consumption while still using a
set, the primary clock is providing the device clock. high accuracy clock source.
When the T1RUN bit is set, the Timer1 oscillator is SEC_RUN mode is entered by setting the SCS1:SCS0
providing the clock. bits to ‘01’. The device clock source is switched to the
Note: Executing a SLEEP instruction does not Timer1 oscillator (see Figure 3-1), the primary
necessarily place the device into Sleep oscillator is shut down, the T1RUN bit (T1CON<6>) is
mode. It acts as the trigger to place the set and the OSTS bit is cleared.
controller into either the Sleep mode, or
one of the Idle modes, depending on the Note: The Timer1 oscillator should already be
setting of the IDLEN bit. running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
3.1.4 MULTIPLE SLEEP COMMANDS SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
The power-managed mode that is invoked with the Timer1 oscillator is enabled but not yet
SLEEP instruction is determined by the setting of the running, device clocks will be delayed until
IDLEN bit at the time the instruction is executed. If the oscillator has started. In such
another SLEEP instruction is executed, the device will situations, initial oscillator operation is far
enter the power-managed mode specified by IDLEN at from stable and unpredictable operation
that time. If IDLEN has changed, the device will enter may result.
the new power-managed mode specified by the new
setting. On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
3.2 Run Modes When the primary clock becomes ready, a clock switch
In the Run modes, clocks to both the core and back to the primary clock occurs (see Figure 3-2).
peripherals are active. The difference between these When the clock switch is complete, the T1RUN bit is
modes is the clock source. cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI 1 2 3 n-1 n
OSC1 Clock Transition(1)
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.

PIC18F2450/4450
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
SCS1:SCS0 bits Changed OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3 RC_RUN MODE This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
In RC_RUN mode, the CPU and peripherals are
cleared; this is to maintain software compatibility with
clocked from the internal oscillator; the primary clock is
future devices. When the clock source is switched to
shut down. When using the INTRC source, this mode
the INTRC (see Figure 3-3), the primary oscillator is
provides the best power conservation of all the Run
shut down and the OSTS bit is cleared.
modes while still executing code. It works well for user
applications which are not highly timing sensitive or do On transitions from RC_RUN mode to PRI_RUN mode,
not require high-speed clocks at all times. the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
If the primary clock source is the internal oscillator
clock becomes ready, a clock switch to the primary
(INTRC), there are no distinguishable differences
clock occurs (see Figure 3-4). When the clock switch is
between the PRI_RUN and RC_RUN modes during
complete, the OSTS bit is set and the primary clock is
execution. However, a clock switch delay will occur dur-
providing the device clock. The IDLEN and SCS bits
ing entry to and exit from RC_RUN mode. Therefore, if
are not affected by the switch. The INTRC source will
the primary clock source is the internal oscillator, the
continue to run if either the WDT or the Fail-Safe Clock
use of RC_RUN mode is not recommended.
Monitor is enabled.

PIC18F2450/4450
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC 1 2 3 n-1 n
OSC1 Clock Transition(1)
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
SCS1:SCS0 bits Changed OSTS bit Set
2: Clock transition typically occurs within 2-4 TOSC.

PIC18F2450/4450
3.3 Sleep Mode 3.4 Idle Modes
The power-managed Sleep mode in the PIC18F2450/ The Idle modes allow the controller’s CPU to be
4450 devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to
offered in all other PICmicro devices. It is entered by operate. Selecting a particular Idle mode allows users
clearing the IDLEN bit (the default state on device to further manage power consumption.
Reset) and executing the SLEEP instruction. This shuts If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
down the selected oscillator (Figure 3-5). All clock executed, the peripherals will be clocked from the clock
source status bits are cleared. source selected using the SCS1:SCS0 bits; however, the
Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are
require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP
needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a
WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode.
operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue
continue to run. to operate. If the Timer1 oscillator is enabled, it will also
When a wake event occurs in Sleep mode (by interrupt, continue to run.
Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only
until the clock source selected by the SCS1:SCS0 bits exits from any of the Idle modes are by interrupt, WDT
becomes ready (see Figure 3-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU
from the internal oscillator if either the Two-Speed execution is delayed by an interval of TCSD
Start-up or the Fail-Safe Clock Monitor are enabled (parameter 38, Table 21-10) while it becomes ready to
(see Section 18.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code,
either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current
is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE
are not affected by the wake-up. mode, the internal oscillator will clock the CPU and
peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS1:SCS0 bits.
FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit Set

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

PIC18F2450/4450
3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE
This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the
modes in that it does not disable the primary device peripherals continue to be clocked from the Timer1
clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by
the fastest resumption of device operation, with its setting the IDLEN bit and executing a SLEEP
more accurate primary clock source, since the clock instruction. If the device is in another Run mode, set
source does not have to “warm up” or transition from IDLEN first, then set SCS1:SCS0 to ‘01’ and execute
another oscillator. SLEEP. When the clock source is switched to the
PRI_IDLE mode is entered from PRI_RUN mode by Timer1 oscillator, the primary oscillator is shut down,
setting the IDLEN bit and executing a SLEEP the OSTS bit is cleared and the T1RUN bit is set.
instruction. If the device is in another Run mode, set When a wake event occurs, the peripherals continue to
IDLEN first, then clear the SCS bits and execute be clocked from the Timer1 oscillator. After an interval of
SLEEP. Although the CPU is disabled, the peripherals TCSD following the wake event, the CPU begins execut-
continue to be clocked from the primary clock source ing code being clocked by the Timer1 oscillator. The
specified by the FOSC3:FOSC0 Configuration bits. IDLEN and SCS bits are not affected by the wake-up;
The OSTS bit remains set (see Figure 3-7). the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be
primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE mode.
required between the wake event and when code If the T1OSCEN bit is not set when the
execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP
become ready to execute instructions. After the wake- instruction will be ignored and entry to
up, the OSTS bit remains set. The IDLEN and SCS bits SEC_IDLE mode will not occur. If the
are not affected by the wake-up (see Figure 3-8). Timer1 oscillator is enabled but not yet run-
ning, peripheral clocks will be delayed until
the oscillator has started. In such situations,
initial oscillator operation is far from stable
and unpredictable operation may result.
FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter PC PC + 2
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event

PIC18F2450/4450
3.4.3 RC_IDLE MODE A fixed delay of interval TCSD, following the wake event,
is required when leaving Sleep and Idle modes. This
In RC_IDLE mode, the CPU is disabled but the periph-
delay is required for the CPU to prepare for execution.
erals continue to be clocked from the internal oscillator,
Instruction execution resumes on the first clock cycle
INTRC. This mode allows for controllable power
following this delay.
conservation during Idle periods.
From RC_RUN, this mode is entered by setting the 3.5.2 EXIT BY WDT TIME-OUT
IDLEN bit and executing a SLEEP instruction. If the
A WDT time-out will cause different actions depending
device is in another Run mode, first set IDLEN, then set
on which power-managed mode the device is in when
the SCS1 bit and execute SLEEP. Although its value is
the time-out occurs.
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future If the device is not executing code (all Idle modes and
devices. When the clock source is switched to the Sleep mode), the time-out will result in an exit from the
INTRC, the primary oscillator is shut down and the power-managed mode (see Section 3.2 “Run
OSTS bit is cleared. Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
When a wake event occurs, the peripherals continue to
result in a WDT Reset (see Section 18.2 “Watchdog
be clocked from the INTRC. After a delay of TCSD fol-
Timer (WDT)”).
lowing the wake event, the CPU begins executing code
being clocked by the INTRC. The IDLEN and SCS bits 3.5.3 EXIT BY RESET
are not affected by the wake-up. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock Normally, the device is held in Reset by the Oscillator
Monitor is enabled. Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code.
3.5 Exiting Idle and Sleep Modes
The exit delay time from Reset to the start of code
An exit from Sleep mode or any of the Idle modes is execution depends on both the clock sources before
triggered by an interrupt, a Reset or a WDT time-out. and after the wake-up and the type of oscillator if the
This section discusses the triggers that cause exits new clock source is the primary clock. Exit delays are
from power-managed modes. The clocking subsystem summarized in Table 3-2.
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3 Code execution can begin before the primary clock
“Sleep Mode” and Section 3.4 “Idle Modes”). becomes ready. If either the Two-Speed Start-up (see
Section 18.3 “Two-Speed Start-up”) or Fail-Safe
3.5.1 EXIT BY INTERRUPT Clock Monitor (see Section 18.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
Any of the available interrupt sources can cause the as soon as the Reset source has cleared. Execution is
device to exit from an Idle mode, or the Sleep mode, to clocked by the INTRC driven by the internal oscillator.
a Run mode. To enable this functionality, an interrupt Execution is clocked by the internal oscillator until
source must be enabled by setting its enable bit in one either the primary clock becomes ready or a power-
of the INTCON or PIE registers. The exit sequence is managed mode is entered before the primary clock
initiated when the corresponding interrupt flag bit is set. becomes ready; the primary clock is then shut down.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execution
continues or resumes without branching (see
Section 8.0 “Interrupts”).

PIC18F2450/4450
3.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either
START-UP DELAY does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
Certain exits from power-managed modes do not
require an oscillator start-up delay (EC and any internal
invoke the OST at all. There are two cases:
oscillator modes). However, a fixed delay of interval
• PRI_IDLE mode, where the primary clock source TCSD following the wake event is still required when
is not stopped; and leaving Sleep and Idle modes to allow the CPU to
• the primary clock source is not any of the XT or prepare for execution. Instruction execution resumes
HS modes. on the first clock cycle following this delay.
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source Clock Ready Status
Exit Delay
Before Wake-up After Wake-up Bit (OSCCON)
XT, HS
Primary Device Clock XTPLL, HSPLL
None OSTS
(PRI_IDLE mode) EC
INTRC(1)
XT, HS TOST(3)
XTPLL, HSPLL TOST + trc(3)
T1OSC or INTRC(1) OSTS
EC TCSD(2)
INTRC(1) TIOBST(4)
XT, HS TOST(3)
XTPLL, HSPLL TOST + trc(3)
INTRC(1) OSTS
EC TCSD(2)
INTRC(1) None
XT, HS TOST(3)
None XTPLL, HSPLL TOST + trc(3)
OSTS
(Sleep mode) EC TCSD(2)
INTRC(1) TIOBST(4)
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: TOST is the Oscillator Start-up Timer period (parameter 32, Table 21-10). trc is the PLL lock time-out
(parameter F12, Table 21-7); it is also designated as TPLL.
4: Execution continues during TIOBST (parameter 39, Table 21-10), the INTRC stabilization period.

PIC18F2450/4450
4.0 RESET A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
The PIC18F2450/4450 devices differentiate between
various kinds of Reset: 4.1 RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
b) MCLR Reset during normal operation
register (Register 4-1). The lower five bits of the
c) MCLR Reset during power-managed modes register indicate that a specific Reset event has
d) Watchdog Timer (WDT) Reset (during occurred. In most cases, these bits can only be cleared
execution) by the event and must be set by the application after
e) Programmable Brown-out Reset (BOR) the event. The state of these flag bits, taken together,
f) RESET Instruction can be read to indicate the type of Reset that just
occurred. This is described in more detail in
g) Stack Full Reset
Section 4.6 “Reset State of Registers”.
h) Stack Underflow Reset
The RCON register also has control bits for setting
This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the
POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in
start-up timers. Stack Reset events are covered in Section 8.0 “Interrupts”. BOR is covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”. Section 4.4 “Brown-out Reset (BOR)”.
WDT Resets are covered in Section 18.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET Instruction
Stack Stack Full/Underflow Reset

Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse

Detect
VDD
Brown-out
Reset
BOREN S
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-bit Ripple Counter R Q
OSC1
32 μs 65.5 ms
PWRT
INTRC(1) 11-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.

PIC18F2450/4450
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after POR).

PIC18F2450/4450
4.2 Master Clear Reset (MCLR) FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
The MCLR pin provides a method for triggering an
SLOW VDD POWER-UP)
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small VDD VDD
pulses.
The MCLR pin is not driven low by any internal Resets, D R
including the WDT. R1
MCLR
In PIC18F2450/4450 devices, the MCLR input can be
disabled with the MCLRE Configuration bit. When C PIC18FXXXX
MCLR is disabled, the pin becomes a digital input. See
Section 9.5 “PORTE, TRISE and LATE Registers”
for more information.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
4.3 Power-on Reset (POR) The diode D helps discharge the capacitor
quickly when VDD powers down.
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This 2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
allows the device to start in the initialized state when
the device’s electrical specification.
VDD is adequate for operation.
3: R1 ≥ 1 kΩ will limit any current flowing into
To take advantage of the POR circuitry, tie the MCLR pin MCLR from external capacitor C, in the event
through a resistor (1 kΩ to 10 kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to Electro-
eliminate external RC components usually needed to static Discharge (ESD) or Electrical
create a Power-on Reset delay. A minimum rise rate for Overstress (EOS).
VDD is specified (parameter D004, Section267 “DC
Characteristics”). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.

PIC18F2450/4450
4.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
PIC18F2450/4450 devices implement a BOR circuit environment without having to reprogram the device to
that provides the user with a number of configuration change BOR configuration. It also allows the user to
and power-saving options. The BOR is controlled by tailor device power consumption in software by eliminat-
the BORV1:BORV0 and BOREN1:BOREN0 ing the incremental current that the BOR consumes.
Configuration bits. There are a total of four BOR While the BOR current is typically very small, it may have
configurations which are summarized in Table 4-1. some impact in low-power applications.
The BOR threshold is set by the BORV1:BORV0 bits. If
Note: Even when BOR is under software control,
BOR is enabled (any values of BOREN1:BOREN0
the BOR Reset voltage level is still set by
except ‘00’), any drop of VDD below VBOR (parameter
the BORV1:BORV0 Configuration bits. It
D005, Section 267 “DC Characteristics: Supply
cannot be changed in software.
Voltage”) for greater than TBOR (parameter 35,
Table 21-10) will reset the device. A Reset may or may
4.4.2 DETECTING BOR
not occur if VDD falls below VBOR for less than TBOR.
The chip will remain in Brown-out Reset until VDD rises When BOR is enabled, the BOR bit always resets to ‘0’
above VBOR. on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
If the Power-up Timer is enabled, it will be invoked after
the state of BOR alone. A more reliable method is to
VDD rises above VBOR; it then will keep the chip in
simultaneously check the state of both POR and BOR.
Reset for an additional time delay, TPWRT
This assumes that the POR bit is reset to ‘1’ in software
(parameter 33, Table 21-10). If VDD drops below VBOR
immediately after any POR event. IF BOR is ‘0’ while
while the Power-up Timer is running, the chip will go
POR is ‘1’, it can be reliably assumed that a BOR event
back into a Brown-out Reset and the Power-up Timer
has occurred.
will be initialized. Once VDD rises above VBOR, the
Power-up Timer will execute the additional time delay. 4.4.3 DISABLING BOR IN SLEEP MODE
BOR and the Power-on Timer (PWRT) are When BOREN1:BOREN0 = 10, the BOR remains
independently configured. Enabling BOR Reset does under hardware control and operates as previously
not automatically enable the PWRT. described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
4.4.1 SOFTWARE ENABLED BOR
device returns to any other operating mode, BOR is
When BOREN1:BOREN0 = 01, the BOR can be automatically re-enabled.
enabled or disabled by the user in software. This is
This mode allows for applications to recover from
done with the control bit, SBOREN (RCON<6>).
brown-out situations, while actively executing code,
Setting SBOREN enables the BOR to function as
when the device requires BOR protection the most. At
previously described. Clearing SBOREN disables the
the same time, it saves additional power in Sleep mode
BOR entirely. The SBOREN bit operates only in this
by eliminating the small incremental BOR current.
mode; otherwise, it is read as ‘0’.
TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Status of
SBOREN BOR Operation
BOREN1 BOREN0 (RCON<6>)
0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
0 1 Available BOR enabled in software; operation controlled by SBOREN.
1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.

PIC18F2450/4450
4.5 Device Reset Timers 4.5.3 PLL LOCK TIME-OUT
PIC18F2450/4450 devices incorporate three separate With the PLL enabled in its PLL mode, the time-out
on-chip timers that help regulate the Power-on Reset sequence following a Power-on Reset is slightly differ-
process. Their main function is to ensure that the ent from other oscillator modes. A separate timer is
device clock is stable before code is executed. These used to provide a fixed time-out that is sufficient for the
timers are: PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
• Power-up Timer (PWRT) oscillator start-up time-out.
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out 4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
4.5.1 POWER-UP TIMER (PWRT)
1. After the POR condition has cleared, PWRT
The Power-up Timer (PWRT) of the PIC18F2450/4450 time-out is invoked (if enabled).
devices is an 11-bit counter which uses the INTRC
2. Then, the OST is activated.
source as the clock input. This yields an approximate
time interval of 2048 x 32 μs = 65.6 ms. While the The total time-out will vary based on oscillator configu-
PWRT is counting, the device is held in Reset. ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
The power-up time delay depends on the INTRC clock
depict time-out sequences on power-up, with the
and will vary from chip to chip due to temperature and
Power-up Timer enabled and the device operating in
process variation. See DC parameter 33 (Table 21-10)
HS Oscillator mode. Figure 4-3 through Figure 4-6 also
for details.
apply to devices operating in XT mode. For devices in
The PWRT is enabled by clearing the PWRTEN RC mode and with the PWRT disabled, on the other
Configuration bit. hand, there will be no time-out at all.
4.5.2 OSCILLATOR START-UP Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
TIMER (OST)
Bringing MCLR high will begin execution immediately
The Oscillator Start-up Timer (OST) provides a (Figure 4-5). This is useful for testing purposes or to
1024 oscillator cycle (from OSC1 input) delay after the synchronize more than one PIC18FXXXX device
PWRT delay is over (parameter 33, Table 21-10). This operating in parallel.
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Power-up(2) and Brown-out Exit from

Configuration PWRTEN = 0 PWRTEN = 1 Power-Managed Mode
HS, XT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC

HSPLL, XTPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
EC, ECIO 66 ms(1) — —
ECPLL, ECPIO 66 ms(1) + 2 ms(2) 2 ms(2) 2 ms(2)
INTIO, INTCKO 66 ms(1) — —
INTHS, INTXT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.

PIC18F2450/4450
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET

PIC18F2450/4450
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD 0V 1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT TPLL
PLL TIME-OUT
INTERNAL RESET
Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the Power-up Timer.

PIC18F2450/4450
4.6 Reset State of Registers POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
Most registers are unaffected by a Reset. Their status are used in software to determine the nature of the
is unknown on POR and unchanged by all other Reset.
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred. Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Most registers are not affected by a WDT wake-up, Power-on and Brown-out Resets, Master Clear and
since this is viewed as the resumption of normal oper- WDT Resets and WDT wake-ups.
ation. Status bits from the RCON register, RI, TO, PD,
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Program RCON Register STKPTR Register

Condition
Counter SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
(2)
Brown-out 0000h u 1 1 1 u 0 u u
MCLR during Power-Managed 0000h u(2) u 1 u u u u u
Run modes
MCLR during Power-Managed 0000h u(2) u 1 0 u u u u
Idle modes and Sleep mode
WDT Time-out during Full Power or 0000h u(2) u 0 u u u u u
Power-Managed Run modes
MCLR during Full Power Execution 0000h u(2) u u u u u u u
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
(2)
Stack Underflow Reset 0000h u u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an actual 0000h u(2) u u u u u u 1
Reset, STVREN = 0)
WDT Time-out during Power-Managed PC + 2 u(2) u 0 0 u u u u
Idle or Sleep modes
Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u
Power-Managed modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

PIC18F2450/4450
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
Power-on Reset, WDT Reset, Wake-up via WDT
Register Applicable Devices
Brown-out Reset RESET Instruction, or Interrupt
Stack Resets
TOSU 2450 4450 ---0 0000 ---0 0000 ---0 uuuu(1)
TOSH 2450 4450 0000 0000 0000 0000 uuuu uuuu(1)
TOSL 2450 4450 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR 2450 4450 00-0 0000 uu-0 0000 uu-u uuuu(1)
PCLATU 2450 4450 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2450 4450 0000 0000 0000 0000 uuuu uuuu
PCL 2450 4450 0000 0000 0000 0000 PC + 2(3)
TBLPTRU 2450 4450 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2450 4450 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2450 4450 0000 0000 0000 0000 uuuu uuuu
TABLAT 2450 4450 0000 0000 0000 0000 uuuu uuuu
PRODH 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2450 4450 0000 000x 0000 000u uuuu uuuu(2)
INTCON2 2450 4450 1111 -1-1 1111 -1-1 uuuu -u-u(2)
INTCON3 2450 4450 11-0 0-00 11-0 0-00 uu-u u-uu(2)
INDF0 2450 4450 N/A N/A N/A
POSTINC0 2450 4450 N/A N/A N/A
POSTDEC0 2450 4450 N/A N/A N/A
PREINC0 2450 4450 N/A N/A N/A
PLUSW0 2450 4450 N/A N/A N/A
FSR0H 2450 4450 ---- 0000 ---- 0000 ---- uuuu
FSR0L 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2450 4450 N/A N/A N/A
PLUSW1 2450 4450 N/A N/A N/A
FSR1H 2450 4450 ---- 0000 ---- 0000 ---- uuuu
BSR 2450 4450 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2450/4450
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Stack Resets
INDF2 2450 4450 N/A N/A N/A
PLUSW2 2450 4450 N/A N/A N/A
FSR2H 2450 4450 ---- 0000 ---- 0000 ---- uuuu
STATUS 2450 4450 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2450 4450 0000 0000 0000 0000 uuuu uuuu
TMR0L 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2450 4450 1111 1111 1111 1111 uuuu uuuu
OSCCON 2450 4450 0--- q-00 0--- 0-q0 u--- u-qu
HLVDCON 2450 4450 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 2450 4450 ---- ---0 ---- ---0 ---- ---u
(4)
RCON 2450 4450 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2450 4450 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2450 4450 0000 0000 0000 0000 uuuu uuuu
PR2 2450 4450 1111 1111 1111 1111 1111 1111
T2CON 2450 4450 -000 0000 -000 0000 -uuu uuuu
ADRESH 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2450 4450 --00 0000 --00 0000 --uu uuuu
ADCON1 2450 4450 --00 qqqq --00 qqqq --uu uuuu
ADCON2 2450 4450 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2450 4450 --00 0000 --00 0000 --uu uuuu
SPBRG 2450 4450 0000 0000 0000 0000 uuuu uuuu
RCREG 2450 4450 0000 0000 0000 0000 uuuu uuuu
TXREG 2450 4450 0000 0000 0000 0000 uuuu uuuu
hardware stack.

PIC18F2450/4450
MCLR Resets,
Stack Resets
TXSTA 2450 4450 0000 0010 0000 0010 uuuu uuuu
RCSTA 2450 4450 0000 000x 0000 000x uuuu uuuu
EECON2 2450 4450 0000 0000 0000 0000 0000 0000
EECON1 2450 4450 -x-0 x00- -u-0 u00- -u-0 u00-
IPIR2 2450 4450 1-1- -1-- 1-1- -1-- u-u- -u--
PIR2 2450 4450 0-0- -0-- 0-0- -0-- u-u- -u--(2)
PIE2 2450 4450 0-0- -0-- 0-0- -0-- u-u- -u--
IPR1 2450 4450 -111 -111 -111 -111 -uuu -uuu
PIR1 2450 4450 -000 -000 -000 -000 -uuu -uuu(2)
PIE1 2450 4450 -000 -000 -000 -000 -uuu -uuu
TRISE 2450 4450 ---- -111 ---- -111 uuuu -uuu
TRISD 2450 4450 1111 1111 1111 1111 uuuu uuuu
TRISC 2450 4450 11-- -111 11-- -111 uu-- -uuu
TRISB 2450 4450 1111 1111 1111 1111 uuuu uuuu
(5)
TRISA 2450 4450 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 2450 4450 ---- -xxx ---- -uuu ---- -uuu
LATD 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2450 4450 xx-- -xxx uu-- -uuu uu-- -uuu
LATB 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 2450 4450 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 2450 4450 ---- x000 ---- x000 ---- uuuu
PORTD 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2450 4450 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
(5)
PORTA 2450 4450 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
UEP15 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP14 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP13 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP12 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP11 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP10 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP9 2450 4450 ---0 0000 ---0 0000 ---u uuuu
hardware stack.

PIC18F2450/4450
MCLR Resets,
Stack Resets
UEP8 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP7 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP6 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP5 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP4 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP3 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP2 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP1 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP0 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UCFG 2450 4450 00-0 0000 00-0 0000 uu-u uuuu
UADDR 2450 4450 -000 0000 -000 0000 -uuu uuuu
UCON 2450 4450 -0x0 000- -0x0 000- -uuu uuu-
USTAT 2450 4450 -xxx xxx- -xxx xxx- -uuu uuu-
UEIE 2450 4450 0--0 0000 0--0 0000 u--u uuuu
UEIR 2450 4450 0--0 0000 0--0 0000 u--u uuuu
UIE 2450 4450 -000 0000 -000 0000 -uuu uuuu
UIR 2450 4450 -000 0000 -000 0000 -uuu uuuu
UFRMH 2450 4450 ---- -xxx ---- -xxx ---- -uuu
UFRML 2450 4450 xxxx xxxx xxxx xxxx uuuu uuuu
hardware stack.

PIC18F2450/4450
5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization
There are two types of memory in PIC18F2450/4450 PIC18 microcontrollers implement a 21-bit program
microcontroller devices: counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
• Program Memory
the upper boundary of the physically implemented
• Data RAM memory and the 2-Mbyte address will return all ‘0’s (a
As Harvard architecture devices, the data and program NOP instruction).
memories use separate busses; this allows for The PIC18F2450 and PIC18F4450 each have 16 Kbytes
concurrent access of the two memory spaces. of Flash memory and can store up to 8192 single-word
Additional detailed information on the operation of the instructions.
Flash program memory is provided in Section 6.0 PIC18 devices have two interrupt vectors. The Reset
“Flash Program Memory”. vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for PIC18F2450 and
PIC18F4450 devices are shown in Figure 5-1.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2450/4450 DEVICES
PIC18F2450/4450
PC<20:0>
CALL, RCALL, RETURN, 21
RETFIE, RETLW, CALLW,
ADDULNK, SUBULNK
Stack Level 1
•
•
•
Stack Level 31
Reset Vector 0000h
High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h
On-Chip
Program Memory
3FFFh
4000h
User Memory Space
Read ‘0’
1FFFFFh
200000h

PIC18F2450/4450
5.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
The Program Counter (PC) specifies the address of the
part of either program or data space. The Stack Pointer
instruction to fetch for execution. The PC is 21 bits wide
is readable and writable and the address on the top of
and is contained in three separate 8-bit registers. The
the stack is readable and writable through the Top-of-
low byte, known as the PCL register, is both readable
Stack Special Function Registers. Data can also be
and writable. The high byte, or PCH register, contains
pushed to, or popped from the stack, using these
the PC<15:8> bits; it is not directly readable or writable.
registers.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack.
register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location
directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the
register are performed through the PCLATU register. contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
The contents of PCLATH and PCLATU are transferred
a pop from the stack. The contents of the location
to the program counter by any operation that writes
pointed to by the STKPTR are transferred to the PC
PCL. Similarly, the upper two bytes of the program
and then the Stack Pointer is decremented.
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all
offsets to the PC (see Section 5.1.4.1 “Computed Resets. There is no RAM associated with the location
GOTO”). corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
The PC addresses bytes in the program memory. To
full, has overflowed or has underflowed.
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
5.1.2.1 Top-of-Stack Access
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory. Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
The CALL, RCALL and GOTO program branch
TOSU:TOSH:TOSL, hold the contents of the stack loca-
instructions write to the program counter directly. For
tion pointed to by the STKPTR register (Figure 5-2). This
these instructions, the contents of PCLATH and
allows users to implement a software stack if necessary.
PCLATU are not transferred to the program counter.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
5.1.2 RETURN ADDRESS STACK
registers. These values can be placed on a user-defined
The return address stack allows any combination of up software stack. At return time, the software can return
to 31 program calls and interrupts to occur. The PC is these values to TOSU:TOSH:TOSL and do a return.
pushed onto the stack when a CALL or RCALL
The user must disable the global interrupt enable bits
instruction is executed or an interrupt is Acknowledged.
while accessing the stack to prevent inadvertent stack
The PC value is pulled off the stack on a RETURN,
corruption.
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack<20:0>
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
TOSU TOSH TOSL STKPTR<4:0>

00h 1Ah 34h 00010
00011
Top-of-Stack 001A34h 00010
000D58h 00001
00000

PIC18F2450/4450
5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
The STKPTR register (Register 5-1) contains the Stack
to the PC and sets the STKUNF bit, while the Stack
Pointer value, the STKFUL (Stack Full) status bit and
Pointer remains at zero. The STKUNF bit will remain
the STKUNF (Stack Underflow) status bit. The value of
set until cleared by software or until a POR occurs.
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an
stack and decrements after values are popped off the underflow has the effect of vectoring the
stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the
The user may read and write the Stack Pointer value. stack conditions can be verified and
This feature can be used by a Real-Time Operating appropriate actions can be taken. This is
System (RTOS) for return stack maintenance. not the same as a Reset, as the contents
After the PC is pushed onto the stack 31 times (without of the SFRs are not affected.
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a 5.1.2.3 PUSH and POP Instructions
POR. Since the Top-of-Stack is readable and writable, the
The action that takes place when the stack becomes ability to push values onto the stack and pull values off
full depends on the state of the STVREN (Stack the stack, without disturbing normal program execu-
Overflow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set
Section 18.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit
the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control.
(default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data
onto the stack, set the STKFUL bit and reset the or a return address on the stack.
device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto
Pointer will be set to zero. the stack. This increments the Stack Pointer and loads
If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack.
31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by
Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value
and the STKPTR will remain at 31. pushed onto the stack then becomes the TOS value.
REGISTER 5-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend: C = Clearable bit

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F2450/4450
5.1.2.4 Stack Full and Underflow Resets 5.1.4 LOOK-UP TABLES IN PROGRAM
Device Resets on stack overflow and stack underflow MEMORY
conditions are enabled by setting the STVREN bit in There may be programming situations that require the
Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in
or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables
or STKUNF bit and then cause a device Reset. When can be implemented in two ways:
STVREN is cleared, a full or underflow condition will set
• Computed GOTO
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are • Table Reads
cleared by user software or a Power-on Reset.
5.1.4.1 Computed GOTO
5.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset
A Fast Register Stack is provided for the STATUS, to the program counter. An example is shown in
WREG and BSR registers to provide a “fast return” Example 5-2.
option for interrupts. Each stack is only one level deep A look-up table can be formed with an ADDWF PCL
and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The
current value of the corresponding register when the W register is loaded with an offset into the table before
processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the
will push values into the stack registers. The values in called routine is the ADDWF PCL instruction. The next
the registers are then loaded back into their associated instruction executed will be one of the RETLW nn
registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling
return from the interrupt. function.
If both low and high priority interrupts are enabled, the The offset value (in WREG) specifies the number of
stack registers cannot be used reliably to return from bytes that the program counter should advance and
low priority interrupts. If a high priority interrupt occurs should be multiples of 2 (LSb = 0).
while servicing a low priority interrupt, the stack register In this method, only one data byte may be stored in
values stored by the low priority interrupt will be each instruction location and room on the return
overwritten. In these cases, users must save the key address stack is required.
registers in software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING
Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE
interrupts are used, the Fast Register Stack can be
MOVF OFFSET, W
used to restore the STATUS, WREG and BSR registers
CALL TABLE
at the end of a subroutine call. To use the Fast Register ORG nn00h
Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL
instruction must be executed to save the STATUS, RETLW nnh
WREG and BSR registers to the Fast Register Stack. A RETLW nnh
RETURN, FAST instruction is then executed to restore RETLW nnh
these registers from the Fast Register Stack. .
.
Example 5-1 shows a source code example that uses .
the Fast Register Stack during a subroutine call and
return.
5.1.4.2 Table Reads and Table Writes
EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory
CODE EXAMPLE allows two bytes of data to be stored in each instruction
location.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per
;STACK program word by using table reads and writes. The
• Table Pointer (TBLPTR) register specifies the byte
• address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
SUB1 •
memory. Data is transferred to or from program
•
RETURN, FAST ;RESTORE VALUES SAVED
memory one byte at a time.
;IN FAST REGISTER STACK Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.

PIC18F2450/4450
5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are
The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one
internal or external source, is internally divided by four instruction cycle, while the decode and execute takes
to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the
(Q1, Q2, Q3 and Q4). Internally, the program counter is pipelining, each instruction effectively executes in one
incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to
from the program memory and latched into the Instruc- change (e.g., GOTO), then two cycles are required to
tion Register (IR) during Q4. The instruction is decoded complete the instruction (Example 5-3).
and executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC)
clocks and instruction execution flow are shown in incrementing in Q1.
Figure 5-3.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 Phase
Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

PIC18F2450/4450
5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute
MEMORY program memory address embedded into the
instruction. Since instructions are always stored on word
The program memory is addressed in bytes.
boundaries, the data contained in the instruction is a
Instructions are stored as two bytes or four bytes in
word address. The word address is written to PC<20:1>,
program memory. The Least Significant Byte of an
which accesses the desired byte address in program
instruction word is always stored in a program memory
memory. Instruction #2 in Figure 5-4 shows how the
location with an even address (LSb = 0). To maintain
instruction, GOTO 0006h, is encoded in the program
alignment with instruction boundaries, the PC
memory. Program branch instructions, which encode a
increments in steps of 2 and the LSb will always read
relative address offset, operate in the same manner. The
‘0’ (see Section 5.1.1 “Program Counter”).
offset value stored in a branch instruction represents the
Figure 5-4 shows an example of how instruction words number of single-word instructions that the PC will be
are stored in the program memory. offset by. Section 19.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

Word Address
LSB = 1 LSB = 0 ↓
Program Memory 000000h
Byte Locations → 000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
5.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is
skipped for some reason and the second word is
The standard PIC18 instruction set has four two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all
necessary for cases when the two-word instruction is
cases, the second word of the instructions always has
preceded by a conditional instruction that changes the
‘1111’ as its four Most Significant bits; the other 12 bits
PC. Example 5-4 shows how this works.
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section 5.5 “Program Memory and
specifies a special form of NOP. If the instruction is the Extended Instruction Set” for
executed in proper sequence, immediately after the information on two-word instruction in the
first word, the data in the second word is accessed and extended instruction set.
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2450/4450
5.3 Data Memory Organization 5.3.2 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
Note: The operation of some aspects of data
addressing scheme to make rapid access to any
memory are changed when the PIC18
address possible. Ideally, this means that an entire
extended instruction set is enabled. See
address does not need to be provided for each read or
Section 5.6 “Data Memory and the
write operation. For PIC18 devices, this is
Extended Instruction Set” for more
accomplished with a RAM banking scheme. This
information.
divides the memory space into 16 contiguous banks of
The data memory in PIC18 devices is implemented as 256 bytes. Depending on the instruction, each location
static RAM. Each register in the data memory has a can be addressed directly by its full 12-bit address, or
12-bit address, allowing up to 4096 bytes of data an 8-bit low-order address and a 4-bit Bank Pointer.
memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use
16 banks that contain 256 bytes each. PIC18F2450/ of the Bank Pointer, known as the Bank Select Register
4450 devices implement three complete banks, for a (BSR). This SFR holds the 4 Most Significant bits of a
total of 768 bytes. Figure 5-5 shows the data memory location’s address; the instruction itself includes the
organization for the devices. 8 Least Significant bits. Only the four lower bits of the
The data memory contains Special Function Registers BSR are implemented (BSR3:BSR0). The upper four
(SFRs) and General Purpose Registers (GPRs). The bits are unused; they will always read ‘0’ and cannot be
SFRs are used for control and status of the controller written to. The BSR can be loaded directly by using the
and peripheral functions, while GPRs are used for data MOVLB instruction.
storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data
application. Any read of an unimplemented location will memory. The eight bits in the instruction show the loca-
read as ‘0’s. tion in the bank and can be thought of as an offset from
The instruction set and architecture allow operations the bank’s lower boundary. The relationship between
across all banks. The entire data memory may be the BSR’s value and the bank division in data memory
accessed by Direct, Indirect or Indexed Addressing is shown in Figure 5-6.
modes. Addressing modes are discussed later in this Since up to 16 registers may share the same low-order
subsection. address, the user must always be careful to ensure that
To ensure that commonly used registers (SFRs and the proper bank is selected before performing a data
select GPRs) can be accessed in a single cycle, PIC18 read or write. For example, writing what should be
devices implement an Access Bank. This is a 256-byte program data to an 8-bit address of F9h, while the BSR
memory space that provides fast access to SFRs and is 0Fh, will end up resetting the program counter.
the lower portion of GPR Bank 0 without using the While any bank can be selected, only those banks that
BSR. Section 5.3.3 “Access Bank” provides a are actually implemented can be read or written to.
detailed description of the Access RAM. Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
5.3.1 USB RAM so, the STATUS register will still be affected as if the
Bank 4 of the data memory is actually mapped to operation was successful. The data memory map in
special dual port RAM. When the USB module is Figure 5-6 indicates which banks are implemented.
disabled, the GPRs in these banks are used like any In the core PIC18 instruction set, only the MOVFF
other GPR in the data memory space. instruction fully specifies the 12-bit address of the
When the USB module is enabled, the memory in this source and target registers. This instruction ignores the
bank is allocated as buffer RAM for USB operation. BSR completely when it executes. All other instructions
This area is shared between the microcontroller core include only the low-order address as an operand and
and the USB Serial Interface Engine (SIE) and is used must use either the BSR or the Access Bank to locate
to transfer data directly between the two. their target registers.
It is theoretically possible to use this area of USB RAM
that is not allocated as USB buffers for normal scratch-
pad memory or other variable storage. In practice, the
dynamic nature of buffer allocation makes this risky at
best. Bank 4 is also used for USB buffer management
when the module is enabled and should not be used for
any other purposes during that time.
Additional information on USB RAM and buffer
operation is provided in Section 14.0 “Universal
Serial Bus (USB)”.

PIC18F2450/4450
FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2450/4450 DEVICES
When a = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh
Bank 0 060h The first 96 bytes are
FFh GPR 0FFh general purpose RAM
00h 100h (from Bank 0).
= 0001
Bank 1 GPR The remaining 160 bytes are
FFh 1FFh Special Function Registers
= 0010 00h 200h (from Bank 15).
Bank 2 Unused
Read as 00h When a = 1:
FFh 2FFh
= 0011 00h 300h The BSR specifies the bank
Bank 3 Unused
used by the instruction.
Read as 00h
FFh 3FFh
00h 400h
= 0100 Bank 4 GPR(1)
FFh 4FFh
= 0101 00h 800h
Bank 5
Access Bank
00h
Access RAM Low
5Fh
Access RAM High 60h
(SFRs) FFh
to
Unused
Read as 00h
= 1110
Bank 14
FFh EFFh
00h Unused F00h
= 1111 F5Fh
Bank 15
SFR F60h
FFh FFFh
Note 1: This bank also serve as RAM buffer for USB operation. See Section 5.3.1 “USB RAM” for more
information.

PIC18F2450/4450
FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
Data Memory From Opcode(2)
7 0 000h 00h 7 0
0 0 0 0 0 0 1 1 Bank 0 1 1 1 1 1 1 1 1
100h FFh
00h
Bank 1
Bank Select(2) 200h FFh
00h
Bank 2
300h FFh
00h
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
5.3.3 ACCESS BANK however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
While the use of the BSR, with an embedded 8-bit
ignored entirely.
address, allows users to address the entire range of
data memory, it also means that the user must always Using this “forced” addressing allows the instruction to
ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle without
data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 60h and
This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate
of an operation but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 60h
Verifying and/or changing the BSR for each read or is a good place for data values that the user might need
write to data memory can become very inefficient. to access rapidly, such as immediate computational
results or common program variables. Access RAM
To streamline access for the most commonly used data
also allows for faster and more code efficient context
memory locations, the data memory is configured with
saving and switching of variables.
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different
The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST
memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail
memory (60h-FFh) in Block 15. The lower half is known in Section 5.6.3 “Mapping the Access Bank in
as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”.
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the 5.3.4 GENERAL PURPOSE
Access Bank and can be addressed in a linear fashion REGISTER FILE
by an 8-bit address (Figure 5-5). PIC18 devices may have banked memory in the GPR
The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all
that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0
the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of
uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on
opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets.

PIC18F2450/4450
5.3.5 SPECIAL FUNCTION REGISTERS peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
The Special Function Registers (SFRs) are registers ALU’s STATUS register is described later in this
used by the CPU and peripheral modules for controlling section. Registers related to the operation of a
the desired operation of the device. These registers are peripheral feature are described in the chapter for that
implemented as static RAM in the data memory space. peripheral.
SFRs start at the top of data memory and extend
downward to occupy the top segment of Bank 15, from The SFRs are typically distributed among the
F60h to FFFh. A list of these registers is given in peripherals whose functions they control. Unused SFR
Table 5-1 and Table 5-2. locations are unimplemented and read as ‘0’s.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES

Address Name Address Name Address Name Address Name Address Name
(1)
FFFh TOSU FDFh INDF2 FBFh CCPR1H F9Fh IPR1 F7Fh UEP15
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh UEP14
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh UEP13
FFCh STKPTR FDCh PREINC2(1) FBCh —(2) F9Ch —(2) F7Ch UEP12
FFBh PCLATU FDBh PLUSW2(1) FBBh —(2) F9Bh —(2) F7Bh UEP11
FFAh PCLATH FDAh FSR2H FBAh —(2) F9Ah —(2) F7Ah UEP10
FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) F79h UEP9
FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) F78h UEP8
FF7h TBLPTRH FD7h TMR0H FB7h —(2) F97h —(2) F77h UEP7
FF6h TBLPTRL FD6h TMR0L FB6h —(2) F96h TRISE(3) F76h UEP6
(2) (3)
FF5h TABLAT FD5h T0CON FB5h — F95h TRISD F75h UEP5
FF4h PRODH FD4h —(2) FB4h —(2) F94h TRISC F74h UEP4
FF3h PRODL FD3h OSCCON FB3h —(2) F93h TRISB F73h UEP3
FF2h INTCON FD2h HLVDCON FB2h —(2) F92h TRISA F72h UEP2
FF1h INTCON2 FD1h WDTCON FB1h —(2) F91h —(2) F71h UEP1
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) F70h UEP0
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) F6Fh UCFG
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) F6Eh UADDR
(1) (3)
FEDh POSTDEC0 FCDh T1CON FADh TXREG F8Dh LATE F6Dh UCON
FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch USTAT
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE
FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah UEIR
FE9h FSR0L FC9h —(2) FA9h —(2) F89h LATA F69h UIE
FE8h WREG FC8h —(2) FA8h —(2) F88h —(2) F68h UIR
FE7h INDF1(1) FC7h —(2) FA7h EECON2(1) F87h —(2) F67h UFRMH
FE6h POSTINC1(1) FC6h —(2) FA6h EECON1 F86h —(2) F66h UFRML
(1) (2) (2) (2)
FE5h POSTDEC1 FC5h — FA5h — F85h — F65h —(2)
(1) (2)
FE4h PREINC1 FC4h ADRESH FA4h — F84h PORTE F64h —(2)
FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) F63h —(2)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h —(2)
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2)
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2)
Note 1: Not a physical register.

2: Unimplemented registers are read as ‘0’.
3: These registers are implemented only on 40/44-pin devices.

PIC18F2450/4450
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450)
Value on Details
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR on page
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 54
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 54
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55
PCLATU — — — Holding Register for PC<20:16> ---0 0000 49, 54
PCLATH Holding Register for PC<15:8> 0000 0000 49, 54
PCL PC Low Byte (PC<7:0>) 0000 0000 49, 54
TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 76
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 76
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 76
TABLAT Program Memory Table Latch 0000 0000 49, 76
PRODH Product Register High Byte xxxx xxxx 49, 83
PRODL Product Register Low Byte xxxx xxxx 49, 83
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 87
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 49, 88
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 89
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 68
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 69
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 69
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 49, 69
value of FSR0 offset by W
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 49, 68
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 68
WREG Working Register xxxx xxxx 49,
BSR — — — — Bank Select Register ---- 0000 49, 59
STATUS — — — N OV Z DC C ---x xxxx 50, 66
TMR0H Timer0 Register High Byte 0000 0000 50, 113
TMR0L Timer0 Register Low Byte xxxx xxxx 50, 113
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 111
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

PIC18F2450/4450
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Value on Details
POR, BOR on page
OSCCON IDLEN — — — OSTS — SCS1 SCS0 0--- q-00 50, 31

HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 183
WDTCON — — — — — — — SWDTEN --- ---0 50, 202
(2)
RCON IPEN SBOREN — RI TO PD POR BOR 0q-1 11q0 50, 42
TMR1H Timer1 Register High Byte xxxx xxxx 50, 119
TMR1L Timer1 Register Low Byte xxxx xxxx 50, 119
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 115
TMR2 Timer2 Register 0000 0000 50, 122
PR2 Timer2 Period Register 1111 1111 50, 122
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 121
ADRESH A/D Result Register High Byte xxxx xxxx 50, 182
ADRESL A/D Result Register Low Byte xxxx xxxx 50, 182
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 50, 173
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq 50, 174
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 50, 175
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 50, 124
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 50, 124
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 50, 123,
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 51, 156,
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 50, 157
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 50, 157
RCREG EUSART Receive Register 0000 0000 50, 164
TXREG EUSART Transmit Register 0000 0000 50, 162
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 154
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 155
EECON2 Data Memory Control Register 2 (not a physical register) 0000 0000 51, 74
EECON1 — CFGS — FREE WRERR WREN WR — -x-0 x00- 51, 75
IPR2 OSCFIP — USBIP — — HLVDIP — — 1-1- -1-- 51, 95
PIR2 OSCFIF — USBIF — — HLVDIF — — 0-0- -0-- 51, 91
PIE2 OSCFIE — USBIE — — HLVDIE — — 0-0- -0-- 51, 93
IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 51, 94
PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 51, 90
PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 51, 92
TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 ---- -111 51, 110
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 51, 108
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 11-- -111 51, 106
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 51, 103
TRISA — TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 51, 100
LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx 51, 110
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 51, 108
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xx-- -xxx 51, 106
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 51, 103
LATA — LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 51, 100
PORTE — — — — RE3(5) RE2(3) RE1(3) RE0(3) ---- x000 51, 109
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 51, 108

PIC18F2450/4450
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Value on Details
POR, BOR on page
PORTC RC7 RC6 RC5(6) RC4(6) — RC2 RC1 RC0 xxxx -xxx 51, 106
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 51, 100
PORTA — RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 51, 100
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 52, 132
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 52, 136
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 52, 130
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 52, 134
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 52, 147
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 52, 146
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 52, 145
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 52, 144
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 52, 136
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 52, 136

PIC18F2450/4450
5.3.6 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
The STATUS register, shown in Register 5-2, contains
register because these instructions do not affect the Z,
the arithmetic status of the ALU. As with any other SFR,
C, DC, OV or N bits in the STATUS register.
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
If the STATUS register is the destination for an instruction
the instruction set summaries in Table 19-2 and
that affects the Z, DC, C, OV or N bits, the results of the
Table 19-3.
instruction are not written; instead, the STATUS register
is updated according to the instruction performed. Note: The C and DC bits operate as the Borrow
Therefore, the result of an instruction with the STATUS and Digit Borrow bits, respectively, in
register as its destination may be different than intended. subtraction.
As an example, CLRF STATUS will set the Z bit and leave
the remaining Status bits unchanged (‘000u u1uu’).
REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(2)
bit 7 bit 0
Legend:

bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.

PIC18F2450/4450
5.4 Data Addressing Modes Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
Note: The execution of some instructions in the source for the instruction.
core PIC18 instruction set are changed
The Access RAM bit ‘a’ determines how the address is
when the PIC18 extended instruction
interpreted. When ‘a’ is ‘1’, the contents of the BSR
set is enabled. See Section 5.6 “Data
(Section 5.3.2 “Bank Select Register (BSR)”) are
Memory and the Extended Instruction
used with the address to determine the complete 12-bit
Set” for more information.
address of the register. When ‘a’ is ‘0’, the address is
While the program memory can be addressed in only interpreted as being a register in the Access Bank.
one way – through the program counter – information Addressing that uses the Access RAM is sometimes
in the data memory space can be addressed in several also known as Direct Forced Addressing mode.
ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire
fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their
depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely.
not the extended instruction set is enabled.
The destination of the operation’s results is determined
The addressing modes are: by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
• Inherent stored back in the source register, overwriting its origi-
• Literal nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
• Direct
have a destination that is implicit in the instruction; their
• Indirect destination is either the target register being operated
An additional addressing mode, Indexed Literal Offset, on or the W register.
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is 5.4.3 INDIRECT ADDRESSING
discussed in greater detail in Section 5.6.1 “Indexed Indirect Addressing allows the user to access a location
Addressing with Literal Offset”. in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
5.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written
ADDRESSING to. Since the FSRs are themselves located in RAM as
Many PIC18 control instructions do not need any Special Function Registers, they can also be directly
argument at all; they either perform an operation that manipulated under program control. This makes FSRs
globally affects the device or they operate implicitly on very useful in implementing data structures, such as
one register. This addressing mode is known as tables and arrays in data memory.
Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also
and DAW. implemented with Indirect File Operands (INDFs) that
Other instructions work in a similar way but require an permit automatic manipulation of the pointer value with
additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting
known as Literal Addressing mode because they with another value. This allows for efficient code, using
require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM
include ADDLW and MOVLW, which respectively, add or bank in Example 5-5.
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit EXAMPLE 5-5: HOW TO CLEAR RAM
program memory address. (BANK 1) USING
INDIRECT ADDRESSING
5.4.2 DIRECT ADDRESSING
LFSR FSR0, 100h ;
Direct Addressing mode specifies all or part of the NEXT CLRF POSTINC0 ; Clear INDF
source and/or destination address of the operation ; register then
within the opcode itself. The options are specified by ; inc pointer
the arguments accompanying the instruction. BTFSS FSR0H, 1 ; All done with
; Bank1?
In the core PIC18 instruction set, bit-oriented and byte- BRA NEXT ; NO, clear next
oriented instructions use some version of Direct CONTINUE ; YES, continue
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.4 “General

PIC18F2450/4450
5.4.3.1 FSR Registers and the mapped in the SFR space but are not physically
INDF Operand implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
At the core of Indirect Addressing are three sets of
register pair. A read from INDF1, for example, reads
registers: FSR0, FSR1 and FSR2. Each represents a
the data at the address indicated by FSR1H:FSR1L.
pair of 8-bit registers: FSRnH and FSRnL. The four
Instructions that use the INDF registers as operands
upper bits of the FSRnH register are not used, so each
actually use the contents of their corresponding FSR as
FSR pair holds a 12-bit value. This represents a value
a pointer to the instruction’s target. The INDF operand
that can address the entire range of the data memory
is just a convenient way of using the pointer.
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
Indirect Addressing is accomplished with a set of
contents of the BSR and the Access RAM bit have no
Indirect File Operands, INDF0 through INDF2. These
effect on determining the target address.
can be thought of as “virtual” registers; they are
FIGURE 5-7: INDIRECT ADDRESSING
000h
Using an instruction with one of the ADDWF, INDF1, 1 Bank 0
indirect addressing registers as the 100h
operand.... Bank 1
200h
Bank 2
300h
...uses the 12-bit address stored in FSR1H:FSR1L
the FSR pair associated with that
7 0 7 0
register....
x x x x 1 1 1 0 1 1 0 0 1 1 0 0 Bank 3
through
Bank 13
...to determine the data memory

location to be used in that operation.
In this case, the FSR1 pair contains E00h
ECCh. This means the contents of Bank 14
location ECCh will be added to that F00h
of the W register and stored back in Bank 15
ECCh. FFFh
Data Memory

PIC18F2450/4450
5.4.3.2 FSR Registers and POSTINC, 5.4.3.3 Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs
In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For
also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual
these are “virtual” registers that cannot be indirectly registers will not result in successful operations. As a
read or written to. Accessing these registers actually specific case, assume that FSR0H:FSR0L contains
accesses the associated FSR register pair, but also FE7h, the address of INDF1. Attempts to read the
performs a specific action on it stored value. They are: value of INDF1, using INDF0 as an operand, will return
00h. Attempts to write to INDF1, using INDF0 as the
• POSTDEC: accesses the FSR value, then
operand, will result in a NOP.
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to
automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
• PREINC: increments the FSR value by ‘1’, then
incrementing or decrementing. Thus, writing to INDF2
uses it in the operation
or POSTDEC2 will write the same value to the
• PLUSW: adds the signed value of the W register FSR2H:FSR2L.
(range of -127 to 128) to that of the FSR and uses
the new value in the operation. Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
In this context, accessing an INDF register uses the operations. Users should proceed cautiously when
value in the FSR registers without changing them. working on these registers, particularly if their code
Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing.
value offset by that in the W register; neither value is
actually changed in the operation. Accessing the other Similarly, operations by Indirect Addressing are
virtual registers changes the value of the FSR generally permitted on all other SFRs. Users should
registers. exercise the appropriate caution that they do not
inadvertently change settings that might affect the
Operations on the FSRs with POSTDEC, POSTINC operation of the device.
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register from FFh to 00h carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.

PIC18F2450/4450
5.5 Program Memory and the When using the extended instruction set, this
Extended Instruction Set addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
The operation of program memory is unaffected by the
and
use of the extended instruction set.
• The file address argument is less than or equal
Enabling the extended instruction set adds eight to 5Fh.
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW, Under these conditions, the file address of the
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These instruction is not interpreted as the lower byte of an
instructions are executed as described in address (used with the BSR in Direct Addressing), or
Section 5.2.4 “Two-Word Instructions”. as an 8-bit address in the Access Bank. Instead, the
value is interpreted as an offset value to an Address
Pointer specified by FSR2. The offset and the contents
5.6 Data Memory and the Extended of FSR2 are added to obtain the target address of the
Instruction Set operation.
Enabling the PIC18 extended instruction set (XINST
5.6.2 INSTRUCTIONS AFFECTED BY
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. INDEXED LITERAL OFFSET MODE
Specifically, the use of the Access Bank for many of the Any of the core PIC18 instructions that can use Direct
core PIC18 instructions is different. This is due to the Addressing are potentially affected by the Indexed
introduction of a new addressing mode for the data Literal Offset Addressing mode. This includes all byte-
memory space. This mode also alters the behavior of oriented and bit-oriented instructions, or almost one-half
Indirect Addressing using FSR2 and its associated of the standard PIC18 instruction set. Instructions that
operands. only use Inherent or Literal Addressing modes are
What does not change is just as important. The size of unaffected.
the data memory space is unchanged, as well as its Additionally, byte-oriented and bit-oriented instructions
linear addressing. The SFR map remains the same. are not affected if they use the Access Bank (Access
Core PIC18 instructions can still operate in both Direct RAM bit is ‘1’) or include a file address of 60h or above.
and Indirect Addressing mode; inherent and literal Instructions meeting these criteria will continue to
instructions do not change at all. Indirect Addressing execute as before. A comparison of the different
with FSR0 and FSR1 also remains unchanged. possible addressing modes when the extended
instruction set is enabled in shown in Figure 5-8.
5.6.1 INDEXED ADDRESSING WITH
Those who desire to use byte-oriented or bit-oriented
LITERAL OFFSET instructions in the Indexed Literal Offset mode should
Enabling the PIC18 extended instruction set changes note the changes to assembler syntax for this mode.
the behavior of Indirect Addressing using the FSR2 This is described in more detail in Section 19.2.1
register pair and its associated file operands. Under the “Extended Instruction Syntax”.
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.

PIC18F2450/4450
FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0 and f ≥ 60h:
The instruction executes in 060h
Direct Forced mode. ‘f’ is inter- 080h Bank 0
preted as a location in the 100h
Access RAM between 060h 00h
and 0FFh. This is the same as Bank 1 60h
the SFRs or locations F60h to through
Bank 14 Valid range
0FFh (Bank 15) of data for ‘f’
memory.
FFh
F00h Access RAM
Locations below 60h are not
Bank 15
available in this addressing F60h
mode.
SFRs
FFFh
Data Memory
When a = 0 and f ≤ 5Fh: 000h

The instruction executes in Bank 0
Indexed Literal Offset mode. ‘f’ 080h
is interpreted as an offset to the

100h 001001da ffffffff
address value in FSR2. The
two are added together to
Bank 1
obtain the address of the target through
register for the instruction. The Bank 14
address can be anywhere in FSR2H FSR2L
the data memory space.
F00h
Note that in this mode, the Bank 15
F60h
correct syntax is now:
ADDWF [k], d SFRs
where ‘k’ is the same as ‘f’. FFFh
Data Memory
BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
080h
Direct mode (also known as
Direct Long mode). ‘f’ is inter- 100h
preted as a location in one of
the 16 banks of the data 001001da ffffffff
Bank 1
memory space. The bank is through
designated by the Bank Select Bank 14
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
F60h
space.
SFRs
FFFh
Data Memory

PIC18F2450/4450
5.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to
INDEXED LITERAL OFFSET MODE operations using the Indexed Literal Offset mode.
Operations that use the BSR (Access RAM bit is ‘1’) will
The use of Indexed Literal Offset Addressing mode
continue to use Direct Addressing as before. Any
effectively changes how the lower portion of Access
indirect or indexed operation that explicitly uses any of
RAM (00h to 5Fh) is mapped. Rather than containing
the indirect file operands (including FSR2) will continue
just the contents of the bottom half of Bank 0, this mode
to operate as standard Indirect Addressing. Any
maps the contents from Bank 0 and a user-defined
instruction that uses the Access Bank, but includes a
“window” that can be located anywhere in the data
register address of greater than 05Fh, will use Direct
memory space. The value of FSR2 establishes the
Addressing and the normal Access Bank map.
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2 5.6.4 BSR IN INDEXED LITERAL
plus 95 (5Fh). Addresses in the Access RAM above
OFFSET MODE
5Fh are mapped as previously described (see
Section 5.3.3 “Access Bank”). An example of Access Although the Access Bank is remapped when the
Bank remapping in this addressing mode is shown in extended instruction set is enabled, the operation of the
Figure 5-9. BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL

OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a 000h
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 Pointer 100h
(120h) to the pointer plus 120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the Bank 1
Access RAM (000h-05Fh). 200h Bank 1 “Window”
5Fh
Special Function Regis-
60h
ters at F60h through FFFh
are mapped to 60h Bank 2
through FFh as usual. through SFRs
Bank 0 addresses below Bank 14
5Fh are not available in FFh
this mode. They can still Access Bank
be addressed by using the F00h
BSR. Bank 15
F60h
SFRs
FFFh
Data Memory

PIC18F2450/4450
6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes
The Flash program memory is readable, writable and In order to read and write program memory, there are
erasable, during normal operation over the entire VDD two operations that allow the processor to move bytes
range. between the program memory space and the data RAM:
A read from program memory is executed on one byte • Table Read (TBLRD)
at a time. A write to program memory is executed on • Table Write (TBLWT)
blocks of 16 bytes at a time. Program memory is
The program memory space is 16 bits wide, while the
erased in blocks of 64 bytes at a time. A Bulk Erase
data RAM space is 8 bits wide. Table reads and table
operation may not be issued from user code.
writes move data between these two memory spaces
Writing or erasing program memory will cease through an 8-bit register (TABLAT).
instruction fetches until the operation is complete. The
Table read operations retrieve data from program
program memory cannot be accessed during the write
memory and place it into the data RAM space.
or erase, therefore, code cannot execute. An internal
Figure 6-1 shows the operation of a table read with
programming timer terminates program memory writes
program memory and data RAM.
and erases.
Table write operations store data from the data memory
A value written to program memory does not need to be
space into holding registers in program memory. The
a valid instruction. Executing a program memory
procedure to write the contents of the holding registers
location that forms an invalid instruction results in a
into program memory is detailed in Section 6.5 “Writing
NOP.
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1: TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.

PIC18F2450/4450
FIGURE 6-2: TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 16 holding registers, the address of which is determined by
TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
6.2 Control Registers The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register On power-up, the WREN bit is clear. The WRERR bit is
• TABLAT register set in hardware when the WREN bit is set and cleared
• TBLPTR registers when the internal programming timer expires and the
write operation is complete.
6.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is
The EECON1 register (Register 6-1) is the control read as ‘1’. This can indicate that a write
register for memory accesses. The EECON2 register is operation was prematurely terminated by
not a physical register; it is used exclusively in the a Reset or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
The CFGS control bit determines if the access will be cannot be cleared, only set, in software; it is cleared in
to the Configuration/Calibration registers or to program hardware at the completion of the write operation.
memory.

PIC18F2450/4450
REGISTER 6-1: EECON1: MEMORY CONTROL REGISTER 1
U-0 R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0
(1)
— CFGS — FREE WRERR WREN WR —
bit 7 bit 0
Legend:

bit 6 CFGS: Flash Program or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program
0 = Inhibits write cycles to Flash program
bit 1 WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle complete
Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.

PIC18F2450/4450
6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the
into the SFR space. The Table Latch register is used to Flash program memory.
hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR
memory and data RAM. determine which byte is read from program memory
into TABLAT.
6.2.3 TABLE POINTER REGISTER
(TBLPTR) When a TBLWT is executed, the four LSbs of the Table
Pointer register (TBLPTR<3:0>) determine which of the
The Table Pointer (TBLPTR) register addresses a byte 16 program memory holding registers is written to.
within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via
of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR
Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:4>) determine which program memory
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers block of 16 bytes is written to. For more detail, see
join to form a 22-bit wide pointer. The low-order 21 bits Section 6.5 “Writing to Flash Program Memory”.
allow the device to address up to 2 Mbytes of program
memory space. The 22nd bit allows access to the device When an erase of program memory is executed, the
ID, the user ID and the Configuration bits. 16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored.
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table opera- Figure 6-3 describes the relevant boundaries of the
tion. These operations are shown in Table 6-1. These TBLPTR based on Flash program memory operations.
operations on the TBLPTR only affect the low-order
21 bits.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
TABLE ERASE
TBLPTR<21:6>
TABLE WRITE – TBLPTR<21:4>
TABLE READ – TBLPTR<21:0>

PIC18F2450/4450
6.3 Reading the Flash Program TBLPTR points to a byte address in program space.
Memory Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
The TBLRD instruction is used to retrieve data from automatically for the next table read operation.
program memory and places it into data RAM. Table
The internal program memory is typically organized by
reads from program memory are performed one byte at
words. The Least Significant bit of the address selects
a time.
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address) (Odd Byte Address)
TBLPTR = xxxxx1 TBLPTR = xxxxx0
Instruction Register TABLAT

FETCH TBLRD
(IR) Read Register
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF WORD_ODD

PIC18F2450/4450
6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through The sequence of events for erasing a block of internal
ICSP control, can larger blocks of program memory be program memory is:
Bulk Erased. Word Erase in the Flash array is not 1. Load Table Pointer register with address of row
supported. being erased.
When initiating an erase sequence from the 2. Set the EECON1 register for the erase operation:
microcontroller itself, a block of 64 bytes of program • clear the CFGS bit to access program memory;
memory is erased. The Most Significant 16 bits of the • set WREN bit to enable writes;
TBLPTR<21:6> point to the block being erased.
• set FREE bit to enable the erase.
TBLPTR<5:0> are ignored.
3. Disable interrupts.
The EECON1 register commands the erase operation.
4. Write 55h to EECON2.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. 5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the Row Erase
For protection, the write initiate sequence for EECON2
cycle.
must be used.
7. The CPU will stall for duration of the erase
A long write is necessary for erasing the internal Flash. (about 2 ms using internal timer).
Instruction execution is halted while in a long write
8. Re-enable interrupts.
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

PIC18F2450/4450
6.5 Writing to Flash Program Memory The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
The minimum programming block is 8 words or long write cycle. The long write will be terminated by
16 bytes. Word or byte programming is not supported. the internal programming timer.
Table writes are used internally to load the holding The write/erase voltages are generated by an on-chip
registers needed to program the Flash memory. There charge pump, rated to operate over the voltage range
are 16 holding registers used by the table writes for of the device.
programming.
Note: The default value of the holding registers on
Since the Table Latch (TABLAT) is only a single byte, the
device Resets and after write operations is
TBLWT instruction may need to be executed 16 times for
FFh. A write of FFh to a holding register
each programming operation. All of the table write oper-
does not modify that byte. This means that
ations will essentially be short writes because only the
individual bytes of program memory may be
holding registers are written. At the end of updating the
modified, provided that the change does not
16 holding registers, the EECON1 register must be
attempt to change any bit from a ‘0’ to a ‘1’.
written to in order to start the programming operation
with a long write. When modifying individual bytes, it is not
necessary to load all 16 holding registers
before executing a write operation.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8 8 8 8
TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxxF
Holding Register Holding Register Holding Register Holding Register
Program Memory
6.5.1 FLASH PROGRAM MEMORY WRITE 10. Write 0AAh to EECON2.

SEQUENCE 11. Set the WR bit. This will begin the write cycle.
The sequence of events for programming an internal 12. The CPU will stall for duration of the write (about
program memory location should be: 2 ms using internal timer).
13. Re-enable interrupts.
1. Read 64 bytes into RAM.
14. Repeat steps 6 through 14 once more to write
2. Update data values in RAM as necessary.
64 bytes.
3. Load Table Pointer register with address being
15. Verify the memory (table read).
erased.
4. Execute the Row Erase procedure. This procedure will require about 8 ms to update one
5. Load Table Pointer register with address of first row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
byte being written.
6. Write 16 bytes into the holding registers with Note: Before setting the WR bit, the Table
auto-increment. Pointer address needs to be within the
7. Set the EECON1 register for the write operation: intended address range of the 16 bytes in
• clear the CFGS bit to access program memory; the holding register.
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.

PIC18F2450/4450
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, FREE ; enable Row Erase operation
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
BSF EECON1, WR ; start erase (CPU stall)
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW D’4’
MOVWF COUNTER1
WRITE_BUFFER_BACK
MOVLW D’16’ ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS

PIC18F2450/4450
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
BSF EECON1, WR ; start program (CPU stall)
DECFSZ COUNTER1
BRA WRITE_BUFFER_BACK
BCF EECON1, WREN ; disable write to memory
6.5.2 WRITE VERIFY 6.5.4 PROTECTION AGAINST SPURIOUS

Depending on the application, good programming WRITES
practice may dictate that the value written to the To protect against spurious writes to Flash program
memory should be verified against the original value. memory, the write initiate sequence must also be
This should be used in applications where excessive followed. See Section 18.0 “Special Features of the
writes can stress bits near the specification limit. CPU” for more detail.
6.5.3 UNEXPECTED TERMINATION OF 6.6 Flash Program Operation During

WRITE OPERATION
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory See Section 18.5 “Program Verification and Code
location just programmed should be verified and Protection” for details on code protection of Flash
reprogrammed if needed. If the write operation is program memory.
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on page
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49
TABLAT Program Memory Table Latch 49
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
EECON2 Control Register 2 (not a physical register) 51
EECON1 — CFGS — FREE WRERR WREN WR — 51
IPR2 OSCFIP — USBIP — — HLVDIP — — 51
PIR2 OSCFIF — USBIF — — HLVDIF — — 51
PIE2 OSCFIE — USBIE — — HLVDIE — — 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
7.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 7-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
7.1 Introduction MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register. EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
MOVF ARG1, W
be completed in a single instruction cycle. This has the
MULWF ARG2 ; ARG1 * ARG2 ->
advantages of higher computational throughput and
; PRODH:PRODL
reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit
allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH
tions previously reserved for digital signal processors. ; - ARG1
A comparison of various hardware and software MOVF ARG2, W
multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit
and execution time, is shown in Table 7-1. SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
7.2 Operation
Example 7-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 7-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs
8 x 8 unsigned
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Hardware multiply 6 6 600 ns 2.4 μs 6 μs
16 x 16 unsigned
Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs
16 x 16 signed
Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs

PIC18F2450/4450
Example 7-3 shows the sequence to do a 16 x 16 EQUATION 7-2: 16 x 16 SIGNED
unsigned multiplication. Equation 7-1 shows the MULTIPLICATION
algorithm that is used. The 32-bit result is stored in four ALGORITHM
registers (RES3:RES0). RES3:RES0= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
EQUATION 7-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) +
MULTIPLICATION (ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
ALGORITHM
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216)
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) + EXAMPLE 7-4: 16 x 16 SIGNED
(ARG1L • ARG2L) MULTIPLY ROUTINE
MOVF ARG1L, W
EXAMPLE 7-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L ->
MULTIPLY ROUTINE ; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVF ARG1L, W
MOVFF PRODL, RES0 ;
MULWF ARG2L ; ARG1L * ARG2L->
;
; PRODH:PRODL
MOVF ARG1H, W
MOVFF PRODH, RES1 ;
MULWF ARG2H ; ARG1H * ARG2H ->
MOVFF PRODL, RES0 ;
; PRODH:PRODL
;
MOVFF PRODH, RES3 ;
MOVF ARG1H, W
MOVFF PRODL, RES2 ;
MULWF ARG2H ; ARG1H * ARG2H->
;
; PRODH:PRODL
MOVF ARG1L,W
MOVFF PRODH, RES3 ;
MULWF ARG2H ; ARG1L * ARG2H ->
MOVFF PRODL, RES2 ;
; PRODH:PRODL
;
MOVF PRODL, W ;
MOVF ARG1L, W
ADDWF RES1, F ; Add cross
MULWF ARG2H ; ARG1L * ARG2H->
MOVF PRODH, W ; products
; PRODH:PRODL
ADDWFC RES2, F ;
MOVF PRODL, W ;
CLRF WREG ;
ADDWFC RES3, F ;
;
ADDWFC RES2, F ;
MOVF ARG1H, W ;
CLRF WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
ADDWFC RES3, F ;
; PRODH:PRODL
;
MOVF PRODL, W ;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
ADDWFC RES2, F ;
MOVF PRODL, W ;
CLRF WREG ;
ADDWFC RES3, F ;
;
ADDWFC RES2, F ;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
CLRF WREG ;
BRA SIGN_ARG1 ; no, check ARG1
ADDWFC RES3, F ;
MOVF ARG1L, W ;
SUBWF RES2 ;
Example 7-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ;
signed multiply. Equation 7-2 shows the algorithm SUBWFB RES3
used. The 32-bit result is stored in four registers ;
(RES3:RES0). To account for the sign bits of the SIGN_ARG1
arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
and the appropriate subtractions are done.
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:

PIC18F2450/4450
8.0 INTERRUPTS When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
The PIC18F2450/4450 devices have multiple interrupt IPEN bit is cleared, this is the GIE bit. If interrupt priority
sources and an interrupt priority feature that allows levels are used, this will be either the GIEH or GIEL bit.
each interrupt source to be assigned a high priority High priority interrupt sources can interrupt a low
level or a low priority level. The high priority interrupt priority interrupt. Low priority interrupts are not
vector is at 000008h and the low priority interrupt vector processed while high priority interrupts are in progress.
is at 000018h. High priority interrupt events will
The return address is pushed onto the stack and the PC
interrupt any low priority interrupts that may be in
is loaded with the interrupt vector address (000008h or
progress.
000018h). Once in the Interrupt Service Routine, the
There are ten registers which are used to control source(s) of the interrupt can be determined by polling
interrupt operation. These registers are: the interrupt flag bits. The interrupt flag bits must be
• RCON cleared in software before re-enabling interrupts to avoid
• INTCON recursive interrupts.
• INTCON2 The “return from interrupt” instruction, RETFIE, exits
• INTCON3 the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
• PIR1, PIR2
• PIE1, PIE2 For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
• IPR1, IPR2
will be three to four instruction cycles. The exact
It is recommended that the Microchip header files latency is the same for one or two-cycle instructions.
supplied with MPLAB® IDE be used for the symbolic bit Individual interrupt flag bits are set regardless of the
names in these registers. This allows the assembler/ status of their corresponding enable bit or the GIE bit.
compiler to automatically take care of the placement of
these bits within the specified register. Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
Each interrupt source has three bits to control its any interrupt is enabled. Doing so may
operation. The functions of these bits are: cause erratic microcontroller behavior.
• Flag bit to indicate that an interrupt event
occurred 8.1 USB Interrupts
• Enable bit that allows program execution to
Unlike other peripherals, the USB module is capable of
branch to the interrupt vector address when the
generating a wide range of interrupts for many types of
flag bit is set
events. These include several types of normal commu-
• Priority bit to select high priority or low priority nication and status events and several module level
The interrupt priority feature is enabled by setting the error events.
IPEN bit (RCON<7>). When interrupt priority is To handle these events, the USB module is equipped
enabled, there are two bits which enable interrupts with its own interrupt logic. The logic functions in a
globally. Setting the GIEH bit (INTCON<7>) enables all manner similar to the microcontroller level interrupt
interrupts that have the priority bit set (high priority). funnel, with each interrupt source having separate flag
Setting the GIEL bit (INTCON<6>) enables all and enable bits. All events are funneled to a single
interrupts that have the priority bit cleared (low priority). device level interrupt, USBIF (PIR2<5>). Unlike the
When the interrupt flag, enable bit and appropriate device level interrupt logic, the individual USB interrupt
global interrupt enable bit are set, the interrupt will events cannot be individually assigned their own prior-
vector immediately to address 000008h or 000018h, ity. This is determined at the device level interrupt
depending on the priority bit setting. Individual inter- funnel for all USB events by the USBIP bit.
rupts can be disabled through their corresponding
enable bits. For additional details on USB interrupt logic, refer to
Section 14.5 “USB Interrupts”.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.

PIC18F2450/4450
FIGURE 8-1: INTERRUPT LOGIC
Wake-up if in Sleep Mode

TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
INT1IF Vector to Location
INT1IE
INT1IP 0008h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit INT2IF
Peripheral Interrupt Priority bit INT2IE
INT2IP
TMR1IF GIE/GIEH
TMR1IE
TMR1IP IPEN
From USB IPEN

USBIF
Interrupt Logic USBIE PEIE/GIEL
USBIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
TMR0IF Vector to Location
TMR0IE 0018h
TMR1IF TMR0IP
TMR1IE
TMR1IP RBIF
RBIE
From USB USBIF
Interrupt Logic RBIP PEIE/GIEL
USBIE
GIE/GIEH
USBIP
INT1IF
Additional Peripheral Interrupts INT1IE
INT1IP
INT2IF
INT2IE
INT2IP

PIC18F2450/4450
8.2 INTCON Registers Note: Interrupt flag bits are set when an interrupt
The INTCON registers are readable and writable condition occurs regardless of the state of
registers which contain various enable, priority and flag its corresponding enable bit or the global
bits. interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)
bit 7 bit 0
Legend:
bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.

PIC18F2450/4450
REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP
bit 7 bit 0
Legend:
bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F2450/4450
REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
Legend:
bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F2450/4450
8.3 PIR Registers Note 1: Interrupt flag bits are set when an interrupt
The PIR registers contain the individual flag bits for the condition occurs regardless of the state of
peripheral interrupts. Due to the number of peripheral its corresponding enable bit or the Global
interrupt sources, there are two Peripheral Interrupt Interrupt Enable bit, GIE (INTCON<7>).
Request (Flag) registers (PIR1 and PIR2). 2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
— ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:

bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

PIC18F2450/4450
REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
OSCFIF — USBIF — — HLVDIF — —
bit 7 bit 0
Legend:
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0 = System clock operating
bit 5 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A high/low-voltage condition occurred
0 = No high/low-voltage event has occurred

PIC18F2450/4450
8.4 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1 and PIE2). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 8-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:

bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

PIC18F2450/4450
REGISTER 8-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
OSCFIE — USBIE — — HLVDIE — —
bit 7 bit 0
Legend:
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 = Disabled
bit 5 USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled

PIC18F2450/4450
8.5 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 8-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:

bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority

PIC18F2450/4450
REGISTER 8-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 U-0 R/W-1 U-0 U-0 R/W-1 U-0 U-0
OSCFIP — USBIP — — HLVDIP — —
bit 7 bit 0
Legend:
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority
0 = Low priority
bit 5 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority

PIC18F2450/4450
8.6 RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 8-10: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
For details of bit operation, see Register 4-1.
bit 4 RI: RESET Instruction Flag bit
bit 3 TO: Watchdog Time-out Flag bit
bit 2 PD: Power-Down Detection Flag bit
bit 1 POR: Power-on Reset Status bit(2)
bit 0 BOR: Brown-out Reset Status bit
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register 4-1 for additional information.
2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.

PIC18F2450/4450
8.7 INTn Pin Interrupts 8.8 TMR0 Interrupt
External interrupts on the RB0/AN12/INT0, RB1/AN10/ In 8-bit mode (which is the default), an overflow in the
INT1and RB2/AN8/INT2/VMO pins are edge-triggered. TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
If the corresponding INTEDGx bit in the INTCON2 16-bit mode, an overflow in the TMR0H:TMR0L
register is set (= 1), the interrupt is triggered by a rising register pair (FFFFh → 0000h) will set TMR0IF. The
edge; if the bit is clear, the trigger is on the falling edge. interrupt can be enabled/disabled by setting/clearing
When a valid edge appears on the RBx/INTx pin, the enable bit, TMR0IE (INTCON<5>). Interrupt priority for
corresponding flag bit, INTxIF, is set. This interrupt can Timer0 is determined by the value contained in the
be disabled by clearing the corresponding enable bit, interrupt priority bit, TMR0IP (INTCON2<2>). See
INTxIE. Flag bit, INTxIF, must be cleared in software in Section 12.0 “Timer2 Module” for further details on
the Interrupt Service Routine before re-enabling the the Timer0 module.
interrupt.
All external interrupts (INT0, INT1 and INT2) can wake- 8.9 PORTB Interrupt-on-Change
up the processor from the power-managed modes if bit,
An input change on PORTB<7:4> sets flag bit, RBIF
INTxIE, was set prior to going into the power-managed
(INTCON<0>). The interrupt can be enabled/disabled
modes. If the Global Interrupt Enable bit, GIE, is set, the
by setting/clearing enable bit, RBIE (INTCON<3>).
processor will branch to the interrupt vector following
Interrupt priority for PORTB interrupt-on-change is
wake-up.
determined by the value contained in the interrupt
Interrupt priority for INT1 and INT2 is determined by the priority bit, RBIP (INTCON2<0>).
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is 8.10 Context Saving During Interrupts
no priority bit associated with INT0. It is always a high
priority interrupt source. During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 8-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F2450/4450
NOTES:

PIC18F2450/4450
9.0 I/O PORTS Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
Depending on the device selected and features
The Data Latch register (LATA) is also memory
enabled, there are up to five ports available. Some pins
mapped. Read-modify-write operations on the LATA
of the I/O ports are multiplexed with an alternate
register read and write the latched output value for
function from the peripheral features on the device. In
PORTA.
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin. The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
Each port has three registers for its operation. These
is multiplexed with the main oscillator pin; it is enabled
registers are:
as an oscillator or I/O pin by the selection of the main
• TRIS register (data direction register) oscillator in Configuration Register 1H (see
• PORT register (reads the levels on the pins of the Section 18.1 “Configuration Bits” for details). When
device) not used as a port pin, RA6 and its associated TRIS
• LAT register (output latch) and LAT bits are read as ‘0’.
The Data Latch register (LATA) is useful for read- RA4 is also multiplexed with the USB module; it serves
modify-write operations on the value driven by the I/O as a receiver input from an external USB transceiver.
pins. For details on configuration of the USB module, see
Section 14.2 “USB Status and Control”.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1. Several PORTA pins are multiplexed with analog inputs.
The operation of pins RA5 and RA3:RA0 as A/D
FIGURE 9-1: GENERIC I/O PORT converter inputs is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
OPERATION
Register 1).
Note: On a Power-on Reset, RA5 and RA3:RA0
RD LAT
are configured as analog inputs and read
Data as ‘0’. RA4 is configured as a digital input.
Bus D Q
All other PORTA pins have TTL input levels and full
WR LAT I/O pin(1)
or PORT CMOS output drivers.
CK
The TRISA register controls the direction of the RA
Data Latch
pins, even when they are being used as analog inputs.
D Q The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR TRIS
CK
TRIS Latch Input EXAMPLE 9-1: INITIALIZING PORTA
Buffer CLRF PORTA ; Initialize PORTA by
; clearing output
RD TRIS
; data latches
CLRF LATA ; Alternate method
Q D ; to clear output
; data latches
MOVLW 0Fh ; Configure A/D
ENEN
MOVWF ADCON1 ; for digital inputs
RD PORT MOVLW 0CFh ; Value used to
; initialize data
Note 1: I/O pins have diode protection to VDD and VSS. ; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
9.1 PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).

PIC18F2450/4450
TABLE 9-1: PORTA I/O SUMMARY
TRIS
Pin Function I/O I/O Type Description
Setting
RA0/AN0 RA0 0 OUT DIG LATA<0> data output; not affected by analog input.
1 IN TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 IN ANA A/D input channel 0. Default configuration on POR; does not affect
digital output.
RA1/AN1 RA1 0 OUT DIG LATA<1> data output; not affected by analog input.
1 IN TTL PORTA<1> data input; reads ‘0’ on POR.
AN1 1 IN ANA A/D input channel 1. Default configuration on POR; does not affect
digital output.
RA2/AN2/ RA2 0 OUT DIG LATA<2> data output; not affected by analog input.
VREF- 1 IN TTL PORTA<2> data input. Disabled when analog functions enabled.
AN2 1 IN ANA A/D input channel 2. Default configuration on POR; not affected by
analog output.
VREF- 1 IN ANA A/D voltage reference low input.
VREF+ 1 IN TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 IN ANA A/D input channel 3. Default configuration on POR.
VREF+ 1 IN ANA A/D voltage reference high input.
RA4/T0CKI/ RA4 0 OUT DIG LATA<4> data output; not affected by analog input.
RCV 1 IN ST PORTA<4> data input; disabled when analog input enabled.
T0CKI 1 IN ST Timer0 clock input.
RCV x IN TTL External USB transceiver RCV input.
HLVDIN 1 IN TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 IN ANA A/D input channel 4. Default configuration on POR.
HLVDIN 1 IN ANA High/Low-Voltage Detect external trip point input.
OSC2/CLKO/ OSC2 x OUT ANA Main oscillator feedback output connection (all XT and HS modes).
RA6 CLKO x OUT DIG System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6 0 OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
1 IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Reset
on page
PORTA — RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 51
LATA — LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 51
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 51
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.

PIC18F2450/4450
9.2 PORTB, TRISB and LATB A mismatch condition will continue to set flag bit, RBIF.
Registers Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
PORTB is an 8-bit wide, bidirectional port. The
The interrupt-on-change feature is recommended for
corresponding data direction register is TRISB. Setting
wake-up on key depression operation and operations
a TRISB bit (= 1) will make the corresponding PORTB
where PORTB is only used for the interrupt-on-change
pin an input (i.e., put the corresponding output driver in
feature. Polling of PORTB is not recommended while
a high-impedance mode). Clearing a TRISB bit (= 0)
using the interrupt-on-change feature.
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin). Pins, RB2 and RB3, are multiplexed with the USB
peripheral and serve as the differential signal outputs
The Data Latch register (LATB) is also memory
for an external USB transceiver (TRIS configuration).
mapped. Read-modify-write operations on the LATB
Refer to Section 14.2.2.2 “External Transceiver” for
additional information on configuring the USB module
PORTB.
for operation with an external transceiver.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is EXAMPLE 9-2: INITIALIZING PORTB
performed by clearing bit, RBPU (INTCON2<7>). The CLRF PORTB ; Initialize PORTB by
weak pull-up is automatically turned off when the port ; clearing output
pin is configured as an output. The pull-ups are ; data latches
disabled on a Power-on Reset. CLRF LATB ; Alternate method
; to clear output
Note: On a Power-on Reset, RB4:RB0 are ; data latches
configured as analog inputs by default and MOVLW 0Eh ; Set RB<4:0> as
read as ‘0’; RB7:RB5 are configured as MOVWF ADCON1 ; digital I/O pins
digital inputs. ; (required if config bit
By programming the Configuration bit, ; PBADEN is set)
MOVLW 0CFh ; Value used to
PBADEN (CONFIG3H<1>), RB4:RB0 will
; initialize data
alternatively be configured as digital inputs ; direction
on POR. MOVWF TRISB ; Set RB<3:0> as inputs
Four of the PORTB pins (RB7:RB4) have an interrupt- ; RB<5:4> as outputs
; RB<7:6> as inputs
on-change feature. Only pins configured as inputs can
cause this interrupt to occur. Any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison. The pins are compared with
the old value latched on the last read of PORTB. The
“mismatch” outputs of RB7:RB4 are ORed together to
generate the RB Port Change Interrupt with Flag bit,
RBIF (INTCON<0>).
The interrupt-on-change can be used to wake the
device from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit, RBIF.

PIC18F2450/4450
TABLE 9-3: PORTB I/O SUMMARY
TRIS
Setting
RB0/AN12/ RB0 0 OUT DIG LATB<0> data output; not affected by analog input.
INT0
1 IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN12 1 IN ANA A/D input channel 12.(1)
INT0 1 IN ST External interrupt 0 input.
INT1
INT2/VMO
VMO 0 OUT DIG External USB transceiver VMO data output.
RB3/AN9/VPO RB3 0 OUT DIG LATB<3> data output; not affected by analog input.
VPO 0 OUT DIG External USB transceiver VPO data output.
KBI0
KBI0 1 IN TTL Interrupt-on-pin change.
RB5/KBI1/ RB5 0 OUT DIG LATB<5> data output.
PGM
PGM x IN ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
PGC
PGC x IN ST Serial execution (ICSP) clock input for ICSP and ICD operation.(2)
PGD 1 IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
PGD x OUT DIG Serial execution data output for ICSP and ICD operation.(2)
x IN ST Serial execution data input for ICSP and ICD operation.(2)
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: All other pin functions are disabled when ICSP™ or ICD operation is enabled.

PIC18F2450/4450
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
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PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 51
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 51
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 51
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 49
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 49
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

PIC18F2450/4450
9.3 PORTC, TRISC and LATC When enabling peripheral functions on PORTC pins
Registers other than RC4 and RC5, care should be taken in
defining the TRIS bits. Some peripherals override the
PORTC is a 7-bit wide, bidirectional port. The TRIS bit to make a pin an output, while other
corresponding data direction register is TRISC. Setting peripherals override the TRIS bit to make a pin an
a TRISC bit (= 1) will make the corresponding PORTC input. The user should refer to the corresponding
pin an input (i.e., put the corresponding output driver in peripheral section for the correct TRIS bit settings.
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e., Note: On a Power-on Reset, these pins, except
put the contents of the output latch on the selected pin). RC4 and RC5, are configured as digital
inputs. To use pins RC4 and RC5 as
In PIC18F2450/4450 devices, the RC3 pin is not digital inputs, the USB module must be
implemented. disabled (UCON<3> = 0) and the on-chip
The Data Latch register (LATC) is also memory USB transceiver must be disabled
mapped. Read-modify-write operations on the LATC (UCFG<3> = 1).
PORTC. The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
PORTC is primarily multiplexed with serial the current contents, even though a peripheral device
communication modules, including the EUSART and may be overriding one or more of the pins.
the USB module (Table 9-5). Except for RC4 and RC5,
PORTC uses Schmitt Trigger input buffers.
EXAMPLE 9-3: INITIALIZING PORTC
Pins RC4 and RC5 are multiplexed with the USB CLRF PORTC ; Initialize PORTC by
module. Depending on the configuration of the module, ; clearing output
they can serve as the differential data lines for the on- ; data latches
chip USB transceiver, or the data inputs from an CLRF LATC ; Alternate method
external USB transceiver. Both RC4 and RC5 have ; to clear output
TTL input buffers instead of the Schmitt Trigger buffers ; data latches
on the other pins. MOVLW 07h ; Value used to
; initialize data
Unlike other PORTC pins, RC4 and RC5 do not have ; direction
TRISC bits associated with them. As digital ports, they MOVWF TRISC ; RC<5:0> as outputs
can only function as digital inputs. When configured for ; RC<7:6> as inputs
USB operation, the data direction is determined by the
configuration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the
on-chip transceiver is used, the data direction is
determined by the operation being performed by the
module at that time.
When the external transceiver is enabled, RC2 also
serves as the output enable control to the transceiver.
Additional information on configuring USB options is
provided in Section 14.2.2.2 “External Transceiver”.

PIC18F2450/4450
TABLE 9-5: PORTC I/O SUMMARY
TRIS
Setting
RC0/T1OSO/ RC0 0 OUT DIG LATC<0> data output.

T1CKI 1 IN ST PORTC<0> data input.
T1OSO x OUT ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T1CKI 1 IN ST Timer1 counter input.
RC1/T1OSI/ RC1 0 OUT DIG LATC<1> data output.
UOE 1 IN ST PORTC<1> data input.
T1OSI x IN ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
UOE 0 OUT DIG External USB transceiver OE output.
RC2/CCP1 RC2 0 OUT DIG LATC<2> data output.
1 IN ST PORTC<2> data input.
CCP1 0 OUT DIG CCP1 Compare and PWM output; takes priority over port data.
1 IN ST CCP1 Capture input.
RC4/D-/VM RC4 —(1) IN TTL PORTC<4> data input; disabled when USB module or on-chip
transceiver is enabled.
D- —(1) OUT XCVR USB bus differential minus line output (internal transceiver).
(1)
— IN XCVR USB bus differential minus line input (internal transceiver).
VM —(1) IN TTL External USB transceiver VM input.
RC5/D+/VP RC5 —(1) IN TTL PORTC<5> data input; disabled when USB module or on-chip
transceiver is enabled.
D+ —(1) OUT XCVR USB bus differential plus line output (internal transceiver).
—1) IN XCVR USB bus differential plus line input (internal transceiver).
VP —1) IN TTL External USB transceiver VP input.
RC6/TX/CK RC6 0 OUT DIG LATC<6> data output.
TX 0 OUT DIG Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.
CK 0 OUT DIG Synchronous serial clock output (EUSART module); takes priority
over port data.
1 IN ST Synchronous serial clock input (EUSART module).
RC7/RX/DT RC7 0 OUT DIG LATC<7> data output.
RX 1 IN ST Asynchronous serial receive data input (EUSART module).
DT 1 OUT DIG Synchronous serial data output (EUSART module).
1 IN ST Synchronous serial data input (EUSART module). User must
configure as an input.
TTL = TTL Buffer Input, XCVR = USB Transceiver, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.

PIC18F2450/4450
TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
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PORTC RC7 RC6 RC5(1) RC4(1) — RC2 RC1 RC0 51
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 51
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

PIC18F2450/4450
9.4 PORTD, TRISD and LATD EXAMPLE 9-4: INITIALIZING PORTD
Registers CLRF PORTD ; Initialize PORTD by
; clearing output
Note: PORTD is only available on 40/44-pin ; data latches
devices. CLRF LATD ; Alternate method
; to clear output
PORTD is an 8-bit wide, bidirectional port. The ; data latches
corresponding data direction register is TRISD. Setting MOVLW 0CFh ; Value used to
a TRISD bit (= 1) will make the corresponding PORTD ; initialize data
pin an input (i.e., put the corresponding output driver in ; direction
a high-impedance mode). Clearing a TRISD bit (= 0) MOVWF TRISD ; Set RD<3:0> as inputs
will make the corresponding PORTD pin an output (i.e., ; RD<5:4> as outputs
put the contents of the output latch on the selected pin). ; RD<7:6> as inputs
The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.

PIC18F2450/4450
TABLE 9-7: PORTD I/O SUMMARY
TRIS
Setting
RD0 RD0 0 OUT DIG LATD<0> data output.
1 IN ST PORTD<0> data input.
RD5 RD5 0 OUT DIG LATD<5> data output
1 IN ST PORTD<5> data input
Legend: OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input
TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Reset
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PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 51
LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 51
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 51
Note 1: These registers and/or bits are unimplemented on 28-pin devices.

PIC18F2450/4450
9.5 PORTE, TRISE and LATE functions as a digital input only pin; as such, it does not
Registers have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
Depending on the particular PIC18F2450/4450 device In either configuration, RE3 also functions as the
selected, PORTE is implemented in two different ways. programming voltage input during programming.
For 40/44-pin devices, PORTE is a 4-bit wide port. Note: On a Power-on Reset, RE3 is enabled as
Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are a digital input only if Master Clear
individually configurable as inputs or outputs. These functionality is disabled.
pins have Schmitt Trigger input buffers. When selected
as an analog input, these pins will read as ‘0’s.
EXAMPLE 9-5: INITIALIZING PORTE
The corresponding data direction register is TRISE. CLRF PORTE ; Initialize PORTE by
Setting a TRISE bit (= 1) will make the corresponding ; clearing output
PORTE pin an input (i.e., put the corresponding output ; data latches
driver in a high-impedance mode). Clearing a TRISE bit CLRF LATE ; Alternate method
(= 0) will make the corresponding PORTE pin an output ; to clear output
(i.e., put the contents of the output latch on the selected ; data latches
pin). MOVLW 0Ah ; Configure A/D
MOVWF ADCON1 ; for digital inputs
TRISE controls the direction of the RE pins, even when MOVLW 03h ; Value used to
they are being used as analog inputs. The user must ; initialize data
make sure to keep the pins configured as inputs when ; direction
using them as analog inputs. MOVWF TRISC ; Set RE<0> as inputs
; RE<1> as inputs
Note: On a Power-on Reset, RE2:RE0 are ; RE<2> as outputs
configured as analog inputs.
The Data Latch register (LATE) is also memory 9.5.1 PORTE IN 28-PIN DEVICES
mapped. Read-modify-write operations on the LATE For 28-pin devices, PORTE is only available when
register read and write the latched output value for Master Clear functionality is disabled (MCLRE = 0). In
PORTE. these cases, PORTE is a single bit, input only port
The fourth pin of PORTE (MCLR/VPP/RE3) is an input comprised of RE3 only. The pin operates as previously
only pin. Its operation is controlled by the MCLRE Config- described.
uration bit. When selected as a port pin (MCLRE = 0), it
REGISTER 9-1: PORTE REGISTER

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/W-0 R/W-0
— — — — RE3(1,2) RE2(3) RE1(3) RE0(3)
bit 7 bit 0
Legend:

bit 3-0 RE3:RE0: PORTE Data Input bits(1,2,3)
Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: Unimplemented in 28-pin devices; read as ‘0’.

PIC18F2450/4450
TABLE 9-9: PORTE I/O SUMMARY
TRIS
Setting
RE0/AN5 RE0 0 OUT DIG LATE<0> data output; not affected by analog input.
1 IN ST PORTE<0> data input; disabled when analog input enabled.
AN5 1 IN ANA A/D input channel 5; default configuration on POR.
MCLR/VPP/ RE3 — (1) IN ST PORTE<3> data input; enabled when MCLRE Configuration bit
RE3 is clear.
MCLR —(1) IN ST External Master Clear input; enabled when MCLRE Configuration bit
is set.
VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input.
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

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PORTE — — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 51
LATE(3) — — — — — LATE2 LATE1 LATE0 51
TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 51
Legend: — = unimplemented, read as ‘0’
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.

PIC18F2450/4450
10.0 TIMER0 MODULE The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
The Timer0 module incorporates the following features: prescale selection. It is both readable and writable.
• Software selectable operation as a timer or A simplified block diagram of the Timer0 module in
counter in both 8-Bit or 16-Bit modes 8-Bit mode is shown in Figure 10-1. Figure 10-2 shows
• Readable and writable registers a simplified block diagram of the Timer0 module in 16-
• Dedicated 8-bit, software programmable Bit mode.
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value

PIC18F2450/4450
10.1 Timer0 Operation internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
Timer0 can operate as either a timer or a counter; the timer/counter.
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments 10.2 Timer0 Reads and Writes in
on every clock by default unless a different prescaler 16-Bit Mode
value is selected (see Section 10.3 “Prescaler”). If
the TMR0 register is written to, the increment is TMR0H is not the actual high byte of Timer0 in 16-Bit
inhibited for the following two instruction cycles. The mode; it is actually a buffered version of the real high
user can work around this by writing an adjusted value byte of Timer0, which is not directly readable nor
to the TMR0 register. writable (refer to Figure 10-2). TMR0H is updated with
The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of
(= 1). In Counter mode, Timer0 increments either on TMR0L. This provides the ability to read all 16 bits of
every rising or falling edge of pin RA4/T0CKI. The Timer0 without having to verify that the read of the high
incrementing edge is determined by the Timer0 Source and low byte were valid, due to a rollover between
Edge Select bit, T0SE (T0CON<4>); clearing this bit successive reads of the high and low byte.
selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also
clock input are discussed below. take place through the TMR0H Buffer register. The high
An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a
however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0
that the external clock can be synchronized with the to be updated at once.
FIGURE 10-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
Programmable Clocks on Overflow
T0CKI pin 0
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS2:T0PS0
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.
FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0
High Byte TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS2:T0PS0
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.

PIC18F2450/4450
10.3 Prescaler 10.3.1 SWITCHING PRESCALER
ASSIGNMENT
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software
its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program
(T0CON<3:0>) which determine the prescaler execution.
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the 10.4 Timer0 Interrupt
Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0
from 1:2 through 1:256, in power-of-2 increments, are register overflows from FFh to 00h in 8-Bit mode, or
selectable. from FFFFh to 0000h in 16-Bit mode. This overflow
When assigned to the Timer0 module, all instructions sets the TMR0IF flag bit. The interrupt can be masked
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF by clearing the TMR0IE bit (INTCON<5>). Before re-
TMR0, BSF TMR0,etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0
count but will not change the prescaler interrupt cannot awaken the processor from Sleep.
assignment.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0

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TMR0L Timer0 Register Low Byte 50
TMR0H Timer0 Register High Byte 50
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
11.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure 11-2.
features:
The module incorporates its own low-power oscillator
• Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1
counter oscillator can also be used as a low-power clock source
• Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation.
and TMR1L) Timer1 can also be used to provide Real-Time Clock
• Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal
device clock or Timer1 oscillator internal options addition of external components and code overhead.
• Interrupt on overflow Timer1 is controlled through the T1CON Control
• Module Reset on CCP Special Event Trigger register (Register 11-1). It also contains the Timer1
• Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC0/T1OSO/T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

PIC18F2450/4450
11.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled.
• Timer When Timer1 is enabled, the RC1/T1OSI/UOE and
• Synchronous Counter RC0/T1OSO/T1CKI pins become inputs. This means
• Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 11-1: TIMER1 BLOCK DIAGRAM

Timer1 Oscillator
On/Off 1
T1OSO/T1CKI 1
Prescaler Synchronize
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN(1) TMR1CS Timer1
On/Off
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator
1
T1OSO/T1CKI 1
Prescaler Synchronize
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
(1) TMR1CS Timer1
T1OSCEN
T1CKPS1:T1CKPS0 On/Off
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

PIC18F2450/4450
11.2 Timer1 16-Bit Read/Write Mode TABLE 11-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR(2,3,4)
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit Osc Type Freq C1 C2
(T1CON<7>) is set, the address for TMR1H is mapped LP 32 kHz 27 pF(1) 27 pF(1)
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of Note 1: Microchip suggests these values as a
Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator
the user with the ability to accurately read all 16 bits of circuit.
Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability
the high byte, followed by a read of the low byte, has of the oscillator but also increases the
become invalid due to a rollover between reads. start-up time.
A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own
through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult
byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for
write occurs to TMR1L. This allows a user to write all appropriate values of external
16 bits to both the high and low bytes of Timer1 at once. components.
The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance
writable in this mode. All reads and writes must take only.
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler. 11.3.1 USING TIMER1 AS A CLOCK
The prescaler is only cleared on writes to TMR1L. SOURCE
The Timer1 oscillator is also available as a clock source
11.3 Timer1 Oscillator in power-managed modes. By setting the clock select
An on-chip crystal oscillator circuit is incorporated bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode. Both the CPU and
output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP
low-power circuit rated for 32 kHz crystals. It will instruction is executed, the device enters SEC_IDLE
continue to run during all power-managed modes. The mode. Additional details are available in Section 3.0
circuit for a typical LP oscillator is shown in Figure 11-3. “Power-Managed Modes”.
Table 11-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock
oscillator. source, the Timer1 system clock status flag, T1RUN
The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the
proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
FIGURE 11-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
COMPONENTS FOR THE
the T1RUN bit will indicate whether the clock is being
TIMER1 LP OSCILLATOR
provided by the Timer1 oscillator or another source.
C1
PIC18FXXXX 11.3.2 LOW-POWER TIMER1 OPTION
33 pF
T1OSI
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
XTAL
When the LPT1OSC Configuration bit is set, the Timer1
32.768 kHz
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
T1OSO
level. Power consumption for a particular mode is
C2
33 pF relatively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
Note: See the Notes with Table 11-1 for additional power mode.
information about capacitor selection.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.

PIC18F2450/4450
11.3.3 TIMER1 OSCILLATOR LAYOUT 11.5 Resetting Timer1 Using the CCP
CONSIDERATIONS Special Event Trigger
The Timer1 oscillator circuit draws very little power If the CCP module is configured in Compare mode
during operation. Due to the low-power nature of the to generate a Special Event Trigger
oscillator, it may also be sensitive to rapidly changing (CCP1M3:CCP1M0 = 1011), this signal will reset
signals in close proximity. Timer1. The trigger from CCP1 will also start an A/D
The oscillator circuit, shown in Figure 11-3, should be conversion if the A/D module is enabled (see
located as close as possible to the microcontroller. Section 13.3.4 “Special Event Trigger” for more
There should be no circuits passing within the oscillator information).
circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a
If a high-speed circuit must be located near the oscilla- synchronous counter to take advantage of this feature.
tor (such as the CCP1 pin in Output Compare or PWM When used this way, the CCPRH:CCPRL register pair
mode, or the primary oscillator using the OSC2 pin), a effectively becomes a period register for Timer1.
grounded guard ring around the oscillator circuit, as If Timer1 is running in Asynchronous Counter mode,
shown in Figure 11-4, may be helpful when used on a this Reset operation may not work.
single-sided PCB or in addition to a ground plane.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
FIGURE 11-4: OSCILLATOR CIRCUIT precedence.
WITH GROUNDED
GUARD RING Note: The Special Event Triggers from the
CCP1 module will not set the TMR1IF
VDD interrupt flag bit (PIR1<0>).
VSS
11.6 Using Timer1 as a Real-Time
OSC1 Clock
OSC2 Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
RC0
inexpensive watch crystal to provide an accurate time
RC1 base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
RC2 completely eliminate the need for a separate RTC
device and battery backup.
Note: Not drawn to scale.
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
11.4 Timer1 Interrupt increment a counter at one-second intervals using an
The TMR1 register pair (TMR1H:TMR1L) increments Interrupt Service Routine. Incrementing the TMR1
from 0000h to FFFFh and rolls over to 0000h. The register pair to overflow triggers the interrupt and calls
Timer1 interrupt, if enabled, is generated on overflow the routine which increments the seconds counter by
which is latched in interrupt flag bit, TMR1IF one. Additional counters for minutes and hours are
(PIR1<0>). This interrupt can be enabled or disabled incremented as the previous counter overflows.
by setting or clearing the Timer1 Interrupt Enable bit, Since the register pair is 16 bits wide, counting up to
TMR1IE (PIE1<0>). overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.

PIC18F2450/4450
EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1OSC ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW d’12’
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW d’59’ ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW d’59’ ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW d’23’ ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
MOVLW d’01’ ; Reset hours to 1
MOVWF hours
RETURN ; Done
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Reset
on page
PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 51
PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 51
IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP 51
TMR1H TImer1 Register High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
12.0 TIMER2 MODULE 12.1 Timer2 Operation
The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on
features: each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
• 8-bit timer and period registers (TMR2 and PR2,
16 prescale options. These are selected by the prescaler
respectively)
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
• Readable and writable (both registers) value of TMR2 is compared to that of the period register,
• Software programmable prescaler (1:1, 1:4 and PR2, on each clock cycle. When the two values match,
1:16) the comparator generates a match signal as the timer
• Software programmable postscaler (1:1 through output. This signal also resets the value of TMR2 to 00h
1:16) on the next cycle and drives the output counter/
• Interrupt on TMR2 to PR2 match postscaler (see Section 12.2 “Timer2 Interrupt”).
The module is controlled through the T2CON register The TMR2 and PR2 registers are both directly readable
(Register 12-1) which enables or disables the timer and and writable. The TMR2 register is cleared on any
configures the prescaler and postscaler. Timer2 can be device Reset, while the PR2 register initializes at FFh.
shut off by clearing control bit, TMR2ON (T2CON<2>), Both the prescaler and postscaler counters are cleared
to minimize power consumption. on the following events:
A simplified block diagram of the module is shown in • a write to the TMR2 register
Figure 12-1. • a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
•
•
•
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

PIC18F2450/4450
12.2 Timer2 Interrupt A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
Timer2 also can generate an optional device interrupt. bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/
12.3 TMR2 Output
postscaler. This counter generates the TMR2 match
interrupt flag which is latched in TMR2IF (PIR1<1>). The unscaled output of TMR2 is available primarily to
The interrupt is enabled by setting the TMR2 Match the CCP module, where it is used as a time base for
Interrupt Enable bit, TMR2IE (PIE1<1>). operations in PWM mode.
FIGURE 12-1: TIMER2 BLOCK DIAGRAM
4 1:1 to 1:16
T2OUTPS3:T2OUTPS0 Set TMR2IF
Postscaler
2
T2CKPS1:T2CKPS0 TMR2 Output
(to PWM)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Reset
on page
TMR2 Timer2 Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period Register 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

PIC18F2450/4450
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
PIC18F2450/4450 devices have one CCP (Capture/
Compare/PWM) module. The module contains a 16-bit
register, which can operate as a 16-bit Capture register,
a 16-bit Compare register or a PWM Master/Slave Duty
Cycle register.
REGISTER 13-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:

bit 5-4 DC1B1:DC1B0: PWM Duty Cycle for CCP Module bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty
cycle are found in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: CCP Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode: toggle output on match (CCP1IF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCP1 pin low; on compare match, force CCP1 pin high
(CCP1IF bit is set)
1001 = Compare mode: initialize CCP1 pin high; on compare match, force CCP1 pin low
(CCP1IF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCP1IF bit is set,
CCP1 pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer and start A/D conversion on CCP1 match
(CCP1IF bit is set)
11xx = PWM mode

PIC18F2450/4450
13.1 CCP Module Configuration 13.2.1 CCP1 PIN CONFIGURATION
The Capture/Compare/PWM module is associated with In Capture mode, the CCP1 pin should be configured
a control register (generically, CCP1CON) and a data as an input by setting the corresponding TRIS direction
register (CCPR1). The data register, in turn, is bit.
comprised of two 8-bit registers: CCPR1L (low byte) Note: If RC2/CCP1 is configured as an output, a
and CCPR1H (high byte). All registers are both write to the port can cause a capture
readable and writable. condition.
13.1.1 CCP MODULE AND TIMER 13.2.2 SOFTWARE INTERRUPT
RESOURCES
When the Capture mode is changed, a false capture
The CCP module utilizes Timer1 or Timer2, depending interrupt may be generated. The user should keep the
on the mode selected. Timer1 is available to the mod- CCP1IE interrupt enable bit clear to avoid false
ule in Capture or Compare modes, while Timer2 is interrupts. The interrupt flag bit, CCP1IF, should also
available for modules in PWM mode. be cleared following any such change in operating
mode.
TABLE 13-1: CCP MODE – TIMER
RESOURCE 13.2.3 CCP PRESCALER
CCP Mode Timer Resource There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
Capture Timer1 selected by the mode select bits (CCP1M3:CCP1M0).
Compare Timer1 Whenever the CCP module is turned off or Capture
PWM Timer2 mode is disabled, the prescaler counter is cleared. This
In Timer1 in Asynchronous Counter mode, the capture means that any Reset will clear the prescaler counter.
operation will not work. Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
13.2 Capture Mode not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 13-1 shows the
In Capture mode, the CCPR1H:CCPR1L register pair recommended method for switching between capture
captures the 16-bit value of the TMR1 register when an prescalers. This example also clears the prescaler
event occurs on the corresponding CCP1 pin. An event counter and will not generate the “false” interrupt.
is defined as one of the following:
• every falling edge EXAMPLE 13-1: CHANGING BETWEEN
• every rising edge CAPTURE PRESCALERS
• every 4th rising edge (CCP1 SHOWN)
• every 16th rising edge CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
The event is selected by the mode select bits, ; new prescaler mode
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture ; value and CCP ON
is made, the interrupt request flag bit, CCP1IF, is set; it MOVWF CCP1CON ; Load CCP1CON with
must be cleared in software. If another capture occurs ; this value
before the value in register CCPR1 is read, the old
captured value is overwritten by the new captured value.
FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
CCP1 pin
Prescaler and CCPR1H CCPR1L
÷ 1, 4, 16 Edge Detect
TMR1
Enable
4 TMR1H TMR1L
CCP1CON<3:0>
4
Q1:Q4

PIC18F2450/4450
13.3 Compare Mode 13.3.3 SOFTWARE INTERRUPT MODE
In Compare mode, the 16-bit CCPR1 register value is When the Generate Software Interrupt mode is chosen
constantly compared against the TMR1 register pair (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
value. When a match occurs, the CCP1 pin can be: affected. Only a CCP interrupt is generated, if enabled,
and the CCP1IE bit is set.
• driven high
• driven low 13.3.4 SPECIAL EVENT TRIGGER
• toggled (high-to-low or low-to-high) The CCP module is equipped with a Special Event
• remain unchanged (that is, reflects the state of the Trigger. This is an internal hardware signal generated
I/O latch) in Compare mode to trigger actions by other modules.
The action on the pin is based on the value of the mode The Special Event Trigger is enabled by selecting
select bits (CCP1M3:CCP1M0). At the same time, the the Compare Special Event Trigger mode
interrupt flag bit, CCP1IF, is set. (CCP1M3:CCP1M0 = 1011).
For the CCP module, the Special Event Trigger resets
13.3.1 CCP1 PIN CONFIGURATION the Timer1 register pair. This allows the CCPR1
The user must configure the CCP1 pin as an output by registers to serve as a programmable period register
clearing the appropriate TRIS bit. for the Timer1.
Note: Clearing the CCP1CON register will force The Special Event Trigger for CCP1 can also start an
the RC2 compare output latch to the A/D conversion. In order to do this, the A/D converter
default low level. must already be enabled.
13.3.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or
Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger

Set CCP1IF (Timer1 Reset)
CCPR1H CCPR1L
CCP1 pin
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCP1CON<3:0>
TMR1H TMR1L

PIC18F2450/4450
TABLE 13-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1
Reset
on page
RCON IPEN SBOREN(1) — RI TO PD POR BOR 50
TMR1H Timer1 Register High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
CCPR1L Capture/Compare/PWM Register 1 Low Byte 50
CCPR1H Capture/Compare/PWM Register 1 High Byte 50
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare and Timer1.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.

PIC18F2450/4450
13.4 PWM Mode 13.4.1 PWM PERIOD
In Pulse-Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2
produces up to a 10-bit resolution PWM output. register. The PWM period can be calculated using the
following formula:
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
EQUATION 13-1:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.4.3 PWM Period = [(PR2) + 1] • 4 • TOSC •
“Setup for PWM Operation”. (TMR2 Prescale Value)
FIGURE 13-3: SIMPLIFIED PWM BLOCK PWM frequency is defined as 1/[PWM period].
DIAGRAM When TMR2 is equal to PR2, the following three events
CCP1CON<5:4> occur on the next increment cycle:
Duty Cycle Registers
• TMR2 is cleared
CCPR1L
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H (Slave) CCPR1H
Note: The Timer2 postscalers (see Section 12.0
Comparator R Q “Timer2 Module”) are not used in the
CCP1 determination of the PWM frequency. The
Output postscaler could be used to have a servo
TMR2 (Note 1)
S update rate at a different frequency than
the PWM output.
Comparator Corresponding
Clear Timer, TRIS bit
CCP1 pin and 13.4.2 PWM DUTY CYCLE
latch D.C.
PR2 The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create to 10-bit resolution is available. The CCPR1L contains
the 10-bit time base. the eight MSbs and the CCP1CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
A PWM output (Figure 13-4) has a time base (period) CCPR1L:CCP1CON<5:4>. The following equation is
and a time that the output stays high (duty cycle). used to calculate the PWM duty cycle in time:
The frequency of the PWM is the inverse of the
period (1/period).
EQUATION 13-2:
FIGURE 13-4: PWM OUTPUT PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Period
CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into
Duty Cycle
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
TMR2 = PR2 CCPR1H is a read-only register.
TMR2 = Duty Cycle

TMR2 = PR2

PIC18F2450/4450
The CCPR1H register and a 2-bit internal latch are 13.4.3 SETUP FOR PWM OPERATION
used to double-buffer the PWM duty cycle. This
The following steps should be taken when configuring
double-buffering is essential for glitchless PWM
the CCP module for PWM operation:
operation.
1. Set the PWM period by writing to the PR2
When the CCPR1H and 2-bit latch match TMR2,
register.
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared. 2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
The maximum PWM resolution (bits) for a given PWM
3. Make the CCP1 pin an output by clearing the
frequency is given by the equation:
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
EQUATION 13-3:
Timer2 by writing to T2CON.
log ⎛ ---------------⎞
F OSC 5. Configure the CCP module for PWM operation.
⎝ F PWM⎠
PWM Resolution (max) = -----------------------------bits
log ( 2 )
Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be
cleared.
TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
TABLE 13-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Reset
on page
TMR2 Timer2 Register 50
PR2 Timer2 Period Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
CCPR1L Capture/Compare/PWM Register 1 Low Byte 50
CCPR1H Capture/Compare/PWM Register 1 High Byte 50
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.

PIC18F2450/4450
14.0 UNIVERSAL SERIAL BUS any USB host and the PIC® microcontroller. The SIE can
be interfaced directly to the USB, utilizing the internal
(USB)
transceiver, or it can be connected through an external
This section describes the details of the USB peripheral. transceiver. An internal 3.3V regulator is also available
Because of the very specific nature of the module, to power the internal transceiver in 5V applications.
knowledge of USB is expected. Some high-level USB Some special hardware features have been included to
information is provided in Section 14.9 “Overview of improve performance. Dual port memory in the
USB” only for application design reference. Designers device’s data memory space (USB RAM) has been
are encouraged to refer to the official specification supplied to share direct memory access between the
published by the USB Implementers Forum (USB-IF) for microcontroller core and the SIE. Buffer descriptors are
the latest information. USB Specification Revision 2.0 is also provided, allowing users to freely program
the most current specification at the time of publication endpoint memory usage within the USB RAM space.
of this document.
Figure 14-1 presents a general overview of the USB
peripheral and its features.
14.1 Overview of the USB Peripheral
The PIC18F2450/4450 device family contains a full-
speed and low-speed compatible USB Serial Interface
Engine (SIE) that allows fast communication between
FIGURE 14-1: USB PERIPHERAL AND OPTIONS
PIC18F2450/4450 Family
3.3V Regulator External 3.3V

VUSB
Supply(3)
VREGEN EN
External
Pull-ups(2)
FSEN
(Full (Low
UTRDIS Speed) Speed)
Transceiver
USB Bus
USB Clock from the FS
D+
Oscillator Module
OE D-
External
UOE(1) Transceiver
USB Control and VM(1) USB Bus
Configuration
VP(1)
RCV(1)
USB
VMO(1)
SIE
VPO(1)
256-Byte
USB RAM
Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The pull-ups can be supplied either from the VUSB pin or from an external 3.3V supply.
3: Do not enable the internal regulator when using an external 3.3V supply.

PIC18F2450/4450
14.2 USB Status and Control In addition, the USB Control register contains a status
bit, SE0 (UCON<5>), which is used to indicate the
The operation of the USB module is configured and occurrence of a single-ended zero on the bus. When
managed through three control registers. In addition, a the USB module is enabled, this bit should be
total of 22 registers are used to manage the actual USB monitored to determine whether the differential data
transactions. The registers are: lines have come out of a single-ended zero condition.
• USB Control register (UCON) This helps to differentiate the initial power-up state from
• USB Configuration register (UCFG) the USB Reset signal.
• USB Transfer Status register (USTAT) The overall operation of the USB module is controlled
• USB Device Address register (UADDR) by the USBEN bit (UCON<3>). Setting this bit activates
• Frame Number registers (UFRMH:UFRML) the module and resets all of the PPBI bits in the Buffer
• Endpoint Enable registers 0 through 15 (UEPn) Descriptor Table to ‘0’. This bit also activates the on-
chip voltage regulator, if enabled. Thus, this bit can be
14.2.1 USB CONTROL REGISTER (UCON) used as a soft attach/detach to the USB. Although all
status and control bits are ignored when this bit is clear,
The USB Control register (Register 14-1) contains bits
the module needs to be fully preconfigured prior to
needed to control the module behavior during transfers.
setting this bit.
The register contains bits that control the following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
REGISTER 14-1: UCON: USB CONTROL REGISTER

U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
bit 7 bit 0
Legend: C = Clearable bit


bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate

PIC18F2450/4450
The PPBRST bit (UCON<6>) controls the Reset status The UCFG register also contains two bits which aid in
when Double-Buffering mode (ping-pong buffering) is module testing, debugging and USB certifications.
used. When the PPBRST bit is set, all Ping-Pong These bits control output enable state monitoring and
Buffer Pointers are set to the Even buffers. PPBRST eye pattern generation.
has to be cleared by firmware. This bit is ignored in
Note: The USB speed, transceiver and pull-up
buffering modes not using ping-pong buffering.
should only be configured during the mod-
The PKTDIS bit (UCON<4>) is a flag indicating that the ule setup phase. It is not recommended to
SIE has disabled packet transmission and reception. switch these settings while the module is
This bit is set by the SIE when a SETUP token is enabled.
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it 14.2.2.1 Internal Transceiver
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer The USB peripheral has a built-in, USB 2.0, full-speed
Descriptor Table will still be available, indicated within and low-speed compliant transceiver, internally con-
the USTAT register’s FIFO buffer. nected to the SIE. This feature is useful for low-cost
single chip applications. The UTRDIS bit (UCFG<3>)
The RESUME bit (UCON<2>) allows the peripheral to controls the transceiver; it is enabled by default
perform a remote wake-up by executing Resume (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
signaling. To generate a valid remote wake-up, transceiver speed; setting the bit enables full-speed
firmware must set RESUME for 10 ms and then clear operation.
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0 The USB specification requires 3.3V operation for
specification. communications; however, the rest of the chip may be
running at a higher voltage. Thus, the transceiver is
The SUSPND bit (UCON<1>) places the module and supplied power from a separate source, VUSB.
supporting circuitry (i.e., voltage regulator) in a low-
power mode. The input clock to the SIE is also 14.2.2.2 External Transceiver
disabled. This bit should be set by the software in
This module provides support for use with an off-chip
response to an IDLEIF interrupt. It should be reset by
transceiver. The off-chip transceiver is intended for
the microcontroller firmware after an ACTVIF interrupt
applications where physical conditions dictate the
is observed. When this bit is active, the device remains
location of the transceiver to be away from the SIE. For
attached to the bus but the transceiver outputs remain
example, applications that require isolation from the
Idle. The voltage on the VUSB pin may vary depending
USB could use an external transceiver through some
on the value of this bit. Setting this bit before a IDLEIF
isolation to the microcontroller’s SIE (Figure 14-2).
request will result in unpredictable bus behavior.
External transceiver operation is enabled by setting the
Note: While in Suspend mode, a typical bus UTRDIS bit.
powered USB device is limited to 500 μA
of current. This is the complete current FIGURE 14-2: TYPICAL EXTERNAL
drawn by the PICmicro device and its sup- TRANSCEIVER WITH
porting circuitry. Care should be taken to ISOLATION
assure minimum current draw when the
device enters Suspend mode. VDD Isolated 3.3V Derived
PIC®
Microcontroller from USB from USB
14.2.2 USB CONFIGURATION REGISTER VDD
VUSB
(UCFG)
1.5 kΩ
VM Isolation Transceiver
Prior to communicating over USB, the module’s VP
associated internal and/or external hardware must be RCV D+
configured. Most of the configuration is performed with VMO
D-
VPO
the UCFG register (Register 14-2). The separate USB
UOE
voltage regulator (see Section 14.2.2.7 “Internal
Regulator”) is controlled through the Configuration
registers. Note: The above setting shows a simplified schematic
The UFCG register contains most of the bits that for a full-speed configuration using an external
transceiver with isolation.
control the system level behavior of the USB module.
These include:
• Bus Speed (full speed versus low speed)
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage

PIC18F2450/4450
REGISTER 14-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0
bit 7 bit 0
Legend:
bit 7 UTEYE: USB Eye Pattern Test Enable bit

1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6 UOEMON: USB OE Monitor Enable bit(1)
1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving
0 = UOE signal inactive
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit(2)
1 = On-chip transceiver disabled; digital transceiver interface enabled
0 = On-chip transceiver active
bit 2 FSEN: Full-Speed Enable bit(2)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Enabled for all endpoints except Endpoint 0
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
There are 6 signals from the module to communicate The VPO and VMO signals are outputs from the SIE to
with and control an external transceiver: the external transceiver. The RCV signal is the output
• VM: Input from the single-ended D- line from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
• VP: Input from the single-ended D+ line
into a single pulse train. The VM and VP signals are
• RCV: Input from the differential receiver used to report conditions on the serial bus to the SIE
• VMO: Output to the differential line driver that can’t be captured with the RCV signal. The
• VPO: Output to the differential line driver combinations of states of these signals and their
• UOE: Output enable interpretation are listed in Table 14-1 and Table 14-2.

PIC18F2450/4450
TABLE 14-1: DIFFERENTIAL OUTPUTS TO 14.2.2.5 USB Output Enable Monitor
TRANSCEIVER The USB OE monitor provides indication as to whether
VPO VMO Bus State the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
0 0 Single-Ended Zero transceiver or when UCFG<6> = 1.
0 1 Differential ‘0’ The USB OE monitoring is useful for initial system
1 0 Differential ‘1’ debugging, as well as scope triggering during eye
pattern generation tests.
1 1 Illegal Condition
14.2.2.6 Eye Pattern Test Enable
TABLE 14-2: SINGLE-ENDED INPUTS
An automatic eye pattern test can be generated by the
FROM TRANSCEIVER module when the UCFG<7> bit is set. The eye pattern
VP VM Bus State output will be observable based on module settings,
meaning that the user is first responsible for configuring
0 0 Single-Ended Zero the SIE clock settings, pull-up resistor and Transceiver
0 1 Low Speed mode. In addition, the module has to be enabled.
1 0 High Speed Once UTEYE is set, the module emulates a switch from
1 1 Error a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
The UOE signal toggles the state of the external sequence will be repeated indefinitely while the Eye
transceiver. This line is pulled low by the device to Pattern Test mode is enabled.
enable the transmission of data from the SIE to an
Note that this bit should never be set while the module
external device.
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB
14.2.2.3 Pull-up Resistors
certification tests. It is intended to show a system
The PIC18F2450/4450 devices require an external pull- developer the noise integrity of the USB signals which
up resistor to meet the requirements for low-speed and can be affected by board traces, impedance
full-speed USB. Either an external 3.3V supply or the mismatches and proximity to other system
VUSB pin may be used to pull up D+ or D-. The pull-up components. It does not properly test the transition
resistor must be 1.5 kΩ (±5%) as required by the USB from a receive to a transmit state. Although the eye
specifications. Figure 14-3 shows an example with the pattern is not meant to replace the more complex USB
VUSB pin. certification test, it should aid during first order system
debugging.
FIGURE 14-3: EXTERNAL CIRCUITRY
14.2.2.7 Internal Regulator
PIC® Host
Microcontroller Controller/HUB The PIC18F2450/4450 devices have a built-in 3.3V
regulator to provide power to the internal transceiver and
provide a source for the external pull-ups. An external
VUSB 220 nF (±20%) capacitor is required for stability.
Note: The drive from VUSB is sufficient to only
drive an external pull-up in addition to the
internal transceiver.
1.5 kΩ
D+ The regulator is enabled by default and can be disabled
D- through the VREGEN Configuration bit. When enabled,
the voltage is visible on pin VUSB. When the regulator
is disabled, a 3.3V source must be provided through
the VUSB pin for the internal transceiver. If the internal
Note: The above setting shows a typical connection transceiver is disabled, VUSB is not used.
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor. Note 1: Do not enable the internal regulator if an
external regulator is connected to VUSB.
2: VDD must be greater than VUSB at all
14.2.2.4 Ping-Pong Buffer Configuration times, even with the regulator disabled.
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 14.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.

PIC18F2450/4450
14.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
The USB Status register reports the transaction status
FIFO holding register is valid, the SIE will immediately
within the SIE. When the SIE issues a USB transfer
reassert the interrupt. If no additional data is present,
complete interrupt, USTAT should be read to determine
TRNIF will remain clear; USTAT data will no longer be
the status of the transfer. USTAT contains the transfer
reliable.
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used). Note: If an endpoint request is received while the
USTAT FIFO is full, the SIE will
Note: The data in the USB Status register is valid
automatically issue a NAK back to the
only when the TRNIF interrupt flag is
host.
asserted.
The USTAT register is actually a read window into a FIGURE 14-4: USTAT FIFO
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the USTAT from SIE
SIE processes additional endpoints (Figure 14-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
4-byte FIFO Clearing TRNIF
complete interrupt is serviced, the SIE will store the Advances FIFO
for USTAT
status of the next transfer into the status FIFO.
Data Bus
REGISTER 14-3: USTAT: USB STATUS REGISTER

U-0 R-x R-x R-x R-x R-x R-x U-0
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0
Legend:

bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.

PIC18F2450/4450
14.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Each of the 16 possible bidirectional endpoints has its
Endpoint 0 as the default control endpoint.
own independent control register, UEPn (where ‘n’ rep-
resents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or dis-
identical complement of control bits. The prototype is able USB OUT transactions from the host. Setting this
shown in Register 14-4. bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
The EPHSHK bit (UEPn<4>) controls handshaking for
from the host.
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using The EPSTALL bit (UEPn<0>) is used to indicate a
isochronous endpoints. STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
The EPCONDIS bit (UEPn<3>) is used to enable or
point pair will be set by the SIE. This bit remains set
disable USB control operations (SETUP) through the
until it is cleared through firmware, or until the SIE is
endpoint. Clearing this bit enables SETUP
reset.
transactions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 14-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
Legend:

bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint Stall Enable bit(1)
1 = Endpoint n is stalled
0 = Endpoint n is not stalled
Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.

PIC18F2450/4450
14.2.5 USB ADDRESS REGISTER FIGURE 14-5: IMPLEMENTATION OF
(UADDR) USB RAM IN DATA
The USB Address register contains the unique USB MEMORY SPACE
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received, 000h
indicated by URSTIF, or when a Reset is received from Banks 0
to 1 User Data
the microcontroller. The USB address must be written
1FFh
by the microcontroller during the USB setup phase 200h
(enumeration) as part of the Microchip USB firmware Banks 2
Unused
to 3
support.
3FFh
Buffer Descriptors, 400h
14.2.6 USB FRAME NUMBER REGISTERS Bank 4
USB Data or User Data 4FFh
(UFRMH:UFRML) 500h
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML, USB Data or
while the three high-order bits are contained in User Data
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used for 7FFh
isochronous transfers. 800h
Banks 5 Unused
to 14
14.3 USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the normal data memory space in Bank 4
(400h to 4FFh) for a total of 256 bytes (Figure 14-5).
Some portion of Bank 4 (400h through 4FFh) is used
specifically for endpoint buffer control, while the
remaining portion is available for USB data. Depending
on the type of buffering being used, all but 8 bytes of
Bank 4 may also be available for use as USB buffer
F00h
space. F80h
Bank15
SFRs
Although USB RAM is available to the microcontroller FFFh
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 14.4.1.1 “Buffer
Ownership”.

PIC18F2450/4450
14.4 Buffer Descriptors and the Buffer 14.4.1 BD STATUS AND CONFIGURATION
Descriptor Table Buffer descriptors not only define the size of an
endpoint buffer, but also determine its configuration
The registers in Bank 4 are used specifically for end-
and control. Most of the configuration is done with the
point buffer control in a structure known as the Buffer
BD Status register, BDnSTAT. Each BD has its own
Descriptor Table (BDT). This provides a flexible method
unique and correspondingly numbered BDnSTAT
for users to construct and control endpoint buffers of
register.
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which FIGURE 14-6: EXAMPLE OF A BUFFER
are used to define and control the actual buffers in the
DESCRIPTOR
USB RAM space. Each BD, in turn, consists of four
registers, where n represents one of the 64 possible Address Registers Contents
BDs (range of 0 to 63): 400h BD0STAT (xxh)
• BDnSTAT: BD Status register Buffer 401h BD0CNT 10h Size of Block
• BDnCNT: BD Byte Count register Descriptor 402h BD0ADRL 80h
Starting
• BDnADRL: BD Address Low register 403h BD0ADRH 04h Address
• BDnADRH: BD Address High register
480h
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in Buffer USB Data
hexadecimal) from 400h, with n being the buffer
descriptor number.
Depending on the buffering configuration used 48Fh
(Section 14.4.4 “Ping-Pong Buffering”), there are up Note: Memory regions not to scale.
to 32, 33 or 64 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because Unlike other control registers, the bit configuration for
the USB specification mandates that every device must the BDnSTAT register is context sensitive. There are
have Endpoint 0 with both input and output for initial two distinct configurations, depending on whether the
setup. Depending on the endpoint and buffering microcontroller or the USB module is modifying the BD
configuration, the BDT can be as long as 256 bytes. and buffer at a particular time. Only three bit definitions
Although they can be thought of as Special Function are shared between the two.
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional 14.4.1.1 Buffer Ownership
microcontroller SFRs in Bank 15 are. If the endpoint cor- Because the buffers and their BDs are shared between
responding to a particular BD is not enabled, its registers the CPU and the USB module, a simple semaphore
are not used. Instead of appearing as unimplemented mechanism is used to distinguish which is allowed to
addresses, however, they appear as available RAM. update the BD and associated buffers in memory.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses This is done by using the UOWN bit (BDnSTAT<7>) as
become functional as BD registers. As with any address a semaphore to distinguish which is allowed to update
in the data memory space, the BD registers have an the BD and associated buffers in memory. UOWN is the
indeterminate value on any device Reset. only bit that is shared between the two configurations
of BDnSTAT.
A total of 256 bytes of address space in Bank 4 is
available for BDT and USB data RAM. In Ping-Pong When UOWN is clear, the BD entry is “owned” by the
Buffer mode, all the 16 bidirectional endpoints can not microcontroller core. When the UOWN bit is set, the BD
be implemented where BDT itself can be as long as entry and the buffer memory are “owned” by the USB
256 bytes. In the majority of USB applications, few peripheral. The core should not modify the BD or its
endpoints are required to be implemented. Hence, a corresponding data buffer during this time. Note that
small portion of the 256 bytes will be used for BDT and the microcontroller core can still read BDnSTAT while
the rest can be used for USB data. the SIE owns the buffer and vice versa.
An example of a BD for a 16-byte buffer, starting at The buffer descriptors have a different meaning based
480h, is shown in Figure 14-6. A particular set of BD on the source of the register update. Prior to placing
registers is only valid if the corresponding endpoint has ownership with the USB peripheral, the user can con-
been enabled using the UEPn register. All BD registers figure the basic operation of the peripheral through the
are available in USB RAM. The BD for each endpoint BDnSTAT bits. During this time, the byte count and
should be set up prior to enabling the endpoint. buffer location registers can also be set.

PIC18F2450/4450
When UOWN is set, the user can no longer depend on the USB RAM and the USB transfer complete interrupt
the values that were written to the BDs. From this point, flag will not be set. The SIE will send an ACK token
the SIE updates the BDs as necessary, overwriting the back to the host to Acknowledge receipt, however. The
original BD values. The BDnSTAT register is updated effects of the DTSEN bit on the SIE are summarized in
by the SIE with the token PID and the transfer count, Table 14-3.
BDnCNT, is updated. The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
The BDnSTAT byte of the BDT should always be the support for control transfers, usually one-time stalls on
last byte updated when preparing to arm an endpoint. Endpoint 0. It also provides support for the
The SIE will clear the UOWN bit when a transaction SET_FEATURE/CLEAR_FEATURE commands speci-
has completed. The only exception to this is when KEN fied in Chapter 9 of the USB specification; typically,
is enabled and/or BSTALL is enabled. continuous STALLs to any endpoint other than the
No hardware mechanism exists to block access when default control endpoint.
the UOWN bit is set. Thus, unexpected behavior can The BSTALL bit enables buffer stalls. Setting BSTALL
occur if the microcontroller attempts to modify memory causes the SIE to return a STALL token to the host if a
when the SIE owns it. Similarly, reading such memory received token would use the BD in that location. The
may produce inaccurate data until the USB peripheral EPSTALL bit in the corresponding UEPn control
returns ownership to the microcontroller. register is set and a STALL interrupt is generated when
a STALL is issued to the host. The UOWN bit remains
14.4.1.2 BDnSTAT Register (CPU Mode) set and the BDs are not changed unless a SETUP
When UOWN = 0, the microcontroller core owns the token is received. In this case, the STALL condition is
BD. At this point, the other seven bits of the register cleared and the ownership of the BD is returned to the
take on control functions. microcontroller core.
The Data Toggle Sync Enable bit, DTSEN The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
(BDnSTAT<3>), controls data toggle parity checking. significant digits of the SIE byte count; the lower 8 digits
Setting DTSEN enables data toggle synchronization by are stored in the corresponding BDnCNT register. See
the SIE. When enabled, it checks the data packet’s Section 14.4.2 “BD Byte Count” for more
parity against the value of DTS (BDnSTAT<6>). If a information.
packet arrives with an incorrect synchronization, the
data will essentially be ignored. It will not be written to
TABLE 14-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

OUT Packet BDnSTAT Settings Device Response after Receiving Packet
from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA0 1 1 ACK 0 1 Updated
DATA1 1 1 ACK 1 0 Not Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care

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REGISTER 14-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS (2)
— (3)
— (3)
DTSEN BSTALL BC9 BC8
bit 7 bit 0
Legend:
bit 7 UOWN: USB Own bit(1)

0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5-4 Reserved: These bits should always be programmed to ‘0’(3)
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained
as ‘0’.

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14.4.1.3 BDnSTAT Register (SIE Mode) byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
When the BD and its buffer are owned by the SIE, most
byte count will not be updated.
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 14-6. Once UOWN is The 10-bit byte count is distributed over two registers.
set, any data or control settings previously written there The lower 8 bits of the count reside in the BDnCNT
by the user will be overwritten with data from the SIE. register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
14.4.3 BD ADDRESS VALIDATION
BDnSTAT<5:3>. The transfer count in the
corresponding BDnCNT register is updated. Values The BD Address register pair contains the starting RAM
that overflow the 8-bit register carry over to the two address location for the corresponding endpoint buffer.
most significant digits of the count, stored in For an endpoint starting location to be valid, it must fall
BDnSTAT<1:0>. in the range of the USB RAM, 400h to 7FFh. No
mechanism is available in hardware to validate the BD
14.4.2 BD BYTE COUNT address.
The byte count represents the total number of bytes If the value of the BD address does not point to an
that will be transmitted during an IN transfer. After an IN address in the USB RAM, or if it points to an address
transfer, the SIE will return the number of bytes sent to within another endpoint’s buffer, data is likely to be lost
the host. or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
For an OUT transfer, the byte count represents the
unexpected results. When developing USB
maximum number of bytes that can be received and
applications, the user may want to consider the
stored in USB RAM. After an OUT transfer, the SIE will
inclusion of software-based address validation in their
return the actual number of bytes received. If the
code.
number of bytes received exceeds the corresponding
REGISTER 14-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0
Legend:
bit 7 UOWN: USB Own bit

1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.

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14.4.4 PING-PONG BUFFERING SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
An endpoint is defined to have a ping-pong buffer when
toggled back to the Even BD and so on.
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the The Even/Odd status of the last transaction is stored in
CPU to process one BD while the SIE is processing the the PPBI bit of the USTAT register. The user can reset
other BD. Double-buffering BDs in this way allows for all Ping-Pong Pointers to Even using the PPBRST bit.
maximum throughput to/from the USB. Figure 14-7 shows the three different modes of
The USB module supports three modes of operation: operation and how USB RAM is filled with the BDs.
• No ping-pong support BDs have a fixed relationship to a particular endpoint,
• Ping-pong buffer support for OUT Endpoint 0 only depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 14-4. This
• Ping-pong buffer support for all endpoints
relationship also means that gaps may occur in the
The ping-pong buffer settings are configured using the BDT if endpoints are not enabled contiguously. This
PPB1:PPB0 bits in the UCFG register. theoretically means that the BDs for disabled endpoints
The USB module keeps track of the Ping-Pong Pointer could be used as buffer space. In practice, users
individually for each endpoint. All pointers are initially should avoid using such spaces in the BDT unless a
reset to the Even BD when the module is enabled. After method of validating BD addresses is implemented.
the completion of a transaction (UOWN cleared by the
FIGURE 14-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

PPB1:PPB0 = 00 PPB1:PPB0 = 01 PPB1:PPB0 = 10
No Ping-Pong Buffers Ping-Pong Buffer on EP0 OUT Ping-Pong Buffers on all EPs
400h 400h 400h
EP0 OUT EP0 OUT Even EP0 OUT Even
Descriptor Descriptor Descriptor
EP0 IN EP0 OUT Odd EP0 OUT Odd

Descriptor Descriptor Descriptor
EP1 OUT EP0 IN Even

Descriptor EP0 IN Descriptor
Descriptor
EP1 IN EP0 IN Odd
Descriptor EP1 OUT Descriptor
Descriptor
EP1 OUT Even
EP1 IN Descriptor
Descriptor
EP1 OUT Odd
EP15 IN
Descriptor
Descriptor
47Fh
EP1 IN Even
EP15 IN Descriptor
483h Descriptor
EP1 IN Odd
Descriptor
Available
as
Available
Data RAM
as
Data RAM
EP15 IN Odd
Descriptor
4FFh 4FFh 4FFh
Maximum Memory Used: 128 bytes Maximum Memory Used: 132 bytes Maximum Memory Used: 256 bytes
Maximum BDs: 32 (BD0 to BD31) Maximum BDs: 33 (BD0 to BD32) Maximum BDs: 64 (BD0 to BD63)
Note: Memory area not shown to scale.

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TABLE 14-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BDs Assigned to Endpoint
Mode 0 Mode 1 Mode 2

Endpoint
(No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs)
Out In Out In Out In

0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O)
1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O)
8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O)
9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O)
10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O)
11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O)
12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O)
13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O)
14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O)
15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
TABLE 14-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8
DTSEN(3) BSTALL(3)
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT
register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.

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14.5 USB Interrupts Figure 14-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
The USB module can generate multiple interrupt the USB module. The top level consists of overall USB
conditions. To accommodate all of these interrupt status interrupts; these are enabled and flagged in the
sources, the module is provided with its own interrupt UIE and UIR registers, respectively. The second level
logic structure, similar to that of the microcontroller. consists of USB error conditions, which are enabled
USB interrupts are enabled with one set of control and flagged in the UEIR and UEIE registers. An
registers and trapped with a separate set of flag regis- interrupt condition in any of these triggers a USB Error
ters. All sources are funneled into a single USB inter- Interrupt Flag (UERRIF) in the top level.
rupt request, USBIF (PIR2<5>), in the
microcontroller’s interrupt logic. Interrupts may be used to trap routine events in a USB
transaction. Figure 14-9 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 14-8: USB INTERRUPT LOGIC FUNNEL

Second Level USB Interrupts Top Level USB Interrupts
(USB Error Conditions) (USB Status Interrupts)
UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers
SOFIF
SOFIE
BTSEF
BTSEE TRNIF USBIF
TRNIE
BTOEF
BTOEE
IDLEIF
DFN8EF IDLEIE
DFN8EE UERRIF
CRC16EF UERRIE
CRC16EE
CRC5EF STALLIF
STALLIE
CRC5EE
PIDEF
PIDEE ACTVIF
ACTVIE
URSTIF
URSTIE
FIGURE 14-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

From Host From Host To Host
SETUPToken Data ACK Set TRNIF
From Host To Host From Host

IN Token Data ACK Set TRNIF
USB Reset
URSTIF
From Host From Host To Host
START-OF-FRAME
OUT Token Empty Data ACK Set TRNIF
SOFIF
Transaction
Transaction
Complete
RESET SOF SETUP DATA STATUS SOF

Differential Data
Control Transfer(1)
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.

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14.5.1 USB INTERRUPT STATUS Once an interrupt bit has been set by the SIE, it must
REGISTER (UIR) be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
The USB Interrupt Status register (Register 14-7)
debugging.
contains the flag bits for each of the USB status
interrupt sources. Each of these sources has a
corresponding interrupt enable bit in the UIE register. All
of the USB status flags are ORed together to generate
the USBIF interrupt flag for the microcontroller’s
interrupt funnel.
REGISTER 14-7: UIR: USB INTERRUPT STATUS REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0
Legend:

bit 6 SOFIF: START-OF-FRAME Token Interrupt bit
1 = A START-OF-FRAME token received by the SIE
0 = No START-OF-FRAME token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.

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14.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation
REGISTER (UIE) of an interrupt condition to the microcontroller’s
interrupt logic. The flag bits are still set by their
The USB Interrupt Enable register (Register 14-8)
interrupt conditions, allowing them to be polled and
contains the enable bits for the USB status interrupt
serviced without actually generating an interrupt.
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
REGISTER 14-8: UIE: USB INTERRUPT ENABLE REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0
Legend:

bit 6 SOFIE: START-OF-FRAME Token Interrupt Enable bit
1 = START-OF-FRAME token interrupt enabled
0 = START-OF-FRAME token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled

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14.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is
REGISTER (UEIR) detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
The USB Error Interrupt Status register (Register 14-9)
contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must
within the USB peripheral. Each of these sources is be cleared by software by writing a ‘0’.
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.
REGISTER 14-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER

R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
bit 7 BTSEF: Bit Stuff Error Flag bit

1 = A bit stuff error has been detected
0 = No bit stuff error
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed

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14.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the
REGISTER (UEIE) propagation of an interrupt condition to the
microcontroller’s interrupt logic. The flag bits are still
The USB Error Interrupt Enable register (Register 14-10)
set by their interrupt conditions, allowing them to be
contains the enable bits for each of the USB error
polled and serviced without actually generating an
interrupt sources. Setting any of these bits will enable the
interrupt.
respective error interrupt source in the UEIR register to
propagate into the UERR bit at the top level of the
interrupt logic.
REGISTER 14-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0
Legend:
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled

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14.6 USB Power Modes 14.6.3 DUAL POWER WITH SELF-POWER
DOMINANCE
Many USB applications will likely have several different
sets of power requirements and configuration. The Some applications may require a dual power option.
most common power modes encountered are Bus This allows the application to use internal power prima-
Power Only, Self-Power Only and Dual Power with rily, but switch to power from the USB when no internal
Self-Power Dominance. The most common cases are power is available. Figure 14-12 shows a simple Dual
presented here. Power with Self-Power Dominance example, which
automatically switches between Self-Power Only and
14.6.1 BUS POWER ONLY USB Bus Power Only modes.
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 14-10). This is FIGURE 14-12: DUAL POWER EXAMPLE
effectively the simplest power method for the device.
100 kΩ Attach Sense
I/O pin
FIGURE 14-10: BUS POWER ONLY
VBUS VDD
~5V
VBUS VDD
~5V 100 kΩ VUSB
VSELF VSS
VUSB ~5V
VSS
Note: Users should keep in mind the limits for

devices drawing power from the USB.
14.6.2 SELF-POWER ONLY According to USB Specification 2.0, this
In Self-Power Only mode, the USB application provides cannot exceed 100 mA per low-power
its own power, with very little power being pulled from device or 500 mA per high-power device.
the USB. Figure 14-11 shows an example. Note that an
attach indication is added to indicate when the USB 14.7 Oscillator
has been connected.
The USB module has specific clock requirements. For
FIGURE 14-11: SELF-POWER ONLY full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
Attach Sense are not required to run at that clock speed or even from
VBUS I/O pin the same clock source. Available clocking options are
~5V
100 kΩ described in detail in Section 2.3 “Oscillator Settings
VSELF VDD for USB”.
~5V
100 kΩ VUSB
14.8 USB Firmware and Drivers
Microchip provides a number of application-specific
VSS resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.

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TABLE 14-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Details on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
page

UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 52
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 52
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 52
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 52
UFRMH — — — — — FRM10 FRM9 FRM8 52
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 52
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 52
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 52
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 52
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5.

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14.9 Overview of USB 14.9.3 TRANSFERS
This section presents some of the basic USB concepts There are four transfer types defined in the USB
and useful information necessary to design a USB specification.
device. Although much information is provided in this • Isochronous: This type provides a transfer
section, there is a plethora of information provided method for large amounts of data (up to
within the USB specifications and class specifications. 1023 bytes) with timely delivery ensured;
Thus, the reader is encouraged to refer to the USB however, the data integrity is not ensured. This is
specifications for more information (www.usb.org). If good for streaming applications where small data
you are very familiar with the details of USB, then this loss is not critical, such as audio.
section serves as a basic, high-level refresher of USB. • Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
14.9.1 LAYERED FRAMEWORK data integrity; however, the delivery timeliness is
USB device functionality is structured into a layered not ensured.
framework graphically shown in Figure 14-13. Each • Interrupt: This type of transfer provides for
level is associated with a functional level within the ensured timely delivery for small blocks of data;
device. The highest layer, other than the device, is the plus data integrity is ensured.
configuration. A device may have multiple configura- • Control: This type provides for device setup
tions. For example, a particular device may have control.
multiple power requirements based on Self-Power Only
or Bus Power Only modes. While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
For each configuration, there may be multiple transfers only.
interfaces. Each interface could support a particular
mode of that configuration. 14.9.4 POWER
Below the interface is the endpoint(s). Data is directly Power is available from the Universal Serial Bus. The
moved at this level. There can be as many as USB specification defines the bus power requirements.
16 bidirectional endpoints. Endpoint 0 is always a Devices may either be self-powered or bus powered.
control endpoint and by default, when the device is on Self-powered devices draw power from an external
the bus, Endpoint 0 must be available to configure the source, while bus powered devices use power supplied
device. from the bus.
14.9.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 14-9 shows an example of a
transaction within a frame.
FIGURE 14-13: USB LAYERS
Device
To other Configurations (if any)
Configuration
To other Interfaces (if any)
Interface Interface
Endpoint Endpoint Endpoint Endpoint Endpoint

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The USB specification limits the power taken from the 14.9.6.2 Configuration Descriptor
bus. Each device is ensured 100 mA at approximately 5V
The configuration descriptor provides information on
(one-unit load). Additional power may be requested, up
the power requirements of the device and how many
to a maximum of 500 mA. Note that power above a one-
different interfaces are supported when in this
unit load is a request and the host or hub is not obligated
configuration. There may be more than one configura-
to provide the extra current. Thus, a device capable of
tion for a device (i.e., low-power and high-power
consuming more than a one-unit load must be able to
configurations).
maintain a low-power configuration of a one-unit load or
less, if necessary. 14.9.6.3 Interface Descriptor
The USB specification also defines a Suspend mode. The interface descriptor details the number of
In this situation, current must be limited to 500 μA, endpoints used in this interface, as well as the class of
averaged over 1 second. A device must enter a the interface. There may be more than one interface for
Suspend state after 3 ms of inactivity (i.e., no SOF a configuration.
tokens for 3 ms). A device entering Suspend mode
must drop current consumption within 10 ms after 14.9.6.4 Endpoint Descriptor
Suspend. Likewise, when signaling a wake-up, the
device must signal a wake-up within 10 ms of drawing The endpoint descriptor identifies the transfer type
current above the Suspend limit. (Section 14.9.3 “Transfers”) and direction, as well as
some other specifics for the endpoint. There may be
14.9.5 ENUMERATION many endpoints in a device and endpoints may be
shared in different configurations.
When the device is initially attached to the bus, the host
enters an enumeration process in an attempt to identify 14.9.6.5 String Descriptor
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data Many of the previous descriptors reference one or
rates and sizes, protocol and other descriptive more string descriptors. String descriptors provide
information; descriptors contain this information. A human readable information about the layer
typical enumeration process would be as follows: (Section 14.9.1 “Layered Framework”) they
describe. Often these strings show up in the host to
1. USB Reset: Reset the device. Thus, the device help the user identify the device. String descriptors are
is not configured and does not have an address generally optional to save memory and are encoded in
(address 0). a unicode format.
2. Get Device Descriptor: The host requests a
small portion of the device descriptor. 14.9.7 BUS SPEED
3. USB Reset: Reset the device again. Each USB device must indicate its bus presence and
4. Set Address: The host assigns an address to the speed to the host. This is accomplished through a
device. 1.5 kΩ resistor which is connected to the bus at the
5. Get Device Descriptor: The host retrieves the time of the attachment event.
device descriptor, gathering info such as Depending on the speed of the device, the resistor
manufacturer, type of device, maximum control either pulls up the D+ or D- line to 3.3V. For a low-
packet size. speed device, the pull-up resistor is connected to the
6. Get configuration descriptors. D- line. For a full-speed device, the pull-up resistor is
7. Get any other descriptors. connected to the D+ line.
8. Set a configuration.
14.9.8 CLASS SPECIFICATIONS AND
The exact enumeration process depends on the host. DRIVERS
14.9.6 DESCRIPTORS USB specifications include class specifications which
operating system vendors optionally support.
There are eight different standard descriptor types of Examples of classes include Audio, Mass Storage,
which five are most important for this device. Communications and Human Interface (HID). In most
cases, a driver is required at the host side to ‘talk’ to the
14.9.6.1 Device Descriptor
USB device. In custom applications, a driver may need
The device descriptor provides general information, to be developed. Fortunately, drivers are available for
such as manufacturer, product number, serial number, most common host systems for the most common
the class of the device and the number of configurations. classes of devices. Thus, these drivers can be reused.
There is only one device descriptor.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
15.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed with
PORTC. In order to configure RC6/TX/CK and RC7/RX/
SYNCHRONOUS RECEIVER
DT as an EUSART:
TRANSMITTER (EUSART)
• bit SPEN (RCSTA<7>) must be set (= 1)
The Universal Synchronous Asynchronous Receiver • bit TRISC<7> must be set (= 1)
Transmitter (USART) module is one of the two serial • bit TRISC<6> must be cleared (= 0) for
I/O modules. (USART is also known as a Serial Asynchronous and Synchronous Master modes
Communications Interface or SCI.) The USART can be or set (= 1) for Synchronous Slave mode
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as Note: The EUSART control will automatically
CRT terminals and personal computers. It can also be reconfigure the pin from input to output as
configured as a half-duplex synchronous system that needed.
can communicate with peripheral devices, such as A/D The operation of the Enhanced USART module is
or D/A integrated circuits, serial EEPROMs and so on. controlled through three registers:
The Enhanced Universal Synchronous Receiver • Transmit Status and Control (TXSTA)
Transmitter (EUSART) module implements additional • Receive Status and Control (RCSTA)
features, including Automatic Baud Rate Detection
• Baud Rate Control (BAUDCON)
(ABD) and calibration, automatic wake-up on Sync
Break reception and 12-bit Break character transmit. These are detailed on the following pages in
These features make it ideally suited for use in Local Register 15-1, Register 15-2 and Register 15-3,
Interconnect Network bus (LIN bus) systems. respectively.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity

PIC18F2450/4450
REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
(1)
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous
Slave mode.

PIC18F2450/4450
REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F2450/4450
REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:

PIC18F2450/4450
15.1 Baud Rate Generator (BRG) the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
The BRG is a dedicated 8-bit or 16-bit generator that for a fast oscillator frequency.
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates Writing a new value to the SPBRGH:SPBRG registers
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>) causes the BRG timer to be reset (or cleared). This
selects 16-bit mode. ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits 15.1.1 OPERATION IN POWER-MANAGED
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also MODES
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 15-1 shows the formula for computation The device clock is used to generate the desired baud
of the baud rate for different EUSART modes which rate. When one of the power-managed modes is
only apply in Master mode (internally generated clock). entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
Given the desired baud rate and FOSC, the nearest the value in the SPBRG register pair.
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 15-1. From this, 15.1.2 SAMPLING
the error in baud rate can be determined. An example
calculation is shown in Example 15-1. Typical baud rates The data on the RX pin is sampled three times by a
and error values for the various Asynchronous modes majority detect circuit to determine if a high or a low
are shown in Table 15-2. It may be advantageous to use level is present at the RX pin.
TABLE 15-1: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n + 1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
EXAMPLE 15-1: CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 15-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Reset
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 50
SPBRG EUSART Baud Rate Generator Register Low Byte 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

PIC18F2450/4450
TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 0

BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate value Rate value Rate value
Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal)
0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51

1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12
2.4 2.404 0.16 25 2403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
% % % %
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
% % %
Error Error Error
0.3 — — — — — — 300 -0.16 207

1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —

PIC18F2450/4450
TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
% % % %
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
% % %
Error Error Error
0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
% % % %
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
% % %
Error Error Error
0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832
1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207
2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25
19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12
57.6 58.824 2.12 16 55555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —

PIC18F2450/4450
15.1.3 AUTO-BAUD RATE DETECT While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
The Enhanced USART module supports the automatic
once the fifth rising edge on RX is detected. The value
detection and calibration of baud rate. This feature is
in the RCREG needs to be read to clear the RCIF
active only in Asynchronous mode and while the WUE
interrupt. The contents of RCREG should be discarded.
bit is clear.
The automatic baud rate measurement sequence Note 1: If the WUE bit is set with the ABDEN bit,
(Figure 15-1) begins whenever a Start bit is received Auto-Baud Rate Detection will occur on
and the ABDEN bit is set. The calculation is self-aver- the byte following the Break character.
aging. 2: It is up to the user to determine that the
In the Auto-Baud Rate Detect (ABD) mode, the clock to incoming character baud rate is within the
the BRG is reversed. Rather than the BRG clocking the range of the selected BRG clock source.
incoming RX signal, the RX signal is timing the BRG. In Some combinations of oscillator fre-
ABD mode, the internal Baud Rate Generator is used quency and EUSART baud rates are not
as a counter to time the bit period of the incoming serial possible due to bit error rates. Overall
byte stream. system timing and communication baud
rates must be taken into consideration
Once the ABDEN bit is set, the state machine will clear when using the Auto-Baud Rate
the BRG and look for a Start bit. The Auto-Baud Rate Detection feature.
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure- TABLE 15-4: BRG COUNTER
ment is taken over both a low and a high bit time in CLOCK RATES
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG BRG16 BRGH BRG Counter Clock
begins counting up, using the preselected clock source 0 0 FOSC/512
on the first rising edge of RX. After eight bits on the RX
0 1 FOSC/128
pin, or the fifth rising edge, an accumulated value
totalling the proper BRG period is left in the 1 0 FOSC/128
SPBRGH:SPBRG register pair. Once the 5th edge is 1 1 FOSC/32
seen (this should correspond to the Stop bit), the Note: During the ABD sequence, SPBRG and
ABDEN bit is automatically cleared. SPBRGH are both used as a 16-bit counter,
If a rollover of the BRG occurs (an overflow from FFFFh independent of the BRG16 setting.
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll- 15.1.3.1 ABD and EUSART Transmission
overs and can be set or cleared by the user in software. Since the BRG clock is reversed during ABD
ABD mode remains active after rollover events and the acquisition, the EUSART transmitter cannot be used
ABDEN bit remains set (Figure 15-2). during ABD. This means that whenever the ABDEN bit
While calibrating the baud rate period, the BRG is set, TXREG cannot be written to. Users should also
registers are clocked at 1/8th the preconfigured clock ensure that ABDEN does not become set during a
rate. Note that the BRG clock will be configured by the transmit sequence. Failing to do this may result in
BRG16 and BRGH bits. Independent of the BRG16 bit unpredictable EUSART operation.
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 15-4 for counter
clock rates to the BRG.

PIC18F2450/4450
FIGURE 15-1: AUTOMATIC BAUD RATE CALCULATION
BRG Value XXXXh 0000h 001Ch
Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto-Cleared

ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
SPBRG XXXXh 1Ch
SPBRGH XXXXh 00h
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 15-2: BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX pin Start bit 0
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h

PIC18F2450/4450
15.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is empty
The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can
clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt
EUSART uses the standard Non-Return-to-Zero (NRZ) enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
format (one Start bit, eight or nine data bits and one the state of TXIE; it cannot be cleared in software. TXIF
Stop bit). The most common data format is eight bits. is also not cleared immediately upon loading TXREG but
An on-chip dedicated 8-bit/16-bit Baud Rate Generator becomes valid in the second instruction cycle following
can be used to derive standard baud rate frequencies the load instruction. Polling TXIF immediately following a
from the oscillator. load of TXREG will return invalid results.
The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register,
EUSART’s transmitter and receiver are functionally another bit, TRMT (TXSTA<1>), shows the status of
independent but use the same data format and baud the TSR register. TRMT is a read-only bit which is set
rate. The Baud Rate Generator produces a clock, either when the TSR register is empty. No interrupt logic is
x16 or x64 of the bit shift rate depending on the BRGH tied to this bit so the user has to poll this bit in order to
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity determine if the TSR register is empty.
is not supported by the hardware but can be
implemented in software and stored as the ninth data bit. Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART memory so it is not available to the user.
module consists of the following important elements: 2: Flag bit TXIF is set when enable bit TXEN
• Baud Rate Generator is set.
• Sampling Circuit To set up an Asynchronous Transmission:
• Asynchronous Transmitter 1. Initialize the SPBRGH:SPBRG registers for the
• Asynchronous Receiver appropriate baud rate. Set or clear the BRGH
• Auto-Wake-up on Sync Break Character and BRG16 bits, as required, to achieve the
• 12-Bit Break Character Transmit desired baud rate.
• Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
15.2.1 EUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit TXIE.
TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit
The EUSART transmitter block diagram is shown in TX9. Can be used as address/data bit.
Figure 15-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit TXEN
(Serial) Shift Register (TSR). The Shift register obtains which will also set bit TXIF.
its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit
TXREG. The TXREG register is loaded with data in should be loaded in bit TX9D.
software. The TSR register is not loaded until the Stop 7. Load data to the TXREG register (starts
bit has been transmitted from the previous load. As transmission).
soon as the Stop bit is transmitted, the TSR is loaded
8. If using interrupts, ensure that the GIE and PEIE
with new data from the TXREG register (if available).
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 15-3: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIF TXREG Register

TXIE
8
MSb LSb
(8) • • • 0 Pin Buffer
and Control
TSR Register TX pin
Interrupt
TXEN Baud Rate CLK
TRMT SPEN
BRG16 SPBRGH SPBRG
TX9
Baud Rate Generator TX9D

PIC18F2450/4450
FIGURE 15-4: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(pin) Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
FIGURE 15-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX
(pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2

(Interrupt Reg. Flag)
1 TCY
Word 1 Word 2
TRMT bit Transmit Shift Reg. Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 15-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Reset
on page
TXREG EUSART Transmit Register 50
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

PIC18F2450/4450
15.2.2 EUSART ASYNCHRONOUS 15.2.3 SETTING UP 9-BIT MODE WITH
RECEIVER ADDRESS DETECT
The receiver block diagram is shown in Figure 15-6. This mode would typically be used in RS-485 systems.
The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address
recovery block. The data recovery block is actually a Detect Enable:
high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the
whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH
bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the
in RS-232 systems. desired baud rate.
To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing
1. Initialize the SPBRGH:SPBRG registers for the the SYNC bit and setting the SPEN bit.
appropriate baud rate. Set or clear the BRGH 3. If interrupts are required, set the RCEN bit and
and BRG16 bits, as required, to achieve the select the desired priority level with the RCIP bit.
desired baud rate. 4. Set the RX9 bit to enable 9-bit reception.
2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect.
bit SYNC and setting bit SPEN. 6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit RCIE. 7. The RCIF bit will be set when reception is
4. If 9-bit reception is desired, set bit RX9. complete. The interrupt will be Acknowledged if
5. Enable the reception by setting bit CREN. the RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is 8. Read the RCSTA register to determine if any
complete and an interrupt will be generated if error occurred during reception, as well as read
enable bit RCIE was set. bit 9 of data (if applicable).
7. Read the RCSTA register to get the ninth bit (if 9. Read RCREG to determine if the device is being
enabled) and determine if any error occurred addressed.
during reception. 10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the
RCREG register. ADDEN bit to allow all received data into the
9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU.
enable bit CREN.
set.
FIGURE 15-6: EUSART RECEIVE BLOCK DIAGRAM
CREN OERR FERR
x64 Baud Rate CLK

÷ 64 MSb RSR Register LSb
BRG16 SPBRGH SPBRG or
÷ 16
or Stop (8) 7 • • • 1 0 Start
Baud Rate Generator ÷4
RX9
Pin Buffer Data

and Control Recovery
RX RX9D RCREG Register
FIFO
SPEN
8
Interrupt RCIF Data Bus

RCIE

PIC18F2450/4450
FIGURE 15-7: ASYNCHRONOUS RECEPTION
Start Start Start
RX (pin) bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Reset
on page
RCREG EUSART Receive Register 50
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC18F2450/4450
15.2.4 AUTO-WAKE-UP ON SYNC BREAK Character and cause data or framing errors. To work
CHARACTER properly, therefore, the initial character in the
transmission must be all ‘0’s. This can be 00h (8 bytes)
During Sleep mode, all clocks to the EUSART are for standard RS-232 devices or 000h (12 bits) for LIN
suspended. Therefore, the Baud Rate Generator is bus.
inactive and proper byte reception cannot be
performed. The auto-wake-up feature allows the Oscillator start-up time must also be considered,
controller to wake-up due to activity on the RX/DT line especially in applications using oscillators with longer
while the EUSART is operating in Asynchronous mode. start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
The auto-wake-up feature is enabled by setting the sufficient length and be followed by a sufficient interval
WUE bit (BAUDCON<1>). Once set, the typical receive to allow enough time for the selected oscillator to start
sequence on RX/DT is disabled and the EUSART and provide proper initialization of the EUSART.
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event 15.2.4.2 Special Considerations Using
consists of a high-to-low transition on the RX/DT line. the WUE Bit
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.) The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
Following a wake-up event, the module generates an
received data. As noted, setting the WUE bit places the
RCIF interrupt. The interrupt is generated
EUSART in an Idle mode. The wake-up event causes
synchronously to the Q clocks in normal operating
a receive interrupt by setting the RCIF bit. The WUE bit
modes (Figure 15-8) and asynchronously if the device
is cleared after this when a rising edge is seen on RX/
is in Sleep mode (Figure 15-9). The interrupt condition
DT. The interrupt condition is then cleared by reading
is cleared by reading the RCREG register.
the RCREG register. Ordinarily, the data in RCREG will
The WUE bit is automatically cleared once a low-to-high be dummy data and should be discarded.
transition is observed on the RX line following the wake- The fact that the WUE bit has been cleared (or is still
up event. At this point, the EUSART module is in Idle set) and the RCIF flag is set should not be used as an
mode and returns to normal operation. This signals to indicator of the integrity of the data in RCREG. Users
the user that the Sync Break event is over. should consider implementing a parallel method in
firmware to verify received data integrity.
15.2.4.1 Special Considerations Using
To assure that no actual data is lost, check the RCIDL
Auto-Wake-up
bit to verify that a receive operation is not in process. If
Since auto-wake-up functions by sensing rising edge a receive operation is not occurring, the WUE bit may
transitions on RX/DT, information with any state then be set just prior to entering the Sleep mode.
changes before the Stop bit may signal a false End-of-
FIGURE 15-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit(1)
RX/DT Line
RCIF
Cleared due to user read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 15-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit(2)
RX/DT Line Note 1

RCIF
Cleared due to user read of RCREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC18F2450/4450
15.2.5 BREAK CHARACTER SEQUENCE 3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
The EUSART module has the capability of sending the
special Break character sequences that are required by 4. Write ‘55h’ to TXREG to load the Sync character
the LIN bus standard. The Break character transmit into the transmit FIFO buffer.
consists of a Start bit, followed by twelve ‘0’ bits and a 5. After the Break has been sent, the SENDB bit is
Stop bit. The Frame Break character is sent whenever reset by hardware. The Sync character now
the SENDB and TXEN bits (TXSTA<3> and transmits in the preconfigured mode.
TXSTA<5>) are set while the Transmit Shift Register is When the TXREG becomes empty, as indicated by the
loaded with data. Note that the value of data written to TXIF, the next data byte can be written to TXREG.
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after 15.2.6 RECEIVING A BREAK CHARACTER
the corresponding Stop bit is sent. This allows the user The Enhanced USART module can receive a Break
to preload the transmit FIFO with the next transmit byte character in two ways.
following the Break character (typically, the Sync
The first method forces configuration of the baud rate
character in the LIN specification).
at a frequency of 9/13 the typical speed. This allows for
Note that the data value written to the TXREG for the the Stop bit transition to be at the correct sampling
Break character is ignored. The write simply serves the location (13 bits for Break versus Start bit and eight
purpose of initiating the proper sequence. data bits for typical data).
The TRMT bit indicates when the transmit operation is The second method uses the auto-wake-up feature
active or Idle, just as it does during normal transmission. described in Section 15.2.4 “Auto-Wake-up on Sync
See Figure 15-10 for the timing of the Break character Break Character”. By enabling this feature, the
sequence. EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
15.2.5.1 Break and Sync Transmit Sequence followed by another interrupt.
The following sequence will send a message frame Note that following a Break character, the user will
header made up of a Break, followed by an Auto-Baud typically want to enable the Auto-Baud Rate Detect
Sync byte. This sequence is typical of a LIN bus master. feature. For both methods, the user can set the ABD bit
1. Configure the EUSART for the desired mode. once the TXIF interrupt is observed.
2. Set the TXEN and SENDB bits to set up the
Break character.
FIGURE 15-10: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)

PIC18F2450/4450
15.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR
Master Mode register (occurs in one TCYCLE), the TXREG register is
empty and the TXIF flag bit (PIR1<4>) is set. The
The Synchronous Master mode is entered by setting interrupt can be enabled or disabled by setting or
the CSRC bit (TXSTA<7>). In this mode, the data is clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF
transmitted in a half-duplex manner (i.e., transmission is set regardless of the state of enable bit TXIE; it
and reception do not occur at the same time). When cannot be cleared in software. It will reset only when
transmitting data, the reception is inhibited and vice new data is loaded into the TXREG register.
versa. Synchronous mode is entered by setting bit,
While flag bit, TXIF, indicates the status of the TXREG
SYNC (TXSTA<4>). In addition, enable bit, SPEN
register, another bit, TRMT (TXSTA<1>), shows the
(RCSTA<7>), is set in order to configure the TX and RX
status of the TSR register. TRMT is a read-only bit which
pins to CK (clock) and DT (data) lines, respectively.
is set when the TSR is empty. No interrupt logic is tied to
The Master mode indicates that the processor this bit so the user must poll this bit in order to determine
transmits the master clock on the CK line. Clock if the TSR register is empty. The TSR is not mapped in
polarity is selected with the SCKP bit (BAUDCON<4>). data memory so it is not available to the user.
Setting SCKP sets the Idle state on CK as high, while
To set up a Synchronous Master Transmission:
clearing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module. 1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
15.3.1 EUSART SYNCHRONOUS MASTER bit, as required, to achieve the desired baud
TRANSMISSION rate.
The EUSART transmitter block diagram is shown in 2. Enable the synchronous master serial port by
Figure 15-3. The heart of the transmitter is the Transmit setting bits SYNC, SPEN and CSRC.
(Serial) Shift Register (TSR). The Shift register obtains 3. If interrupts are desired, set enable bit TXIE.
its data from the Read/Write Transmit Buffer register, 4. If 9-bit transmission is desired, set bit TX9.
TXREG. The TXREG register is loaded with data in 5. Enable the transmission by setting bit TXEN.
software. The TSR register is not loaded until the last 6. If 9-bit transmission is selected, the ninth bit
bit has been transmitted from the previous load. As should be loaded in bit TX9D.
soon as the last bit is transmitted, the TSR is loaded
7. Start transmission by loading data to the TXREG
with new data from the TXREG (if available).
register.
set.
FIGURE 15-11: SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit ‘1’ ‘1’
Note: Sync Master mode (SPBRG = 0), continuous transmission of two 8-bit words.

PIC18F2450/4450
FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Reset
on page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

PIC18F2450/4450
15.3.2 EUSART SYNCHRONOUS MASTER 3. Ensure bits CREN and SREN are clear.
RECEPTION 4. If interrupts are desired, set enable bit RCIE.
Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit RX9.
enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit SREN.
SREN (RCSTA<5>), or the Continuous Receive For continuous reception, set bit CREN.
Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. Interrupt flag bit RCIF will be set when reception
RX pin on the falling edge of the clock. is complete and an interrupt will be generated if
If enable bit SREN is set, only a single word is received. the enable bit RCIE was set.
If enable bit CREN is set, the reception is continuous 8. Read the RCSTA register to get the ninth bit (if
until CREN is cleared. If both bits are set, then CREN enabled) and determine if any error occurred
takes precedence. during reception.
To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRGH:SPBRG registers for the
10. If any error occurred, clear the error by clearing
appropriate baud rate. Set or clear the BRG16
bit CREN.
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
set.
FIGURE 15-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Reset
on page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC18F2450/4450
15.4 EUSART Synchronous To set up a Synchronous Slave Transmission:
Slave Mode 1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
Synchronous Slave mode is entered by clearing bit,
CSRC.
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is 2. Clear bits CREN and SREN.
supplied externally at the CK pin (instead of being 3. If interrupts are desired, set enable bit TXIE.
supplied internally in Master mode). This allows the 4. If 9-bit transmission is desired, set bit TX9.
device to transfer or receive data while in any low-power 5. Enable the transmission by setting enable bit
mode. TXEN.
6. If 9-bit transmission is selected, the ninth bit
15.4.1 EUSART SYNCHRONOUS
should be loaded in bit TX9D.
SLAVE TRANSMIT
7. Start transmission by loading data to the TXREG
The operation of the Synchronous Master and Slave register.
modes is identical, except in the case of Sleep mode. 8. If using interrupts, ensure that the GIE and PEIE
If two words are written to the TXREG register and then bits in the INTCON register (INTCON<7:6>) are
the SLEEP instruction is executed, the following will occur: set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Reset
on page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F2450/4450
15.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception:
RECEPTION 1. Enable the synchronous master serial port by
The operation of the Synchronous Master and Slave setting bits SYNC and SPEN and clearing bit
modes is identical, except in the case of Sleep or any CSRC.
Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit RCIE.
Slave mode. 3. If 9-bit reception is desired, set bit RX9.
If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit CREN.
entering Sleep or any Idle mode, then a word may be 5. Flag bit RCIF will be set when reception is
received while in this low-power mode. Once the word complete. An interrupt will be generated if
is received, the RSR register will transfer the data to the enable bit RCIE was set.
RCREG register. If the RCIE enable bit is set, the 6. Read the RCSTA register to get the ninth bit (if
interrupt generated will wake the chip from the low- enabled) and determine if any error occurred
power mode. If the global interrupt is enabled, the during reception.
program will branch to the interrupt vector.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
set.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Reset
on page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC18F2450/4450
16.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register 16-1,
controls the operation of the A/D module. The
CONVERTER (A/D) MODULE
ADCON1 register, shown in Register 16-2, configures
The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register,
10 inputs for the 28-pin devices and 13 for the 40/44-pin shown in Register 16-3, configures the A/D clock
devices. This module allows conversion of an analog source, programmed acquisition time and justification.
input signal to a corresponding 10-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0

U0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:

bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F2450/4450
U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1)
— — VCFG0 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:

bit 5 VCFG0: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
AN7(2)
AN6(2)
AN5(2)
AN12
AN10
AN11
PCFG3:
AN9
AN8
AN4
AN3
AN2
AN1
AN0
PCFG0
0000(1) A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A
0010 A A A A A A A A A A A A A
0011 D A A A A A A A A A A A A
0100 D D A A A A A A A A A A A
0101 D D D A A A A A A A A A A
0110 D D D D A A A A A A A A A
0111(1) D D D D D A A A A A A A A
1000 D D D D D D A A A A A A A
1001 D D D D D D D A A A A A A
1010 D D D D D D D D A A A A A
1011 D D D D D D D D D A A A A
1100 D D D D D D D D D D A A A
1101 D D D D D D D D D D D A A
1110 D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D
A = Analog input D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN
Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.

PIC18F2450/4450
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F2450/4450
The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state.
either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any
(VDD and VSS) or the voltage level on the RA3/AN3/ conversion in progress is aborted.
VREF+ and RA2/AN2/VREF- pins. Each port pin associated with the A/D converter can be
The A/D converter has a unique feature of being able configured as an analog input or as a digital I/O. The
to operate while the device is in Sleep mode. To ADRESH and ADRESL registers contain the result of
operate in Sleep, the A/D conversion clock must be the A/D conversion. When the A/D conversion is com-
derived from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL
The output of the sample and hold is the input into the register pair, the GO/DONE bit (ADCON0 register) is
converter, which generates the result via successive cleared and A/D Interrupt Flag bit, ADIF, is set. The block
approximation. diagram of the A/D module is shown in Figure 16-1.
FIGURE 16-1: A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
(Input Voltage) 0011
10-Bit AN3
Converter
A/D 0010
AN2
0001
VCFG1:VCFG0 AN1
VDD(2) 0000
AN0
X0
VREF+ X1
Reference 1X
Voltage VREF- 0X
VSS(2)
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.

PIC18F2450/4450
The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either:
modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared
registers will contain unknown data after a Power-on
OR
Reset.
• Waiting for the A/D interrupt
After the A/D module has been configured as desired, the
selected channel must be acquired before the conver- 6. Read A/D Result registers (ADRESH:ADRESL);
sion is started. The analog input channels must have clear bit ADIF, if required.
their corresponding TRIS bits selected as an input. To 7. For next conversion, go to step 1 or step 2, as
determine acquisition time, see Section 16.1 “A/D required. The A/D conversion time per bit is
Acquisition Requirements”. After this acquisition time defined as TAD. A minimum wait of 3 TAD is
has elapsed, the A/D conversion can be started. An required before the next acquisition starts.
acquisition time can be programmed to occur between
setting the GO/DONE bit and the actual start of the FIGURE 16-2: A/D TRANSFER FUNCTION
conversion.
The following steps should be followed to perform an 3FFh
A/D conversion:
1. Configure the A/D module: 3FEh
Digital Code Output

• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2) 003h
• Select A/D conversion clock (ADCON2)

002h
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired): 001h
• Clear ADIF bit
• Set ADIE bit 000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
3 LSB
1022 LSB
1022.5 LSB
1023 LSB
1023.5 LSB
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0 register)
FIGURE 16-3: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
Rs
ANx RIC ≤ 1k SS RSS
VAIN CPIN ILEAKAGE

VT = 0.6V CHOLD = 25 pF
5 pF ±100 nA
VSS
Legend: CPIN = Input Capacitance

VT = Threshold Voltage 6V
ILEAKAGE = Leakage Current at the pin due to 5V
VDD 4V
various junctions 3V
RIC = Interconnect Resistance 2V
SS = Sampling Switch
CHOLD = Sample/hold Capacitance (from DAC) 1 2 3 4
RSS = Sampling Switch Resistance Sampling Switch (kΩ)

PIC18F2450/4450
16.1 A/D Acquisition Requirements To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The
the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D
to fully charge to the input channel voltage level. The to meet its specified resolution.
analog input model is shown in Figure 16-3. The
source impedance (RS) and the internal sampling Example 16-3 shows the calculation of the minimum
switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is
required to charge the capacitor CHOLD. The sampling based on the following application system
switch (RSS) impedance varies over the device voltage assumptions:
(VDD). The source impedance affects the offset voltage CHOLD = 25 pF
at the analog input (due to pin leakage current). The Rs = 2.5 kΩ
maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb
sources is 2.5 kΩ. After the analog input channel is VDD = 5V → RSS = 2 kΩ
selected (changed), the channel must be sampled for Temperature = 85°C (system max.)
at least the minimum acquisition time before starting a
conversion.
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 16-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
EQUATION 16-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 16-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ = TAMP + TC + TCOFF
TAMP = 0.2 μs
TCOFF = (Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ = 0.2 μs + 1 μs + 1.2 μs
2.4 μs

PIC18F2450/4450
16.2 Selecting and Configuring 16.3 Selecting the A/D Conversion
Acquisition Time Clock
The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The
acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion.
bit is set. It also gives users the option to use an The source of the A/D conversion clock is software
automatically determined acquisition time. selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0 • 2 TOSC
bits (ADCON2<5:3>) which provide a range of 2 to • 4 TOSC
20 TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC
continues to sample the input for the selected
• 16 TOSC
acquisition time, then automatically begins a
conversion. Since the acquisition time is programmed, • 32 TOSC
there may be no need to wait for an acquisition time • 64 TOSC
between selecting a channel and setting the GO/DONE • Internal RC Oscillator
bit.
For correct A/D conversions, the A/D conversion clock
Manual acquisition is selected when (TAD) must be as short as possible but greater than the
ACQT2:ACQT0 = 000. When the GO/DONE bit is set, minimum TAD (see parameter 130 in Table 21-18 for
sampling is stopped and a conversion begins. The user more information).
is responsible for ensuring the required acquisition time
Table 16-1 shows the resultant TAD times derived from
has passed between selecting the desired input
the device operating frequencies and the A/D clock
channel and setting the GO/DONE bit. This option is
source selected.
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS0 PIC18FXXXX PIC18LFXXXX(4)

2 TOSC 000 2.86 MHz 1.43 kHz
4 TOSC 100 5.71 MHz 2.86 MHz
8 TOSC 001 11.43 MHz 5.72 MHz
16 TOSC 101 22.86 MHz 11.43 MHz
32 TOSC 010 40.0 MHz 22.86 MHz
64 TOSC 110 40.0 MHz 22.86 MHz
RC(3) x11 1.00 MHz(1) 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 1.2 μs.
2: The RC source has a typical TAD time of 2.5 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power devices only.

PIC18F2450/4450
16.4 Operation in Power-Managed 16.5 Configuring Analog Port Pins
Modes The ADCON1, TRISA, TRISB and TRISE registers all
The selection of the automatic acquisition time and configure the A/D port pins. The port pins needed as
A/D conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits
source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital
mode. output level (VOH or VOL) will be converted.
If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the
a power-managed mode, the ACQT2:ACQT0 and CHS3:CHS0 bits and the TRIS bits.
ADCS2:ADCS0 bits in ADCON2 should be updated in Note 1: When reading the PORT register, all pins
accordance with the clock source to be used in that configured as analog input channels will
mode. After entering the mode, an A/D acquisition or read as cleared (a low level). Pins config-
conversion may be started. Once started, the device ured as digital inputs will convert as ana-
should continue to be clocked by the same clock log inputs. Analog levels on a digitally
source until the conversion has been completed. configured input will be accurately
If desired, the device may be placed into the converted.
corresponding Idle mode during the conversion. If the 2: Analog levels on any pin defined as a
device clock frequency is less than 1 MHz, the A/D RC digital input may cause the digital input
clock source should be selected. buffer to consume current out of the
Operation in the Sleep mode requires the A/D FRC device’s specification limits.
clock to be selected. If bits ACQT2:ACQT0 are set to 3: The PBADEN bit in Configuration
‘000’ and a conversion is started, the conversion will be Register 3H configures PORTB pins to
delayed one instruction cycle to allow execution of the reset as analog or digital pins by control-
SLEEP instruction and entry to Sleep mode. The IDLEN ling how the PCFG0 bits in ADCON1 are
bit (OSCCON<7>) must have already been cleared reset.
prior to starting the conversion.

PIC18F2450/4450
16.6 A/D Conversions After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
Figure 16-4 shows the operation of the A/D converter started. After this wait, acquisition on the selected
after the GO/DONE bit has been set and the channel is automatically started.
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into Note: The GO/DONE bit should NOT be set in
Sleep mode before the conversion begins. the same instruction that turns on the A/D.
Figure 16-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the 16.7 Discharge
ACQT2:ACQT0 bits are set to ‘010’ and selecting a The discharge phase is used to initialize the value of
4 TAD acquisition time before the conversion starts. the capacitor array. The array is discharged before
Clearing the GO/DONE bit during a conversion will every sample. This feature helps to optimize the unity-
abort the current conversion. The A/D Result register gain amplifier as the circuit always needs to charge the
pair will NOT be updated with the partially completed capacitor array, rather than charge/discharge based on
A/D conversion sample. This means the previous measurement values.
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 16-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts Discharge

Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit

On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 16-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQ Cycles TAD Cycles
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts Discharge
Time (Holding capacitor is disconnected)
Set GO/DONE bit

(Holding capacitor continues On the following cycle:
acquiring input) ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

PIC18F2450/4450
16.8 Use of the CCP1 Trigger (moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
An A/D conversion can be started by the Special Event and the minimum acquisition period is either timed by
Trigger of the CCP1 module. This requires that the the user, or an appropriate TACQ time selected before
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be the Special Event Trigger sets the GO/DONE bit (starts
programmed as ‘1011’ and that the A/D module is a conversion).
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition If the A/D module is not enabled (ADON is cleared), the
and conversion and the Timer1 counter will be reset to Special Event Trigger will be ignored by the A/D
zero. Timer1 is reset to automatically repeat the A/D module but will still reset the Timer1 counter.
acquisition period with minimal software overhead
TABLE 16-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset
on page
ADRESH A/D Result Register High Byte 50
ADRESL A/D Result Register Low Byte 50
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 50
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 50
PORTA — RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 51
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 51
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 51
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 51
PORTE — — — — RE3(1,3) RE2(4) RE1(4) RE0(4) 51
TRISE(4) — — — — — TRISE2(4) TRISE1(4) TRISE0(4) 51
(4)
LATE — — — — — LATE2(4) LATE1(4) LATE0(4) 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers and/or bits are not implemented on 28-pin devices.

PIC18F2450/4450
17.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register
(Register 17-1) completely controls the operation of the
(HLVD)
HLVD module. This allows the circuitry to be “turned
PIC18F2450/4450 devices have a High/Low-Voltage off” by the user under software control which minimizes
Detect module (HLVD). This is a programmable circuit the current consumption for the device.
that allows the user to specify both a device voltage trip The block diagram for the HLVD module is shown in
point and the direction of change from that point. If the Figure 17-1.
device experiences an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the
interrupt vector address and the software can then
respond to the interrupt.
REGISTER 17-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)
bit 7 bit 0
Legend:
bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage
trip point
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
trip point and the LVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1)
1111 = Reserved
1110 = Maximum setting
.
.
.
0000 = Minimum setting
Note 1: See Table 21-4 in Section 21.0 “Electrical Characteristics” for specifications.

PIC18F2450/4450
The module is enabled by setting the HLVDEN bit. event, depending on the configuration of the module.
Each time that the HLVD module is enabled, the When the supply voltage is equal to the trip point, the
circuitry requires some time to stabilize. The IRVST bit voltage tapped off of the resistor array is equal to the
is a read-only bit and is used to indicate when the circuit internal reference voltage generated by the voltage
is stable. The module can only generate an interrupt reference module. The comparator then generates an
after the circuit is stable and IRVST is set. interrupt signal by setting the HLVDIF bit.
The VDIRMAG bit determines the overall operation of The trip point voltage is software programmable to any
the module. When VDIRMAG is cleared, the module one of 16 values. The trip point is selected by
monitors for drops in VDD below a predetermined set programming the HLVDL3:HLVDL0 bits
point. When the bit is set, the module monitors for rises (HLVDCON<3:0>).
in VDD above the set point. The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
17.1 Operation external source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, the
When the HLVD module is enabled, a comparator uses
comparator input is multiplexed from the external input
an internally generated reference voltage as the set
pin, HLVDIN. This gives users flexibility because it
point. The set point is compared with the trip point,
allows them to configure the High/Low-Voltage Detect
where each node in the resistor divider represents a
interrupt to occur at any voltage in the valid operating
trip point voltage. The “trip point” voltage is the voltage
range.
level at which the device detects a high or low-voltage
FIGURE 17-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Externally Generated
Trip Point
VDD
VDD
HLVDL3:HLVDL0 HLVDCON
Register
HLVDEN VDIRMAG
HLVDIN
16-to-1 MUX
Set
HLVDIF
HLVDEN
Internal Voltage
Reference
BOREN 1.2V Typical

PIC18F2450/4450
17.2 HLVD Setup Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only
module: need to be enabled for short periods where the voltage
1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module
(HLVDCON<4>). may be disabled.
2. Write the value to the HLVDL3:HLVDL0 bits that
selects the desired HLVD trip point. 17.4 HLVD Start-up Time
3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module,
(VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter D420 (see
4. Enable the HLVD module by setting the Table 21-4 in Section 21.0 “Electrical Characteris-
HLVDEN bit. tics”), may be used by other internal circuitry, such as
5. Clear the HLVD Interrupt Flag, HLVDIF the Programmable Brown-out Reset. If the HLVD or
(PIR2<2>), which may have been set from a other circuits using the voltage reference are disabled to
previous interrupt. lower the device’s current consumption, the reference
6. Enable the HLVD interrupt, if interrupts are voltage circuit will require time to become stable before
desired, by setting the HLVDIE and GIE/GIEH a low or high-voltage condition can be reliably detected.
bits (PIE2<2> and INTCON<7>). An interrupt This start-up time, TIRVST, is an interval that is
will not be generated until the IRVST bit is set. independent of device clock speed. It is specified in
electrical specification parameter 36 (Table 21-10).
17.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may
and voltage divider are enabled and will consume static not be detected during this interval. Refer to Figure 17-2
current. The total current consumption, when enabled, or Figure 17-3.
is specified in electrical specification parameter D022
(Section 268 “DC Characteristics”).
FIGURE 17-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

CASE 1:
HLVDIF may not be set
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
IRVST TIRVST
Internal Reference is stable HLVDIF cleared in software
HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

PIC18F2450/4450
FIGURE 17-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be set
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST

CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists
17.5 Applications FIGURE 17-4: TYPICAL

HIGH/LOW-VOLTAGE
In many applications, the ability to detect a drop below
DETECT APPLICATION
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example, VA
3.3V to 5V (the voltage on USB) and vice versa for a VB
detach. This feature could save a design a few extra
Voltage
components and an attach signal (input pin).

For general battery applications, Figure 17-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “house- TA TB
Time
keeping tasks” and perform a controlled shutdown
before the device voltage exits the valid operating Legend: VA = HLVD trip point
range at TB. The HLVD, thus, would give the applica- VB = Minimum valid device
tion a time window, represented by the difference operating voltage
between TA and TB, to safely exit.

PIC18F2450/4450
17.6 Operation During Sleep 17.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state.
during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off.
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
TABLE 17-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Reset
on page
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
18.0 SPECIAL FEATURES OF THE In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2450/4450 devices
CPU have a Watchdog Timer, which is either permanently
PIC18F2450/4450 devices include several features enabled via the Configuration bits or software controlled
intended to maximize reliability and minimize cost (if configured as disabled).
through elimination of external components. These are: The inclusion of an internal RC oscillator also provides
• Oscillator Selection the additional benefits of a Fail-Safe Clock Monitor
• Resets: (FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
- Power-on Reset (POR)
automatic switchover in the event of its failure. Two-
- Power-up Timer (PWRT) Speed Start-up enables code to be executed almost
- Oscillator Start-up Timer (OST) immediately on start-up, while the primary clock source
- Brown-out Reset (BOR) completes its start-up delays.
• Interrupts All of these features are enabled and configured by
• Watchdog Timer (WDT) setting the appropriate Configuration register bits.
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.

PIC18F2450/4450
18.1 Configuration Bits Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
The Configuration bits can be programmed (read as WR bit in the EECON1 register starts a self-timed write
‘0’) or left unprogrammed (read as ‘1’) to select various to the Configuration register. In normal operation mode,
device configurations. These bits are mapped starting a TBLWT instruction, with the TBLPTR pointing to the
at program memory location 300000h. Configuration register, sets up the address and the
The user will note that address 300000h is beyond the data for the Configuration register write. Setting the WR
user program memory space. In fact, it belongs to the bit starts a long write to the Configuration register. The
configuration memory space (300000h-3FFFFFh), which Configuration registers are written a byte at a time. To
can only be accessed using table reads and table writes. write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDs

Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value
300000h CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L — — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN — 1--- -01-
300006h CONFIG4L DEBUG XINST ICPRT(2) — BBSIZ LVP — STVREN 100- 01-1
300008h CONFIG5L — — — — — — CP1 CP0 ---- --11
300009h CONFIG5H — CPB — — — — — — -1-- ----
30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11
30000Bh CONFIG6H — WRTB WRTC — — — — — -11- ----
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010(1)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed
by the user.
2: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.

PIC18F2450/4450
REGISTER 18-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-1 R/P-1 R/P-1
— — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 5 USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the primary oscillator block with no postscale
bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits
For XT, HS, EC and ECIO Oscillator modes:
11 = Primary oscillator divided by 4 to derive system clock
00 = Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11 = 96 MHz PLL divided by 6 to derive system clock
bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits
111 = Divide by 12 (48 MHz oscillator input)
000 = No prescale (4 MHz oscillator input drives PLL directly)

PIC18F2450/4450
REGISTER 18-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1
IESO FCMEN — — FOSC3(1) FOSC2(1) FOSC1(1) FOSC0(1)
bit 7 bit 0
Legend:
bit 7 IESO: Internal/External Oscillator Switchover bit

1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 3-0 FOSC3:FOSC0: Oscillator Selection bits(1)
111x = HS oscillator, PLL enabled (HSPLL)
110x = HS oscillator (HS)
1011 = Internal oscillator, HS oscillator used by USB (INTHS)
1010 = Internal oscillator, XT used by USB (INTXT)
1001 = Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO)
0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
0110 = EC oscillator, PLL enabled, port function on RA6 (ECPIO)
0101 = EC oscillator, CLKO function on RA6 (EC)
0100 = EC oscillator, port function on RA6 (ECIO)
001x = XT oscillator, PLL enabled (XTPLL)
000x = XT oscillator (XT)
Note 1: The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and
EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the
microcontroller uses the internal oscillator.

PIC18F2450/4450

U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
(1) (1) (2) (2)
— — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN(2)
bit 7 bit 0
Legend:

bit 5 VREGEN: USB Internal Voltage Regulator Enable bit
1 = USB voltage regulator enabled
0 = USB voltage regulator disabled
bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1)
11 = Minimum setting
.
.
.
00 = Maximum setting
bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2)
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset disabled in hardware and software
bit 0 PWRTEN: Power-up Timer Enable bit(2)
1 = PWRT disabled
0 = PWRT enabled
Note 1: See Section 21.0 “Electrical Characteristics” for the specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.

PIC18F2450/4450
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
Legend:

bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)

PIC18F2450/4450
R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 U-0
MCLRE — — — — LPT1OSC PBADEN —
bit 7 bit 0
Legend:
bit 7 MCLRE: MCLR Pin Enable bit

1 = MCLR pin enabled, RA5 input pin disabled
0 = RA5 input pin enabled, MCLR pin disabled
bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
bit 1 PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset

PIC18F2450/4450
R/P-1 R/P-0 R/P-0 U-0 R/P-0 R/P-1 U-0 R/P-1
(1)
DEBUG XINST ICPRT — BBSIZ LVP — STVREN
bit 7 bit 0
Legend:
bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5 ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)
1 = ICPORT enabled
0 = ICPORT disabled
bit 3 BBSIZ: Boot Block Size Select bit
1 = 2 kW Boot Block size
0 = 1 kW Boot Block size
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other
devices.

PIC18F2450/4450
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — CP1 CP0
bit 7 bit 0
Legend:

bit 1 CP1: Code Protection bit
1 = Block 1 (002000-003FFFh) is not code-protected
0 = Block 1 (002000-003FFFh) is code-protected
bit 0 CP0: Code Protection bit
1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not code-protected
0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is code-protected

U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
— CPB — — — — — —
bit 7 bit 0
Legend:

bit 6 CPB: Boot Block Code Protection bit
1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not code-protected
0 = Boot block (000000-0007FFh) or (000000-000FFFh) is code-protected

PIC18F2450/4450
REGISTER 18-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — WRT1 WRT0
bit 7 bit 0
Legend:

bit 1 WRT1: Write Protection bit
1 = Block 1 (002000-003FFFh) is not write-protected
0 = Block 1 (002000-003FFFh) is write-protected
bit 0 WRT0: Write Protection bit
1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected
0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected
REGISTER 18-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)

U-0 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0
— WRTB WRTC(1) — — — — —
bit 7 bit 0
Legend:

bit 6 WRTB: Boot Block Write Protection bit
1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not write-protected
0 = Boot block (000000-0007FFh) or (000000-000FFFh) is write-protected
bit 5 WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers (300000-3000FFh) are not write-protected
0 = Configuration registers (300000-3000FFh) are write-protected
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

PIC18F2450/4450
REGISTER 18-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — EBTR1 EBTR0
bit 7 bit 0
Legend:

bit 1 EBTR1: Table Read Protection bit
1 = Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) is protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit
1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not protected from table reads executed in
other blocks
0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is protected from table reads executed in other
blocks
REGISTER 18-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)

U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
— EBTRB — — — — — —
bit 7 bit 0
Legend:

bit 6 EBTRB: Boot Block Table Read Protection bit
1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not protected from table reads executed
in other blocks
0 = Boot block (000000-0007FFh) or (000000-000FFFh) is protected from table reads executed in
other blocks

PIC18F2450/4450
REGISTER 18-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2450/4450 DEVICES
R R R R R R R R
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
bit 7-5 DEV2:DEV0: Device ID bits

001 = PIC18F2450
000 = PIC18F4450
bit 4-0 REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 18-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2450/4450 DEVICES

R R R R R R R R
DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
bit 7-0 DEV10:DEV3: Device ID bits(1)

These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify the part number.
0010 0100 = PIC18F2450/4450 devices
Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.

PIC18F2450/4450
18.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions
For PIC18F2450/4450 devices, the WDT is driven by clear the WDT and postscaler counts
the INTRC source. When the WDT is enabled, the when executed.
clock source is also enabled. The nominal WDT period 2: When a CLRWDT instruction is executed,
is 4 ms and has the same stability as the INTRC the postscaler count will be cleared.
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit 18.2.1 CONTROL REGISTER
postscaler. Any output of the WDT postscaler is
Register 18-15 shows the WDTCON register. This is a
selected by a multiplexer, controlled by bits in
readable and writable register which contains a control
Configuration Register 2H. Available periods range
bit that allows software to override the WDT enable
from 4 ms to 131.072 seconds (2.18 minutes). The
Configuration bit, but only if the Configuration bit has
WDT and postscaler are cleared when any of the
disabled the WDT.
following events occur: a SLEEP or CLRWDT instruction
is executed or a clock failure has occurred.
.
FIGURE 18-1: WDT BLOCK DIAGRAM
SWDTEN Enable WDT

INTRC Control
WDTEN
WDT Counter
INTRC Source ÷128 Wake-up from

Power-Managed
Modes
CLRWDT Programmable Postscaler Reset WDT

All Device Resets Reset
1:1 to 1:32,768
WDT
4
WDTPS<3:0>
SLEEP

PIC18F2450/4450
REGISTER 18-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SWDTEN(1)
bit 7 bit 0
Legend:

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 18-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Reset
on page

WDTCON — — — — — — — SWDTEN 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

PIC18F2450/4450
18.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
The Two-Speed Start-up feature helps to minimize the selected clock source until the primary clock source
latency period, from oscillator start-up to code becomes available. The setting of the IESO bit is
execution, by allowing the microcontroller to use the ignored.
INTRC oscillator as a clock source until the primary
clock source is available. It is enabled by setting the 18.3.1 SPECIAL CONSIDERATIONS FOR
IESO Configuration bit. USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the While using the INTRC oscillator in Two-Speed Start-up,
primary oscillator mode is XT, HS, XTPLL or HSPLL the device still obeys the normal command sequences
(Crystal-based modes). Other sources do not require for entering power-managed modes, including serial
an OST start-up delay; for these, Two-Speed Start-up SLEEP instructions (refer to Section 3.1.4 “Multiple
should be disabled. Sleep Commands”). In practice, this means that user
When enabled, Resets and wake-ups from Sleep mode code can change the SCS1:SCS0 bit settings or issue
cause the device to configure itself to run from the SLEEP instructions before the OST times out. This would
internal oscillator as the clock source, following the allow an application to briefly wake-up, perform routine
time-out of the Power-up Timer after a Power-on Reset “housekeeping” tasks and return to Sleep before the
is enabled. This allows almost immediate code device starts to operate from the primary oscillator.
execution while the primary oscillator starts and the User code can also check if the primary clock source is
OST is running. Once the OST times out, the device currently providing the device clocking by checking the
automatically switches to PRI_RUN mode. status of the OSTS bit (OSCCON<3>). If the bit is set,
Because the OSCCON register is cleared on Reset the primary oscillator is providing the clock. Otherwise,
events, the INTRC clock is used directly at its base the internal oscillator is providing the clock during
frequency. wake-up from Reset or Sleep mode.
FIGURE 18-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake from Interrupt Event OSTS bit Set

PIC18F2450/4450
18.4 Fail-Safe Clock Monitor The FSCM will detect failures of the primary or
secondary clock sources only. If the internal oscillator
The Fail-Safe Clock Monitor (FSCM) allows the fails, no failure would be detected, nor would any action
microcontroller to continue operation in the event of an be possible.
external oscillator failure by automatically switching the
device clock to the internal oscillator. The FSCM function 18.4.1 FSCM AND THE WATCHDOG TIMER
is enabled by setting the FCMEN Configuration bit.
Both the FSCM and the WDT are clocked by the
When FSCM is enabled, the INTRC oscillator runs at all INTRC oscillator. Since the WDT operates with a
times to monitor clocks to peripherals and provide a separate divider and counter, disabling the WDT has
backup clock in the event of a clock failure. Clock no effect on the operation of the INTRC oscillator when
monitoring (shown in Figure 18-3) is accomplished by the FSCM is enabled.
creating a sample clock signal, which is the INTRC output
If the WDT is enabled with a small prescale value, a
divided by 64. This allows ample time between FSCM
decrease in clock speed allows a WDT time-out to
sample clocks for a peripheral clock edge to occur. The
occur and a subsequent device Reset. For this reason,
peripheral device clock and the sample clock are
Fail-Safe Clock Monitor events also reset the WDT and
presented as inputs to the Clock Monitor latch (CM). The
postscaler, allowing it to start timing from when execu-
CM is set on the falling edge of the device clock source,
tion speed was changed and decreasing the likelihood
but cleared on the rising edge of the sample clock.
of an erroneous time-out.
FIGURE 18-3: FSCM BLOCK DIAGRAM 18.4.2 EXITING FAIL-SAFE OPERATION
Clock Monitor The fail-safe condition is terminated by either a device
Latch (CM)
(edge-triggered) Reset or by entering a power-managed mode. On
Peripheral
S Q
Reset, the controller starts the primary clock source
Clock specified in Configuration Register 1H (with any start-
up delays that are required for the oscillator mode,
INTRC
÷ 64 C Q such as OST or PLL timer). The INTRC provides the
Source
device clock until the primary clock source becomes
(32 μs) 488 Hz ready (similar to a Two-Speed Start-up). The clock
(2.048 ms) source is then switched to the primary clock (indicated
Clock
Failure by the OSTS bit in the OSCCON register becoming
Detected set). The Fail-Safe Clock Monitor then resumes
monitoring the peripheral clock.
Clock failure is tested for on the falling edge of the The primary clock source may never become ready
sample clock. If a sample clock falling edge occurs during start-up. In this case, operation is clocked by the
while CM is still set, a clock failure has been detected INTRC. The OSCCON register will remain in its Reset
(Figure 18-4). This causes the following: state until a power-managed mode is entered.
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator (OSCCON is not updated to show the cur-
rent clock source – this is the fail-safe condition); and
• the WDT is reset.

PIC18F2450/4450
FIGURE 18-4: FSCM TIMING DIAGRAM
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test CM Test CM Test

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
18.4.3 FSCM INTERRUPTS IN considerably longer than the FCSM sample clock time,
POWER-MANAGED MODES a false clock failure may be detected. To prevent this,
the internal oscillator is automatically configured as the
By entering a power-managed mode, the clock multi-
device clock and functions until the primary clock is
plexer selects the clock source selected by the OSCCON
stable (the OST and PLL timers have timed out). This
register. Fail-Safe Clock Monitoring of the power-
is identical to Two-Speed Start-up mode. Once the
managed clock source resumes in the power-managed
primary clock is stable, the INTRC returns to its role as
mode.
the FSCM source.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether Note: The same logic that prevents false oscilla-
or not the oscillator failure interrupt is enabled. If tor failure interrupts on POR or wake from
enabled (OSCFIF = 1), code execution will be clocked Sleep will also prevent the detection of the
by the INTRC. An automatic transition back to the failed oscillator’s failure to start at all following
clock source will not occur. these events. This can be avoided by
monitoring the OSTS bit and using a
If the interrupt is disabled, subsequent interrupts while timing routine to determine if the oscillator
in Idle mode will cause the CPU to begin executing is taking too long to start. Even so, no
instructions while being clocked by the INTRC source. oscillator failure interrupt will be flagged.
18.4.4 POR OR WAKE-UP FROM SLEEP As noted in Section 18.3.1 “Special Considerations
The FSCM is designed to detect oscillator failure at any for Using Two-Speed Start-up”, it is also possible to
point after the device has exited Power-on Reset select another clock configuration and enter an alternate
(POR) or Low-Power Sleep mode. When the primary power-managed mode while waiting for the primary
device clock is either EC or INTRC, monitoring can clock to become stable. When the new power-managed
begin immediately following these events. mode is selected, the primary clock is disabled.
For oscillator modes involving a crystal or resonator
(HS, HSPLL or XT), the situation is somewhat different.
Since the oscillator may require a start-up time

PIC18F2450/4450
18.5 Program Verification and Each of the three blocks has three code protection bits
Code Protection associated with them. They are:
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other • Write-Protect bit (WRTn)
PICmicro® devices. • External Block Table Read bit (EBTRn)
The user program memory is divided into three blocks. Figure 18-5 shows the program memory organization
One of these is a boot block of 1 or 2 Kbytes. The for 24 and 32-Kbyte devices and the specific code
remainder of the memory is divided into two blocks on protection bit associated with each block. The actual
binary boundaries. locations of the bits are summarized in Table 18-3.
FIGURE 18-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
MEMORY SIZE/DEVICE
Block Code Protection
16 Kbytes Address Controlled By:
(PIC18F2450/4450) Range
000000h
Boot Block 0007FFh CPB, WRTB, EBTRB
000FFFh
001000h
Block 0 CP0, WRT0, EBTR0
001FFFh
002000h
Block 1 CP1, WRT1, EBTR1
003FFFh
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s (Unimplemented Memory Space)
1FFFFFh
TABLE 18-3: SUMMARY OF CODE PROTECTION REGISTERS

300008h CONFIG5L — — — — — — CP1 CP0
300009h CONFIG5H — CPB — — — — — —
30000Ah CONFIG6L — — — — — — WRT1 WRT0
30000Bh CONFIG6H — WRTB WRTC — — — — —
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.

PIC18F2450/4450
18.5.1 PROGRAM MEMORY A table read instruction that executes from a location
CODE PROTECTION outside of that block is not allowed to read and will
result in reading ‘0’s. Figures207 through208 illustrate
The program memory may be read to or written from
table write and table read protection.
any location using the table read and table write
instructions. The device ID may be read with table Note: Code protection bits may only be written to
reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to
written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code
In normal execution mode, the CPn bits have no direct protection bits are only set to ‘1’ by a full
effect. CPn bits inhibit external reads and writes. A Chip Erase or Block Erase function. The
block of user memory may be protected from table full Chip Erase and Block Erase functions
writes if the WRTn Configuration bit is ‘0’. The EBTRn can only be initiated via ICSP operation or
bits control table reads. For a block of user memory an external programmer.
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 18-6: TABLE WRITE (WRTn) DISALLOWED
Register Values Program Memory Configuration Bit Settings

000000h
0007FFh WRTB, EBTRB = 11
000FFFh
001000h
TBLPTR = 0008FFh WRT0, EBTR0 = 01
PC = 001FFEh TBLWT* 001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
Results: All table writes disabled to Blockn whenever WRTn = 0.

PIC18F2450/4450
FIGURE 18-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

000000h
000FFFh
001000h
TBLPTR = 0008FFh WRT0, EBTR0 = 10

001FFFh
002000h
WRT1, EBTR1 = 11
PC = 003FFEh TBLRD*
003FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 18-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

000000h
000FFFh
TBLPTR = 0008FFh 001000h
WRT0, EBTR0 = 10
PC = 001FFEh TBLRD* 001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

PIC18F2450/4450
18.5.2 CONFIGURATION REGISTER To use the In-Circuit Debugger function of the
PROTECTION microcontroller, the design must implement In-Circuit
Serial Programming connections to MCLR/VPP/RE3,
The Configuration registers can be write-protected.
VDD, VSS, RB7 and RB6. This will interface to the
The WRTC bit controls protection of the Configuration
In-Circuit Debugger module available from Microchip
registers. In normal execution mode, the WRTC bit is
or one of the third party development tool companies.
readable only. WRTC can only be written via ICSP
operation or an external programmer.
18.9 Special ICPORT Features
18.6 ID Locations (Designated Packages Only)
Eight memory locations (200000h-200007h) are Under specific circumstances, the No Connect (NC)
designated as ID locations, where the user can store pins of PIC18F4450 devices in 44-pin TQFP packages
checksum or other code identification numbers. These can provide additional functionality. These features are
locations are both readable and writable during normal controlled by device Configuration bits and are
execution through the TBLRD and TBLWT instructions available only in this package type and pin count.
or during program/verify. The ID locations can be read
18.9.1 DEDICATED ICD/ICSP PORT
when the device is code-protected.
The 44-pin TQFP devices can use NC pins to provide an
18.7 In-Circuit Serial Programming alternate port for In-Circuit Debugging (ICD) and In-
Circuit Serial Programming (ICSP). These pins are
PIC18F2450/4450 microcontrollers can be serially collectively known as the dedicated ICSP/ICD port, since
programmed while in the end application circuit. This is they are not shared with any other function of the device.
simply done with two lines for clock and data and three
When implemented, the dedicated port activates three
other lines for power, ground and the programming
NC pins to provide an alternate device Reset, data and
voltage. This allows customers to manufacture boards
clock ports. None of these ports overlap with standard
with unprogrammed devices and then program the
I/O pins, making the I/O pins available to the user’s
microcontroller just before shipping the product. This
application.
also allows the most recent firmware or a custom
firmware to be programmed. The dedicated ICSP/ICD port is enabled by setting the
ICPRT Configuration bit. The port functions the same
18.8 In-Circuit Debugger way as the legacy ICSP/ICD port on RB6/RB7.
Table 18-5 identifies the functionally equivalent pins for
When the DEBUG Configuration bit is programmed to ICSP and ICD purposes.
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when TABLE 18-5: EQUIVALENT PINS FOR
used with MPLAB® IDE. When the microcontroller has LEGACY AND DEDICATED
this feature enabled, some resources are not available ICD/ICSP™ PORTS
for general use. Table 18-4 shows which resources are
Pin Name
required by the background debugger. Pin
Legacy Dedicated Pin Function
Type
TABLE 18-4: DEBUGGER RESOURCES Port Port
I/O pins: RB6, RB7 MCLR/VPP/ NC/ICRST/ P Device Reset and
Stack: 2 levels RE3 ICVPP Programming
Program Memory: 512 bytes Enable
RB6/KBI2/ NC/ICCK/ I Serial Clock
Data Memory: 10 bytes
PGC ICPGC
RB7/KBI3/ NC/ICDT/ I/O Serial Data
PGD ICPGD
Legend: I = Input, O = Output, P = Power

PIC18F2450/4450
Even when the dedicated port is enabled, the ICSP and Note 1: High-Voltage Programming is always
ICD functions remain available through the legacy port. available, regardless of the state of the
When VIH is seen on the MCLR/VPP/RE3 pin, the state LVP bit, by applying VIHH to the MCLR pin.
of the ICRST/ICVPP pin is ignored.
2: While in Low-Voltage ICSP Programming
Note 1: The ICPRT Configuration bit can only be mode, the RB5 pin can no longer be used
programmed through the default ICSP as a general purpose I/O pin and should
port. be held low during normal operation.
2: The ICPRT Configuration bit must be 3: When using Low-Voltage ICSP Program-
maintained clear for all 28-pin and 40-pin ming (LVP) and the pull-ups on PORTB
devices; otherwise, unexpected operation are enabled, bit 5 in the TRISB register
may occur. must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
18.9.2 28-PIN EMULATION the device.
PIC18F4450 devices in 44-pin TQFP packages also 4: If the device Master Clear is disabled,
have the ability to change their configuration under verify that either of the following is done to
external control for debugging purposes. This allows ensure proper entry into ICSP mode:
the device to behave as if it were a PIC18F2455/2550
a) disable Low-Voltage Programming
28-pin device.
(CONFIG4L<2> = 0); or
This 28-pin Configuration mode is controlled through a b) make certain that RB5/KBI1/PGM
single pin, NC/ICPORTS. Connecting this pin to VSS is held low during entry into ICSP.
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin If Single-Supply ICSP Programming mode will not be
devices are disabled, along with their corresponding used, the LVP bit can be cleared. RB5/KBI1/PGM then
control registers and bits. On the other hand, becomes available as the digital I/O pin, RB5. The LVP
connecting the pin to VDD forces the device to function bit may be set or cleared only when using standard
in its default configuration. high-voltage programming (VIHH applied to the MCLR/
The configuration option is only available when VPP/RE3 pin). Once LVP has been disabled, only the
background debugging and the dedicated ICD/ICSP standard high-voltage programming is available and
port are both enabled (DEBUG Configuration bit is must be used to program the device.
clear and ICPRT Configuration bit is set). When Memory that is not code-protected can be erased using
disabled, NC/ICPORTS is a No Connect pin. either a Block Erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
18.10 Single-Supply ICSP Programming erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
The LVP Configuration bit enables Single-Supply the device must be supplied with VDD of 4.5V to 5.5V.
ICSP Programming (formerly known as Low-Voltage
ICSP Programming or LVP). When Single-Supply
Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/
PGM pin is then dedicated to controlling Program
mode entry and is not available as a general purpose
I/O pin.
While programming using Single-Supply Program-
ming, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.

PIC18F2450/4450
19.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following
operands:
PIC18F2450/4450 devices incorporate the standard
• A literal value to be loaded into a file register
set of 75 PIC18 core instructions, as well as an
(specified by ‘k’)
extended set of eight new instructions for the
optimization of code that is recursive or that utilizes a • The desired FSR register to load the literal value
software stack. The extended set is discussed later in into (specified by ‘f’)
this section. • No operand required
(specified by ‘—’)
19.1 Standard Instruction Set The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro instruction • A program memory address (specified by ‘n’)
sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions
PICmicro instruction sets. Most instructions are a (specified by ‘s’)
single program memory word (16 bits) but there are • The mode of the table read and table write
four instructions that require two program memory instructions (specified by ‘m’)
locations. • No operand required
Each single-word instruction is a 16-bit word divided (specified by ‘—’)
into an opcode, which specifies the instruction type and All instructions are a single word, except for four
one or more operands, which further specify the double-word instructions. These instructions were
operation of the instruction. made double-word to contain the required information
The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
into four basic categories: this second word is executed as an instruction (by
• Byte-oriented operations itself), it will execute as a NOP.
• Bit-oriented operations All single-word instructions are executed in a single
• Literal operations instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
• Control operations
tion. In these cases, the execution takes two instruction
The PIC18 instruction set summary in Table 19-2 lists cycles with the additional instruction cycle(s) executed
byte-oriented, bit-oriented, literal and control as a NOP.
operations. Table 19-1 shows the opcode field
The double-word instructions execute in two instruction
descriptions.
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4 MHz, the normal
2. The destination of the result (specified by ‘d’) instruction execution time is 1 μs. If a conditional test is
3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
The file register designator ‘f’ specifies which file Two-word branch instructions (if true) would take 3 μs.
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the Figure 19-1 shows the general formats that the
operation is to be placed. If ‘d’ is zero, the result is instructions can have. All examples use the convention
placed in the WREG register. If ‘d’ is one, the result is ‘nnh’ to represent a hexadecimal number.
placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table 19-2,
All bit-oriented instructions have three operands: lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
1. The file register (specified by ‘f’)
Section 19.1.1 “Standard Instruction Set” provides
2. The bit in the file register (specified by ‘b’)
a description of each instruction.
3. The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.

PIC18F2450/4450
TABLE 19-1: OPCODE FIELD DESCRIPTIONS
Field Description
a RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs 12-bit register file address (000h to FFFh). This is the source address.
fd 12-bit register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-Down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a program memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for indirect addressing of register files (source).
zd 7-bit offset value for indirect addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
→ Assigned to.
< > Register bit field.
∈ In the set of.
italics User-defined term (font is Courier).

PIC18F2450/4450
FIGURE 19-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations Example Instruction
15 10 9 8 7 0
OPCODE d a f (FILE #) ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)

15 12 11 0
OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2
15 12 11 0
1111 f (Destination FILE #)
Bit-oriented file register operations

15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank
a = 1 for BSR to select bank
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
n = 20-bit immediate value
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC

PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
borrow
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
assigned.

PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
assigned.

PIC18F2450/4450
19.1.1 STANDARD INSTRUCTION SET
ADDLW ADD Literal to W ADDWF ADD W to f
Syntax: ADDLW k Syntax: ADDWF f {,d {,a}}

Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
Operation: (W) + k → W
a ∈ [0,1]
Status Affected: N, OV, C, DC, Z
Operation: (W) + (f) → dest
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
Encoding: 0010 01da ffff ffff
8-bit literal ‘k’ and the result is placed in
W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
Words: 1 result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
Cycles: 1 (default).
Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode Read Process Write to W
If ‘a’ is ‘0’ and the extended instruction
literal ‘k’ Data
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Example: ADDLW 15h
Section 19.2.3 “Byte-Oriented and
Before Instruction Bit-Oriented Instructions in Indexed
W = 10h Literal Offset Mode” for details.
After Instruction
Words: 1
W = 25h
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination
Example: ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

PIC18F2450/4450
ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W
Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k

Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255
d ∈ [0,1] Operation: (W) .AND. k → W
a ∈ [0,1]
Status Affected: N, Z
Operation: (W) + (f) + (C) → dest
Description: The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Description: Add W, the Carry flag and data memory
Words: 1
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is Cycles: 1
placed in data memory location ‘f’. Q Cycle Activity:
If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). Decode Read literal Process Write to W
If ‘a’ is ‘0’ and the extended instruction ‘k’ Data
in Indexed Literal Offset Addressing Example: ANDLW 05Fh
Before Instruction
W = A3h
Bit-Oriented Instructions in Indexed
After Instruction
Literal Offset Mode” for details.
W = 03h
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: ADDWFC REG, 0, 1

Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h

PIC18F2450/4450
ANDWF AND W with f BC Branch if Carry
Syntax: ANDWF f {,d {,a}} Syntax: BC n

Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127
d ∈ [0,1] Operation: if Carry bit is ‘1’
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: (W) .AND. (f) → dest
Status Affected: None
Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ‘1’, then the program
Description: The contents of W are ANDed with will branch.
register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is
in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have
in register ‘f’ (default). incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be
If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a
GPR bank (default). two-cycle instruction.
Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f ≤ 95 (5Fh). See Q Cycle Activity:
Section 19.2.3 “Byte-Oriented and If Jump:
Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC
Words: 1 ‘n’ Data
Cycles: 1 No No No No
operation operation operation operation
Q Cycle Activity:
Q1 Q2 Q3 Q4 If No Jump:
Decode Read Process Write to Q1 Q2 Q3 Q4

register ‘f’ Data destination Decode Read literal Process No
‘n’ Data operation
Example: ANDWF REG, 0, 0

Example: HERE BC 5
Before Instruction
W = 17h Before Instruction
REG = C2h PC = address (HERE)
After Instruction After Instruction
W = 02h If Carry = 1;
REG = C2h PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)

PIC18F2450/4450
BCF Bit Clear f BN Branch if Negative
Syntax: BCF f, b {,a} Syntax: BN n

0≤b≤7 Operation: if Negative bit is ‘1’
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: 0 → f
Status Affected: None Encoding: 1110 0110 nnnn nnnn
Encoding: 1001 bbba ffff ffff
Description: If the Negative bit is ‘1’, then the
Description: Bit ‘b’ in register ‘f’ is cleared. program will branch.
If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is
If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have
GPR bank (default). incremented to fetch the next
If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be
set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a
in Indexed Literal Offset Addressing two-cycle instruction.
Words: 1
Bit-Oriented Instructions in Indexed Cycles: 1(2)
Literal Offset Mode” for details. Q Cycle Activity:
Words: 1 If Jump:
Q1 Q2 Q3 Q4
Cycles: 1
Q Cycle Activity:
‘n’ Data
Q1 Q2 Q3 Q4
No No No No
Decode Read Process Write operation operation operation operation
register ‘f’ Data register ‘f’ If No Jump:
Q1 Q2 Q3 Q4
Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No
Before Instruction ‘n’ Data operation
FLAG_REG = C7h
After Instruction
Example: HERE BN Jump
FLAG_REG = 47h
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;

PIC18F2450/4450
BNC Branch if Not Carry BNN Branch if Not Negative
Syntax: BNC n Syntax: BNN n

Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127
Operation: if Carry bit is ‘0’ Operation: if Negative bit is ‘0’
(PC) + 2 + 2n → PC (PC) + 2 + 2n → PC
Status Affected: None Status Affected: None
Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn
Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the
will branch. program will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
‘n’ Data ‘n’ Data
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation
Example: HERE BNC Jump Example: HERE BNN Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
If Carry = 0; If Negative = 0;
PC = address (Jump) PC = address (Jump)
If Carry = 1; If Negative = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

PIC18F2450/4450
BNOV Branch if Not Overflow BNZ Branch if Not Zero
Syntax: BNOV n Syntax: BNZ n

Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127
Operation: if Overflow bit is ‘0’ Operation: if Zero bit is ‘0’
(PC) + 2 + 2n → PC (PC) + 2 + 2n → PC
Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn
Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program
program will branch. will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
‘n’ Data ‘n’ Data
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation
Example: HERE BNOV Jump Example: HERE BNZ Jump

If Overflow = 0; If Zero = 0;
PC = address (Jump) PC = address (Jump)
If Overflow = 1; If Zero = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

PIC18F2450/4450
BRA Unconditional Branch BSF Bit Set f
Syntax: BRA n Syntax: BSF f, b {,a}

Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255
Operation: (PC) + 2 + 2n → PC 0≤b≤7
a ∈ [0,1]
Operation: 1 → f
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set.
instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected.
PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the
two-cycle instruction. GPR bank (default).
Words: 1
Cycles: 2 in Indexed Literal Offset Addressing
Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See
Q1 Q2 Q3 Q4
‘n’ Data
No No No No Words: 1
operation operation operation operation Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: HERE BRA Jump
Decode Read Process Write
Before Instruction
register ‘f’ Data register ‘f’
PC = address (HERE)
After Instruction
PC = address (Jump) Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah

PIC18F2450/4450
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}

Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
0≤b≤7 0≤b<7
a ∈ [0,1] a ∈ [0,1]
Operation: skip if (f) = 0 Operation: skip if (f) = 1
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a two-cycle instruction. this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in set is enabled, this instruction operates
Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh).
See Section 19.2.3 “Byte-Oriented and See Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register ‘f’ Data operation register ‘f’ Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0

FALSE : FALSE :
TRUE : TRUE :
If FLAG<1> = 0; If FLAG<1> = 0;
PC = address (TRUE) PC = address (FALSE)
If FLAG<1> = 1; If FLAG<1> = 1;
PC = address (FALSE) PC = address (TRUE)

PIC18F2450/4450
BTG Bit Toggle f BOV Branch if Overflow
Syntax: BTG f, b {,a} Syntax: BOV n

0≤b<7 Operation: if Overflow bit is ‘1’
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: (f) → f
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is ‘1’, then the
Description: Bit ‘b’ in data memory location ‘f’ is program will branch.
inverted. The 2’s complement number ‘2n’ is
If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have
If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next
GPR bank (default). instruction, the new address will be
If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a
set is enabled, this instruction operates two-cycle instruction.
Words: 1
Section 19.2.3 “Byte-Oriented and Cycles: 1(2)
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Literal Offset Mode” for details. If Jump:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1 Decode Read literal Process Write to PC
‘n’ Data
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal Process No
Example: BTG PORTC, 4, 0 ‘n’ Data operation
Before Instruction:
PORTC = 0111 0101 [75h]
Example: HERE BOV Jump
After Instruction:
PORTC = 0110 0101 [65h] Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;

PIC18F2450/4450
BZ Branch if Zero CALL Subroutine Call
Syntax: BZ n Syntax: CALL k {,s}

Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575
Operation: if Zero bit is ‘1’ s ∈ [0,1]
(PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Encoding: 1110 0000 nnnn nnnn (W) → WS,
Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS,
will branch. (BSR) → BSRS
The 2’s complement number ‘2n’ is Status Affected: None
added to the PC. Since the PC will have
Encoding:
incremented to fetch the next
1st word (k<7:0>) 1110 110s k7kkk kkkk0
instruction, the new address will be
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8
PC + 2 + 2n. This instruction is then a
two-cycle instruction. Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
Words: 1
(PC + 4) is pushed onto the return
Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and
Q Cycle Activity: BSR
If Jump: registers are also pushed into their
respective shadow registers, WS,
Q1 Q2 Q3 Q4
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
‘n’ Data
20-bit value ‘k’ is loaded into PC<20:1>.
No No No No CALL is a two-cycle instruction.
Words: 2
If No Jump:
Cycles: 2
Q1 Q2 Q3 Q4
Decode Read literal Process No Q Cycle Activity:
‘n’ Data operation Q1 Q2 Q3 Q4
Decode Read literal Push PC to Read literal
Example: HERE BZ Jump ‘k’<7:0>, stack ‘k’<19:8>,
Write to PC
Before Instruction
No No No No
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump) Example: HERE CALL THERE,1
If Zero = 0;
PC = address (HERE + 2) Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = STATUS

PIC18F2450/4450
CLRF Clear f CLRWDT Clear Watchdog Timer
Syntax: CLRF f {,a} Syntax: CLRWDT

Operands: 0 ≤ f ≤ 255 Operands: None
a ∈ [0,1] Operation: 000h → WDT,
Operation: 000h → f, 000h → WDT postscaler,
1→Z 1 → TO,
1 → PD
Status Affected: Z
Status Affected: TO, PD
Encoding: 0110 101a ffff ffff
Encoding: 0000 0000 0000 0100
Description: Clears the contents of the specified
register. Description: CLRWDT instruction resets the
If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the
If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO
GPR bank (default). and PD, are set.
If ‘a’ is ‘0’ and the extended instruction Words: 1
in Indexed Literal Offset Addressing Cycles: 1
mode whenever f ≤ 95 (5Fh). See Q Cycle Activity:
Section 19.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4
Decode No Process No
operation Data operation
Words: 1
Cycles: 1 Example: CLRWDT
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 WDT Counter = ?
Decode Read Process Write After Instruction
register ‘f’ Data register ‘f’ WDT Counter = 00h
WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1
PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h

PIC18F2450/4450
COMF Complement f CPFSEQ Compare f with W, Skip if f = W
Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a}

d ∈ [0,1] a ∈ [0,1]
a ∈ [0,1] Operation: (f) – (W),
skip if (f) = (W)
Operation: (f) → dest
(unsigned comparison)
Description: The contents of register ‘f’ are Description: Compares the contents of data memory
complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by
stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction.
stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is
If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed
If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle
GPR bank (default). instruction.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected.
set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the
in Indexed Literal Offset Addressing GPR bank (default).
mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction
Section 19.2.3 “Byte-Oriented and set is enabled, this instruction operates
Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing
Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See
Words: 1 Section 19.2.3 “Byte-Oriented and
Cycles: 1
Q Cycle Activity:
Words: 1
Q1 Q2 Q3 Q4
Cycles: 1(2)
Decode Read Process Write to Note: 3 cycles if skip and followed
register ‘f’ Data destination by a 2-word instruction.
Q Cycle Activity:
Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No
REG = 13h register ‘f’ Data operation
After Instruction If skip:
REG = 13h Q1 Q2 Q3 Q4
W = ECh
No No No No
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
No No No No
Example: HERE CPFSEQ REG, 0

NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG ≠ W;
PC = Address (NEQUAL)

PIC18F2450/4450
CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
a ∈ [0,1] a ∈ [0,1]
Operation: (f) – (W),
Operation: (f) – (W),
skip if (f) > (W)
skip if (f) < (W)
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location ‘f’ to the contents of W by
If the contents of ‘f’ are greater than the performing an unsigned subtraction.
contents of WREG, then the fetched If the contents of ‘f’ are less than the
instruction is discarded and a NOP is contents of W, then the fetched
executed instead, making this a instruction is discarded and a NOP is
two-cycle instruction. executed instead, making this a
If ‘a’ is ‘0’, the Access Bank is selected. two-cycle instruction.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the
If ‘a’ is ‘0’ and the extended instruction GPR bank (default).
set is enabled, this instruction operates Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Literal Offset Mode” for details. Q Cycle Activity:
Cycles: 1(2) Decode Read Process No
Note: 3 cycles if skip and followed register ‘f’ Data operation
by a 2-word instruction. If skip:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
Decode Read Process No operation operation operation operation
register ‘f’ Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No
Example: HERE CPFSLT REG, 1
NLESS :
No No No No
LESS :
Before Instruction
Example: HERE CPFSGT REG, 0 PC = Address (HERE)
W = ?
NGREATER :
After Instruction
GREATER :
If REG < W;
Before Instruction PC = Address (LESS)
PC = Address (HERE) If REG ≥ W;
W = ? PC = Address (NLESS)
After Instruction
If REG > W;
PC = Address (GREATER)
If REG ≤ W;
PC = Address (NGREATER)

PIC18F2450/4450
DAW Decimal Adjust W Register DECF Decrement f
Syntax: DAW Syntax: DECF f {,d {,a}}

Operands: None Operands: 0 ≤ f ≤ 255
Operation: If [W<3:0> > 9] or [DC = 1] then d ∈ [0,1]
a ∈ [0,1]
(W<3:0>) + 6 → W<3:0>;
else Operation: (f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected: C, DC, N, OV, Z
If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff

(W<7:4>) + 6 + DC → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
else result is stored in W. If ‘d’ is ‘1’, the
(W<7:4>) + DC → W<7:4> result is stored back in register ‘f’
Status Affected: C (default).
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W, GPR bank (default).
resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction
variables (each in packed BCD format) set is enabled, this instruction operates
and produces a correct packed BCD in Indexed Literal Offset Addressing
result. mode whenever f ≤ 95 (5Fh). See
Words: 1 Section 19.2.3 “Byte-Oriented and
Cycles: 1 Literal Offset Mode” for details.
Q Cycle Activity: Words: 1
Q1 Q2 Q3 Q4
Cycles: 1
Q Cycle Activity:
register W Data W
Q1 Q2 Q3 Q4
Example 1: Decode Read Process Write to
DAW
Before Instruction
W = A5h
C = 0 Example: DECF CNT, 1, 0
DC = 0
Before Instruction
After Instruction
CNT = 01h
W = 05h Z = 0
C = 1
DC = 0 After Instruction
CNT = 00h
Example 2: Z = 1
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0

PIC18F2450/4450
DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0
Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}}

d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) – 1 → dest, Operation: (f) – 1 → dest,
skip if result = 0 skip if result ≠ 0
Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction, If the result is not ‘0’, the next
which is already fetched, is discarded instruction, which is already fetched, is
and a NOP is executed instead, making discarded and a NOP is executed
it a two-cycle instruction. instead, making it a two-cycle
If ‘a’ is ‘0’, the Access Bank is selected. instruction.
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing
Section 19.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 19.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Words: 1
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed Cycles: 1(2)
by a 2-word instruction. Note: 3 cycles if skip and followed
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
No No No No operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT – 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT ≠ 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP ≠ 0;
PC = Address (NZERO)

PIC18F2450/4450
GOTO Unconditional Branch INCF Increment f
Syntax: GOTO k Syntax: INCF f {,d {,a}}

Operation: k → PC<20:1> d ∈ [0,1]
a ∈ [0,1]
Operation: (f) + 1 → dest
Encoding:
1st word (k<7:0>) 1110 1111 k7kkk kkkk0 Status Affected: C, DC, N, OV, Z
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff
Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are
anywhere within the entire incremented. If ‘d’ is ‘0’, the result is
2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is
value ‘k’ is loaded into PC<20:1>. GOTO placed back in register ‘f’ (default).
is always a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected.
Words: 2 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Cycles: 2 If ‘a’ is ‘0’ and the extended instruction
Q Cycle Activity: set is enabled, this instruction operates
Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing
Decode Read literal No Read literal
‘k’<7:0>, operation ‘k’<19:8>,
Write to PC
No No No No
Words: 1
Cycles: 1
Example: GOTO THERE Q Cycle Activity:
After Instruction Q1 Q2 Q3 Q4
PC = Address (THERE) Decode Read Process Write to
Example: INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1

PIC18F2450/4450
INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0
Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}}

d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) + 1 → dest,
Operation: (f) + 1 → dest,
skip if result ≠ 0
skip if result = 0
Description: The contents of register ‘f’ are
Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is
incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
placed back in register ‘f’. (default) If the result is not ‘0’, the next
If the result is ‘0’, the next instruction, instruction, which is already fetched, is
which is already fetched, is discarded discarded and a NOP is executed
and a NOP is executed instead, making instead, making it a two-cycle
it a two-cycle instruction. instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates set is enabled, this instruction operates
in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register ‘f’ Data destination register ‘f’ Data destination
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0

NZERO : ZERO
ZERO : NZERO
PC = Address (HERE) PC = Address (HERE)
CNT = CNT + 1 REG = REG + 1
If CNT = 0; If REG ≠ 0;
PC = Address (ZERO) PC = Address (NZERO)
If CNT ≠ 0; If REG = 0;
PC = Address (NZERO) PC = Address (ZERO)

PIC18F2450/4450
IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f
Syntax: IORLW k Syntax: IORWF f {,d {,a}}

Operation: (W) .OR. k → W d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .OR. (f) → dest
Description: The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W. Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
Words: 1
the result is placed back in register ‘f’
Cycles: 1 (default).
Q1 Q2 Q3 Q4
GPR bank (default).
Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction
literal ‘k’ Data
Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See
Before Instruction
W = 9Ah
After Instruction
W = BFh Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: IORWF RESULT, 0, 1

Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h

PIC18F2450/4450
LFSR Load FSR MOVF Move f
Syntax: LFSR f, k Syntax: MOVF f {,d {,a}}

Operands: 0≤f≤2 Operands: 0 ≤ f ≤ 255
0 ≤ k ≤ 4095 d ∈ [0,1]
a ∈ [0,1]
Operation: k → FSRf
Operation: f → dest
Encoding: 1110 1110 00ff k11kkk Status Affected: N, Z
1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff
Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to
File Select Register pointed to by ‘f’. a destination dependent upon the
Words: 2 status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
Cycles: 2 placed back in register ‘f’ (default).
Q Cycle Activity: Location ‘f’ can be anywhere in the
Q1 Q2 Q3 Q4 256-byte bank.
Decode Read literal Process Write
‘k’ MSB Data literal ‘k’ MSB
GPR bank (default).
to FSRfH
Decode Read literal Process Write literal ‘k’ set is enabled, this instruction operates
‘k’ LSB Data to FSRfL in Indexed Literal Offset Addressing
Example: LFSR 2, 3ABh Section 19.2.3 “Byte-Oriented and
After Instruction Literal Offset Mode” for details.
FSR2H = 03h
FSR2L = ABh Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write W
register ‘f’ Data
Example: MOVF REG, 0, 0

Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h

PIC18F2450/4450
MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR
Syntax: MOVFF fs,fd Syntax: MOVLW k

Operands: 0 ≤ fs ≤ 4095 Operands: 0 ≤ k ≤ 255
0 ≤ fd ≤ 4095
Operation: k → BSR
Operation: (fs) → fd
Encoding:
Description: The eight-bit literal ‘k’ is loaded into the
1st word (source) 1100 ffff ffff ffffs
Bank Select Register (BSR). The value
2nd word (destin.) 1111 ffff ffff ffffd
of BSR<7:4> always remains ‘0’
Description: The contents of source register ‘fs’ are regardless of the value of k7:k4.
moved to destination register ‘fd’.
Words: 1
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to Cycles: 1
FFFh) and location of destination ‘fd’ Q Cycle Activity:
can also be anywhere from 000h to Q1 Q2 Q3 Q4
FFFh.
Decode Read Process Write literal
Either source or destination can be W
literal ‘k’ Data ‘k’ to BSR
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a Example: MOVLB 5
peripheral register (such as the transmit
Before Instruction
buffer or an I/O port).
BSR Register = 02h
The MOVFF instruction cannot use the
After Instruction
PCL, TOSU, TOSH or TOSL as the
BSR Register = 05h
destination register.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
register ‘f’ Data operation
(src)
Decode No No Write
operation operation register ‘f’
No dummy (dest)
read
Example: MOVFF REG1, REG2

Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h

PIC18F2450/4450
MOVLW Move Literal to W MOVWF Move W to f
Syntax: MOVLW k Syntax: MOVWF f {,a}

Operation: k→W a ∈ [0,1]
Operation: (W) → f
Description: The eight-bit literal ‘k’ is loaded into W.
Description: Move data from W to register ‘f’.
Words: 1
Location ‘f’ can be anywhere in the
Cycles: 1 256-byte bank.
Q1 Q2 Q3 Q4
GPR bank (default).
Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction
literal ‘k’ Data set is enabled, this instruction operates
Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See
After Instruction
W = 5Ah
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: MOVWF REG, 0

Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh

PIC18F2450/4450
MULLW Multiply Literal with W MULWF Multiply W with f
Syntax: MULLW k Syntax: MULWF f {,a}

Operation: (W) x k → PRODH:PRODL a ∈ [0,1]
Operation: (W) x (f) → PRODH:PRODL
Description: An unsigned multiplication is carried
out between the contents of W and the Description: An unsigned multiplication is carried
8-bit literal ‘k’. The 16-bit result is out between the contents of W and the
placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit
PRODH contains the high byte. result is stored in the PRODH:PRODL
W is unchanged. register pair. PRODH contains the
None of the Status flags are affected. high byte. Both W and ‘f’ are
Note that neither Overflow nor Carry is unchanged.
possible in this operation. A zero result None of the Status flags are affected.
is possible but not detected. Note that neither Overflow nor Carry is
possible in this operation. A zero
Words: 1
result is possible but not detected.
Cycles: 1 If ‘a’ is ‘0’, the Access Bank is
Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used
Q1 Q2 Q3 Q4 to select the GPR bank (default).
set is enabled, this instruction
literal ‘k’ Data registers
operates in Indexed Literal Offset
PRODH:
Addressing mode whenever
PRODL
f ≤ 95 (5Fh). See Section 19.2.3
“Byte-Oriented and Bit-Oriented
Example: MULLW 0C4h Instructions in Indexed Literal Offset
Mode” for details.
Before Instruction
W = E2h Words: 1
PRODH = ?
PRODL = ? Cycles: 1
After Instruction Q Cycle Activity:
W = E2h Q1 Q2 Q3 Q4
PRODH = ADh
PRODL = 08h Decode Read Process Write
register ‘f’ Data registers
PRODH:
PRODL
Example: MULWF REG, 1

Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h

PIC18F2450/4450
NEGF Negate f NOP No Operation
Syntax: NEGF f {,a} Syntax: NOP

Operands: 0 ≤ f ≤ 255 Operands: None
a ∈ [0,1] Operation: No operation
Operation: (f) + 1 → f
Encoding: 0000 0000 0000 0000
Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx
Description: Location ‘f’ is negated using two’s Description: No operation.
complement. The result is placed in the
Words: 1
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1
If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity:
GPR bank (default).
Q1 Q2 Q3 Q4
set is enabled, this instruction operates Decode No No No
in Indexed Literal Offset Addressing operation operation operation
Section 19.2.3 “Byte-Oriented and Example:
None.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: NEGF REG, 1

Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]

PIC18F2450/4450
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: POP Syntax: PUSH

Operands: None Operands: None
Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack.
Words: 1
Words: 1 Cycles: 1
Cycles: 1
Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode Push PC + 2 No No
Decode No Pop TOS No onto return operation operation
operation value operation stack
Example: POP Example: PUSH

GOTO NEW Before Instruction
Before Instruction TOS = 345Ah
TOS = 0031A2h PC = 0124h
Stack (1 level down) = 014332h
After Instruction
After Instruction PC = 0126h
TOS = 014332h TOS = 0126h
PC = NEW Stack (1 level down) = 345Ah

PIC18F2450/4450
RCALL Relative Call RESET Reset
Syntax: RCALL n Syntax: RESET

Operands: -1024 ≤ n ≤ 1023 Operands: None
Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are
(PC) + 2 + 2n → PC affected by a MCLR Reset.
Status Affected: None Status Affected: All
Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111
Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to
from the current location. First, return execute a MCLR Reset in software.
address (PC + 2) is pushed onto the
Words: 1
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will Cycles: 1
have incremented to fetch the next Q Cycle Activity:
instruction, the new address will be Q1 Q2 Q3 Q4
PC + 2 + 2n. This instruction is a
Decode Start No No
two-cycle instruction.
Reset operation operation
Words: 1
Cycles: 2 Example: RESET
Q Cycle Activity: After Instruction
Q1 Q2 Q3 Q4 Registers = Reset Value
Decode Read literal Process Write to PC Flags* = Reset Value
‘n’ Data
Push PC to
stack
No No No No
Example: HERE RCALL Jump

Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)

PIC18F2450/4450
RETFIE Return from Interrupt RETLW Return Literal to W
Syntax: RETFIE {s} Syntax: RETLW k

Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255
Operation: (TOS) → PC, Operation: k → W,
1 → GIE/GIEH or PEIE/GIEL, (TOS) → PC,
if s = 1 PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk
PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’.
Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the
top of the stack (the return address).
Encoding: 0000 0000 0001 000s
The high address latch (PCLATH)
Description: Return from interrupt. Stack is popped remains unchanged.
and Top-of-Stack (TOS) is loaded into
Words: 1
the PC. Interrupts are enabled by
setting either the high or low priority Cycles: 2
global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity:
contents of the shadow registers WS,
Q1 Q2 Q3 Q4
STATUSS and BSRS are loaded into
Decode Read Process Pop PC from
their corresponding registers, W,
literal ‘k’ Data stack, Write
STATUS and BSR. If ‘s’ = 0, no update
to W
of these registers occurs (default).
No No No No
Words: 1
Cycles: 2
Q Cycle Activity: Example:
Q1 Q2 Q3 Q4
Decode No No Pop PC from CALL TABLE ; W contains table
operation operation stack ; offset value
; W now has
Set GIEH or
; table value
GIEL
:
No No No No TABLE
operation operation operation operation ADDWF PCL ; W = offset
RETLW k0 ; Begin table
Example: RETFIE 1 RETLW k1 ;
:
After Interrupt
:
PC = TOS
W = WS RETLW kn ; End of table
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1 Before Instruction
W = 07h
After Instruction
W = value of kn

PIC18F2450/4450
RETURN Return from Subroutine RLCF Rotate Left f through Carry
Syntax: RETURN {s} Syntax: RLCF f {,d {,a}}

Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255
Operation: (TOS) → PC, d ∈ [0,1]
a ∈ [0,1]
if s = 1
(WS) → W, Operation: (f<n>) → dest<n + 1>,
(STATUSS) → STATUS, (f<7>) → C,
(BSRS) → BSR, (C) → dest<0>
PCLATU, PCLATH are unchanged Status Affected: C, N, Z
Encoding: 0000 0000 0001 001s
Description: The contents of register ‘f’ are rotated
Description: Return from subroutine. The stack is one bit to the left through the Carry
popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in
is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back
‘s’= 1, the contents of the shadow in register ‘f’ (default).
registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is
loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to
registers, W, STATUS and BSR. If select the GPR bank (default).
‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction
occurs (default). set is enabled, this instruction
Words: 1 operates in Indexed Literal Offset
Cycles: 2 f ≤ 95 (5Fh). See Section 19.2.3
Q Cycle Activity: “Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Q1 Q2 Q3 Q4
Decode No Process Pop PC
operation Data from stack C register f
No No No No
operation operation operation operation Words: 1
Cycles: 1
Q Cycle Activity:
Example: RETURN Q1 Q2 Q3 Q4
After Instruction: Decode Read Process Write to
PC = TOS register ‘f’ Data destination
Example: RLCF REG, 0, 0

Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1

PIC18F2450/4450
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}

d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>,
(f<7>) → dest<0> (f<0>) → C,
(C) → dest<7>
Status Affected: C, N, Z
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated
is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry
stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in
If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default).
GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the
set is enabled, this instruction operates GPR bank (default).
in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction
mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates
Section 19.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing
Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See
Literal Offset Mode” for details. Section 19.2.3 “Byte-Oriented and
register f
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0

PIC18F2450/4450
RRNCF Rotate Right f (No Carry) SETF Set f
Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a}

d ∈ [0,1] a ∈ [0,1]
a ∈ [0,1]
Operation: FFh → f
Operation: (f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Description: The contents of the specified register
are set to FFh.
Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected.
one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the
is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default).
placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction
If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates
selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing
is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See
per the BSR value (default). Section 19.2.3 “Byte-Oriented and
If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed
set is enabled, this instruction operates Literal Offset Mode” for details.
Words: 1
Section 19.2.3 “Byte-Oriented and Cycles: 1
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Q1 Q2 Q3 Q4
register f Decode Read Process Write
Words: 1
Cycles: 1 Example: SETF REG,1
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 REG = 5Ah
After Instruction
REG = FFh
Example 1: RRNCF REG, 1, 0

Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0

Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111

PIC18F2450/4450
SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow
Syntax: SLEEP Syntax: SUBFWB f {,d {,a}}

Operands: None Operands: 0 ≤ f ≤ 255
Operation: 00h → WDT, d ∈ [0,1]
a ∈ [0,1]
0 → WDT postscaler,
1 → TO, Operation: (W) – (f) – (C) → dest
0 → PD
Status Affected: TO, PD Encoding: 0101 01da ffff ffff
Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag
Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement
cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored
is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in
postscaler are cleared. register ‘f’ (default).
The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is
with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
Words: 1
Cycles: 1 set is enabled, this instruction
Q Cycle Activity: operates in Indexed Literal Offset
Q1 Q2 Q3 Q4
f ≤ 95 (5Fh). See Section 19.2.3
Decode No Process Go to “Byte-Oriented and Bit-Oriented
operation Data Sleep Instructions in Indexed Literal Offset
Example: SLEEP Words: 1
Before Instruction Cycles: 1
TO = ?
PD = ? Q Cycle Activity:
TO = 1† Decode Read Process Write to
PD = 0 register ‘f’ Data destination
Example 1: SUBFWB REG, 1, 0
† If WDT causes wake-up, this bit is cleared.
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0

PIC18F2450/4450
SUBLW Subtract W from Literal SUBWF Subtract W from f
Syntax: SUBLW k Syntax: SUBWF f {,d {,a}}

Operation: k – (W) → W d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – (W) → dest
Description W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Description: Subtract W from register ‘f’ (2’s
Words: 1
complement method). If ‘d’ is ‘0’, the
Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the
Q Cycle Activity: result is stored back in register ‘f’
(default).
Q1 Q2 Q3 Q4
If ‘a’ is ‘0’, the Access Bank is
Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used
literal ‘k’ Data to select the GPR bank (default).
Example 1: SUBLW 02h If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
Before Instruction operates in Indexed Literal Offset
W = 01h
C = ? Addressing mode whenever
After Instruction f ≤ 95 (5Fh). See Section 19.2.3
W = 01h “Byte-Oriented and Bit-Oriented
C = 1 ; result is positive Instructions in Indexed Literal Offset
Z = 0 Mode” for details.
N = 0
Words: 1
Example 2: SUBLW 02h
Cycles: 1
Before Instruction
W = 02h Q Cycle Activity:
C = ?
Q1 Q2 Q3 Q4
After Instruction
W = 00h Decode Read Process Write to
C = 1 ; result is zero register ‘f’ Data destination
Z = 1
N = 0 Example 1: SUBWF REG, 1, 0
Example 3: SUBLW 02h Before Instruction
REG = 3
Before Instruction W = 2
W = 03h C = ?
C = ? After Instruction
After Instruction REG = 1
W = FFh ; (2’s complement) W = 2
C = 0 ; result is negative C = 1 ; result is positive
Z = 0 Z = 0
N = 1 N = 0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2’s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1

PIC18F2450/4450
SUBWFB Subtract W from f with Borrow SWAPF Swap f

Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}}
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) – (W) – (C) → dest
Operation: (f<3:0>) → dest<7:4>,
Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0>
Encoding: 0101 10da ffff ffff Status Affected: None
Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register
in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result
in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is
If ‘a’ is ‘0’, the Access Bank is selected. placed in register ‘f’ (default).
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing
Section 19.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 19.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
register ‘f’ Data destination Decode Read Process Write to
Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 19h (0001 1001) Example: SWAPF REG, 1, 0
W = 0Dh (0000 1101)
C = 1 Before Instruction
After Instruction REG = 53h
REG = 0Ch (0000 1011) After Instruction
W = 0Dh (0000 1101)
C = 1 REG = 35h
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; [2’s comp]
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative

PIC18F2450/4450
TBLRD Table Read TBLRD Table Read (Continued)
Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ;

Operands: None Before Instruction
TABLAT = 55h
Operation: if TBLRD *
TBLPTR = 00A356h
(Prog Mem (TBLPTR)) → TABLAT; MEMORY (00A356h) = 34h
TBLPTR – No Change; After Instruction
if TBLRD *+ TABLAT = 34h
(Prog Mem (TBLPTR)) → TABLAT; TBLPTR = 00A357h
(TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ;
if TBLRD *-
(Prog Mem (TBLPTR)) → TABLAT; Before Instruction
(TBLPTR) – 1 → TBLPTR; TABLAT = AAh
TBLPTR = 01A357h
if TBLRD +*
MEMORY (01A357h) = 12h
(TBLPTR) + 1 → TBLPTR; MEMORY (01A358h) = 34h
(Prog Mem (TBLPTR)) → TABLAT After Instruction
Status Affected: None TABLAT = 34h
TBLPTR = 01A358h
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No operation No No operation
operation (Read Program operation (Write
Memory) TABLAT)

PIC18F2450/4450
TBLWT Table Write TBLWT Table Write (Continued)

Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+;
Operands: None Before Instruction
Operation: if TBLWT* TABLAT = 55h
(TABLAT) → Holding Register; TBLPTR = 00A356h
HOLDING REGISTER
TBLPTR – No Change;
(00A356h) = FFh
if TBLWT*+
After Instructions (table write completion)
(TABLAT) → Holding Register;
TABLAT = 55h
(TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h
if TBLWT*- HOLDING REGISTER
(TABLAT) → Holding Register; (00A356h) = 55h
(TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*;
if TBLWT+*
Before Instruction
(TBLPTR) + 1 → TBLPTR;
TABLAT = 34h
(TABLAT) → Holding Register TBLPTR = 01389Ah
Status Affected: None HOLDING REGISTER
(01389Ah) = FFh
Encoding: 0000 0000 0000 11nn HOLDING REGISTER
nn=0 * (01389Bh) = FFh
=1 *+ After Instruction (table write completion)
=2 *- TABLAT = 34h
=3 +* TBLPTR = 01389Bh
HOLDING REGISTER
Description: This instruction uses the 3 LSBs of TBLPTR (01389Ah) = FFh
to determine which of the 8 holding HOLDING REGISTER
registers the TABLAT is written to. The (01389Bh) = 34h
holding registers are used to program the
contents of Program Memory (P.M.). (Refer
to Section 6.0 “Flash Program Memory”
for additional details on programming Flash
memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No No No
(Read (Write to
TABLAT) Holding
Register)

PIC18F2450/4450
TSTFSZ Test f, Skip if 0

XORLW Exclusive OR Literal with W
Syntax: TSTFSZ f {,a}
Syntax: XORLW k
Operands: 0 ≤ f ≤ 255
Operands: 0 ≤ k ≤ 255
a ∈ [0,1]
Operation: (W) .XOR. k → W
Operation: skip if f = 0
Description: The contents of W are XORed with
Description: If ‘f’ = 0, the next instruction fetched
the 8-bit literal ‘k’. The result is placed
during the current instruction execution
in W.
is discarded and a NOP is executed,
making this a two-cycle instruction. Words: 1
If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1
Q Cycle Activity:
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction Q1 Q2 Q3 Q4
set is enabled, this instruction operates Decode Read Process Write to W
in Indexed Literal Offset Addressing literal ‘k’ Data
Bit-Oriented Instructions in Indexed Example: XORLW 0AFh
Literal Offset Mode” for details. Before Instruction
Words: 1 W = B5h
After Instruction
Cycles: 1(2)
W = 1Ah
Note: 3 cycles if skip and followed
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
register ‘f’ Data operation
If skip:
Q1 Q2 Q3 Q4
No No No No
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
No No No No
Example: HERE TSTFSZ CNT, 1

NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT ≠ 00h,
PC = Address (NZERO)

PIC18F2450/4450
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .XOR. (f) → dest
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
GPR bank (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h

PIC18F2450/4450
19.2 Extended Instruction Set A summary of the instructions in the extended
instruction set is provided in Table 19-3. Detailed
In addition to the standard 75 instructions of the PIC18 descriptions are provided in Section 19.2.2
instruction set, PIC18F2450/4450 devices also provide “Extended Instruction Set”. The opcode field
an optional extension to the core CPU functionality. descriptions in Table 19-1 (page 212) apply to both the
The added features include eight additional standard and extended PIC18 instruction sets.
instructions that augment indirect and indexed
addressing operations and the implementation of Note: The instruction set extension and the
Indexed Literal Offset Addressing mode for many of the Indexed Literal Offset Addressing mode
standard PIC18 instructions. were designed for optimizing applications
written in C; the user may likely never use
The additional features of the extended instruction set
these instructions directly in assembler.
are disabled by default. To enable them, users must set
The syntax for these commands is pro-
the XINST Configuration bit.
vided as a reference for users who may be
The instructions in the extended set can all be reviewing code that has been generated
classified as literal operations, which either manipulate by a compiler.
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and 19.2.1 EXTENDED INSTRUCTION SYNTAX
SUBFSR, each have an additional special instantiation
Most of the extended instructions use indexed
for using FSR2. These versions (ADDULNK and
arguments, using one of the File Select Registers and
SUBULNK) allow for automatic return after execution.
some offset to specify a source or destination register.
The extended instructions are specifically implemented When an argument for an instruction serves as part of
to optimize re-entrant program code (that is, code that Indexed Addressing, it is enclosed in square brackets
is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used
high-level languages, particularly C. Among other as an index or offset. The MPASM™ Assembler will
things, they allow users working in high-level flag an error if it determines that an index or offset value
languages to perform certain operations on data is not bracketed.
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
• Dynamic allocation and deallocation of software are also used to indicate index arguments in byte-
stack space when entering and leaving oriented and bit-oriented instructions. This is in addition
subroutines to other changes in their syntax. For more details, see
• Function Pointer invocation Section 19.2.3.1 “Extended Instruction Syntax with
• Software Stack Pointer manipulation Standard PIC18 Commands”.
• Manipulation of variables located in a software Note: In the past, square brackets have been
stack used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 19-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Description Cycles
ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None

ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None
CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None
MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None
zd (destination) 2nd word 1111 xxxx xzzz zzzz
PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None
decrement FSR2
SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None
SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None
return

PIC18F2450/4450
19.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2,
Operation: FSR(f) + k → FSR(f) (TOS) → PC
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
The instruction takes two cycles to
Q Cycle Activity:
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to This may be thought of as a special
literal ‘k’ Data FSR case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example: ADDFSR 2, 23h Words: 1
Before Instruction Cycles: 2
FSR2 = 03FFh Q Cycle Activity:
FSR2 = 0422h
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Example: ADDULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

PIC18F2450/4450
CALLW Subroutine Call Using WREG MOVSF Move Indexed to f
Syntax: CALLW Syntax: MOVSF [zs], fd

Operands: None Operands: 0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095
Operation: (PC + 2) → TOS,
(W) → PCL, Operation: ((FSR2) + zs) → fd
(PCLATH) → PCH, Status Affected: None
(PCLATU) → PCU
Encoding:
Status Affected: None 1st word (source) 1110 1011 0zzz zzzzs
Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd
Description First, the return address (PC + 2) is Description: The contents of the source register are
pushed onto the return stack. Next, the moved to destination register ‘fd’. The
contents of W are written to PCL; the actual address of the source register is
existing value is discarded. Then the determined by adding the 7-bit literal
contents of PCLATH and PCLATU are offset ‘zs’ in the first word to the value of
latched into PCH and PCU, FSR2. The address of the destination
respectively. The second cycle is register is specified by the 12-bit literal
executed as a NOP instruction while the ‘fd’ in the second word. Both addresses
new next instruction is fetched. can be anywhere in the 4096-byte data
Unlike CALL, there is no option to space (000h to FFFh).
update W, STATUS or BSR. The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
Words: 1
Cycles: 2 If the resultant source address points to
Q Cycle Activity: an indirect addressing register, the
value returned will be 00h.
Q1 Q2 Q3 Q4
Decode Read Push PC to No Words: 2
WREG stack operation Cycles: 2
No No No No Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
Example: HERE CALLW source addr source addr source reg
Before Instruction Decode No No Write

PC = address (HERE) operation operation register ‘f’
PCLATH = 10h No dummy (dest)
PCLATU = 00h read
W = 06h
After Instruction
PC = 001006h
Example: MOVSF [05h], REG2
TOS = address (HERE + 2)
PCLATH = 10h Before Instruction
PCLATU = 00h FSR2 = 80h
W = 06h Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h

PIC18F2450/4450
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255
0 ≤ zd ≤ 127
Operation: k → (FSR2),
Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2
Encoding:
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
Description The contents of the source register are
is decremented by ‘1’ after the operation.
moved to the destination register. The
This instruction allows users to push values
addresses of the source and destination
onto a software stack.
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’, Words: 1
respectively, to the value of FSR2. Both Cycles: 1
registers can be located anywhere in
the 4096-byte data memory space Q Cycle Activity:
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to
PCL, TOSU, TOSH or TOSL as the data destination
If the resultant source address points to
an indirect addressing register, the Example: PUSHL 08h
value returned will be 00h. If the
Before Instruction
resultant destination address points to
FSR2H:FSR2L = 01ECh
an indirect addressing register, the Memory (01ECh) = 00h
instruction will execute as a NOP.
Words: 2 After Instruction
FSR2H:FSR2L = 01EBh
Cycles: 2 Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
Example: MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h

PIC18F2450/4450
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2
Operation: FSRf – k → FSRf (TOS) → PC
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified by contents of the FSR2. A RETURN is then
‘f’. executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Cycles: 1
second cycle.
Q Cycle Activity:
This may be thought of as a special case of
Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary
Decode Read Process Write to ‘11’); it operates only on FSR2.
register ‘f’ Data destination Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h
Q1 Q2 Q3 Q4
Before Instruction
FSR2 = 03FFh Decode Read Process Write to
After Instruction register ‘f’ Data destination
FSR2 = 03DCh No No No No
Operation Operation Operation Operation
Example: SUBULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)

PIC18F2450/4450
19.2.3 BYTE-ORIENTED AND 19.2.3.1 Extended Instruction Syntax with
BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands
INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file
Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and
extension may cause legacy applications bit-oriented commands is replaced with the literal offset
to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with
enabling the extended instruction set also enables the extended instructions, the use of brackets indicates
Indexed Literal Offset Addressing mode (Section 5.6.1 to the compiler that the value is to be interpreted as an
“Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a
a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an
the standard PIC18 instruction set are interpreted. error in the MPASM Assembler.
When the extended set is disabled, addresses If the index argument is properly bracketed for Indexed
embedded in opcodes are treated as literal memory Literal Offset Addressing mode, the Access RAM
locations: either as a location in the Access Bank argument is never specified; it will automatically be
(‘a’ = 0) or in a GPR bank designated by the BSR assumed to be ‘0’. This is in contrast to standard
(‘a’ = 1). When the extended instruction set is enabled operation (extended instruction set disabled) when ‘a’
and ‘a’ = 0, however, a file register argument of 5Fh or is set on the basis of the target address. Declaring the
less is interpreted as an offset from the pointer value in Access RAM bit in this mode will also generate an error
FSR2 and not as a literal address. For practical in the MPASM Assembler.
purposes, this means that all instructions that use the
Access RAM bit as an argument – that is, all byte- The destination argument, ‘d’, functions as before.
oriented and bit-oriented instructions, or almost half of In the latest versions of the MPASM assembler,
the core PIC18 instructions – may behave differently language support for the extended instruction set must
when the extended instruction set is enabled. be explicitly invoked. This is done with either the
When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the
Access RAM are essentially remapped to their original source listing.
values. This may be useful in creating backward
compatible code. If this technique is used, it may be 19.2.4 CONSIDERATIONS WHEN
necessary to save the value of FSR2 and restore it ENABLING THE EXTENDED
when moving back and forth between C and assembly INSTRUCTION SET
routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the
must also keep in mind the syntax requirements of the instruction set may not be beneficial to all users. In
extended instruction set (see Section 19.2.3.1 particular, users who are not writing code that uses a
“Extended Instruction Syntax with Standard PIC18 software stack may not benefit from using the
Commands”). extensions to the instruction set.
Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing
can be very useful for dynamic stack and pointer mode may create issues with legacy applications
manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because
arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address
register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these
programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2
extended instruction set is enabled, register addresses when the instruction set extension is enabled, the
of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data
Addressing. addresses.
Representative examples of typical byte-oriented and When porting an application to the PIC18F2450/4450,
bit-oriented instructions in the Indexed Literal Offset it is very important to consider the type of code. A large,
Addressing mode are provided on the following page to re-entrant application that is written in ‘C’ and would
show how execution is affected. The operand benefit from efficient compilation will do well when
conditions shown in the examples are applicable to all using the instruction set extensions. Legacy applica-
instructions of these types. tions that heavily use the Access Bank will most likely
not benefit from using the extended instruction set.

PIC18F2450/4450
ADD W to Indexed Bit Set Indexed

ADDWF BSF
(Indexed Literal Offset mode) (Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d} Syntax: BSF [k], b

d ∈ [0,1] 0≤b≤7
Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)
Status Affected: N, OV, C, DC, Z Status Affected: None
Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk
Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2,
contents of the register indicated by offset by the value ‘k’, is set.
FSR2, offset by the value ‘k’.
Words: 1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in Cycles: 1
register ‘f’ (default). Q Cycle Activity:
Cycles: 1 Decode Read Process Write to
Q Cycle Activity:
Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7
Decode Read ‘k’ Process Write to Before Instruction
Data destination FLAG_OFST = 0Ah
FSR2 = 0A00h
Example: ADDWF [OFST] ,0 Contents
of 0A0Ah = 55h
Before Instruction
After Instruction
W = 17h
OFST = 2Ch Contents
FSR2 = 0A00h of 0A0Ah = D5h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents Set Indexed
of 0A2Ch = 20h SETF
(Indexed Literal Offset mode)
Syntax: SETF [k]

Operands: 0 ≤ k ≤ 95
Operation: FFh → ((FSR2) + k)
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process Write
Data register
Example: SETF [OFST]

Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh

PIC18F2450/4450
19.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set,
MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
The latest versions of Microchip’s software tools have Depending on the environment being used, this may be
been designed to fully support the extended instruction done in several ways:
set of the PIC18F2450/4450 family of devices. This
includes the MPLAB C18 C compiler, MPASM • A menu option, or dialog box within the
Assembly language and MPLAB Integrated environment, that allows the user to configure the
Development Environment (IDE). language tool and its settings for the project
• A command line option
When selecting a target device for software
development, MPLAB IDE will automatically set default • A directive in the source code
Configuration bits for that device. The default setting for These options vary between different compilers,
the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are
extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany-
Addressing mode. For proper execution of applications ing their development systems for the appropriate
developed to take advantage of the extended information.
instruction set, XINST must be set during
programming.

PIC18F2450/4450
20.0 DEVELOPMENT SUPPORT 20.1 MPLAB Integrated Development
Environment Software
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB ICE 4000 In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
• Low-Cost Demonstration and Development • Integration of select third party tools, such as
Boards and Evaluation Kits HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC18F2450/4450
20.2 MPASM Assembler 20.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PICmicro MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline
assembly code • Command line interface
• Conditional assembly for multi-purpose • Rich directive set
source files • Flexible macro language
• Directives that allow complete control over the • MPLAB IDE compatibility
assembly process
20.6 MPLAB SIM Software Simulator
20.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code
C Compilers development in a PC-hosted environment by simulat-
The MPLAB C18 and MPLAB C30 Code Development ing the PICmicro MCUs and dsPIC® DSCs on an
Systems are complete ANSI C compilers for instruction level. On any given instruction, the data
Microchip’s PIC18 family of microcontrollers and areas can be examined or modified and stimuli can be
dsPIC30F family of digital signal controllers. These applied from a comprehensive stimulus controller.
compilers provide powerful integration capabilities, Registers can be logged to files for further run-time
superior code optimization and ease of use not found analysis. The trace buffer and logic analyzer display
with other compilers. extend the power of the simulator to record and track
program execution, actions on I/O, as well as internal
For easy source level debugging, the compilers provide registers.
symbol information that is optimized to the MPLAB IDE
debugger. The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
20.4 MPLINK Object Linker/ MPLAB ASM30 Assemblers. The software simulator
MPLIB Object Librarian offers the flexibility to develop and debug code outside
The MPLINK Object Linker combines relocatable of the laboratory environment, making it an excellent,
objects created by the MPASM Assembler and the economical software development tool.
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

PIC18F2450/4450
20.7 MPLAB ICE 2000 20.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PICmicro
complete microcontroller design tool set for PICmicro MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2
2000 In-Circuit Emulator is advanced by the MPLAB utilizes the in-circuit debugging capability built into
Integrated Development Environment, which allows the Flash devices. This feature, along with Microchip’s
editing, building, downloading and source debugging In-Circuit Serial ProgrammingTM (ICSPTM) protocol,
from a single environment. offers cost-effective, in-circuit Flash debugging from the
graphical user interface of the MPLAB Integrated
The MPLAB ICE 2000 is a full-featured emulator Development Environment. This enables a designer to
system with enhanced trace, trigger and data monitor- develop and debug source code by setting breakpoints,
ing features. Interchangeable processor modules allow single stepping and watching variables, and CPU
the system to be easily reconfigured for emulation of status and peripheral registers. Running at full speed
different processors. The architecture of the MPLAB enables testing hardware and applications in real
ICE 2000 In-Circuit Emulator allows expansion to time. MPLAB ICD 2 also serves as a development
support new PICmicro microcontrollers. programmer for selected PICmicro devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 20.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
20.8 MPLAB ICE 4000
package types. The ICSP™ cable assembly is included
High-Performance as a standard item. In Stand-Alone mode, the MPLAB
In-Circuit Emulator PM3 Device Programmer can read, verify and program
PICmicro devices without a PC connection. It can also
The MPLAB ICE 4000 In-Circuit Emulator is intended to
set code protection in this mode. The MPLAB PM3
provide the product development engineer with a
connects to the host PC via an RS-232 or USB cable.
complete microcontroller design tool set for high-end
The MPLAB PM3 has high-speed communications and
PICmicro MCUs and dsPIC DSCs. Software control of
optimized algorithms for quick programming of large
the MPLAB ICE 4000 In-Circuit Emulator is provided by
memory devices and incorporates an SD/MMC card for
the MPLAB Integrated Development Environment,
file storage and secure data applications.
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.

PIC18F2450/4450
20.11 PICSTART Plus Development 20.12 Demonstration, Development and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PICmicro MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func-
Integrated Development Environment software makes tional systems. Most boards include prototyping areas for
using the programmer simple and efficient. The adding custom circuitry and provide application firmware
PICSTART Plus Development Programmer supports and source code for examination and modification.
most PICmicro devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs,
Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232
PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional
The PICSTART Plus Development Programmer is CE EEPROM memory.
compliant.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.

PIC18F2450/4450
21.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC18F2450/4450
FIGURE 21-1: PIC18F2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V PIC18F2450/4450
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
FIGURE 21-2: PIC18LF2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V PIC18LF2450/4450
4.5V
4.2V
4.0V
Voltage
3.5V
3.0V
2.5V
2.0V
4 MHz 16 MHz 25 MHz 48 MHz
Frequency
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.

PIC18F2450/4450
21.1 DC Characteristics: Supply Voltage
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial)
PIC18LF2450/4450 Standard Operating Conditions (unless otherwise stated)
(Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2331/2431/4331/4431 Standard Operating Conditions (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage 2.0 — 5.5 V EC, HS, XT and Internal Oscillator modes
3.0 — 5.5 V HSPLL, XTPLL, ECPIO and ECPLL
Oscillator modes
D002 VDR RAM Data Retention 1.5 — — V
Voltage(1)
D003 VPOR VDD Start Voltage — — 0.7 V See Section 4.3 “Power-on Reset (POR)”
to ensure internal Power-on for details
Reset signal
D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section 4.3 “Power-on Reset (POR)”
to ensure internal Power-on for details
Reset signal
D005 VBOR Brown-out Reset Voltage
BORV1:BORV0 = 11 2.00 2.05 2.16 V
BORV1:BORV0 = 10 2.65 2.79 2.93 V
BORV1:BORV0 = 01 4.11 4.33 4.55 V
BORV1:BORV0 = 00 4.36 4.59 4.82 V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.

PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 Standard Operating Conditions (unless otherwise stated)
Param
Device Typ Max Units Conditions
No.
Power-Down Current (IPD)(1)
PIC18F2450/4450 0.1 TBD μA -40°C
VDD = 2.0V
0.1 TBD μA +25°C
(Sleep mode)
0.2 TBD μA +85°C
PIC18LF2450/4450 0.1 TBD μA -40°C
VDD = 3.0V
0.1 TBD μA +25°C
(Sleep mode)
0.3 TBD μA +85°C
All devices 0.1 TBD μA -40°C
VDD = 5.0V
0.1 TBD μA +25°C
(Sleep mode)
0.4 TBD μA +85°C
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.

PIC18F2450/4450
PIC18LF2450/4450 (Industrial) (Continued)
Param
No.
Supply Current (IDD)(2)
PIC18LF2450/4450 15 TBD μA -40°C
15 TBD μA +25°C VDD = 2.0V
15 TBD μA +85°C
PIC18LF2450/4450 40 TBD μA -40°C FOSC = 31 kHz
35 TBD μA +25°C VDD = 3.0V (RC_RUN mode,
30 TBD μA +85°C INTRC source)
All devices 105 TBD μA -40°C
90 TBD μA +25°C VDD = 5.0V
80 TBD μA +85°C

PIC18F2450/4450
Param
No.
PIC18LF2450/4450 2.9 TBD μA -40°C
3.1 TBD μA +25°C VDD = 2.0V
3.6 TBD μA +85°C
PIC18LF2450/4450 4.5 TBD μA -40°C FOSC = 31 kHz
4.8 TBD μA +25°C VDD = 3.0V (RC_IDLE mode,
5.8 TBD μA +85°C INTRC source)
9.8 TBD μA +25°C VDD = 5.0V
11.4 TBD μA +85°C

PIC18F2450/4450
Param
No.
PIC18LF2450/4450 250 TBD μA -40°C
250 TBD μA +25°C VDD = 2.0V
250 TBD μA +85°C
PIC18LF2450/4450 550 TBD μA -40°C FOSC = 1 MHZ
480 TBD μA +25°C VDD = 3.0V (PRI_RUN,
460 TBD μA +85°C EC oscillator)
All devices 1.2 TBD mA -40°C
1.1 TBD mA +25°C VDD = 5.0V
1.0 TBD mA +85°C
PIC18LF2450/4450 0.74 TBD mA -40°C
0.74 TBD mA +25°C VDD = 2.0V
0.74 TBD mA +85°C
PIC18LF2450/4450 1.3 TBD mA -40°C FOSC = 4 MHz
1.3 TBD mA +25°C VDD = 3.0V (PRI_RUN,
1.3 TBD mA +85°C EC oscillator)
2.6 TBD mA +25°C VDD = 5.0V
2.5 TBD mA +85°C
All devices 15 TBD mA -40°C
16 TBD mA +25°C VDD = 4.2V
16 TBD mA +85°C FOSC = 40 MHZ
(PRI_RUN,
All devices 21 TBD mA -40°C EC oscillator)
21 TBD mA +25°C VDD = 5.0V
21 TBD mA +85°C
All devices 20 TBD mA -40°C
20 TBD mA +25°C VDD = 4.2V
20 TBD mA +85°C FOSC = 48 MHZ
(PRI_RUN,
All devices 25 TBD mA -40°C EC oscillator)
25 TBD mA +25°C VDD = 5.0V
25 TBD mA +85°C

PIC18F2450/4450
Param
No.
PIC18LF2450/4450 65 TBD μA -40°C
65 TBD μA +25°C VDD = 2.0V
70 TBD μA +85°C
PIC18LF2450/4450 120 TBD μA -40°C FOSC = 1 MHz
120 TBD μA +25°C VDD = 3.0V (PRI_IDLE mode,
240 TBD μA +25°C VDD = 5.0V
250 TBD μA +85°C
PIC18LF2450/4450 255 TBD μA -40°C
260 TBD μA +25°C VDD = 2.0V
270 TBD μA +85°C
PIC18LF2450/4450 420 TBD μA -40°C FOSC = 4 MHz
430 TBD μA +25°C VDD = 3.0V (PRI_IDLE mode,
0.9 TBD mA +25°C VDD = 5.0V
0.9 TBD mA +85°C
6.2 TBD mA +25°C VDD = 4.2V
6.6 TBD mA +85°C FOSC = 40 MHz
(PRI_IDLE mode,
All devices 8.1 TBD mA -40°C EC oscillator)
8.3 TBD mA +25°C VDD = 5.0V
9.0 TBD mA +85°C
8.1 TBD mA +25°C VDD = 4.2V
8.2 TBD mA +85°C FOSC = 48 MHz
(PRI_IDLE mode,
All devices 9.8 TBD mA -40°C EC oscillator)
10.0 TBD mA +25°C VDD = 5.0V
10.5 TBD mA +85°C

PIC18F2450/4450
Param
No.
PIC18LF2450/4450 14 TBD μA -40°C
15 TBD μA +25°C VDD = 2.0V
16 TBD μA +85°C
PIC18LF2450/4450 40 TBD μA -40°C FOSC = 32 kHz(3)
35 TBD μA +25°C VDD = 3.0V (SEC_RUN mode,
31 TBD μA +85°C Timer1 as clock)
81 TBD μA +25°C VDD = 5.0V
75 TBD μA +85°C
PIC18LF2450/4450 2.5 TBD μA -40°C
3.7 TBD μA +25°C VDD = 2.0V
4.5 TBD μA +85°C
PIC18LF2450/4450 5.0 TBD μA -40°C FOSC = 32 kHz(3)
5.4 TBD μA +25°C VDD = 3.0V (SEC_IDLE mode,
6.3 TBD μA +85°C Timer1 as clock)
9.0 TBD μA +25°C VDD = 5.0V
10.5 TBD μA +85°C

PIC18F2450/4450
Param
No.
D022 Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
(ΔIWDT) Watchdog Timer 1.3 TBD μA -40°C
1.4 TBD μA +25°C VDD = 2.0V
2.0 TBD μA +85°C
1.9 TBD μA -40°C
2.0 TBD μA +25°C VDD = 3.0V
2.8 TBD μA +85°C
4.0 TBD μA -40°C
5.5 TBD μA +25°C VDD = 5.0V
5.6 TBD μA +85°C
D022A Brown-out Reset(4) 35 TBD μA -40°C to +85°C VDD = 3.0V
(ΔIBOR) 40 TBD μA -40°C to +85°C
TBD VDD = 5.0V Sleep mode,
0 μA -40°C to +85°C
BOREN1:BOREN0 = 10
D022B High/Low-Voltage 22 TBD μA -40°C to +85°C VDD = 2.0V
(ΔILVD) Detect(4) 25 TBD μA -40°C to +85°C VDD = 3.0V
29 TBD μA -40°C to +85°C VDD = 5.0V
D025 Timer1 Oscillator 2.1 TBD μA -40°C
(ΔIOSCB) 1.8 TBD μA +25°C VDD = 2.0V 32 kHz on Timer1(3)
2.1 TBD μA +85°C
2.2 TBD μA -40°C
2.6 TBD μA +25°C VDD = 3.0V 32 kHz on Timer1(3)
2.9 TBD μA +85°C
3.0 TBD μA -40°C
3.2 TBD μA +25°C VDD = 5.0V 32 kHz on Timer1(3)
3.4 TBD μA +85°C
D026 A/D Converter 1.0 TBD μA -40°C to +85°C VDD = 2.0V
(ΔIAD) 1.0 TBD μA -40°C to +85°C VDD = 3.0V A/D on, not converting
1.0 TBD μA -40°C to +85°C VDD = 5.0V

PIC18F2450/4450
Param
No.
USB and Related Module Differential Currents (ΔIUSBx, ΔIPLL, ΔIUREG)
ΔIUSBx USB Module TBD TBD mA +25°C VDD = 3.3V
with On-Chip Transceiver TBD TBD mA +25°C VDD = 5.0V
ΔIPLL 96 MHz PLL TBD TBD TBD +25°C VDD = 3.3V
(Oscillator Module) TBD TBD TBD +25°C VDD = 5.0V
ΔIUREG USB Internal Voltage TBD TBD TBD +25°C VDD = 5.0V
Regulator

PIC18F2450/4450
21.3 DC Characteristics: PIC18F2450/4450 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
Sym Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
I/O Ports (except RC4/RC5 in
USB mode):
D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS 0.2 VDD V
RC3 and RC4 VSS 0.3 VDD V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 and T1OSI VSS 0.3 VDD V XT, HS, HSPLL modes(1)
D033 OSC1 VSS 0.2 VDD V EC mode(1)
VILU D+/D- Input — 0.8 V VDD = 4.35V,
USB suspended(5)
VIH Input High Voltage
I/O Ports (except RC4/RC5 in
USB mode):
D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V
D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger buffer 0.8 VDD VDD V
RC3 and RC4 0.7 VDD VDD V
D042 MCLR 0.8 VDD VDD V
D042A OSC1 and T1OSI 0.7 VDD VDD V XT, HS, HSPLL modes(1)
D043 OSC1 0.8 VDD VDD V EC mode(1)
VIHU D+/D- Input 2.4 — V VDD = 4.35V,
USB suspended(5)
IIL Input Leakage Current(2,3)
D060 I/O Ports — ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR — ±5 μA Vss ≤ VPIN ≤ VDD
D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
5: D+ parameters per USB Specification 2.0.

PIC18F2450/4450
21.3 DC Characteristics: PIC18F2450/4450 (Industrial)
DC CHARACTERISTICS
Param
Sym Characteristic Min Max Units Conditions
No.
VOL Output Low Voltage
D080 I/O Ports (except RC4/RC5 in — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
USB mode) -40°C to +85°C
D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
(EC, ECIO modes) -40°C to +85°C
VOLU D+/D- Out — 0.3 VDD = 4.35V,
USB suspended(5)
VOH Output High Voltage(3)
D090 I/O Ports (except RC4/RC5 in VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,
USB mode) -40°C to +85°C
D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,
(EC, ECIO, ECPIO modes) -40°C to +85°C
VOHU D+/D- Out 2.8 3.6 V VDD = 4.35V,
USB suspended(5)
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin — 15 pF In XT and HS modes
when external clock is
used to drive OSC1
D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing
(in RC mode) Specifications
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
5: D+ parameters per USB Specification 2.0.

PIC18F2450/4450
TABLE 21-1: MEMORY PROGRAMMING REQUIREMENTS
DC Characteristics
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
Internal Program Memory
Programming Specifications(1)
D110 VPP Voltage on MCLR/VPP/RE3 pin 9.00 — 13.25 V (Note 2)
D113 IDDP Supply Current during — — 10 mA
Programming
Program Flash Memory
D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP™ port
D132A VIW VDD for Externally Timed Erase 3.0 — 5.5 V Using ICSP port
or Write
D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating
voltage
D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V
D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD > 4.5V
(externally timed)
D133A TIW Self-Timed Write Cycle Time — 2 — ms
D134 TRETD Characteristic Retention 40 100 — Year Provided no other
specifications are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Required only if Single-Supply Programming is disabled.

PIC18F2450/4450
TABLE 21-2: USB MODULE SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
Sym Characteristic Min Typ Max Units Comments
No.
D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on bus must be in this
range for proper USB
operation
D314 IIL Input Leakage on pin — — ±1 μA VSS ≤ VPAD ≤ VDD;
pin at high impedance
D315 VILUSB Input Low Voltage for USB — — 0.8 V For VUSB range
Buffer
D316 VIHUSB Input High Voltage for USB 2.0 — — V For VUSB range
Buffer
D317 VCRS Crossover Voltage 1.3 2.0 V Voltage range for pad_dp and
pad_dm crossover to occur
D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+
and D- must exceed this value
while VCM is met
D319 VCM Differential Common Mode 0.8 — 2.5 V
Range
D320 ZOUT Driver Output Impedance 28 — 44 Ω
D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected to 3.6V
D322 VOH Voltage Output High 2.8 — 3.6 V 15 kΩ load connected to
ground
TABLE 21-3: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
Sym Characteristics Min Typ Max Units Comments
No.
D323 VUSBANA Regulator Output Voltage* 3.0 — 3.6 V
D324 CUSB External Filter Capacitor 220 — — nF Must hold sufficient charge
Value* for peak load with minimal
voltage drop
* These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.

PIC18F2450/4450
FIGURE 21-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
For VDIRMAG = 1: VDD
VHLVD
(HLVDIF set by hardware) (HLVDIF can be

cleared in software)
VHLVD
For VDIRMAG = 0: VDD
HLVDIF
TABLE 21-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Param
Sym Characteristic Min Typ Max Units Conditions
No.
D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06 2.17 2.28 V
Transition High-to-Low HLVDL<3:0> = 0001 2.12 2.23 2.34 V
HLVDL<3:0> = 0010 2.24 2.36 2.48 V
HLVDL<3:0> = 0011 2.32 2.44 2.56 V
HLVDL<3:0> = 0100 2.47 2.60 2.73 V
HLVDL<3:0> = 0101 2.65 2.79 2.93 V
HLVDL<3:0> = 0110 2.74 2.89 3.04 V
HLVDL<3:0> = 0111 2.96 3.12 3.28 V
HLVDL<3:0> = 1000 3.22 3.39 3.56 V
HLVDL<3:0> = 1001 3.37 3.55 3.73 V
HLVDL<3:0> = 1010 3.52 3.71 3.90 V
HLVDL<3:0> = 1011 3.70 3.90 4.10 V
HLVDL<3:0> = 1100 3.90 4.11 4.32 V
HLVDL<3:0> = 1101 4.11 4.33 4.55 V
HLVDL<3:0> = 1110 4.36 4.59 4.82 V

PIC18F2450/4450
21.4 AC (Timing) Characteristics
21.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
mc MCLR
cc CCP1 osc OSC1
ck CLKO wr WR
dt Data in t0 T0CKI
io I/O port t1 T1CKI
:Uppercase Letters and their meanings

S
F Fall P Period
H High R Rise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
High High
Low Low

PIC18F2450/4450
21.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic
The temperature and voltages specified in Table 21-5 terms “PIC18FXXXX” and “PIC18LFXXXX”
apply to all timing specifications unless otherwise are used throughout this section to refer to
noted. Figure 21-4 specifies the load conditions for the the PIC18F2450/4450 and PIC18LF2450/
timing specifications. 4450 families of devices specifically and
only those devices.
TABLE 21-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section 21.1 and
Section 21.3 .
LF parts operate for industrial temperatures only.
FIGURE 21-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 Load Condition 2
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports

PIC18F2450/4450
21.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKO
TABLE 21-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.
Symbol Characteristic Min Max Units Conditions
No.
1A FOSC External CLKI Frequency(1) DC 48 MHz EC, ECIO Oscillator mode
Oscillator Frequency(1) 0.1 4 MHz XT, XTPLL Oscillator mode
4 25 MHz HS Oscillator mode
4 48 MHz HSPLL Oscillator mode
1 TOSC External CLKI Period(1) 20.8 — ns EC, ECIO Oscillator mode
Oscillator Period(1) 250 10,000 ns XT Oscillator mode
25 250 ns HS Oscillator mode
20.8 250 ns HSPLL Oscillator mode
2 TCY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC
3 TosL, External Clock in (OSC1) 30 — ns XT Oscillator mode
TosH High or Low Time 10 — ns HS Oscillator mode
4 TosR, External Clock in (OSC1) — 20 ns XT Oscillator mode
TosF Rise or Fall Time — 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

PIC18F2450/4450
TABLE 21-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
F10 FOSC Oscillator Frequency Range 4 — 48 MHz
F11 FSYS On-Chip VCO System Frequency — 96 — MHz
F12 trc PLL Start-up Time (Lock Time) — — 2 ms
F13 ΔCLK CLKO Stability (Jitter) -0.25 — +0.25 %
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 21-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F2450/4450 (INDUSTRIAL)
PIC18LF2450/4450 (INDUSTRIAL)

Param
Device Min Typ Max Units Conditions
No.
INTRC Accuracy @ Freq = 31 kHz(1)

PIC18LF2450/4450 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V
PIC18F2450/4450 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: INTRC frequency after calibration.
2: Change of INTRC frequency as VDD changes.
FIGURE 21-6: CLKO AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
10 11
CLKO
12
13
14 19 18
16
I/O pin
(Input)
17 15
I/O pin Old Value New Value

(Output)
20, 21
Note: Refer to Figure 21-4 for load conditions.

PIC18F2450/4450
TABLE 21-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)
11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)
12 TckR CLKO Rise Time — 35 100 ns (Note 1)
13 TckF CLKO Fall Time — 35 100 ns (Note 1)
14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)
16 TckH2ioI Port In Hold after CLKO ↑ 0 — — ns (Note 1)
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX 100 — — ns
18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V
(I/O in hold time)
19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns
20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns
20A PIC18LFXXXX — — 60 ns VDD = 2.0V
21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns
21A PIC18LFXXXX — — 60 ns VDD = 2.0V
22† TINP INT Pin High or Low Time TCY — — ns
23† TRBP RB7:RB4 Change INT High or Low Time TCY — — ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset 31
34 34
I/O pins

PIC18F2450/4450
FIGURE 21-8: BROWN-OUT RESET TIMING
VDD BVDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable 36
TABLE 21-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
30 TmcL MCLR Pulse Width (low) 2 — — μs
31 TWDT Watchdog Timer Time-out Period — 4.00 TBD ms
(no postscaler)
32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33 TPWRT Power-up Timer Period — 65.5 TBD ms
34 TIOZ I/O High-Impedance from MCLR — 2 — μs
Low or Watchdog Timer Reset
35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005)
36 TIRVST Time for Internal Reference — 20 50 μs
Voltage to become Stable
37 TLVD Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD
38 TCSD CPU Start-up Time 5 — 10 μs
39 TIOBST Time for INTRC to Stabilize — 1 — ms
Legend: TBD = To Be Determined

PIC18F2450/4450
FIGURE 21-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
TABLE 21-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
42 Tt0P T0CKI Period No prescaler TCY + 10 — ns
With prescaler Greater of: — ns N = prescale
20 ns or value
(TCY + 40)/N (1, 2, 4,..., 256)
45 Tt1H T1CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns
Time Synchronous, PIC18FXXXX 10 — ns
with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
46 Tt1L T1CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns
Time Synchronous, PIC18FXXXX 10 — ns
with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
47 Tt1P T1CKI Input Synchronous Greater of: — ns N = prescale
Period 20 ns or value (1, 2, 4, 8)
(TCY + 40)/N
Asynchronous 60 — ns
Ft1 T1CKI Oscillator Input Frequency Range DC 50 kHz
48 Tcke2tmrI Delay from External T1CKI Clock Edge to Timer 2 TOSC 7 TOSC —
Increment

PIC18F2450/4450
FIGURE 21-10: CAPTURE/COMPARE/PWM TIMINGS (CCP MODULE)
CCP1
(Capture Mode)
50 51
52
CCP1
(Compare or PWM Mode)
53 54
TABLE 21-12: CAPTURE/COMPARE/PWM REQUIREMENTS

Param
No.
50 TccL CCP1 Input No prescaler 0.5 TCY + 20 — ns
Low Time With PIC18FXXXX 10 — ns
prescaler PIC18LFXXXX 20 — ns VDD = 2.0V
51 TccH CCP1 Input No prescaler 0.5 TCY + 20 — ns
High Time With PIC18FXXXX 10 — ns
prescaler PIC18LFXXXX 20 — ns VDD = 2.0V
52 TccP CCP1 Input Period 3 TCY + 40 — ns N = prescale
N value (1, 4 or 16)
53 TccR CCP1 Output Fall Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
54 TccF CCP1 Output Fall Time PIC18FXXXX — 25 ns

PIC18F2450/4450
FIGURE 21-11: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin 121 121
RC7/RX/DT
pin
120
122
TABLE 21-13: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param
No.
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
121 Tckrf Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns
(Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V
122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
FIGURE 21-12: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
TABLE 21-14: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
No.
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns

PIC18F2450/4450
FIGURE 21-13: USB SIGNAL TIMING
USB Data Differential Lines
90%
VCRS
10%
TLR, TFR TLF, TFF
TABLE 21-15: USB LOW-SPEED TIMING REQUIREMENTS

Param
No.
TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF
TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF
TLRFM Rise/Fall Time Matching 80 — 125 %
TABLE 21-16: USB FULL-SPEED REQUIREMENTS

Param
No.
TFR Transition Rise Time 4 — 20 ns CL = 50 pF
TFF Transition Fall Time 4 — 20 ns CL = 50 pF
TFRFM Rise/Fall Time Matching 90 — 111.1 %

PIC18F2450/4450
TABLE 21-17: A/D CONVERTER CHARACTERISTICS: PIC18F2450/4450 (INDUSTRIAL)
PIC18LF2450/4450 (INDUSTRIAL)
Param
No.
A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V
A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A06 EOFF Offset Error — — <±1.5 LSb ΔVREF ≥ 3.0V
A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V
A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range 1.8 — — V VDD < 3.0V
(VREFH – VREFL) 3 — — V VDD ≥ 3.0V
A21 VREFH Reference Voltage High VSS — VREFH V
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage VREFL — VREFH V
A30 ZAIN Recommended Impedance of — — 2.5 kΩ
Analog Voltage Source
A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition.
— — 150 μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 21-14: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
A/D DATA 9 8 7 ... ... 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF TCY(1)
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

PIC18F2450/4450
TABLE 21-18: A/D CONVERSION REQUIREMENTS
Param
No.
130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V
(1)
PIC18LFXXXX 1.4 25.0 μs VDD = 2.0V,
TOSC based, VREF full range
PIC18FXXXX TBD 1 μs A/D RC mode
PIC18LFXXXX TBD 3 μs VDD = 2.0V,
A/D RC mode
131 TCNV Conversion Time 11 12 TAD
(not including acquisition time)(2)
132 TACQ Acquisition Time(3) 1.4 — μs -40°C to +85°C
TBD — μs 0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample — (Note 4)
137 TDIS Discharge Time 0.2 — μs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.

PIC18F2450/4450
22.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
23.0 PACKAGING INFORMATION
23.1 Package Marking Information
28-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXXXXX PIC18F2450-I/SP e3
XXXXXXXXXXXXXXXXX 0510017
YYWWNNN
28-Lead SOIC Example
XXXXXXXXXXXXXXXXXXXX PIC18F2450-E/SO e3
XXXXXXXXXXXXXXXXXXXX 0510017
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead QFN Example
XXXXXXXX 18F2450
XXXXXXXX -I/ML e3
YYWWNNN 0510017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC18F2450/4450
Package Marking Information (Continued)
40-Lead PDIP Example
XXXXXXXXXXXXXXXXXX PIC18F4450-I/P e3
XXXXXXXXXXXXXXXXXX 0510017
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead TQFP Example
XXXXXXXXXX PIC18F4450
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0510017
YYWWNNN
44-Lead QFN Example
XXXXXXXXXX PIC18F4450
XXXXXXXXXX -I/ML e3
XXXXXXXXXX 0510017
YYWWNNN

PIC18F2450/4450
23.2 Package Details
The following sections give the technical details of the
packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
E1
2
n 1 α
E
A2
L
c
β A1 B1
eB B p
Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 28 28
Pitch p .100 2.54
Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06
Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26
Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49
Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65
Lower Lead Width B .016 .019 .022 0.41 0.48 0.56
Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070

PIC18F2450/4450
28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)
E
E1
p
B
2
n 1
h
α
45°
c
A A2
φ
β L A1

Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Overall Length D .695 .704 .712 17.65 17.87 18.08
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle Top φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .013 0.23 0.28 0.33
Lead Width B .014 .017 .020 0.36 0.42 0.51
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052

PIC18F2450/4450
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) –
With 0.55 mm Contact Length (Saw Singulated)
E E2
EXPOSED
METAL
PAD
(NOTE 2)
D D2 b
1 K
OPTIONAL ALTERNATE SEE DETAIL

L
INDEX INDEX
TOP VIEW AREA INDICATORS BOTTOM VIEW
(NOTE 1)
A1
A
DETAIL
ALTERNATE
PAD OUTLINE
Units INCHES MILLIMETERS*

Pitch e .026 BSC 0.65 BSC
Overall Height A .031 .035 .039 0.80 0.90 1.00
Standoff A1 .000 .001 .002 0.00 0.02 0.05
Contact Thickness A3 .008 REF 0.20 REF
Overall Width E .232 .236 .240 5.90 6.00 6.10
Exposed Pad Width E2 .153 .167 .169 3.89 4.24 4.29
Overall Length D .232 .236 .240 5.90 6.00 6.10
Exposed Pad Length D2 .153 .167 .169 3.89 4.24 4.29
Contact Width β .009 .011 .013 0.23 0.28 0.33
Contact Length § L .018 .022 .024 0.45 0.55 0.65
Contact-to-Exposed Pad § K .008 – – 0.20 – –
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exposed pad varies according to die attach paddle size.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC equivalent: MO-220
Revised 09-12-05
Drawing No. C04-105

PIC18F2450/4450
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
E1
2 α
n 1
A A2
L
c
β B1
A1
eB B p

Pitch p .100 2.54
Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88
Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45
Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016

PIC18F2450/4450
44-Lead Plastic Thin-Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45°
α
A
c
φ
β A1 A2
L F

Pitch p .031 0.80
Pins per Side n1 11 11
Overall Height A .039 .043 .047 1.00 1.10 1.20
Standoff A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Footprint (Reference) F .039 REF. 1.00 REF.
Foot Angle φ 0 3.5 7 0 3.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
See ASME Y14.5M
JEDEC Equivalent: MS-026
Drawing No. C04-076 Revised 07-22-05

PIC18F2450/4450
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
E EXPOSED
METAL PAD K
(NOTE 2)
D D2
2 B
1
n PIN 1
OPTIONAL INDEX ON E2
INDEX AREA EXPOSED PAD L
(NOTE 1) (PROFILE MAY VARY)
TOP VIEW BOTTOM VIEW
DETAIL: CONTACT VARIANTS
A3 A1

Number of Contacts n 44 44
Pitch p .026 BSC 0.65 BSC
Overall Height A .031 .035 .039 0.80 0.90 1.00
Standoff A1 .000 .001 .002 0 0.02 0.05
Base Thickness A3 .010 REF 0.25 REF
Overall Width E .309 .315 .321 7.85 8.00 8.15
Exposed Pad Width E2 .236 .258 .260 5.99 6.55 6.60
Overall Length D .309 .315 .321 7.85 8.00 8.15
Exposed Pad Length D2 .236 .258 .260 5.99 6.55 6.60
Contact Width B .008 .013 .013 0.20 0.33 0.35
Contact Length § L .014 .016 .019 0.35 0.40 0.48
Contact-to-Exposed-Pad § K .014 - - 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exposed pad varies according to die attach paddle size.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
See ASME Y14.5M
JEDEC equivalent: M0-220
Drawing No. C04-103 Revised 09-12-05

PIC18F2450/4450
APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE
DIFFERENCES
Revision A (January 2006)
The differences between the devices listed in this data
Original data sheet for PIC18F2450/4450 devices. sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES

Features PIC18F2450 PIC18F4450
Program Memory (Bytes) 16384 16384
Program Memory (Instructions) 8192 8192
Interrupt Sources 13 13
I/O Ports Ports A, B, C, (E) Ports A, B, C, D, E
Capture/Compare/PWM Modules 1 1
10-bit Analog-to-Digital Module 10 input channels 13 input channels
Packages 28-pin SDIP 40-pin PDIP
28-pin SOIC 44-pin TQFP
28-pin QFN 44-pin QFN

PIC18F2450/4450
APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM
CONSIDERATIONS BASELINE TO
This appendix discusses the considerations for ENHANCED DEVICES
converting from previous versions of a device to the This section discusses how to migrate from a Baseline
ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device
are due to the differences in the process technology (i.e., PIC18FXXX).
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B. The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available

PIC18F2450/4450
APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM
MID-RANGE TO HIGH-END TO
ENHANCED DEVICES ENHANCED DEVICES
A detailed discussion of the differences between the A detailed discussion of the migration pathway and
mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e.,
enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e.,
AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. This Application Note is
specific, are generally applicable to all mid-range to available as Literature Number DS00726.
enhanced device migrations.
This Application Note is available as Literature Number
DS00716.

PIC18F2450/4450
NOTES:

PIC18F2450/4450
INDEX
A Fail-Safe Clock Monitor ........................................... 204
Generic I/O Port ......................................................... 99
A/D ................................................................................... 173
High/Low-Voltage Detect with External Input .......... 184
Acquisition Requirements ........................................ 178
Interrupt Logic ............................................................ 86
ADCON0 Register .................................................... 173
On-Chip Reset Circuit ................................................ 41
ADCON1 Register .................................................... 173
PIC18F2450 .............................................................. 10
ADCON2 Register .................................................... 173
PIC18F4450 .............................................................. 11
ADRESH Register ............................................ 173, 176
PLL (HS Mode) .......................................................... 26
ADRESL Register .................................................... 173
PWM Operation (Simplified) .................................... 127
Analog Port Pins, Configuring .................................. 180
Reads from Flash Program Memory ......................... 77
Associated Registers ............................................... 182
Table Read Operation ............................................... 73
Configuring the Module ............................................ 177
Table Write Operation ............................................... 74
Conversion Clock (TAD) ........................................... 179
Conversion Requirements ....................................... 292 Table Writes to Flash Program Memory .................... 79
Timer0 in 16-Bit Mode ............................................. 112
Conversion Status (GO/DONE Bit) .......................... 176
Conversions ............................................................. 181 Timer0 in 8-Bit Mode ............................................... 112
Converter Characteristics ........................................ 291 Timer1 ..................................................................... 116
Timer1 (16-Bit Read/Write Mode) ............................ 116
Converter Interrupt, Configuring .............................. 177
Discharge ................................................................. 181 Timer2 ..................................................................... 122
Operation in Power-Managed Modes ...................... 180 USB Interrupt Logic Funnel ..................................... 143
USB Peripheral and Options ................................... 129
Selecting and Configuring Acquisition Time ............ 179
Special Event Trigger (CCP1) .................................. 182 Watchdog Timer ...................................................... 201
Use of the CCP1 Trigger .......................................... 182 BN .................................................................................... 220
BNC ................................................................................. 221
Absolute Maximum Ratings ............................................. 265
AC (Timing) Characteristics ............................................. 281 BNN ................................................................................. 221
Load Conditions for Device BNOV .............................................................................. 222
BNZ ................................................................................. 222
Timing Specifications ....................................... 282
Parameter Symbology ............................................. 281 BOR. See Brown-out Reset.
BOV ................................................................................. 225
Temperature and Voltage Specifications ................. 282
BRA ................................................................................. 223
Timing Conditions .................................................... 282
Brown-out Reset (BOR) ..................................................... 44
AC Characteristics
Detecting ................................................................... 44
Internal RC Accuracy ............................................... 284
Disabling in Sleep Mode ............................................ 44
ADCON0 Register ............................................................ 173
Software Enabled ...................................................... 44
GO/DONE Bit ........................................................... 176
ADCON1 Register ............................................................ 173 BSF .................................................................................. 223
BTFSC ............................................................................. 224
ADCON2 Register ............................................................ 173
ADDFSR .......................................................................... 254 BTFSS ............................................................................. 224
ADDLW ............................................................................ 217 BTG ................................................................................. 225
BZ .................................................................................... 226
ADDULNK ........................................................................ 254
ADDWF ............................................................................ 217 C
ADDWFC ......................................................................... 218
C Compilers
ADRESH Register ............................................................ 173
MPLAB C18 ............................................................. 262
ADRESL Register .................................................... 173, 176
MPLAB C30 ............................................................. 262
Analog-to-Digital Converter. See A/D.
CALL ................................................................................ 226
ANDLW ............................................................................ 218
CALLW ............................................................................ 255
ANDWF ............................................................................ 219
Capture (CCP Module) .................................................... 124
Assembler
Associated Registers ............................................... 126
MPASM Assembler .................................................. 262
CCP1 Pin Configuration .......................................... 124
Auto-Wake-up on Sync Break Character ......................... 166
CCPR1H:CCPR1L Registers .................................. 124
B Prescaler ................................................................. 124
Software Interrupt .................................................... 124
BC .................................................................................... 219
BCF .................................................................................. 220 Capture/Compare/PWM (CCP) ....................................... 123
Capture Mode. See Capture.
Block Diagrams
CCP Mode and Timer Resources ............................ 124
A/D ........................................................................... 176
CCPR1H Register ................................................... 124
Analog Input Model .................................................. 177
CCPR1L Register .................................................... 124
Capture Mode Operation ......................................... 124
Compare Mode. See Compare.
Compare Mode Operation ....................................... 125
Module Configuration .............................................. 124
Device Clock .............................................................. 24
Clock Sources .................................................................... 30
EUSART Receive .................................................... 164
Selection Using OSCCON Register .......................... 30
EUSART Transmit ................................................... 162
CLRF ............................................................................... 227
External Power-on Reset Circuit
CLRWDT ......................................................................... 227
(Slow VDD Power-up) ......................................... 43

PIC18F2450/4450
Code Examples DC Characteristics ........................................................... 276
16 x 16 Signed Multiply Routine ................................ 84 Power-Down and Supply Current ............................ 268
16 x 16 Unsigned Multiply Routine ............................ 84 Supply Voltage ........................................................ 267
8 x 8 Signed Multiply Routine .................................... 83 DCFSNZ .......................................................................... 231
8 x 8 Unsigned Multiply Routine ................................ 83 DECF ............................................................................... 230
Changing Between Capture Prescalers ................... 124 DECFSZ .......................................................................... 231
Computed GOTO Using an Offset Value ................... 56 Dedicated ICD/ICSP Port ................................................ 209
Erasing a Flash Program Memory Row ..................... 78 Development Support ...................................................... 261
Fast Register Stack .................................................... 56 Device Differences ........................................................... 303
How to Clear RAM (Bank 1) Using Device Overview .................................................................. 7
Indirect Addressing ............................................ 67 Features (table) ........................................................... 9
Implementing a Real-Time Clock Using New Core Features ...................................................... 7
a Timer1 Interrupt Service ............................... 119 Other Special Features ................................................ 8
Initializing PORTA ...................................................... 99 Direct Addressing .............................................................. 68
Initializing PORTB .................................................... 101
Initializing PORTC .................................................... 104 E
Initializing PORTD .................................................... 107 Effect on Standard PIC MCU Instructions ....................... 258
Initializing PORTE .................................................... 109 Electrical Characteristics ................................................. 265
Reading a Flash Program Memory Word .................. 77 Enhanced Universal Synchronous Receiver
Saving STATUS, WREG and Transmitter (USART). See EUSART.
BSR Registers in RAM ....................................... 97 Equations
Writing to Flash Program Memory ....................... 80–81 A/D Acquisition Time ............................................... 178
Code Protection ............................................................... 189 A/D Minimum Charging Time ................................... 178
COMF ............................................................................... 228 Calculating the Minimum Required
Compare (CCP Module) ................................................... 125 A/D Acquisition Time ....................................... 178
Associated Registers ............................................... 126 Errata ................................................................................... 6
CCP1 Pin Configuration ........................................... 125 EUSART
CCPR1 Register ...................................................... 125 Asynchronous Mode ................................................ 162
Software Interrupt .................................................... 125 Associated Registers, Receive ........................ 165
Special Event Trigger ............................................... 125 Associated Registers, Transmit ....................... 163
Timer1 Mode Selection ............................................ 125 Auto-Wake-up on Sync Break ......................... 166
Configuration Bits ............................................................. 190 Break Character Sequence ............................. 167
Configuration Register Protection .................................... 209 Receiver .......................................................... 164
Context Saving During Interrupts ....................................... 97 Setting Up 9-Bit Mode with Address Detect .... 164
Conversion Considerations .............................................. 304 Transmitter ...................................................... 162
CPFSEQ .......................................................................... 228 Baud Rate Generator (BRG) ................................... 157
CPFSGT ........................................................................... 229 Associated Registers ....................................... 157
CPFSLT ........................................................................... 229 Auto-Baud Rate Detect .................................... 160
Crystal Oscillator/Ceramic Resonator ................................ 25 Baud Rate Error, Calculating ........................... 157
Customer Change Notification Service ............................ 315 Baud Rates, Asynchronous Modes ................. 158
Customer Notification Service .......................................... 315 High Baud Rate Select (BRGH Bit) ................. 157
Customer Support ............................................................ 315 Operation in Power-Managed Modes .............. 157
Sampling .......................................................... 157
D Synchronous Master Mode ...................................... 168
Data Addressing Modes ..................................................... 67 Associated Registers, Receive ........................ 170
Comparing Addressing Modes with Associated Registers, Transmit ....................... 169
the Extended Instruction Set Enabled ................ 71 Reception ........................................................ 170
Direct .......................................................................... 67 Transmission ................................................... 168
Indexed Literal Offset ................................................. 70 Synchronous Slave Mode ........................................ 171
BSR Operation ................................................... 72 Associated Registers, Receive ........................ 172
Instructions Affected .......................................... 70 Associated Registers, Transmit ....................... 171
Mapping the Access Bank ................................. 72 Reception ........................................................ 172
Indirect ....................................................................... 67 Transmission ................................................... 171
Inherent and Literal .................................................... 67 Extended Instruction Set .................................................. 253
Data Memory ...................................................................... 59 ADDFSR .................................................................. 254
Access Bank .............................................................. 61 ADDULNK ................................................................ 254
and the Extended Instruction Set ............................... 70 and Using MPLAB IDE Tools ................................... 260
Bank Select Register (BSR) ....................................... 59 CALLW .................................................................... 255
General Purpose Registers ........................................ 61 Considerations for Use ............................................ 258
Map for PIC18F2450/4450 Devices ........................... 60 MOVSF .................................................................... 255
Special Function Registers ........................................ 62 MOVSS .................................................................... 256
Map .................................................................... 62 PUSHL ..................................................................... 256
USB RAM ................................................................... 59 SUBFSR .................................................................. 257
DAW ................................................................................. 230 SUBULNK ................................................................ 257
DC and AC Characteristics Syntax ...................................................................... 253
Graphs and Tables .................................................. 293 External Clock Input ........................................................... 26

PIC18F2450/4450
F Instruction Cycle ................................................................ 57
Fail-Safe Clock Monitor ............................................ 189, 204 Clocking Scheme ....................................................... 57
Interrupts in Power-Managed Modes ....................... 205 Flow/Pipelining .......................................................... 57
Instruction Set .................................................................. 211
POR or Wake-up from Sleep ................................... 205
WDT During Oscillator Failure ................................. 204 ADDLW .................................................................... 217
Fast Register Stack ............................................................ 56 ADDWF ................................................................... 217
ADDWF (Indexed Literal Offset mode) .................... 259
Firmware Instructions ....................................................... 211
Flash Program Memory ..................................................... 73 ADDWFC ................................................................. 218
Associated Registers ................................................. 81 ANDLW .................................................................... 218
ANDWF ................................................................... 219
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74 BC ............................................................................ 219
TABLAT (Table Latch) Register ......................... 76 BCF ......................................................................... 220
BN ............................................................................ 220
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78 BNC ......................................................................... 221
Erasing ....................................................................... 78 BNN ......................................................................... 221
BNOV ...................................................................... 222
Operation During Code-Protect ................................. 81
Protection Against Spurious Writes ........................... 81 BNZ ......................................................................... 222
Reading ...................................................................... 77 BOV ......................................................................... 225
BRA ......................................................................... 223
Table Pointer
Boundaries Based on Operation ........................ 76 BSF .......................................................................... 223
Table Pointer Boundaries .......................................... 76 BSF (Indexed Literal Offset mode) .......................... 259
BTFSC ..................................................................... 224
Table Reads and Table Writes .................................. 73
Unexpected Termination of Write .............................. 81 BTFSS ..................................................................... 224
Write Sequence ......................................................... 79 BTG ......................................................................... 225
BZ ............................................................................ 226
Write Verify ................................................................ 81
Writing To ................................................................... 79 CALL ........................................................................ 226
FSCM. See Fail-Safe Clock Monitor. CLRF ....................................................................... 227
CLRWDT ................................................................. 227
G COMF ...................................................................... 228
GOTO .............................................................................. 232 CPFSEQ .................................................................. 228
CPFSGT .................................................................. 229
H CPFSLT ................................................................... 229
Hardware Multiplier ............................................................ 83 DAW ........................................................................ 230
Introduction ................................................................ 83 DCFSNZ .................................................................. 231
Operation ................................................................... 83 DECF ....................................................................... 230
Performance Comparison .......................................... 83 DECFSZ .................................................................. 231
High/Low-Voltage Detect ................................................. 183 General Format ....................................................... 213
Applications .............................................................. 186 GOTO ...................................................................... 232
Associated Registers ............................................... 187 INCF ........................................................................ 232
Characteristics ......................................................... 280 INCFSZ .................................................................... 233
Current Consumption ............................................... 185 INFSNZ .................................................................... 233
Effects of a Reset ..................................................... 187 IORLW ..................................................................... 234
Operation ................................................................. 184 IORWF ..................................................................... 234
During Sleep .................................................... 187 LFSR ....................................................................... 235
Setup ........................................................................ 185 MOVF ...................................................................... 235
Start-up Time ........................................................... 185 MOVFF .................................................................... 236
Typical Application ................................................... 186 MOVLB .................................................................... 236
HLVD. See High/Low-Voltage Detect. MOVLW ................................................................... 237
MOVWF ................................................................... 237
I MULLW .................................................................... 238
I/O Ports ............................................................................. 99 MULWF ................................................................... 238
ID Locations ............................................................. 189, 209 NEGF ....................................................................... 239
Idle Modes ......................................................................... 37 NOP ......................................................................... 239
INCF ................................................................................. 232 Opcode Field Descriptions ...................................... 212
INCFSZ ............................................................................ 233 POP ......................................................................... 240
In-Circuit Debugger .......................................................... 209 PUSH ....................................................................... 240
In-Circuit Serial Programming (ICSP) ...................... 189, 209 RCALL ..................................................................... 241
Indexed Literal Offset Addressing RESET ..................................................................... 241
and Standard PIC18 Instructions ............................. 258 RETFIE .................................................................... 242
Indexed Literal Offset Mode ............................................. 258 RETLW .................................................................... 242
Indirect Addressing ............................................................ 68 RETURN .................................................................. 243
INFSNZ ............................................................................ 233 RLCF ....................................................................... 243
Initialization Conditions for all Registers ...................... 49–52 RLNCF ..................................................................... 244

PIC18F2450/4450
RRCF ....................................................................... 244 MOVWF ........................................................................... 237
RRNCF .................................................................... 245 MPLAB ASM30 Assembler, Linker, Librarian .................. 262
SETF ........................................................................ 245 MPLAB ICD 2 In-Circuit Debugger .................................. 263
SETF (Indexed Literal Offset mode) ........................ 259 MPLAB ICE 2000 High-Performance
SLEEP ..................................................................... 246 Universal In-Circuit Emulator ................................... 263
Standard Instructions ............................................... 211 MPLAB ICE 4000 High-Performance
SUBFWB .................................................................. 246 Universal In-Circuit Emulator ................................... 263
SUBLW .................................................................... 247 MPLAB Integrated Development
SUBWF .................................................................... 247 Environment Software ............................................. 261
SUBWFB .................................................................. 248 MPLAB PM3 Device Programmer ................................... 263
SWAPF .................................................................... 248 MPLINK Object Linker/MPLIB Object Librarian ............... 262
TBLRD ..................................................................... 249 MULLW ............................................................................ 238
TBLWT ..................................................................... 250 MULWF ............................................................................ 238
TSTFSZ ................................................................... 251
XORLW .................................................................... 251 N
XORWF .................................................................... 252 NEGF ............................................................................... 239
INTCON Register NOP ................................................................................. 239
RBIF Bit .................................................................... 101
INTCON Registers ............................................................. 87
O
Internal Oscillator Block Oscillator Configuration ..................................................... 23
INTHS, INTXT, INTCKO and INTIO Modes ............... 27 EC .............................................................................. 23
Internal RC Oscillator ECIO .......................................................................... 23
Use with WDT .......................................................... 201 ECPIO ....................................................................... 23
Internet Address ............................................................... 315 ECPLL ....................................................................... 23
Interrupt Sources .............................................................. 189 HS .............................................................................. 23
A/D Conversion Complete ....................................... 177 HSPLL ....................................................................... 23
Capture Complete (CCP) ......................................... 124 INTCKO ..................................................................... 23
Compare Complete (CCP) ....................................... 125 Internal Oscillator Block ............................................. 27
Interrupt-on-Change (RB7:RB4) .............................. 101 INTHS ........................................................................ 23
INTn Pin ..................................................................... 97 INTIO ......................................................................... 23
PORTB, Interrupt-on-Change .................................... 97 INTXT ........................................................................ 23
TMR0 ......................................................................... 97 Oscillator Modes and USB Operation ........................ 24
TMR0 Overflow ........................................................ 113 XT .............................................................................. 23
TMR1 Overflow ........................................................ 115 XTPLL ........................................................................ 23
TMR2 to PR2 Match (PWM) .................................... 127 Oscillator Selection .......................................................... 189
Interrupts ............................................................................ 85 Oscillator Settings for USB ................................................ 27
USB ............................................................................ 85 Oscillator Start-up Timer (OST) ................................... 32, 45
Interrupts, Flag Bits Oscillator Switching ........................................................... 30
Interrupt-on-Change (RB7:RB4) Flag Oscillator Transitions ......................................................... 30
(RBIF Bit) ......................................................... 101 Oscillator, Timer1 ............................................................. 115
INTOSC, INTRC. See Internal Oscillator Block.
P
IORLW ............................................................................. 234
IORWF ............................................................................. 234 Packaging Information ..................................................... 295
IPR Registers ..................................................................... 94 Details ...................................................................... 297
Marking .................................................................... 295
L PICSTART Plus Development Programmer .................... 264
LFSR ................................................................................ 235 PIE Registers ..................................................................... 92
Low-Voltage ICSP Programming. Pin Functions
See Single-Supply ICSP Programming. MCLR/VPP/RE3 ................................................... 12, 16
NC/ICCK/ICPGC ........................................................ 21
M NC/ICDT/ICPGD ........................................................ 21
Master Clear Reset (MCLR) ............................................... 43 NC/ICPORTS ............................................................. 21
Memory Organization ......................................................... 53 NC/ICRST/ICVPP ....................................................... 21
Data Memory ............................................................. 59 OSC1/CLKI .......................................................... 12, 16
Program Memory ....................................................... 53 OSC2/CLKO/RA6 ................................................ 12, 16
Memory Programming Requirements .............................. 278 RA0/AN0 .............................................................. 13, 17
Microchip Internet Web Site ............................................. 315 RA1/AN1 .............................................................. 13, 17
Migration from Baseline to Enhanced Devices ................ 304 RA2/AN2/VREF- ................................................... 13, 17
Migration from High-End to Enhanced Devices ............... 305 RA3/AN3/VREF+ .................................................. 13, 17
Migration from Mid-Range to Enhanced Devices ............. 305 RA4/T0CKI/RCV .................................................. 13, 17
MOVF ............................................................................... 235 RA5/AN4/HLVDIN ................................................ 13, 17
MOVFF ............................................................................. 236 RB0/AN12/INT0 ................................................... 14, 18
MOVLB ............................................................................. 236 RB1/AN10/INT1 ................................................... 14, 18
MOVLW ............................................................................ 237 RB2/AN8/INT2/VMO ............................................ 14, 18
MOVSF ............................................................................ 255 RB3/AN9/VPO ..................................................... 14, 18
MOVSS ............................................................................ 256 RB4/AN11/KBI0 ................................................... 14, 18

PIC18F2450/4450
RB5/KBI1/PGM .................................................... 14, 18 Postscaler, WDT
RB6/KBI2/PGC .................................................... 14, 18 Assignment (PSA Bit) .............................................. 113
RB7/KBI3/PGD .................................................... 14, 18 Rate Select (T0PS2:T0PS0 Bits) ............................. 113
RC0/T1OSO/T1CKI ............................................. 15, 19 Power-Managed Modes ..................................................... 33
RC1/T1OSI/UOE .................................................. 15, 19 and A/D Operation ................................................... 180
RC2/CCP1 ........................................................... 15, 19 Clock Sources ........................................................... 33
RC4/D-/VM ........................................................... 15, 19 Clock Transitions and Status Indicators .................... 34
RC5/D+/VP .......................................................... 15, 19 Effects on Various Clock Sources ............................. 32
RC6/TX/CK .......................................................... 15, 19 Entering ..................................................................... 33
RC7/RX/DT .......................................................... 15, 19 Exiting Idle and Sleep Modes .................................... 39
RD0 ............................................................................ 20 by Interrupt ........................................................ 39
RD1 ............................................................................ 20 by Reset ............................................................ 39
RD2 ............................................................................ 20 by WDT Time-out .............................................. 39
RD3 ............................................................................ 20 Without an Oscillator Start-up Delay ................. 40
RD4 ............................................................................ 20 Idle ............................................................................. 37
RD5 ............................................................................ 20 Idle Modes
RD6 ............................................................................ 20 PRI_IDLE .......................................................... 38
RD7 ............................................................................ 20 RC_IDLE ........................................................... 39
RE0/AN5 .................................................................... 21 SEC_IDLE ......................................................... 38
RE1/AN6 .................................................................... 21 Multiple Sleep Commands ......................................... 34
RE2/AN7 .................................................................... 21 Run Modes ................................................................ 34
VDD ...................................................................... 15, 21 PRI_RUN ........................................................... 34
VSS ....................................................................... 15, 21 RC_RUN ............................................................ 35
VUSB ..................................................................... 15, 21 SEC_RUN ......................................................... 34
Pinout I/O Descriptions Selecting .................................................................... 33
PIC18F2450 ............................................................... 12 Sleep ......................................................................... 37
PIC18F4450 ............................................................... 16 Summary (table) ........................................................ 33
PIR Registers ..................................................................... 90 Power-on Reset (POR) ...................................................... 43
PLL Frequency Multiplier ................................................... 26 Power-up Delays ............................................................... 32
HSPLL, XTPLL, ECPLL and ECPIO Power-up Timer (PWRT) ............................................. 32, 45
Oscillator Modes ................................................ 26 Prescaler, Timer0 ............................................................ 113
PLL Lock Time-out ............................................................. 45 Assignment (PSA Bit) .............................................. 113
POP ................................................................................. 240 Rate Select (T0PS2:T0PS0 Bits) ............................. 113
POR. See Power-on Reset. Prescaler, Timer2 ............................................................ 128
PORTA PRI_IDLE Mode ................................................................. 38
Associated Registers ............................................... 100 PRI_RUN Mode ................................................................. 34
I/O Summary ............................................................ 100 Program Counter ............................................................... 54
LATA Register ............................................................ 99 PCL, PCH and PCU Registers .................................. 54
PORTA Register ........................................................ 99 PCLATH and PCLATU Registers .............................. 54
TRISA Register .......................................................... 99 Program Memory
PORTB and the Extended Instruction Set .............................. 70
Associated Registers ............................................... 103 Code Protection ....................................................... 207
I/O Summary ............................................................ 102 Instructions ................................................................ 58
LATB Register .......................................................... 101 Two-Word .......................................................... 58
PORTB Register ...................................................... 101 Interrupt Vector .......................................................... 53
RB7:RB4 Interrupt-on-Change Flag Look-up Tables .......................................................... 56
(RBIF Bit) ......................................................... 101 Map and Stack (diagram) .......................................... 53
TRISB Register ........................................................ 101 Reset Vector .............................................................. 53
PORTC Program Verification and Code Protection ...................... 206
Associated Registers ............................................... 106 Associated Registers ............................................... 206
I/O Summary ............................................................ 105 Programming, Device Instructions ................................... 211
LATC Register ......................................................... 104 Pulse-Width Modulation. See PWM (CCP Module).
PORTC Register ...................................................... 104 PUSH ............................................................................... 240
TRISC Register ........................................................ 104 PUSH and POP Instructions .............................................. 55
PORTD PUSHL ............................................................................. 256
Associated Registers ............................................... 108 PWM (CCP Module)
I/O Summary ............................................................ 108 Associated Registers ............................................... 128
LATD Register ......................................................... 107 Duty Cycle ............................................................... 127
PORTD Register ...................................................... 107 Example Frequencies/Resolutions .......................... 128
TRISD Register ........................................................ 107 Period ...................................................................... 127
PORTE Setup for PWM Operation ....................................... 128
Associated Registers ............................................... 110 TMR2 to PR2 Match ................................................ 127
I/O Summary ............................................................ 110
LATE Register .......................................................... 109 Q
PORTE Register ...................................................... 109 Q Clock ............................................................................ 128
TRISE Register ........................................................ 109

PIC18F2450/4450
R UEPn (USB Endpoint n Control) .............................. 135
RAM. See Data Memory. UIE (USB Interrupt Enable) ..................................... 145
RC_IDLE Mode .................................................................. 39 UIR (USB Interrupt Status) ...................................... 144
USTAT (USB Status) ............................................... 134
RC_RUN Mode .................................................................. 35
RCALL .............................................................................. 241 WDTCON (Watchdog Timer Control) ...................... 202
RCON Register RESET ............................................................................. 241
Reset State of Registers .................................................... 48
Bit Status During Initialization .................................... 48
Reader Response ............................................................ 316 Reset Timers ..................................................................... 45
Register File Summary ................................................. 63–65 Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Registers
ADCON0 (A/D Control 0) ......................................... 173 Power-up Timer (PWRT) ........................................... 45
ADCON1 (A/D Control 1) ......................................... 174 Resets ........................................................................ 41, 189
Brown-out Reset (BOR) ........................................... 189
ADCON2 (A/D Control 2) ......................................... 175
BAUDCON (Baud Rate Control) .............................. 156 Oscillator Start-up Timer (OST) ............................... 189
BDnSTAT (Buffer Descriptor n Status, Power-on Reset (POR) ............................................ 189
Power-up Timer (PWRT) ......................................... 189
CPU Mode) ...................................................... 139
BDnSTAT (Buffer Descriptor n Status, RETFIE ............................................................................ 242
SIE Mode) ........................................................ 140 RETLW ............................................................................ 242
RETURN .......................................................................... 243
CCP1CON (Capture/Compare/PWM
Control) ............................................................ 123 Return Address Stack ........................................................ 54
CONFIG1H (Configuration 1 High) .......................... 192 and Associated Registers .......................................... 54
Return Stack Pointer (STKPTR) ........................................ 55
CONFIG1L (Configuration 1 Low) ............................ 191
CONFIG2H (Configuration 2 High) .......................... 194 Revision History ............................................................... 303
CONFIG2L (Configuration 2 Low) ............................ 193 RLCF ............................................................................... 243
RLNCF ............................................................................. 244
CONFIG3H (Configuration 3 High) .......................... 195
CONFIG4L (Configuration 4 Low) ............................ 196 RRCF ............................................................................... 244
CONFIG5H (Configuration 5 High) .......................... 197 RRNCF ............................................................................ 245
CONFIG5L (Configuration 5 Low) ............................ 197 S
SEC_IDLE Mode ............................................................... 38
SEC_RUN Mode ................................................................ 34
SETF ................................................................................ 245
Single-Supply ICSP Programming ................................... 210
DEVID1 (Device ID 1) .............................................. 200
SLEEP ............................................................................. 246
DEVID2 (Device ID 2) .............................................. 200
Sleep
EECON1 (Memory Control 1) .................................... 75
OSC1 and OSC2 Pin States ...................................... 32
HLVDCON (High/Low-Voltage
Sleep Mode ........................................................................ 37
Detect Control) ................................................. 183
Software Simulator (MPLAB SIM) ................................... 262
INTCON (Interrupt Control) ........................................ 87
Special Event Trigger. See Compare (CCP Module).
INTCON2 (Interrupt Control 2) ................................... 88
Special Features of the CPU ........................................... 189
INTCON3 (Interrupt Control 3) ................................... 89
Special ICPORT Features ............................................... 209
IPR1 (Peripheral Interrupt Priority 1) .......................... 94
Stack Full/Underflow Resets .............................................. 56
IPR2 (Peripheral Interrupt Priority 2) .......................... 95
STATUS Register .............................................................. 66
OSCCON (Oscillator Control) .................................... 31
SUBFSR .......................................................................... 257
PIE1 (Peripheral Interrupt Enable 1) .......................... 92
SUBFWB ......................................................................... 246
PIE2 (Peripheral Interrupt Enable 2) .......................... 93
SUBLW ............................................................................ 247
PIR1 (Peripheral Interrupt Request
SUBULNK ........................................................................ 257
(Flag) 1) ............................................................. 90
SUBWF ............................................................................ 247
PIR2 (Peripheral Interrupt Request
SUBWFB ......................................................................... 248
(Flag) 2) ............................................................. 91
SWAPF ............................................................................ 248
PORTE ..................................................................... 109
RCON (Reset Control) ......................................... 42, 96 T
RCSTA (Receive Status and Control) ...................... 155 T0CON Register
STATUS ..................................................................... 66 PSA Bit .................................................................... 113
STKPTR (Stack Pointer) ............................................ 55
T0CS Bit .................................................................. 112
T0CON (Timer0 Control) .......................................... 111 T0PS2:T0PS0 Bits ................................................... 113
T1CON (Timer1 Control) .......................................... 115
T0SE Bit .................................................................. 112
T2CON (Timer2 Control) .......................................... 121 Table Pointer Operations (table) ........................................ 76
TXSTA (Transmit Status and Control) ..................... 154 Table Reads/Table Writes ................................................. 56
UCFG (USB Configuration) ...................................... 132
TBLRD ............................................................................. 249
UCON (USB Control) ............................................... 130 TBLWT ............................................................................. 250
UEIE (USB Error Interrupt Enable) .......................... 147 Time-out in Various Situations (table) ................................ 45
UEIR (USB Error Interrupt Status) ........................... 146
Time-out Sequence ........................................................... 45

PIC18F2450/4450
Timer0 .............................................................................. 111 Send Break Character Sequence ............................ 167
16-Bit Mode Timer Reads and Writes ...................... 112 Slow Rise Time (MCLR Tied to VDD,
Associated Registers ............................................... 113 VDD Rise > TPWRT) ............................................ 47
Clock Source Edge Select (T0SE Bit) ...................... 112 Synchronous Reception
Clock Source Select (T0CS Bit) ............................... 112 (Master Mode, SREN) ..................................... 170
Operation ................................................................. 112 Synchronous Transmission ..................................... 168
Overflow Interrupt .................................................... 113 Synchronous Transmission (Through TXEN) .......... 169
Prescaler .................................................................. 113 Time-out Sequence on POR w/PLL Enabled
Switching Assignment ...................................... 113 (MCLR Tied to VDD) .......................................... 47
Prescaler. See Prescaler, Timer0. Time-out Sequence on Power-up
Timer1 .............................................................................. 115 (MCLR Not Tied to VDD), Case 1 ...................... 46
16-Bit Read/Write Mode ........................................... 117 Time-out Sequence on Power-up
Associated Registers ....................................... 119, 126 (MCLR Not Tied to VDD), Case 2 ...................... 46
Interrupt .................................................................... 118 Time-out Sequence on Power-up
Operation ................................................................. 116 (MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
Oscillator .......................................................... 115, 117 Timer0 and Timer1 External Clock .......................... 287
Layout Considerations ..................................... 118 Transition for Entry to Idle Mode ............................... 38
Low-Power Option ........................................... 117 Transition for Entry to SEC_RUN Mode .................... 34
Using Timer1 as a Clock Source ..................... 117 Transition for Entry to Sleep Mode ............................ 37
Overflow Interrupt .................................................... 115 Transition for Two-Speed Start-up
Resetting, Using a Special Event Trigger (INTOSC to HSPLL) ........................................ 203
Output (CCP) ................................................... 118 Transition for Wake from Idle to
TMR1H Register ...................................................... 115 Run Mode .......................................................... 38
TMR1L Register ....................................................... 115 Transition for Wake from Sleep (HSPLL) .................. 37
Use as a Real-Time Clock ....................................... 118 Transition from RC_RUN Mode to
Timer2 .............................................................................. 121 PRI_RUN Mode ................................................. 36
Associated Registers ............................................... 122 Transition from SEC_RUN Mode to
Interrupt .................................................................... 122 PRI_RUN Mode (HSPLL) .................................. 35
Operation ................................................................. 121 Transition to RC_RUN Mode ..................................... 36
Output ...................................................................... 122 USB Signal .............................................................. 290
PR2 Register ............................................................ 127 Timing Diagrams and Specifications ............................... 283
TMR2 to PR2 Match Interrupt .................................. 127 Capture/Compare/PWM
Timing Diagrams Requirements (CCP) ....................................... 288
A/D Conversion ........................................................ 291 CLKO and I/O Requirements ................................... 285
Asynchronous Reception ......................................... 165 EUSART Synchronous Receive
Asynchronous Transmission .................................... 163 Requirements .................................................. 289
Asynchronous Transmission EUSART Synchronous Transmission
(Back to Back) ................................................. 163 Requirements .................................................. 289
Automatic Baud Rate Calculation ............................ 161 External Clock Requirements .................................. 283
Auto-Wake-up Bit (WUE) During PLL Clock ................................................................ 284
Normal Operation ............................................ 166 Reset, Watchdog Timer, Oscillator Start-up
Auto-Wake-up Bit (WUE) During Sleep ................... 166 Timer, Power-up Timer and Brown-out
BRG Overflow Sequence ......................................... 161 Reset Requirements ........................................ 286
Brown-out Reset (BOR) ........................................... 286 Timer0 and Timer1 External Clock
Capture/Compare/PWM (CCP) ................................ 288 Requirements .................................................. 287
CLKO and I/O .......................................................... 284 USB Full-Speed Requirements ............................... 290
Clock/Instruction Cycle .............................................. 57 USB Low-Speed Requirements ............................... 290
EUSART Synchronous Receive Top-of-Stack Access .......................................................... 54
(Master/Slave) ................................................. 289 TQFP Packages and Special Features ........................... 209
EUSART Synchronous Transmission TSTFSZ ........................................................................... 251
(Master/Slave) ................................................. 289 Two-Speed Start-up ................................................. 189, 203
External Clock (All Modes Except PLL) ................... 283 Two-Word Instructions
Fail-Safe Clock Monitor ............................................ 205 Example Cases ......................................................... 58
High/Low-Voltage Detect Characteristics ................ 280 TXSTA Register
High-Voltage Detect (VDIRMAG = 1) ...................... 186 BRGH Bit ................................................................. 157
Low-Voltage Detect (VDIRMAG = 0) ....................... 185
PWM Output ............................................................ 127
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) .................................................. 285

PIC18F2450/4450
U W
Universal Serial Bus ........................................................... 59 Watchdog Timer (WDT) ........................................... 189, 201
Address Register (UADDR) ..................................... 136 Associated Registers ............................................... 202
Associated Registers ............................................... 149 Control Register ....................................................... 201
Buffer Descriptor Table ............................................ 137 During Oscillator Failure .......................................... 204
Buffer Descriptors .................................................... 137 Programming Considerations .................................. 201
Address Validation ........................................... 140 WWW Address ................................................................ 315
Assignment in Different WWW, On-Line Support ...................................................... 6
Buffering Modes ....................................... 142
BDnSTAT Register (CPU Mode) ..................... 138 X
BDnSTAT Register (SIE Mode) ....................... 140 XORLW ............................................................................ 251
Byte Count ....................................................... 140 XORWF ........................................................................... 252
Example ........................................................... 137
Memory Map .................................................... 141
Ownership ........................................................ 137
Ping-Pong Buffering ......................................... 141
Register Summary ........................................... 142
Status and Configuration ................................. 137
Class Specifications and Drivers ............................. 151
Descriptors ............................................................... 151
Endpoint Control ...................................................... 135
Enumeration ............................................................. 151
External Transceiver ................................................ 131
Eye Pattern Test Enable .......................................... 133
Firmware and Drivers ............................................... 148
Frame Number Registers ......................................... 136
Frames ..................................................................... 150
Internal Transceiver ................................................. 131
Internal Voltage Regulator ....................................... 133
Interrupts .................................................................. 143
and USB Transactions ..................................... 143
Layered Framework ................................................. 150
Oscillator Requirements ........................................... 148
Output Enable Monitor ............................................. 133
Overview .......................................................... 129, 150
Ping-Pong Buffer Configuration ............................... 133
Power ....................................................................... 150
Power Modes ........................................................... 148
Bus Power Only ............................................... 148
Dual Power with Self-Power
Dominance ............................................... 148
Self-Power Only ............................................... 148
Pull-up Resistors ...................................................... 133
RAM ......................................................................... 136
Memory Map .................................................... 136
Speed ....................................................................... 151
Status and Control ................................................... 130
Transfer Types ......................................................... 150
UFRMH:UFRML Registers ...................................... 136
USB
Internal Voltage Regulator Specifications ................ 279
Module Specifications .............................................. 279
USB. See Universal Serial Bus.

PIC18F2450/4450
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PIC18F2450/4450
READER RESPONSE
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PIC18F2450/4450
PIC18F2450/4450 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC18LF4450-I/P 301 = Industrial temp., PDIP
Range package, Extended VDD limits, QTP pattern
#301.
b) PIC18LF2450-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device PIC18F2450(1), PIC18F4450(1), c) PIC18F4450-I/P = Industrial temp., PDIP
PIC18F2450T(2), PIC18F4450(2); package, normal VDD limits.
VDD range 4.2V to 5.5V
PIC18LF2450(1), PIC18LF4450(1),
PIC18LF2450(2), PIC18LF4450(2);
VDD range 2.0V to 5.5V
Temperature Range I = -40°C to +85°C (Industrial)

E = -40°C to +125°C (Extended)
Package PT = TQFP (Thin Quad Flatpack) Note 1: F = Standard Voltage Range

SO = SOIC
SP = Skinny Plastic DIP LF = Wide Voltage Range
P = PDIP 2: T = in tape and reel TQFP
ML = QFN packages only.
Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

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10/31/05

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PIC18F2450/4450

© 2006 Microchip Technology Inc. Advance Information DS39760A

Information contained in this publication regarding device Trademarks

Microchip received ISO/TS-16949:2002 quality system certification for

DS39760A-page ii Advance Information © 2006 Microchip Technology Inc.

Program Memory Data

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 1

28-Pin SDIP, SOIC

Note: Pinouts are subject to change.

DS39760A-page 2 Advance Information © 2006 Microchip Technology Inc.

Note: Pinouts are subject to change.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 3

Note: Pinouts are subject to change.

DS39760A-page 4 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 5

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS39760A-page 6 Advance Information © 2006 Microchip Technology Inc.

1.1.2 UNIVERSAL SERIAL BUS (USB)

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 7

DS39760A-page 8 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 9

Data Latch RA0/AN0

CCP1 EUSART USB

DS39760A-page 10 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 11

DS39760A-page 12 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 13

DS39760A-page 14 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 15

DS39760A-page 16 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 17

DS39760A-page 18 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 19

RD0 19 38 38 I/O ST Digital I/O.

RD1 20 39 39 I/O ST Digital I/O.

RD2 21 40 40 I/O ST Digital I/O.

RD3 22 41 41 I/O ST Digital I/O.

RD4 27 2 2 I/O ST Digital I/O.

RD5 28 3 3 I/O ST Digital I/O.

RD6 29 4 4 I/O ST Digital I/O.

RD7 30 5 5 I/O ST Digital I/O.

DS39760A-page 20 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 21

DS39760A-page 22 Advance Information © 2006 Microchip Technology Inc.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 23

FIGURE 2-1: PIC18F2450/4450 CLOCK DIAGRAM

PLLDIV USB Clock Source

101 (4 MHz Input Only)

Primary Oscillator 100 96 MHz ÷2 1

OSCCON<6:4> Internal Oscillator

Clock Source Option

WDT, PWRT, FSCM

DS39760A-page 24 Advance Information © 2006 Microchip Technology Inc.

The oscillator design requires the use of a parallel cut XT 4 MHz 27 pF 27 pF

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 25

OSC1/CLKI FIGURE 2-6: PLL BLOCK DIAGRAM

FIGURE 2-5: EXTERNAL CLOCK Loop