CMOS VLSI Design

Question Bank

UNIT I

1. Explain nMOS enhancement transistor.

2. What is Metal Oxide Semiconductor Field Effect Transistor?
3. How many terminals are present in MOS?
4. What do you mean by Enhancement type MOSFET?
5. What are the different regions in which the MOS transistor operates?
6. Show the V-I characteristic of NMOS.
7. Explain pMOS enhancement transistor.
8. Explain threshold voltage & drive threshold voltage equation.
9. Explain Body effect.
10. What is body affect? Discuss different parameters on which threshold voltage
depends?
11. Derive an equation for Ids of an n-channel enhancement MOSFET operating in
saturation region.
12. Explain MOS device design equations.
13. Explain Second Order Effects.
14. Explain doping process in CMOS technology & also explain all types of doping
process in brief.
15. Write a short note on Small Signal AC Characteristics.
16. Drive all required parameter for small signal model.
17. Explain Threshold voltage body effect.
18. Explain Subthreshold Region.
19. Write a short note on
a) Drain Punchthrough.
b) Small Signal AC Characteristics.
20. What is nMOS?
21. (a) Derive the relationship between drain to source current Ids and drain to source
voltage Vds in non saturation and saturation region
(b) Sketch the Ids versus Vds graph for enhancement mode device.
22. What is pMOS?
23. What do you mean by MOSFET?
24. Which material is used to make Gate, Drain and Source?
25. Explain Channel-length Modulation.
26. Explain Mobility Variation.
27. Explain Drain Punchthrough.
28. What are the two basic technologies?
29. Derive an equation for Transconductance of an n channel enhancement MOS-FET
operating in active region.
30. What do you mean by MOS Technology?
31. Explain small signal AC characteristics of MOSFET with its design equations.
 32. Explain Impact Ionization- Hot electrons.
33. Write a short note on
a) Subthreshold Region
b) Channel-length Modulation
34. What is the difference between MOS Capacitor and MOSFET?
35. What do you mean by effective channel length?
36. What do you mean by effective channel length modulation?
37. Define channel length modulation effect on MOSFET with I-V characteristic.
38. Write down all Design rules with appropriate diagram.

UNIT I - Numerical

1. Calculate the native threshold voltage for an n-transistor at 300k for a process
with a Si substrate with NA = 1.8 x 1016 at SiO2 gate oxide with thickness 200A
assume ms = -0.9V, Qfe = 0.
2. Consider the nMOS transistor in a 65 nm process with a nominal threshold voltage
of 0.3 V and a doping level of 8 1017 cm-3. The body is tied to ground with a
substrate contact. How much does the threshold change at room temperature if the
source is at 0.6 V instead of 0V?
3. Consider the nMOS transistor in a 0.6 m process with gate oxide thickness of
100. The doping level is NA = 2 1017 cm-3 and the nominal threshold voltage is
0.7 V. The body is tied to ground with a substrate contact. How much does the
threshold change at room temperature if the source is at 4 V instead of 0?
4. An NMOS Transistor is operated in the triode region with the following
parameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; nCox = 90 A/V2
Find its drain current and drain source resistance.
5. Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10;
nCox = 92A/V2. A PMOS transistor is operated in triode region with the
following parameters. VGS= - 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, nCox
=95A/V2. Find its drain current and drain source resistance.
6.
UNIT II

1. Explain a basic n-well process.

2. Draw the layout for CMOS inverter.
3. What do you mean by CMOS Inverter?
4. What is Wafer Processing? Explain.
5. What is Oxidation? Explain.
6. Explain different fabrication process of CMOS transistor
7. What are Epitaxy, Deposition, Ion-Implantation and Diffusion? Explain.
8. Write a short note on Twin-tub process.
9. Explain a basic p-well process.
10. What are the various cmos technologies?
11. What is twin tub process? Why it is so called?
12. Write a note on Layout Design Rules.
13. Why design rules are essential for fabrication of CMOS ICS.
14. Design the physical layout of
(a) NAND gate and
(b) NOR gate
15. Explain Latch up. How it can be avoided?
16. What are the Layout design rules?
17. What do you mean by Layout, Physical and symbolic?
18. What do you mean by stick diagrams?
19. Is there any difference between Layout and Stick diagrams?
20. Explain briefly the Silicon on Insulator technology with regard to CMOS logic.
21. Draw CMOS logic gate for this given function F by all possible way and select the
optimized circuit.
F = (A+BC)D
Do the transistor sizing (According to 180nm technology) for this gate. Draw all
possible Euler paths for the above given function F. On the basis of Euler paths,
sketch the stick diagram and actual layout of the given function and also estimate
the approximate area of the gate from its layout.
22. Explain basic CMOS fabrication steps with appropriate sketch.
23. Design a stick diagram and layout diagram for the CMOS logic given as :
__________
Y = (A + B) (C + D).

24. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR
gate.
25.
26. Consider the design of a CMOS compound OR-AND-INVERT gate Computing
F = /[(A + B) C].
 a) sketch a transistor-level schematic.
b) sketch a stick diagram.
c) sketch a Layout diagram.
d) Estimate the area from the Layout diagram.
27. Consider the design of a CMOS compound OR-AND-INVERT gate Computing
F = / [(A + B) (C + D)].
a) sketch a transistor-level schematic.
b) sketch a stick diagram.
c) sketch a Layout diagram.
d) Estimate the area from the Layout diagram.
28. A carry look-ahead adder computes A = G3 + P3(G2 + P2(G1 + P1G0)). Consider
Designing a compound gate to compute .
a) sketch a transistor-level schematic
b) sketch a stick diagram
c) estimate the area from the stick diagram
29. With neat sketches necessary, explain the oxidation process in the IC fabrication
process.
30. Explain the following terms related to the fabrication of IC
(a) Diffusion
(b) Oxidation
(c) Lithography
(d) Metallization.
31. Briefly discuss the steps involved in the manufacturing process of an IC.
32. Describe Ion implantation mechanism in IC fabrication.
33. Describe in detail, the diffusion process in IC fabrication.
34. Describe in detail metallization process in IC technology.
UNIT III

1. Explain briefly about MOS transistor switch.

2. Explain the concept of MOSFET as switches
3. What do you mean by Compound gate?
4. What do you mean by Combinational gates?
5. Implement the equation Z = /[(A+B)(C+D+E) F] using depletion load NMOS
design technique, size the devices so that the output resistance is same as that of an
inverter with driver (W/L) = 1.
6. Explain Saturated Load Inverters.
7. What do you mean by switching characteristics?
8. What do you mean by inverter?
9. What do you mean by Static load inverter?
10. Implement the pass transistor logic circuit for the expression Y = A + BC. Show the
design steps clearly.
11. Design a circuit to compute F = AB + CD using NANDs and NORs.
12. Find the value at the point P mentioned in the circuit shown in figure 1 for the
given values and explain it. VDD=5V; VTn=1V; logic1=5V

Fig.:1

13. Design a 2- input EX-OR gate and 4X1 MUX using Transmission gate Logic.
14. Use a combination of CMOS gates to generate the following functions.
(a) Z = A.B + /A. /B (XNOR)
(b) Z = A. /B. /C +/A. /B.C + /A. /C.B +A.B.C
15. Design CMOS logic gates for the following function.
a) Z = /(A.B.C.D)
b) Z = /(A+B+C+D)
16. Design CMOS logic gates for the following function.
a) Z = /[(A.B.C)+D]
b) Z = [(A.B)+C. (A+B)]

17. Design a 4:1 multiplexer using only CMOS logic gates.

18. Write a short note on the Transmission Gate.
19. Draw the Cmos circuit for half adder. (Inverted i/ps are allowed).
20. In the circuit shown in fig. below, find VI, V2, V3, V4 and V5. Justify your answer.
21. Design a 4:1 multiplexer using a combination of CMOS switches and logic gates.
22. Design a 2-input multiplexer that uses CMOS logic gates in place of CMOS
switches.

23. Differentiate between Pass Transistor logic and transmission gate logic.
24. Sketch a transistor-level schematic for a compound CMOS logic gate for each of
the following functions:
a) Y = /[ABC + D]
b) Y = /[(AB + C) D]
c) Y = /[AB + C (A + B)]
25. Give an expression for the output voltage for the pass transistor networks shown in
Figure below. Neglect the body effect.

26. Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in Figure below for the
following. Neglect the body effect.
a) Vin = 0 V
b) Vin = 0.6 V
c) Vin = 0.9 V
d) Vin = 1.2 V.
 27.

UNIT IV

28. What are the advantages of CMOS process?

29. Explain Complementary CMOS Inverter.
30. Explain DC characteristic of CMOS Inverter.
31. Explain bn/bp Ratio.
32. Explain the five regions of operation of CMOS inverter DC transfer characteristic.
Hence write the equations for Vout in the different regions.
33. Explain Noise Margin.
34. The CMOS Inverter as an Amplifier, explain.
35. What is Static Load MOS Inverters, explain.
36. What is Noise Margin for CMOS?
37. What do you mean by BI-CMOS technology?
38. (a) What are the advantages of BICMOS Technology over CMOS Technology?
(b) Explain how a bipolar NPN transistor is included in N well CMOS processing
Draw the cross section of BICMOS transistor.

39. style from the transfer characteristics.

40. Explain the Tristate Inverter.
41. Explain the Transmission gate and the Tristate inverter.
42. Explain the operation of BiCMOS inverter? Clearly specify its characteristics.
43. Write a short note on BICMOS Inverters.
44. Write short notes on
(i) Noise Margin, (ii) Rise Time, (iii) Fall Time.
45. Derive the VOH and VOL for resistive load inverter using an nMOS transistor.
46. Derive the VIH and VIL for resistive load inverter using an nMOS transistor.
47. Implement given functions using Resistive load logic.
(a) Z = A.B + /A. /B (XNOR)
(b) Z = A. /B. /C +/A. /B.C + /A. /C.B +A.B.C
 48. Implement given functions using nMOS load logic.
(a) Z = A.B + /A. /B (XNOR)
(b) Z = A. /B. /C +/A. /B.C + /A. /C.B +A.B.C
49. Implement given functions using pMOS load logic.
(a) Z = A.B + /A. /B (XNOR)
(b) Z = A. /B. /C +/A. /B.C + /A. /C.B +A.B.C
50. What is bn/bp Ratio?
51. Design a 4:1 multiplexer using a combination of CMOS switches and logic gates.
& using only CMOS logic gates. Assess the efficiency of each implementation by
counting the total number of switches used in each implementation. Which is more
efficient? Why?
52. Briefly discuss about the following :
a) Resistive Load inverter
b) nMOS Load inverter
c) Bi-CMOS inverter

UNIT IV- Numerical

1. A CMOS inverter is built in a process where kn=100A/V2, Vtn=+0.7V, k'p =42

A/V2 , Vtp=-0.8V, and a power supply of VDD =3.33V is used .Find (INV
Threshold voltage) mid point voltage VM if (W/L)n =10 and (W/L)p= 14.

2. Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L)
=10;nCox =92 A/V2 and Vds =Veff+0.5V, the output impedance constant _ =
95.3 10-3/V-1.
3. In a 0.5m process n=44.69 x 10-3 m2/V, tox = 14.lnm and the (W/L) = 30/5. The
NMOS has Vt =0.71V and Vgs= 1.5V. At what levels of Vds and id, will the
MOSFET reach pinch off mode? Hint: (ox= 3.9o)

UNIT V

1. What do you mean by Rise time?

2. What do you mean by Fall time?
3. What do you mean by Delay time?
4. Explain Resistance Estimation.
5. Explain Contact and Via Resistance.
6. Explain Capacitance and resistance Estimation.
7. Explain MOS Capacitor Characteristics.
8. Explain MOS Device Capacitances.
 9. Estimate tpdf and tpdr for the 3-input NAND gate. If the output is loaded with h
identical NAND gates.
10. Explain SPICE Modeling of MOS capacitances.
11. What is Fall Time? Explain
12. What is Rise Time? Explain
13. What is Delay Time? Explain
14. Write a short note on Power Dissipation.
15. What is Static Dissipation? Explain.
16. What is Dynamic Dissipation? Explain.
17. What is Short-Circuit Dissipation? Explain.
18. Explain total power dissipation.
19. Explain the concept of static and dynamic power dissipation in CMOS circuits.
20. What is fan-out?
21. What is Static power dissipation for CMOS?
22. What is Input impedance for CMOS?
23. What is Fan-out for CMOS?
24. Find the rising and falling propagation delays of an unloaded AND-OR-INVERT
gate using the Elmore delay model. Estimate the diffusion capacitance based on a
stick diagram of the layout.
25. State various components of power dissipation in CMOS circuits.
26. What do you mean by Edge Triggered D-Register?
27. What do you mean by Rising Edge Triggered D-Register?
28. Discuss how the rise time and fall time of an inverter can be made equal. Suggest
schemes to reduce rise and fall time of an inverter.
29. How is the clocking strategies related to the setup and hold time in a latch?
30. Explain the MOS capacitor characteristics for accumulation, depletion, and
inversion region.
31. Write short note on Charge Sharing.
32. With regard to CMOS D-flip-flop explain the terms setup time and hold time.
What is meta-stability?
33. What is Meta-stability? Explain
34. Design a positive level-sensitive D latch in which the Q output, by a signal
RESET, may be reset to O independently of the state of the CLK signal (i.e.
RESET=1 Q=1). This is the basis for an asynchronously resettable latch.
35. Design a positive edge-triggered D register that can be asynchronously set.

UNIT V-Numerical

1. Calculate the diffusion parasitic Cdb of the drain of a unit-sized contacted nMOS
transistor in a 0.6 m process when the drain is at 0 and at VDD = 5 V. Assume
the substrate is grounded. The transistor characteristics are CJ = 0.42 fF/ m2, MJ
=0.44, CJSW = 0.33 fF/m, MJSW = 0.12, and 0 = 0.98 V at room temperature.
2. Calculate the rise time and fall time of the CMOS inverter (W/L)n = 6 and (W/L)p
=8, K'n =150 A/V2, Vtn =0.7V, K'p= 62 A/V2, Vtp=-0.85V , VDD =3.3V. Total
output capacitance =150 fF.
 3.

UNIT VI

1. Explain the Pseudo-nMOS Inverters.

2. Sketch a pseudo-nMOS gate that implements the function
F = /[A(B +C + D) + E F G]
3. Sketch pseudo-nMOS 3-input NAND and NOR gates. Label the transistor widths.
What are the rising, falling, and average logical efforts of each gate?
4. Implement a 3-input NOR gate in dynamic logic and explain its operation.
5. (a) Explain the concept of charge storage and charge leakage associated with pass
Transistor logic.
(b) Draw and explain the basic structure of CVSL logic.
6. What is Domino CMOS logic? Compare it with conventional CMOS logic. Justify
the same with one example each.
7. Explain the working principle of dynamic CMOS logic and clocked CMOS logic of
"Nand" gate.
8. Write technical note on the following:
a. Dynamic CMOS logic
b. Pass Transistor logic
c. Pseudo NMOS logic
9. For the given function f = AB+CA+A(B+D), obtain
(a) CMOS Pass transistor realization
(b) CMOS transistor realization.
(c) Pseudo NMOS realization.
10. (a) Explain the principle of Pass transistor circuit.
(b) Explain the function of D-latch with gate level schematic and CMOS circuit.
11. Realise the following function f = AB+(C+D)(E+F)+GH. Using
(i) Standard CMOS
 (ii) Domino CMOS
12. Describe the principle, working and use of Pseudo NMOS inverter.
13. Explain Dynamic CMOS logic.
14. What do you mean by static load inverters? Derive the output voltage for the pseudo
inverter by discussing its DC transfer characteristics.
15. Sketch 2-input XOR functions using each of the following circuit techniques:
a) Static CMOS
b) Pseudo-nMOS
c) Pass Transistor logic