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    VL5101 Periodical 1

    Uploaded by

    Darwin
    The document contains details of three periodical tests conducted for the subject CMOS Digital VLSI Design. The tests consisted of two parts - Part A with 5 short answer questions carrying 2 marks each and Part B with long answer questions carrying between 3-10 marks. The questions covered topics like static and dynamic CMOS, Elmore's constant, pass transistor logic, sources of power dissipation in CMOS and techniques to reduce it, pipelining approaches and various latches/registers. The performance of the students in each test is analyzed based on their understanding, analyzing and applying abilities for each question. The total marks scored by the students are also recorded along with the maximum marks for overall assessment.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd

    VL5101 Periodical 1

    Uploaded by

    Darwin
    410 views4 pages
    The document contains details of three periodical tests conducted for the subject CMOS Digital VLSI Design. The tests consisted of two parts - Part A with 5 short answer questions carrying 2 marks each and Part B with long answer questions carrying between 3-10 marks. The questions covered topics like static and dynamic CMOS, Elmore's constant, pass transistor logic, sources of power dissipation in CMOS and techniques to reduce it, pipelining approaches and various latches/registers. The performance of the students in each test is analyzed based on their understanding, analyzing and applying abilities for each question. The total marks scored by the students are also recorded along with the maximum marks for overall assessment.

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    VLSI Questions

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    The document contains details of three periodical tests conducted for the subject CMOS Digital VLSI Design. The tests consisted of two parts - Part A with 5 short answer questions carrying 2 marks each and Part B with long answer questions carrying between 3-10 marks. The questions covered topics like static and dynamic CMOS, Elmore's constant, pass transistor logic, sources of power dissipation in CMOS and techniques to reduce it, pipelining approaches and various latches/registers. The performance of the students in each test is analyzed based on their understanding, analyzing and applying abilities for each question. The total marks scored by the students are also recorded along with the maximum marks for overall assessment.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    410 views4 pages

    VL5101 Periodical 1

    Uploaded by

    Darwin
    The document contains details of three periodical tests conducted for the subject CMOS Digital VLSI Design. The tests consisted of two parts - Part A with 5 short answer questions carrying 2 marks each and Part B with long answer questions carrying between 3-10 marks. The questions covered topics like static and dynamic CMOS, Elmore's constant, pass transistor logic, sources of power dissipation in CMOS and techniques to reduce it, pipelining approaches and various latches/registers. The performance of the students in each test is analyzed based on their understanding, analyzing and applying abilities for each question. The total marks scored by the students are also recorded along with the maximum marks for overall assessment.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 4

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    PERIODICAL TEST – II
    Degree & Branch : M.E- VLSI DESIGN Year / Semester: I / I
    Subject Name : CMOS DIGITAL VLSI DESIGN Subject Code : VL5101
    Date : 22-11-2017 (AN) Time: 3.15 P.M– 4.45 P.M
    Maximum Marks : 50 Marks
    Part –A (Any five) 5 x 2 = 10 Marks
    1. Differentiate Static and Dynamic CMOS?
    2. What is Elmore’s constant? Give its expression
    3. Draw the static CMOS logic circuit for the following expression?
    Y=(D(A+BC), y= (A.B.C.D)
    4. State the advantages of Pass Transistor Logic?
    5. Draw the Pass transistor logic for NAND, NOR gate

    Part –B (40 Marks)


    1. Discuss in detail about Dynamic CMOS Circuits (10)
    2. What are the sources of Power Dissipation in CMOS and discuss the various design techniques
    to reduce the power dissipation in CMOS (10)
    3. Explain in detail various pipelining approaches to optimize sequential circuits (10)
    4. (i) Draw the stick and layout diagram for NAND gate (3)
    (ii)Discuss in detail various Static latches and Registers (7)

    Performance Analysis:
    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4 QUESTION-5
    PART A
    UN AN AP UN AN UN AN AP AP UN AN AP UN AN
    -A P

    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4 QUESTION-5


    PART A A
    UN AN AP UN AN UN AN AP UN AN AP UN AN
    -B P P

    Parameter Maximum Marks Marks Scored Percentage


    Understanding
    Analyzing
    Applying
    Total 50

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


    PERIODICAL TEST – I
    Degree & Branch : M.E- VLSI DESIGN Year / Semester: I / I
    Subject Name : CMOS DIGITAL VLSI DESIGN Subject Code : VL5101
    Date : 15-09-2017 (AN) Time: 3.15 P.M– 4.45 P.M
    Maximum Marks : 50 Marks
    Part –A 5 x 2 = 10 Marks
    1. What is Technology scaling? Give types.
    2. Draw the structure of Ripple carry adder and mention its advantages and disadvantages.
    3. Write the principle of array multiplier?
    4. Write short notes on area and speed tradeoff?
    5. Define propagation delay of CMOS inverter

    Part –B (40 Marks)


    1. Explain in detail about the second order effects in MOS Devices (10)
    2. Design a 4 bit Carry look ahead adder and discuss their features (10)
    3. Explain in detail about MOS Transistor Theory. Write the current equation in the three regions
    of operation of a MOS transistor (10)
    4. Discuss about Static CMOS (10)

    Performance Analysis:
    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4 QUESTION-5
    PART A
    UN AN AP UN AN UN AN AP AP UN AN AP UN AN
    -A P

    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4 QUESTION-5


    PART A A
    UN AN AP UN AN UN AN AP UN AN AP UN AN
    -B P P

    Parameter Maximum Marks Marks Scored Percentage


    Understanding
    Analyzing
    Applying
    Total 50

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


    PERIODICAL TEST – III
    Degree & Branch : M.E- VLSI DESIGN Year / Semester: I / I
    Subject Name : CMOS DIGITAL VLSI DESIGN Subject Code : VL5101
    Date : 15-12-2017 (AN) Time: 3.15 P.M– 4.45 P.M
    Maximum Marks : 50 Marks
    Part –A 5 x 2 = 10 Marks
    1. What is Latch up? How to prevent latch up.
    2. How does the transmission gate and pass transistor logic works?
    3. Write short notes on Synchronous, Mesochronous & Piesiochronous Interconnects?
    4. What do you mean by sheet resistance? (pg:145)
    5. Discuss about Pulsed Register and Sense amplifier based registers.

    Part –B (40 Marks)


    1. Explain in detail about
    (i) Self timed Logic (6)
    (ii) Self timed signalling (6)
    2. Discuss about (i) Clock Skew, Clock Jitter (6)
    (ii) Clock Distribution (4)
    3. Explain the operation of Booth multiplier. List its advantages (8)
    4. Give brief notes on Non-bistable Sequential Circuits (10)

    Performance Analysis:
    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4 QUESTION-5
    PART A
    UN AN AP UN AN UN AN AP AP UN AN AP UN AN
    -A P

    QUESTION-1 QUESTION-2 QUESTION-3 QUESTION-4


    PART A
    UN AN AP UN AN UN AN AP UN AN AP
    -B P

    Parameter Maximum Marks Marks Scored Percentage


    Understanding
    Analyzing
    Applying
    Total 50
    VL 5101 – CMOS DIGITAL VLSI DESIGN
    THEORY COURSE FILE
    [REGULATION – 2017]

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