Evolution of Finfets From 22Nm To 7Nm: September 2019

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Evolution of FinFETs from 22nm to 7nm
Thesis · September 2019

DOI: 10.13140/RG.2.2.14696.21764
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Bachelor Thesis
Evolution of FinFETs
from 22nm to 7nm
Veljko Vukicevic
1528008
September 2019
Supervisor: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Gerhard Hobler

Institut für Festkörperelektronik TU Wien
Table of Contents
1 Abstract ................................................................................................................................................. 2
2 Introduction .......................................................................................................................................... 3
3 22nm FinFET .......................................................................................................................................... 6
3.1 Fin shape ....................................................................................................................................... 6
3.2 High-k/Metal Gate Stack ............................................................................................................... 7
3.3 Selective gate sidewall spacer ...................................................................................................... 9
3.4 Diamond-shaped raised source/drain ........................................................................................ 10
3.5 SiGe and SiC lattice mismatch stress .......................................................................................... 11
3.6 Self-aligned silicide contacts ....................................................................................................... 13
3.7 Results ......................................................................................................................................... 14
4 14nm FinFET ........................................................................................................................................ 16
4.1 Fin shape ..................................................................................................................................... 16
4.2 Shallow trench isolation (STI)...................................................................................................... 17
4.3 Source/Drain epitaxy .................................................................................................................. 19
4.4 Crystal orientation effects .......................................................................................................... 20
4.5 High-K/Metal Gate Last ............................................................................................................... 21
4.6 Back end of line (BEOL) ............................................................................................................... 22
4.7 Results ......................................................................................................................................... 23
5 10nm FinFET ........................................................................................................................................ 25
5.1 Low-power, standard performance and high performance FinFET ............................................ 25
5.2 Device simulation ........................................................................................................................ 27
5.2.1 Drift-diffusion (DD) method ................................................................................................ 27
5.2.2 Monte Carlo (MC) method .................................................................................................. 27
5.2.3 Comparison between DD and MC method ......................................................................... 28
6 7nm FinFET .......................................................................................................................................... 31
6.1 SiGe Source/Drain stressors and stress-relaxed buffer (SRB) ..................................................... 31
6.2 Results ......................................................................................................................................... 34
7 Motivation for further simulations ..................................................................................................... 35
8 Conclusion ........................................................................................................................................... 38
9 References .......................................................................................................................................... 39
Evolution of FinFETs from 22nm to 7nm |1

1 Abstract
After reaching the nanometer scale, further scaling has become slower and almost impossible
using the conventional planar transistor. The FinFET has become the industry standard by replacing the
planar MOSFET. This bachelor thesis investigates four different FinFET technology nodes, 22nm, 14nm,
10nm and 7nm, using simulations from the SentaurusTM TCAD Applications Library. Some of the key
features of the FinFET such as the fin shape, diamond-shaped source/drain region, self-aligned silicide
contacts, stress engineering etc. are investigated and their influence is presented through device
simulations. Apart from the simulations, theoretical background on implementation difficulties and
manufacturing process adjustments are mentioned.

2 Introduction
Since the beginning of the 21st century, the humanity has entered a new era of technology. Apart
from obvious examples where the computing power of modern devices has been put to use, computers
started to embed in our everyday lives. From smartphones, smartwatches and self-driving cars to smart-
dishwashers and ovens, the implementation of technology in all aspects of our society is inevitable. This
rapid process was only possible because of the just as rapid development of continuously faster, smaller
and more accessible computers. The two most crucial elements: processing speed and memory, have
been developing roughly according to Moore’s Law [1] that states that the number of transistor on an
integrated circuit will double roughly every 18 months (Fig. 1). The struggle in the last few years to
continue this trend has become more apparent than ever. At the same time, the society relies and expects
this trend to continue. The driving force behind the performance improvement and cost reduction is the
CMOS transistor and its rapid downscaling. However, after reaching the nanometer scale, further scaling
has become slower and almost impossible using the conventional planar transistor architecture.
Figure 1. : The number of transistors on a chip through the years with the logarithmic vertical axis [2]
Some physical phenomena, that used to have a small importance in large-dimension MOSFETs,
are now crucial for the behavior of MOSFETs in the nanometer scale, many of them grouped under the
common name – short channel effect. The leading candidate to replace the planar MOSFET became the
FinFET [3]. Also known as self-aligned double-gate MOSFET, FinFET has a vertical multi-gate structure that
allows superior electrostatics over gate control, thus reducing the short channel effect and allowing the
VLSI (very large scale integration) to continue. The name FinFET comes from a vertical fin-like channel that

is surrounded by the self-aligned gate as represented on the example of 10nm FinFET in Figure 2. Aside
from the suppression of the short channel effect and other performance improvements, FinFET replaced
the planar MOSFET and became the industry standard because of their similarities. Majority of the
fabrication steps are similar if not the same as in a making of the MOSFET, meaning that the technology
is already tested and developed. That makes the mass production of FinFETs much more feasible. With
the first mass produced FinFET chips already on the market, we can observe the transition from
conventional planar MOSFETs to FinFETs happening around the 22nm and 14nm technology node.
Bearing all that in mind, this paper will investigate the four different FinFET technology nodes:
22nm, 14nm, 10nm and 7nm. The start point for this research are the TCAD models as well as the
accompanying documentation of the mentioned transistors provided by Synopsys’s SentaurusTM [4-7]. In
addition to physical properties, the properties of the model itself will also be discussed. There are
numerous differences to conventional models that have to be taken into account when simulating on such
a small scale objects, because some of the simplifications applied on the larger scale transistors are now
producing significantly bigger errors compared to empirical results. This subject will be covered but to a
smaller extent than the physical features. Starting with the 22nm node, we will go through most of the
crucial technological features that make the FinFET structure possible.
Figure 2. General structure of FinFET (left) and cross-section with active dopant concentration (right)

In order to illustrate the evolution of FinFETs, two examples will be mentioned here: Fin dimensions
and doping. Table 1 contains some of the key dimensions that characterize the FinFET. It is noticeable that
not all of the dimensions shrink proportionally. This is due to the fact that the manufacturing process of
the nanometer dimensions with required precision and durability represents a major problem. Apart from
the shrinkage of dimensions of the transistor, the expected increase in number of transistors per area is
also achieved by making the fin pitch and gate pitch tighter (making the FinFETs closer one to another).
Since the TCAD Simulations uses a single FinFET, these dimensions are not mentioned, even though they
can be crucial to the further very large scale integration (VLSI). Three different dimensions for the width
of the fin top at the 14nm will be discussed later together with the general impact of the fin shape on the
device performance.
Tech. node Gate length Wbottom Wtop Fin Height

22nm 25 17 17 40
14nm 25 15 5/10/15 35
10nm 20 8 8 27
7nm 15 7 5 30
Table 1. Characteristic dimensions of all four technology nodes. All dimensions represented in nm
Other example of how the transistors have evolved through the years are their different doping
profiles. Source and drain regions have kept a pretty similar doping concentration through the years, with
the main focus of keeping the steep doping profile (no diffusion into channel region). The most interesting
advancement is in the channel doping concentration. With the constant downsize of the channel
dimensions, smaller number of dopants are required to achieve the same concentration. The number of
dopants became so small that their behavior is not statistically predictable anymore, which brought
unpredictable variations in the transistors performance like threshold voltage variations for example.
Channel dopants became an error source, so a need for an undoped channel region arose [46]. This was
achieved in the last two technology nodes (1e+15 is considered a background concentration). It is also
noticeable that they have a so called channel stop region underneath the channel (22 and 14 nm FinFETs
have the same concentration in both regions so there is actually no channel stop region). These region
should limit the spread of the channel area and prevent the formation of parasitic inversion channel
regions.
Tech. node S/D Channel Channel stop

22nm 1.5e+20 1.5e+19 1.5+19
14nm 2e+20 2e+18 2e+18
10nm 2e+20 1e+15 2e+18
7nm 1e+20 1e+15 2e+18
Table 2. Overview of doping profiles for all four technology nodes.
All concentrations represented in cm-3

3 22nm FinFET
The 22nm node is the first time that a FinFET has become an industry standard, replacing the
planar MOSFETs so it will be the first model that is discussed. Thanks to constant efforts to improve its
structure and characteristics, their complexity is rapidly increasing. A modern FinFET implements different
enhancement technologies such as work function engineering, channel strain engineering, lowering of the
parasitic resistance and advanced fin shaping. The crucial points, many of which can be observed on the
TCAD model used for this paper will be represented in the subsequent sections.
3.1 Fin shape

Even though the mass production of FinFETs is already in progress, there are some process-related
issues that have to be addressed when creating a fin-like 3D structure. For example, the production of a
narrow fin with consistent dimensions is a challenging process. Narrow fins allow further gate scaling, but
at the same time, the extension resistance increases due to the implant damage. Figure 3 shows the
dependency of the extension resistance (RSD) on the fin width. Although the SiGe selective epitaxial growth
(SEG) in the source/drain region clearly improves the resistance issue (SEG will be discussed separately
later in the paper), it has been determined that nMOS suffers severely from fin width scaling [8]. The
reason is the poorer re-crystallization of As-implants compared to BF2 after the extension
implantation/activation.
Figure 3. Extension resistance as a function of fin width for pMOS and nMOS (with and without SEG) [8]
That is why different extension strategies have been tested using the 25nm nMOS with the goal
of recovering the implant damage [9]. As an example, two strategies with different implant and anneal
conditions have been compared and represented in Fig. 4. With the optimized conditions in process B, the
damage due to implantation has been mostly recovered. This improvement did not only reduce the
extension resistance, but the drain-induced barrier lowering (DIBL) and Ion-Ioff ratio have also been
improved.

Figure 4. TEM cross-sectional image in the extension region after implant and anneal. Process B has
better fin quality then process A [9]
The fin width (Wfin) and height (Hfin) are also directly proportional to threshold voltage roll-off with
the Vth decreasing with the increase of width and height. The ratio between these two dimensions should
be reasonable in a way that the produced shape is actually fin-like. If the fin width is much larger than the
fin height, the device exhibits characteristics much closer to the planar MOSFET [10]. The simulated data
in [10] suggests Vth roll-off saturation with the Hfin increase. The critical height needed for the saturation
depends on the fin width so that larger Wfin requires larger Hfin for the saturation to occur.
Furthermore, the dependence between short-channel effects and cross-sectional channel shape
(ergo fin shape) have been investigated [11]. Experiment included three different fin shapes: rectangular,
triangular and trapezoidal that were achieved using the same wet etching process. The rectangular-cross-
section channel device showed almost ideal subthreshold slope, where in the trapezoidal- and triangular-
cross-section-channel devices an increase in subthreshold slope and off current were observed. But it is
believed that the increase comes from the increase of the fin width, so these results are considered
inconclusive. The rectangular cross-section is usually avoided because of the unwanted corner effects in
the fin. Corner effect occurs because of the higher electrical field density in the corners of the fin, causing
the premature inversion. That means that corners have lower threshold voltage than the rest of the fin,
creating independent channels with different threshold voltages [12]. This effect can be observed as a
“hump” on a subthreshold slope. The 22nm TCAD model does not investigate different fin shapes, but
rather uses fixed values. Fin width is 17nm and the fin height 40nm.The influence of different fin shapes
will be further discussed on the following nodes.
3.2 High-k/Metal Gate Stack

During the decades of an already mentioned transistor scaling, there have been certain rules
regarding a steady reduction in dimensions. There are different possibilities regarding the scaling
proportion between certain properties, for example, the voltages on the transistor cannot be scaled as
fast as the rest because of the constant silicon bandgap energy that the potential difference has to
overcome and because of the subthreshold slope that can reach only a limited steepness [3].
Nevertheless, gate oxide thickness is one of the dimensions that is being scaled proportionally with the
rest of the transistor. The conventional MOS devices used SiO2 as a preferred gate insulator for over 40
years, but by the time scaling reached the 65nm node, this layer has become only a few atomic layers
thick and the gate leakage current caused by carrier tunneling has become an inevitable issue. In order to
use a thicker insulator layer, a material with a higher dielectric constant (High-k dielectric insulator) has

to be implemented, so that the gate capacity does not suffer from the thicker dielectric layer [17]. The
equivalent oxide thickness – EOT is a value often used to describe equivalent SiO2 thickness needed to
achieve the same capacity.
There are a lot of materials that have a much higher dielectric value than SiO2 (its dielectric constant
is 3.9), but there are several issues that have to be taken into account when choosing the appropriate
gate insulator that make the choice much harder. High dielectric constant insulators must be stable in
contact with Silicon and gate electrode, as well as thermodynamically and chemically stable so they can
endure the manufacturing process without altering their composition. Moreover, the band gap has to be
proportionally high for electrons as well as holes, so that the insulation works on both type of transistors
[18]. Considering all of the requirements hafnium-based dielectric insulators have become the industry
standard and the FinFET model used in this project is implemented with HfO2 dielectrics. Several problems
have been reported regarding the Si/HfO2 interface, like the decrease in the carrier mobility and creation
of defects that can change the characteristics of the transistor. A thin interfacial SiO2 layer is grown
between these two materials in order to prevent these unwanted effects [18]. It is also worth mentioning
that the HfO2 is much stiffer then the SiO2, what degrades the level of the stress enhancement that can
be applied to the gate.
In addition to this innovation, the gate material itself has also been changed. Namely, the previously
used Poly-Si gate can lead to variation of threshold voltage due to gate depletion effect so the metal gate
has been reintroduced. One of the reasons why polysilicon was used in the first place was the favorable
poly-Si/SiO2 interface, but with the SiO2 gone, metal gate became the leading candidate to replace the
poly-Si. The metal gate candidates must be thermally and chemically stable in contact with the high-k
layer, but also their work function must be compatible to Si (work function that is within 0.2eV of the
conduction- and valence- band edges of silicon) [19]. The material of choice that fulfills these
requirements and is also used in the Sentaurus model is titanium nitride (TiN, also known as tinite) so
called mid-gap metal because its work function is located in the middle of the silicon bandgap. TiN can be
adjusted to function as a metal gate in nFET as well as in pFET. This method implements the nitrogen-
concertation-controlled titanium-nitride (TiNx, x represents the variable nitrogen concertation). It has
been observed that higher nitrogen concentration lowers the TiNx work function (useful for nMOS) and
the lower concentration makes it higher (useful for pMOS) [20]. The described gate stack is represented
in the Figure 5.
This revolution in the gate stack technology also brought new implementation problems and
possibilities. There are two main integration schemes: gate first (GF) and gate last (GL, also known as
replacement metal gate RMG), first and last regarding to whether the gate stack is deposited before or
after the thermal annealing process. The gate first process is the conventional integration process and has
been used with the poly-Si gate, but with the metal gate sensible to higher temperatures, gate last method
had to be investigated. The 22nm model uses the conventional gate first method and the second method
will be further discussed in the next node section of this thesis. The challenge with the GF method is that
the high-K and the metal gate have to withstand S/D thermal activation anneal. TiN changes its work
function when submitted to high temperatures making the unacceptable shift in the threshold voltage of
the transistor one way to deal with this problem is to add an additional capping layer between the metal
and the dielectric layer that helps achieving the desirable work function (Al-based metal for pMOS and La-
based for nMOS) [18]. It is also important to consider the band gap offset when using the SiGe instead of

the traditional Si, so that the work function (and with that the threshold voltage) have to be adjusted
accordingly.
Figure 5. Cross section of gate stack
3.3 Selective gate sidewall spacer

With the FinFET reaching sub-lithographic dimensions, lowering the lithographic pitch through
different methods, like sidewall transfer (SWT) lithography had to be applied. This method uses sidewall
spacers that form on sides of a previously patterned feature that is then selectively etched, leaving the
sidewall spacers behind. Since every feature has two spacers, the pattern left behind has the double
density, achieving the half pitch of the original lithographical mask. Even though this method brings
indispensable improvements to the FinFET manufacturing, there are certain issues to overcome. Namely
implementing SWT in two orthogonal directions, for both fin and gate formation, represented a challenge.
One of the problems is the residual spacer material that is not properly removed from the fin sidewalls
that subsequently interferes with SiGe epitaxial growth of the S/D regions. The residue on the bottom of
the fin sidewalls reduces the overall diamond epi volume thus increasing the parasitic resistance.
Furthermore, the residue creates a certain height offset so the S/D regions grow higher than expected,
which can lead to bridging with the gate electrode.

Figure 6. Suggested process integration to avoid residue on fin sidewalls (right)
One paper [23] proposes using the filling material in which fins are embedded and the gate is not,
since it goes over the fins and is thereby higher. Subsequently the sidewall spacers are formed exclusively
on the gate, more precisely on the top portion of the gate that protrudes from the filling material. Since
the gate and the fins have a SiN layer on top of them, the filling material is etched leaving the fins, the
gate and the newly formed gate spacers behind. This way, no residual material was observed on the fin’s
sidewalls and the epi growth can continue unhindered.
The spacers are left on the gate sidewalls because they are of big importance for the proper
functioning of a FinFET. Firstly, they make the subsequent S/D extension implantation possible and
secondly they reduce the gate-S/D leakage by isolating the possible shorting. Furthermore, the dielectric
constant of a spacer should be low, so that the parasitic capacity between gate and S/D regions remains
as low as possible. The 22nm model uses the conventional SiN spacer, the more advanced low K spacers
will be discussed by the next node where they are implemented.
In the TCAD simulation there is no danger of unetched residue so the process is done
conventionally, however this obstacle in the FinFET production process was worthy of mention.
3.4 Diamond-shaped raised source/drain

As already shown in the previous section (Fig. 3) selective epitaxial growth in the S/D region can
substantially lower the overall parasitic resistance of the FinFET. The epitaxial growth creates a raised
diamond shaped S/D region so that the FinFET has a wider body in the S/D extensions than in the channel
region. To fully understand the benefits of diamond-shaped S/D, two structures were studied: FinFET with
a diamond-shaped epi and FinFET with a vertical epi and flat-top surface [13]. Because of its
unconventional vertical three dimensional structure, the current path in FinFETs is quite different from
the current path in planar FETs. Charge carriers that are running near the bottom of the fin have to cover
longer distance to reach the silicide contacts. It is clear that the diamond-shaped epi brings the silicide
contacts closer, thus reducing the longest carrier path (Fig. 7). In addition, the simulations have shown
that with diamond-shaped epi, as the interface between silicide and Si becomes larger, the current density
spreads more evenly, making the parasitic resistance even lower. These two key features of diamond-
shaped S/D lead to its inevitable part of contemporary FinFET technology.

The fabrication process includes etching of a recess into the S/D regions followed by already mentioned
selective epitaxial growth of the in-situ Boron-doped SiGe (pMOS) or SiC (nMOS). The specific diamond-
shaped structure comes from the wet etching with an OH-based chemistry that creates (111) lateral
planes under the 54.75° angle with (100) plane, creating a diamond-like shape
Figure 7. Cross section of two FinFETs with merged S/D contacts and longest carrier paths to the contact:
Flat-top epi (a) and diamond-shaped epi (b)
In the real fabrication of a FinFET, special epitaxial growth (SEG) is performed to create the
mentioned diamond-shaped structure. In the Sentaurus’s model, this growth is simulated through the
three dimensional nonatomistic Lattice kinetic Monte Carlo (LKMC) Epitaxy. This process consists of
several steps [4]. First, a doped layer is deposited using native LKMC process. Then, the structure is
updated along with mechanics steps. Finally, doping and diffusion are controlled by the continuum solver
(this paper will not dive further into the properties of numerical evaluations such as this one).
3.5 SiGe and SiC lattice mismatch stress

Next to lower parasitic resistance, mechanical stress on the FinFET channel is one of the most crucial
parts of its production, considering the enormous benefits that it brings to the device performance.
Mechanical stress induces changes in the curvature of the energy band structure of Si, making the
effective mass of the electron lower, which is inversely proportional to the mobility of electrons. This
physical phenomenon is put to use by applying tensile stress to nMOS and compressive stress to pMOS
channel region, thus improving the majority charge carrier mobility.
The stress comes from the lattice mismatch between Si and Ge. Germanium has a bigger lattice
constant then silicon which leads to strain between Si1-xGex and Si areas. The bigger the Ge content, the
higher the induced strain, though the mobility enhancement can reach a saturation point after a certain
percentage of germanium content. There are several drawbacks to the implementation of SiGe, one of
which is the low thermal conductivity of SiGe that can be a crucial problem by high performance devices.
The conventional type of SiGe induced strain was so called global biaxial strain. This method uses
the thin Si layer that is epitaxially grown on a relaxed SiGe substrate. The already mentioned lattice

mismatch between Si and SiGe creates a layer of biaxially strained silicon that increases the mobility in
the channel region [14].
Unlike the traditional biaxial strain technique where strain is applied from the bottom of the
channel, the more efficient uniaxial strain is introduced from the side using Si1-xGex for pMOS [15] and Si:C
for nMOS [16]. The main advantage of uniaxial strain compared to biaxial is surely the much higher
mobility gain, with coefficients of approx. 4.0 and 1.7 for holes and electrons, respectively. The
comparison between the two techniques has been represented in Figure 8. Furthermore under the large
vertical electrical fields, biaxial strain shows near zero mobility improvement, which became a problem
since this is a typical operating regime of a nanoscale MOSFET. Lastly, it is crucial for CMOS technology
that tensile and compressive strain can be locally applied on nMOS and pMOS transistors respectively, the
requirement that the global biaxial strain simply does not meet. All these drawbacks lead to the further
research and development of the uniaxial strain.
To produce a tensile strain, an element with a smaller atomic size than the silicon is needed, that is
why the carbon is used to create embedded SiC source and drain regions. During the epitaxial growth, P
is in-situ doped, followed by thermal annealing. It is also interesting that adding the GeH4 during the
etching process, enhances the etching rate of the undesired amorphous SiC that forms on top of the epi
hardmask [16].
Figure 8. Strain enhanced hole mobility: uniaxial and biaxial strain compared [16]
Considering the trade-offs between higher mobility and downsides of high Ge concentration
(lower thermal conductivity, higher leakage current because SiGe approaches the metallurgical junction),
its percentage must be chosen carefully. Our Sentaurus model uses the Si0.7Ge3 ratio so that germanium
mole fraction is 30%. The percentage of carbon is on the other hand much lower, around 1% and it
produces a lattice constant 0.5% smaller than that of Si. There are several problems connected to the SiC
stressors, one of which is the difficulty of growing SiC stressors with higher C content due to low solid
solubility of C in Si.

Figure 9. Parallel component of stress along the channel (Syy) for nFinFET (left) and pFinFET (right)
The Figure 9 shows the simulated stress modell of 22nm FinFETs where the tensile and compressive
strain for the NFinFET and PFinFET, respectively, is observable. In addition to uniaxial strain induced by
S/D epi pockets, there are several other stress factors that have to be taken into account, they will be
covered later in this paper.
3.6 Self-aligned silicide contacts

As the scaling continues, lowering the contact resistivity of a transistor has become one of the top
priorities for the future of VLSI (very large scale integration) technology. As the conventional CoSi2 contact
produced parasitic resistance that was intolerably high compared to the channel resistance, a new contact
with lower resistance had to be implemented. This was achieved by lowering the Schottky barrier height
for the current carriers between the contact material and the semiconductor (Si, SiGe or SiC) by using self-
aligned silicide contacts.
The silicide approach uses thin metal layer that reacts with the semiconductor on the surface
creating a silicide layer that provides low energy contact, simultaneously lowering the resistance as well
as improving the thermal characteristics. Considering the CMOS technology, one approach is to use two
different metals with appropriate work functions such as erbium (Er) for nMOS and platinum (Pt) for
pMOS contacts. This method is undesirable due to complexity that the integration of two different silicides
can bring into the manufacturing process [21]. The second approach uses the same contact metal for both
nMOS and pMOS with additional tuning of the work function. There are several criteria used when
choosing the adequate metal for silicidation. The metal should consume as least semiconductor as
possible and it should reach its low resistivity phase on a relatively low temperature. Nickel silicide (NiSi)
is the preferred silicide for this purpose and it is also used in the TCAD model for this paper. Its work

function is manipulated via implantation of other elements so that it can provide a low barrier contact for
both type of transistors (Al for nMOS and S for pMOS).
The salicide process consists of a physical vapor deposition of a thin metal film over the whole
transistor structure, annealing to form silicides and wet etching of the rest metal. In order to lower the
silicide resistance (reaching the low resistivity phase), an additional annealing process is performed
subsequently. The name salicide stands for self-aligned silicide, referring that the silicide will be formed
only in contact with Si and not on the oxide regions, so the process does not require a hard mask. This is
possible due to the fact that metal reacts much faster with the Si than with the SiO2 and furthermore the
following wet etch has been developed to etch the metal that has not reacted much faster than the silicide
[22]. This ensures that the silicide is formed in the contact regions only where Si is exposed. By formation
of a NiSi layer on a FinFET structure it is reported that higher annealing temperatures are needed
compared to the conventional planar MOSFET due to different silicide grain formation on the side walls
of the fin.
The reaction between the metal and Si can positively act upon any previously existing defects on
the Si surface, thus lowering the contact resistance additionally. It has also been reported that NiSi exerts
tensile stress on the channel and can bring around 8% enhancement in the Ion/Ioff characteristics of an
nMOS [16]. Furthermore self-aligned process can achieve smaller spacing between contacts since it does
not require lithography. One of the disadvantages of silicidation is the possible bridging between contacts
due to lateral silicide formation that can result in a short circuit. Furthermore, uncontrolled silicide growth
on shallow junction can lead to silicide protrusion into the junction zone and junction leakage.
In our TCAD simulation the salicide process is simplified. Namely, the semiconductor that is
consumed by the silicidation is etched first and then nickel silicide is deposited in its place selectively.
3.7 Results
This section will represent some of the most important characteristics obtained from the simulation
of 22nm pMOS as well as nMOS FinFET. Figure 10 shows the drain current (Id) over gate voltage (Vg) for
both transistors. Two different drain biases were simulated: 0.05 V and 1 V to demonstrate linear and
saturation characteristics of the transistor (Linear – Lin and Saturation – Sat, respectively).

Figure 10. Drain current versus gate voltage for pFET (left) and nFET (right). Both transistors are
simulated for drain voltage of 0.05V (blue) and 1V (red)
The results are similar to those reported in two papers that were used as a guideline for this model
[9, 13]. Some of the characteristic values for both transistors are represented in the Table 3. Vt represents
the threshold voltage, IdLin is the drain current for Vgs = Vdlin (Lin represents the linear field of operation
and VdLin is 0.05V in that case) gmLin is maximum conductance at Vds = Vdlin, SSlin is the subthreshold
slope swing at Vds = Vdlin, IdSat is the saturation drain current at Vds = Vgs = 1V and Ioff is the drain-
leakage current at Vds = 1V and Vgs = 0
nFinFET pFinFET
Vt [V] 0.326 -0.375
IdLin [A] 1.482e-04 1.488e-04
gmLin [S] 1.227e-05 1.366e-05
SSlin [mV/decade] 80.415 92.878
IdSat [A] 6.065e-04 5.931e-04
Ioff [A] 2.833e-09 4.061e-09
Table 3. Characteristics of 22nm nFinFET and pFinFET

4 14nm FinFET
The 14nm technology node is the successor of the 22nm node according to the International
Technology Roadmap for Semiconductors (ITRS) and it is also known as 14/16nm because it was expected
at first that 16nm will be the obtained dimension, but the industry delivered the 14nm transistors. At this
scale, planar MOSFET production is far from feasible so the FinFET persisted as the best solution for the
VLSI technology. One of the most important technologies implemented into a FinFET is the stress
enhancement engineering, crystal orientation effect as well as the impact of the fin shape on FinFET
channel characteristics which will be further discussed through the Sentaurus TCAD model [5].
Furthermore, some of the issues that come with such high scaled devices such as band-to-band tunneling
(BTBT) will be discussed.
4.1 Fin shape

Optimization of the fin shape is one of key considerations for a FinFET performance. As already
mentioned at the previous node, fin should have rounded corners in order to avoid unwanted corner
effect. FinFET used in this thesis has a rounded corner with a 2.5nm radius that is achieved by four-edge
approximation. Furthermore, tapered fin is suggested and three different shapes are investigated. All
three fin shapes have fin width of 15 nm at the bottom (Wb), one fin shape has the same width at the top
(Wtop = 15 nm), other two fins are linearly shrinking to Wtop = 10 nm and Wtop = 5 nm creating a tapered
fin shape. The fin height is selected according to the paper used as a reference for this simulation model
[45] and it is 35 nm (paper suggests 34 nm). The discussed shapes are represented on Figure 11. It is also
worth mentioning that one paper [24] investigated different Wtop dimensions using the Sentaurus model
as well (by adjusting the 22nm model) and reported that fin shape has to be investigated together with
the fin body doping concentration. Namely, by investigating two extremes, with Wtop of 15 nm
(rectangular) and 1 nm (triangular), it has been shown that rectangular shape achieves the lowest leakage
current at 1e18 cm-3 fin body doping concertation and triangular shape at roughly 5e17 cm-3, but this
doping becomes feasible starting from the 5 nm top fin width, so our model does not use the lower dopant
concentration, but rather uses 2e18 cm-3 channel doping concentration. Still the doping trade-off should
be considered for further FinFET scaling. The trade-off comes from the fact that insufficient fin body
doping leads to the increase in SCE leakage current under the active fin region and decrease in the GIDL
due to BTBT at the interface between the drain and the fin body. Different fin shapes achieve different
values of both of the unwanted effects, so the optimal doping concertation must be met.
It should be mentioned that the corner effect could also be reduced by additional corner
implantation that should adjust its threshold voltage to the rest of the fins body [25]. The suggested
process should occur after the shallow trench isolation that will be discussed in the next section. After the
fins have been etched and the wells filled with oxide, top of the fin is covered with the hard mask nitride
layer and additional oxide layer from the former STI isolation. The wafer is then implanted with boron
ions at zero degrees angle with 5keV energy to a dose of 5e13 cm -2. Some of the ions reach through the
oxide and nitride layer and locally increase the corner fin doping reaching the peak concentration of 8e18
cm-3.

Figure 11. Illustration of different fin cross-section shapes with input parameters [5]
Figure 12 shows the simulation results regarding the subthreshold slope and off-current of both
nFinFET as well as pFinFET for different Wtop dimensions. It is clearly observable that the tapered fin shape
exhibits superior characteristics over the rectangular cross-sectional fin shape. At the same time, the
lower on-current is observed with decrease in the fin area. The factor of on-current decrease is slightly
lower than that of the leakage current so the Ion-Ioff ratio rises with the Wtop decrease. It is also interesting
that nMOS shows larger on-current variation, because of the different carrier mobility on the top and side
surface of the fin. The influence of crystal orientation on the carrier mobility will be later further discussed.
82 pMOS nMOS 80.861 pMOS nMOS 11.290

11.000
SSlope [mV/decade]
80
78.508
78 76.935 9.000 8.452
Ioff [pA]
7.552
76 74.8
7.000 6.511
74 73.856
5.000 4.343
72 3.602
70.475
70 3.000
5 10 15 5 10 15
Wtop[nm] Wtop[nm]
Figure 12. Simulated values of tapered fin shape impact on subthreshold slope (left) and leakage current
(right)
4.2 Shallow trench isolation (STI)

With fin pitch getting constantly smaller, the issue of current leakage between two adjacent FinFETs
represents a concern. Shallow trench isolation is the preferable technique of isolation between two
transistors in the sub 0.5µm node technology, replacing the formerly used Local Oxidation of Silicon
(LOCOS). LOCOS produced big deformations in the Si structure around it and produced the so called “birds
beak” thus enlarging the total lateral dimension of the oxide. The continuous scaling lead to LOCOS being
unsuitable for further use in the nineties of last century [26]. Shallow trench isolation, also known as box

isolation technique, is theoretically not much different from LOCOS, but it was rather a technical challenge
to implement it. Namely, the process consists of thin oxide and hard mask layer deposition, RIE, trench fill
with oxide, chemical-mechanical polishing (CMP) and removal of the hard mask. This process was adapted
and adjusted in a FinFET manufacturing process, precisely right after the fin formation. After the SWT
lithography and the following etching step discussed in the former node section, the bottom of the etched
space is filled with oxide, insulating fins one from another (Fig. 13). There are several problems that may
occur during the STI process. Firstly during the gap filling process, voids inside the oxide can be formed
that could get exposed by the subsequent oxide recess, leading to non-uniform oxide surface. By process
optimization, void free STI oxide filling is reported [27]. A potential solution can be a liquid flowable
chemical vapor deposition (FCVD) providing a void free gap fill. This process, however, requires a post-
annealing treatment of oxide for its densification. The anneal process has to be performed carefully so
that the fin structure is not damaged [28].
Next crucial process that has to be optimized is the STI CMP. We can distinguish two types of
uniformity: global and local. Global uniformity mainly depends on the CMP. The mentioned paper [27]
reports very good optimization of this process, creating a uniform pattern. Local uniformity is also
influenced by the local pattern density. For a uniform fin pattern, CMP produces a very good pattern but
variation in fin pitch creates dishing in the oxide layer. This issue can be avoided by creating a dummy fin
in the higher fin pitch zones, so the CMP pattern stays consistent. Fin oxide recess is the most important
step of the STI process because it decides the final oxide profile. The etching is divided into two phases:
before and after the fin hard mask removal, both of which have to be optimized to form the wanted fin
shape. Dilute HF (DHF) and dry etching combination is proposed for this purpose. Dry etching byproducts
can pile at the middle of the trench, causing an uneven profile. On the other hand if the dry etching
amount is too low, oxide footing can be formed, making the oxide layer on the sidewalls thicker. With an
optimal amount of DHF and dry etching, the same mentioned paper achieved uniformed STI profile.
However, TCAD model does not suffer from these issues, the fin is formed and the oxide is subsequently
deposited up to a certain level (Fig. 13).
Furthermore, with the pitch between STI trenches getting smaller, the compressive stress it
produces onto the transistor becomes significant. This can of course enhance the pMOS device
performance because the compressive stress is desirable. But for an nMOS transistor where a tensile
stress is desirable, this brings

Figure 13. Process after the fin formation and STI deposition
an unwanted effect. There are some approaches to reducing the unwanted stress effect on the nMOS like
STI recess, but the TCAD model used here implements 1GPa tensile as a sum of STI stress and contact
metal stress (tensile stress that arises by formation of NiSi contacts, so called silicide induced stress) for
both nMOS and pMOS.
4.3 Source/Drain epitaxy

Analog to the 22nm FinFET, a 14nm FinFET also uses SiGe and SiC S/D regions for pMOS and nMOS,
respectively. This time, the epitaxial growth in the simulation can be controlled much more precisely by
replacing a physically based model with a pure geometry model.
Figure 14. Some of input parameters for the S/D epitaxy
Apart from the general outline, like S/D length from the spacer to the endpoint or the S/D height,
there are some more detailed measurements that can be controlled. Some of them are represented in
Figure 14. In comparison to the previous technology node, this model implements a 6nm fin undercut that
leads to an overlap between gate and source/drain regions. Namely, the production process at such a low
scale produces certain inaccuracies. This can occur due to insufficient accuracy during the S/D doping
(abrupt doping profiles are a big challenge of VLSI technology) that can penetrate into the channel region
or due to low accuracy of metal gate implementation that can partially cover the edges of S/D regions.
This reduces the effective channel length for roughly 6nm from each side, approx. 12nm in total. The
channel length is primarily 25nm but the effective channel length falls down to 14nm after the S/D
implementation. The overlapped structures are reported to exhibit higher short channel effects and a
decrease in Ion/Ioff ratio and the device delay also enhances [29].
The Si stressors concentration is also different from the 22nm node, as it can be observed in Figure
14. The Ge mole fraction is 50% in the S/D regions of pFinFET and carbon concertation lies at 2% for
nFinFET.

4.4 Crystal orientation effects
It has been proven that the carrier mobility depends on the orientation of the Si crystal [30]. This is
explained by the anisotropy of the effective mass of the charge carriers that are, as already mentioned in
section 2.3, directly proportional to their mobility. When it comes to electrons, they demonstrate the
highest mobility on the (100) plane, that is why this became the conventional transistor orientation. Holes
on the other hand exhibit the highest mobility on the (110) plane: as much as 150% higher, while the
electron mobility can by degraded by 70% compared to the (100) crystal plane. Because the FinFET is a
vertical structure and the conducting channel lies on the sidewall of a silicon pillar, channel orientation
can by changed by simple device rotation in the wafer plane [31] (Fig 15, left). Even though it would be
expected that the mobility in nFinFET would significantly decrease with the channel in the (110) plane,
the experimental data shows a slight decrease, while the holes mobility increases significantly (Fig 14,
right). It has been generally observed that the crystal orientation effects on electron mobility begin
significantly to decrease with the channel lengths getting smaller.
Our TCAD model uses the (100) top surface and the (110) channel orientation. Considering the
crystal orientation effect, the simulation calculates Inversion and accumulation mobility with auto-
orientation (IALMob). This means that the inversion layer mobility will be calculated with regards to
surface orientation dependency and according to the experimental data on the universality of inversion
layer mobility [32].
Furthermore, Sentaurus also uses density-gradient quantum correction with auto-orientation.
Namely, quantum separation is a function of the quantization carrier mass and quantization carrier mass
is different for different crystal orientation. So, considering the two different crystal orientations in a fin,
auto-orientation creates an orientation-dependent quantum-correction.
Figure 15. FinFET channel orientations on a (100) wafer (left) and carrier mobility versus doping
concentration for nMOS and pMOS with two different channel orientations (right) [31]

4.5 High-K/Metal Gate Last
As already discussed in the previous chapter, high-K and metal gate are the industry standard for
the optimal gate work function and the continuous aggressive scaling. This model uses a third generation
high-K + metal gate technology reported in [17]. A key challenge in this process is the integration of the
metal gate that is sensible to the subsequent process steps that include thermal annealing. The high
temperature changes the work function of the metal creating unwanted variations in the transistors
threshold voltage. To avoid this effect, a so called dummy gate (poly-Si gate) is primarily deposited, and
after then replaced with the metal gate after all high-temperature processes. This process is also known
as replacement metal gate (RMG) process. High-K dielectric layer can also be deposited before or after
the thermal annealing, subdividing the possibilities to high-K first and high-K last. To be precise, the model
used for these simulations implements the high-K first/metal gate last process.
The metal of choice still has to be chemically stable in contact with the dielectric layer, as well as
thermally stable, though this requirement is not as important as by the gate first process because this
time, the gate metal has to withstand a low temperature anneal (600°C for 1µs in this model).
Nevertheless, a thermally very stable refractory metals are still used for this purpose. Titanium (Ti), used
in the 22nm FinFET can be categorized loosely as a refractory metal (melting point at 1668°C), but
tungsten (W, also known as wolfram) with its 3422°C melting point is a proper refractory metal. Thanks
to its mid gap work function and very low resistivity metal/oxide interface, tungsten is a great candidate
for the dual work function metal gate transistors. Furthermore, chemical mechanical planarization (CMP)
of Tungsten is well investigated and ready for mass implementation. In contrast to conventional physical
vapor deposition (PVD), it is reported that Tungsten gate can be formed by means of atomic layer
deposition (ALD), a process that exhibits superior filling capabilities and very low void formation possibility
compared to the conventional PVD [33].
One additional advantage of the metal gate last approach is the enhanced uniaxial channel strain
that comes from SiGe and SiC source/drain regions. In order to fully exploit this possibility, a process flow
is suggested where the dummy gate is deposited, followed by the standard thermal processing, up until
the self-aligned silicide contact. The wafer is then planarized (CMP) and the dummy gate is etched. The
metal gate is then deposited into the recessed area [34]. By removing the poly gate after the S/D lattice
mismatch strain is already applied, the whole transistor structure becomes weaker and more prone to the
strain effects [35]. This strain enhancement is taken into account in this simulation by adding an additional
1GPa of tensile and compressive stress for nMOS and pMOS, respectively. Analogous to the 22nm FinFET,
a thin interlayer oxide (6Å) is deposited before the HfO2 dielectric layer (17Å).
However, high-K metal gate also degrades the mobility due to several different mechanisms
(remote phonon scattering (RPS), remote Coulomb scattering (RCS) and remote dipole scattering (RDS)).
In this project, all three mechanisms are taken into account according to Advanced Calibration guidelines
[36].

4.6 Back end of line (BEOL)
Back end of line is the later part of the integrated circuit manufacturing process, where all the
transistors are interconnected with each other according to the IC scheme. This process consists of already
mentioned silicidation, followed by interlayer dielectric (ILD) deposition. The dielectric layer is then etched
to create vias for the metal contacts and lastly the metal is deposited. In order to lower the parasitic
capacitance between the metal interconnects a low-K dielectrics is implemented. Interconnects are cone-
shaped: narrow at the bottom in order to minimize the interconnect pitch and wider at the top to lower
the overall resistance. This project uses vias of 18nm diameter at the bottom and 32nm diameter at the
top. A metal of choice for interconnects used to be copper (Cu) or aluminum (Al) but with the constant
scaling their contact resistance became intolerably high, so new tungsten (W) interconnects are proposed.
With shorter mean free electron path and improved reliability compared to Cu, Tungsten is the optimal
candidate for this purpose [37]. This project also uses the tungsten interconnects (Figure 16).
Figure 16. Cross section of the final pFinFET model with tungsten interconnects and CESL
Figure 16 also shows a contact etch stop layer (CESL) on top of the first interconnect layer dielectric
in the gate region (ochre colored). This layer induces additional biaxial stress in the channel region thus
increasing the carrier mobility. This method was first used just for the nMOS transistors for tensile strain
induction, while the pMOS used the SiGe stressors. With the technology advancement, CESL can now
exhibit tensile as well as compressive stress. This process is called dual stress liner (DSL) and it consists of
deposition of highly tensile and highly compressive nitride liner over the nMOS and pMOS, respectively
[38], though this strain component is not considered in this model.

4.7 Results
With all mentioned strain sources taken into account, stress component in the current direction (ZZ)
for a pFinFET reaches the values represented in Figure 17. It is observable that the strain reaches its
maximum in the gate dielectrics, but it cannot be fully transferred onto the channel because of the HfO2
layer that exhibits a relatively high stiffness. As a result, compressive strain reaches more than -5GPa in
the gate stack and around -3GPa in the channel.
Figure 17. Final strain model in the ZZ direction for a pMOS with 5nm top fin width
Furthermore, final current characteristic lines are represented in Figure 18 for both pFinFET and
nFinFET with the top fin width of 5nm. The graph shows the dependence of total drain current (Id) on gate
voltage (Vg) for two different drain voltages (Vd), simulating so called linear (Vd = 0.05 V) and saturation
(Vd = 1 V) scope. A lateral difference between these two curves in the subthreshold regime point to the
existence of the drain-induced barrier lowering (DIBL). DIBL is an effect where higher drain voltage can
directly influence the gate barrier height (lowering it), thus increasing the overall drain current. It can be
roughly calculated from the given plot to 100 mV/V for both pMOS and nMOS devices.

Figure 18. IdVg characteristics of pFinFET (left) and nFinFET (right) for both linear (blue) and saturation
(red) scopes

5 10nm FinFET
The 10nm technology node was planned for the year 2016 according to the ITRS that expects a half
pitch improvement every two years. Even though some companies came through with the 10nm node in
before the end of 2016 (Samsung), some of them (Intel) are postponing its production for as far as 2020.
This should be a reminder of how challenging a production of these scales can be and why the research
in this field is of crucial importance. Apart from their manufacturing process, appropriate simulation
models represent a certain challenge at this dimensions. Since the most key features of 10nm FinFET are
very similar to previous nodes, this chapter will be slightly more oriented towards the challenges in the
simulation process.
5.1 Low-power, standard performance and high

performance FinFET
With the constant evolution of digital devices and their further implementations in almost every
sphere of industry imaginable, the need for more dynamical computing devices is rising. With the
enormous production of smartphones and current expansion of internet of things (IoT), low power
consumption has become as important as the high computing performance of a device. This lead to
development of transistor with various performance and power consumption features in order to make
them more flexible. For wired, so called “always-on” devices, power consumption is not crucial so the high
performance (HP) transistors are still the best option. So called battery-backed devices are dependent on
a battery power in some extent and the trade-off between power and performance is moved to the middle
of that scale. These devices prefer standard performance (SP) transistors. Lastly, for completely mobile,
battery powered devices, power consumption is crucial. That is why a low-power (LP) transistors have
been developed.
The Sentaurus 10nm FinFET model achieves the three different modes by changing the metal gate
work function that is directly proportional to gate barrier height and thus to the threshold voltage of the
transistor. To create a low-power device, reducing the leakage current is of crucial importance, which can
be achieved through higher threshold voltage. On the other hand, lower threshold voltage makes higher
drain current possible as well as shorter response time, both crucial for a high performance device. The
metal work function is an additive term in the threshold voltage. Figure 19 shows the dependency of
leakage, linear and saturation current on the work function for both nFinFET and pFinFET. The exact values
of the work function and their influence on threshold voltage are represented in Table 4.
nFinFET pFinFET
Mode LP SP HP LP SP HP
WF [eV] 4.611 4.511 4.364 4.640 4.733 4.878
Vt [mV] 383 283 136 -356 -263 -118
Table 4. Work function versus the threshold voltage for both nFinFET and pFinFET

The threshold voltage can also be adjusted with the gate length of the transistor, what is certainly
a less effective option then WF modulation that is anyway a part of the production process since two
different band gaps for pMOS and NMOS are created anyway. Doping adjustments are also possible but
unwanted in the manufacturing process so the multi work function remains the best approach [39].
The fin height can also play a significant role in the power/performance trade-off. Namely, tall fins
can increase the transistors delay what is definitely an unwanted effect when it comes to high
performance FinFETs. At the same time, taller fins lower the leakage current thanks to their electrostatic
superiority. Some chips use two different fin heights for this purpose: taller for LP and shorter for HP. This
project uses the same fin height of 27nm for all three scenarios.
Figure 19. Linear (blue), saturation (red) and off (green) current vs the metal work function for
pFinFET (up) and nFinFET (down)

5.2 Device simulation
In order to describe and simulate the transport of the electron and holes inside a transistor, a
Boltzmann transport equation has to be solved for the given parameters. This equation relies on a
statistical behavior of the particles in a thermodynamic system rather than individual position and energy
of every single particle in the system. It uses a probability function for the position and momentum of a
particle and it is primarily used for analyzing the behavior of gases, but the movement of charge carriers
in a semiconductor can also be described with this equation. There are several approaches to solving the
transport equation, but the two most used in TCAD simulations are a drift-diffusion and Monte Carlo
method.
5.2.1 Drift-diffusion (DD) method

For several decades, drift-diffusion model was the basis of modelling the charge carrier transport
in transistors. It is an equation derived from the Boltzmann transport equation and it describes a transfer
through two processes: convection and diffusion. These two further translate into drift current, derived
from the electric field applied onto the system and diffusion current caused by the gradient of the charge
carrier concentration [40]. The drift-diffusion equation is then solved numerically using the Poisson
equation. The issue of this model became apparent around the 50nm node. The drift-diffusion model
assumes the carrier mobility as a constant, an approximation that cannot be applied at the gates shorter
than 50nm [41]. This phenomenon leads to the saturation of the average carrier velocity in the channel
to a so called ballistic limit, instead of its expected increase that is inversely proportional to the gate
length. This ultimately leads to a certain underestimate of the total current value, so called undershoot.
This phenomenon can be alternatively described through ballistic transport of the carriers. Namely, with
the gate length reaching a nanometer scale, there is a greater number of charge carriers that experience
a ballistic transport instead of the conventional scattering transport. This phenomenon has a positive
outcome for a transistor, making its resistivity lower and total current higher, but the drift-diffusion model
is not adequate to simulate this behavior.
However through certain modifications, undershoot can be estimated and taken into account so
that the final solution is close enough to the physical outcome. This Sentaurus project uses ballistic
mobility model and saturation velocity adjustment in order to accurately model the 10nm FinFET. The
reason it is insisted to keep the drift-diffusion equation useable is its relatively low computational effort,
in contrast to the Monte Carlo method with quantum correction.
5.2.2 Monte Carlo (MC) method

The earlier use of planar MOSFET devices was far simpler to simulate. FinFET brings various
challenges to the simulation adjustments. As already mentioned by the 14nm node, crystallographic
orientation dependence on the surface mobility has to be taken into account for the fin sidewalls, non-
linear drift velocity and ballistic undershoot as well as quantum errors. The Monte Carlo method is a
stochastic method that simulates single particle transport one by one through the given medium.
Stochastic means that the scattering events that the particle experiences are determined randomly. This
method is also called semiclassical, meaning that quantum phenomena are taken into account just for a
certain part of the system. In this case, scattering events are treated quantum mechanically whereas the

transport between the scattering events is solved with classical physics. However, with the scaling
reaching the atomic level, quantum transport cannot be ignored anymore. This issue is solved with so
called quantum correction model for Monte Carlo simulation. The method proposed in [42] used in this
project uses a 2D cross section at the middle of the channel for quantum corrections. The quantum
corrections are simulated for: carrier density, gate oxide permittivity and work function, adjusting their
values to the experimental expectations. The goal of this correction is to obtain the corrected permittivity
and work function, so that an identical carrier density to that of the density gradient model can be
achieved. It can be observed from Figure 20 that the quantum correction provides the correct electron
density values. Analogous to the electron sheet density for nMOS presented in Fig. 20, the hole sheet
density for pMOS devices are also simulated correctly.
Figure 20. Accuracy of quantum correction for HP, SP and LP nFinFET. Lines represent the gradient
density model and the dots (correspond perfectly with the lines, so hardly observable) the corrected
semiclassical MC simulation
5.2.3 Comparison between DD and MC method

In order to visualize the undershoot of the drift-diffusion simulation without taking the ballistic
transport into account, linear drain current has been simulated for both pMOS and nMOS FinFET for all
three work function values using both Monte Carlo simulation as well as uncorrected drift-diffusion
simulation. A difference of approximately 40% for pFinFET and 80% for nFinFET are observed in the drain
current values (Figure 21).

Figure 21. Linear drain current vs. the work function for both pFinFET (right) and nFinFET (left).
Dashed lines represent the uncorrected drift-diffusion (DD) and full lines represent the Monte Carlo
(MC) simulation
On the other hand, with the ballistic transport model calibrated to MC results, the corrected drift-
diffusion simulation reproduces the Monte Carlo currents a lot better. Figure 22 shows the simulated
drain current values for both linear (Vd = 0.05V) and saturation (Vd = 0.7V) range. Even though the
difference between two simulations is noticeable, the relative error is reduced to approximately 10% in
the worst case and some values are identical for both simulations. Since the drift-diffusion simulation is
significantly faster than the MC simulation, it is often a more preferable approach to 3D simulations,
where many different scenarios are investigated, so the simulation time plays a substantial role.

Figure 22. Linear and saturation drain current simulated with corrected DD (full lines) and MC (dots) for
both nFinFET (up) and pFinFET (down)

6 7nm FinFET
The ITRS defines 7nm node as the successor of the 10nm technology node and its mass production
started in 2018. The TCAD Sentaurus model of a 7nm FinFET used for this paper has a lot of similarities to
the previously described 10nm node. The project investigates three types of transistors: low power (LP),
standard performance (SP) and high performance (HP) FinFETs using again both drift-diffusion model with
ballistic transport correction as well as Monte Carlo model with quantum correction. Though with the
same idea in mind to achieve FinFETs with three different functionalities, apart from different work
functions, this project also investigates different Ge mole fractions (up to 100%) and their influence on
the FinFETs performance.
6.1 SiGe Source/Drain stressors and stress-relaxed buffer

(SRB)
The idea of implementation of silicon alternative has always been a subject of investigation but
with the recent developments in production technology, this approach became more attractive than ever.
One of the main reasons for the replacement of Si as the main semiconductor material is the higher carrier
mobility. The charge carriers in the 7nm FinFET experience ballistic transport in the extent of around 90%,
which makes it the dominant carrier transport compared to the scattering transport by a clear margin.
Improving the ballistic transport can be achieved by lowering the effective mass of the charge carrier. On
the other hand, these materials also show an increase of the leakage current of the device. With this
trade-off in mind, the right amount of a material with higher carrier mobility can be used to achieve three
different FinFET functionalities. Because of its superior hole mobility and well tested ability to work in the
integrated circuits together with silicon, Germanium became a leading candidate to replace silicon in a
certain extent [43].
Furthermore, already mentioned lattice mismatch between SiGe and Si can be put to use to create
the well needed strain enhancement to the transistor. The non-silicon channel can be achieved through
different techniques, but the epitaxial film growth on top of the Si wafer shows promising advantages and
is also used in this project. Between the Si wafer and the channel a stress-relaxed buffer (SRB) because of
the very large lattice mismatch between pure Si and Ge. This layer also serves as a strain source, to be
more precise a tensile strain in the case of Germanium. This is certainly desired for the nFinFET, but the
pFinFET requires compressive strain in the channel for the increased hole mobility. This is achieved
through SiGe epitaxially grown S/D regions with the higher Ge mole fraction than the channel. It has been
shown that this not only compensates for the tensile stress of the SRB, but actually creates even bigger
strain onto the channel than without the SRB.
Considering the performance/leakage trade-off connected to the Ge percentage and the strain
enhancement that it simultaneously brings, the following Ge mole fractions are used for LP, SP and HP
nFinFET and pFinFET: For low power devices, channel is kept free of Germanium, the SRB though has 20%
Ge that provides beneficial tensile stress for nFinFET. To compensate this, pFinFET uses Si0.3Ge0.7
epitaxially grown in the S/D region, creating the compressive stress in the channel. For standard
performance devices, Ge mole fraction of 50% is used for both channel and the SRB. The lattice mismatch

strain comes solely from epi S/D. The lower Ge concentration in S/D creates tensile stress and higher
concentration creates compressive stress. That is why the pFinFET uses 85% and nFinFET 15% Ge
concentration in the epitaxial growth process. Lastly, the high performance FinFET uses pure Germanium
channel for the highest on-current. The 80% Ge in the SRB creates compressive stress in the channel, so
the nFinFET uses Si0.7Ge0.3 to achieve the tensile channel stress. The explained percentages can be
observed in Figure 23 with the S/D regions symmetrically aligned around the channel region and the SRB
layer underneath all three of them.
Figure 23. Germanium mole fractions for pFinFET (top row) and nFinFET (bottom row) for LP (left
column), SP (middle column) and HP (right column)
Together with the poly gate removal, STI and contact stress components already described in
previous sections, the final strain on the transistor is presented in Figure 24 for all transistor variations. It
is observable how the strain reaches the highest values in the top of the fin thanks to the dummy gate
removal process. Furthermore, strain is the strongest where the difference in Ge concentration between
the channel and the S/D regions is the highest, pointing out that the uniaxial stress from the epitaxial S/D

regions is much more important than the biaxial stress from the SRB. Nevertheless, the negative influence
of the SRB can be noticed in the LP pFinFET (upper left corner) in a form of lesser stress level in the bottom
of the fin, as well as the HP nFinFET (lower right corner). On the other hand, those two transistors also
experience the biggest strain in the top fin region.
Figure 24. Stress along the channel (Szz) for pFinFET (top row) and nFinFET (bottom row) for for LP (left
column), SP (middle column) and HP (right column)
Even though this paper uses only silicon and germanium, it is worth mentioning that there are
further experimenting possibilities. One paper [44] suggests adding Tin (Sn) to the SiGe, creating a Sn-
based alloy. One of the reasons is that the GeSn alloy offer the largest lattice constant in group IV, which
allows even more aggressive strain engineering. Furthermore, through the adjustment of Si/Sn ratio, the
work function can be adjusted more flexibly. The Sn concentration of 8% is proposed for this purpose.
One more feature connected to the surface-relaxation buffer is its tapered shape that follows the
slightly tapered fin. As shown in Figure 25, there is a subtle but noticeable difference in the slope angle of
the fin and the SRB. The reason for this is that the constant need for narrower fins lead to their

Figure 25. Cross section of the 50% Ge pFinFET
Mechanical instability. In order to keep the structure stable, the SRB expands in the width faster than the
fin.
6.2 Results
Considering the three different splits, Figure 26 visualizes the leakage, linear and saturation current
in dependence on Ge channel concentration. For the two extreme cases with 0% and 100% Ge, the trade-
off is obvious, but for the SP case, especially in the nFinFET ,the increase in leakage current is observed
without a significant gain in the on current. At the same time, a great agreement between adjusted drift-
diffusion and corrected Monte Carlo model can be observed.
Figure 26. Off, linear and saturation current vs Ge Mole Fraction for pFinFET (up) and nFinFET (down)
simulated with DD (lines) and MC (dots)

7 Motivation for further simulations
This thesis started subsequently to the course “Nanoelectronics and Information Technology”, where
among other subjects, a Sentaurus TCAD Simulation of a planar MOSFET is investigated by alteration of
certain parameters and observation of its effect on the MOSFET performance. This thesis should give
insight into the FinFETs simulation flow so that the course exercises can be performed on the cutting-edge
nano-devices. For this purpose, a 14nm FinFET is chosen, since its model is more extensive than the one
used at the previous technology node, especially in the section of mechanical stress simulation.
Furthermore it features the possibility of alternating the channel and wafer crystal orientation. On the
other hand, the successor nodes (10 and 7 nm) are more oriented towards the investigation of different
simulation models, whereas the FinFET performance plots are not of a primary interest.
This section investigates the influence of channel orientation variation as well as total strain impact
on the FinFETs charge carrier mobility. The Sentaurus project described in [5] is adjusted so that it
simulates two channel orientations: (110) and (100) for both pMOS and nMOS FinFETs and include or
exclude stress model from the simulation. Figure 27 shows the Sentaurus workbench after the parameter
extension. The left red square shows two different channel orientations that will be simulated. The right
red square points out the parameter that decides if the mechanical strain will be taken into account (value
is 1) or not (value is 0). With two different FinFET types (nMOS and pMOS) and three different top fin
widths, further parameter variations create an extensive amount of possible scenarios to be simulated.
The black and the blue square point out the two cases used in this thesis in order to present the parameter
influence. Both the crystal orientation and mechanical strain are shown for pMOS with Wtop = 5nm.
Figure 27. Sentaurus workbench of 14nm FinFET with proposed variations
As already mentioned in the 14nm section, channel orientation can be changed by wafer rotation
of 45 degrees. The (110) channel showed better performance trade-offs for the CMOS implementation
but the constant developments in the production technology can lead to certain enhancements in only
one type of transistor, thus moving the trade-off equilibrium point in favor of the (100) channel. The
alternation of input parameters for the channel direction and wafer orientation are defined with
preprocessor statements. Four different combinations of these two parameters are handled by “#if”

query, that directly saves this information for the simulation. The simulation then uses already mentioned
Inversion and accumulation mobility with auto-orientation (IALMob) model to create an orientation-
dependent FinFET model. For the pMOS, holes are the majority charge carriers and their mobility is the
one of interest for our simulation. Figure 28. Illustrates the hole mobility (hMobility) for (110) - left and
(100) - right channel orientation. The higher mobility zones are clearly observable in the (110) channel.
Figure 28. Hole mobility for the (110) and (100) channel orientation left and right, respectively (pFinFET
Wtop = 5nm, strain impact included)
Next to the crystal orientation dependence, the mobility enhancement induced by mechanical
strain is also investigated (Fig. 29). The “Strain_impact” parameter of the device simulation showed in
Figure 27 controles 5 preprocessor queries that, depending on the parameter value, include or omit the
stress impact.
Figure 29. Hole mobility with (left) and without (right) the strain impact included. (pFinFET Wtop = 5nm,
(110) channel direction)

The strain is calculated for: STI Oxide, epi S/D, dummy gate removal, metal gate deposition and
self-aligned contacts. Changing the parameter value to ‘0’, strain calculations are not used in the device
simulation. Figure 29 illustrates the stress impact on the hole mobility in the pFinFET. The impact is much
bigger than the one of the channel direction and shows the importance of further research in the strain
enhancement methods.

8 Conclusion
In this work a theoretical basis for 4 different non-planar FinFETs is presented. Some of the key
process steps are investigated and compared to the preceding planar MOSFET process flow. An
evolution of the FinFET production is presented through subsequent technology nodes: 22nm, 14nm,
10nm and 7nm. In this way a chronological development in the manufacturing process can be
observed, as well as the trends that are most likely to be implemented in the subsequent technology
nodes. Among other, the importance of strain enhancement technology, lower parasitic resistance
and parasitic capacity is for lower leakage currents, higher on currents and faster switching speeds
are discussed. Also, an unconventional transition to non-Si transistor channel is investigated with its
possible advantages and implementation possibilities. In view of the constant expansion of mobile,
wearable, always-on, battery-powered devices, three different FinFET types are discussed for the
10nm and 7nm technology node.
This work used FinFET models offered by the TCAD Sentaurus as recommended architecture for
the mentioned nodes. This provided a more thorough insight into the FinFETs process flow, as well
in its characteristic performance features. On a second level, challenges of fast and correct simulation
models for nano-device simulations are discussed. Physical phenomena that lead to the need of new
transport models, as well as the correction of already used models is presented with the accent on
the simulation speed optimization.

9 References
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Hiermit erkläre ich, dass die vorliegende Arbeit ohne unzulässige Hilfe Dritter und ohne
Benutzung anderer als der angegebenen Hilfsmittel angefertigt wurde. Die aus anderen Quellen oder
indirekt übernommenen Daten und Konzepte sind unter Angabe der Quelle gekennzeichnet. Die Arbeit
wurde bisher weder im In– noch im Ausland in gleicher oder in ähnlicher Form in anderen
Prüfungsverfahren vorgelegt.
Wien,
Veljko Vukicevic
_______________________
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Evolution of FinFETs from 22nm to 7nm

Thesis · September 2019

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Supervisor: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Gerhard Hobler

Evolution of FinFETs from 22nm to 7nm |1

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Tech. node Gate length Wbottom Wtop Fin Height

Tech. node S/D Channel Channel stop

All concentrations represented in cm-3

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3.1 Fin shape

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3.2 High-k/Metal Gate Stack

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Figure 5. Cross section of gate stack

3.3 Selective gate sidewall spacer

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3.4 Diamond-shaped raised source/drain

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3.5 SiGe and SiC lattice mismatch stress

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3.6 Self-aligned silicide contacts

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4.1 Fin shape

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82 pMOS nMOS 80.861 pMOS nMOS 11.290

4.2 Shallow trench isolation (STI)

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4.3 Source/Drain epitaxy

Figure 14. Some of input parameters for the S/D epitaxy

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5.1 Low-power, standard performance and high

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5.2.1 Drift-diffusion (DD) method

5.2.2 Monte Carlo (MC) method

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5.2.3 Comparison between DD and MC method

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6.1 SiGe Source/Drain stressors and stress-relaxed buffer

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