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    Lab 12 Task 01 Simulation For Up Down Counter Using Behaviour Modeling

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    Dilawar Tanvir
    This document contains a module description and test bench for an 8-bit up-down counter simulation. The module uses a clock input and active-high reset to control an 8-bit output register. When reset is active, the output is set to 0. On each clock edge, if up_down is 1 then output is incremented, otherwise it is decremented. The test bench initializes the clock, resets the counter, toggles the up_down input to count up and down, and resets during the count.

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    Lab 12 Task 01 Simulation For Up Down Counter Using Behaviour Modeling

    Uploaded by

    Dilawar Tanvir
    21 views2 pages
    This document contains a module description and test bench for an 8-bit up-down counter simulation. The module uses a clock input and active-high reset to control an 8-bit output register. When reset is active, the output is set to 0. On each clock edge, if up_down is 1 then output is incremented, otherwise it is decremented. The test bench initializes the clock, resets the counter, toggles the up_down input to count up and down, and resets during the count.

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    This document contains a module description and test bench for an 8-bit up-down counter simulation. The module uses a clock input and active-high reset to control an 8-bit output register. When reset is active, the output is set to 0. On each clock edge, if up_down is 1 then output is incremented, otherwise it is decremented. The test bench initializes the clock, resets the counter, toggles the up_down input to count up and down, and resets during the count.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    21 views2 pages

    Lab 12 Task 01 Simulation For Up Down Counter Using Behaviour Modeling

    Uploaded by

    Dilawar Tanvir
    This document contains a module description and test bench for an 8-bit up-down counter simulation. The module uses a clock input and active-high reset to control an 8-bit output register. When reset is active, the output is set to 0. On each clock edge, if up_down is 1 then output is incremented, otherwise it is decremented. The test bench initializes the clock, resets the counter, toggles the up_down input to count up and down, and resets during the count.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    Lab 12

    Task 01
    Simulation for up down counter using behaviour modeling
    ;module up_down_counter (out,up_down,clk,reset)
    ;output [7:0] out
    ;input up_down,clk, reset
    ;reg [7:0] out
    always @(posedge clk)
    if (reset) begin // active high reset
    ; out <= 8'b0
    end
    else if (up_down) begin
    out <= out + 1;end else begin
    out <= out - 1;end
    endmodule

    Test Bench
    ;module tb_counter
    ;reg Clk; reg reset; reg UpOrDown
    ;wire [3:0] Count
    (
    ) upordown_counter uut
    ,Clk(Clk).
    ,reset(reset).
    ,UpOrDown(UpOrDown).
    Count(Count).
    ;(
    ;initial Clk = 0
    ;always #5 Clk = ~Clk
    initial begin
    ;reset = 0

    ;UpOrDown = 0
    ;#300
    ;UpOrDown = 1
    ;#300
    ;reset = 1
    ;UpOrDown = 0
    ;#100
    ;reset = 0
    end
    endmodule

    Simulation Result

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