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    Sequential Design Using Verilog HDL: D Flip Flop Using Gate Level

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    Yudhajit Roy
    The document contains code for sequential logic circuits like D flip flop, SR latch, and SR flip flop using both gate level and behavioral modeling in Verilog. It provides code for the module, testbench, and output for each circuit using both approaches.

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    © All Rights Reserved
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    Sequential Design Using Verilog HDL: D Flip Flop Using Gate Level

    Uploaded by

    Yudhajit Roy
    210 views9 pages
    The document contains code for sequential logic circuits like D flip flop, SR latch, and SR flip flop using both gate level and behavioral modeling in Verilog. It provides code for the module, testbench, and output for each circuit using both approaches.

    Original Description:

    LAB MATERIAL

    Original Title

    Analog(Virtual)

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    The document contains code for sequential logic circuits like D flip flop, SR latch, and SR flip flop using both gate level and behavioral modeling in Verilog. It provides code for the module, testbench, and output for each circuit using both approaches.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    210 views9 pages

    Sequential Design Using Verilog HDL: D Flip Flop Using Gate Level

    Uploaded by

    Yudhajit Roy
    The document contains code for sequential logic circuits like D flip flop, SR latch, and SR flip flop using both gate level and behavioral modeling in Verilog. It provides code for the module, testbench, and output for each circuit using both approaches.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 9

    Name: Monjil Chakraborty

    Registration no.: 17BLC1154

    Faculty: Niraj Kumar

    Slot: L9+L10

    Sequential Design using Verilog HDL

    D Flip Flop using Gate level:

    module dflipflop();

    wire Q,Q_BAR;

    reg D,CLK;

    nand U1 (X,D,CLK) ;

    nand U2 (Y,X,CLK) ;

    nand U3 (Q,Q_BAR,X);

    nand U4 (Q_BAR,Q,Y);

    // Testbench of above code

    initial begin

    $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);

    CLK = 0;

    D = 0;

    #3 D = 1;

    #3 D = 0;

    #3 $finish;

    end

    always #2 CLK = ~CLK;

    endmodule
    Output:

    D Flip Flop using Behavioral model:

    module dflipflopmod(q, d, clk);

    output q;
    input d;
    input clk;
    reg q;
    always @(posedge clk)
    q=d;
    endmodule

    module dflipflopt_b;
    reg d;
    reg clk;
    wire q;
    dflipflopmod uut (.q(q),.d(d), .clk(clk) );
    initial begin
    // Initialize Inputs
    d = 0;
    clk = 0;
    end
    always #3 clk=~clk;
    always #5 d=~d;
    initial #100 $stop;
    endmodule
    Output:

    SR Latch using gate level:

    module srlatch(Q,Qbar,R,S);

    output Q,Qbar;

    input R,S;

    nor n1(Q,R,Qbar);

    nor n2(Qbar,S,Q);

    endmodule

    module srlatch_tb();

    wire q,qbar;

    reg set,reset;

    srlatch m1(q, qbar, reset, set);

    initial

    begin

    $monitor("set=%b reset=%b q=%b\n",set,reset,q);

    set=0; reset=0;

    #5 reset=1;

    #10 reset=0; set=1;

    #15 set=1; reset=1;

    #20 set=1; reset=0;


    end

    endmodule

    Output:

    SR Latch using Behavioral model:

    module Srlatchbehav( s ,r ,enable ,reset ,q ,qb);

    output q ;

    reg q ;

    output qb ;

    reg qb ;

    input s ;

    wire s ;

    input r ;

    wire r ;

    input enable ;

    wire enable ;

    input reset ;

    wire reset ;
    always @ (enable or s or r or reset) begin

    if (reset) begin

    q = 0;

    qb = 1;

    end else if (enable) begin

    if (s!=r) begin

    q = s;

    qb = r;

    end else if (s==1 && r==1) begin

    q = 1'bZ;

    qb = 1'bZ;

    end

    end

    end

    endmodule

    Output:
    SR Flip Flop using Gate level:

    module SR(
    input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );
    and (y,S,clk);
    nor (Q,Qbar,y);
    and (z,R,clk);
    nor (Qbar,z,Q);
    endmodule

    module testSR;
    reg [0:0] S;
    reg [0:0] R;
    reg clk;
    wire [0:0] Q;
    wire [0:0] Qbar;
    wire [0:0] Qx;
    wire [0:0] Qbarx;
    // Instantiate the Unit Under Test (UUT)
    SR uut (
    .S(S),
    .R(R),
    .clk(clk),
    .Q(Qx),
    .Qbar(Qbarx)
    );
    initial begin
    // Initialize Inputs
    S = 0;
    R = 0;
    clk = 0;
    fork
    #8 S = 0;
    #8 R = 1;
    #16 S = 1;
    #16 R = 0;
    #24 S = 1;
    #24 R = 1;
    #32 S = 0;
    #32 R = 0;
    join

    end
    SR slave(Qx,Qbarx,~clk,Q,Qbar);
    always #4 clk = ! clk;
    endmodule

    Output:

    SR Flip Flop using Behavioral model:

    module Main(input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );
    reg M,N;

    always @(posedge clk) begin


    M <= !(S & clk);
    N <= !(R & clk);
    end
    assign Q = !(M & Qbar);
    assign Qbar = !(N & Q);

    endmodule

    module TestSR;

    // Inputs
    reg S;
    reg R;
    reg clk;
    // Outputs
    wire Q;
    wire Qbar;

    // Instantiate the Unit Under Test (UUT)


    Main uut (
    .S(S),
    .R(R),
    .clk(clk),
    .Q(Q),
    .Qbar(Qbar)
    );

    initial begin
    // Initialize Inputs
    S = 0;
    R = 0;
    clk = 0;
    fork
    #5 S = 0;
    #10 R = 1;
    #15 S = 0;
    #20 R = 0;
    #25 S = 0;
    #30 R = 1;
    #35 S = 1;
    #40 R = 0;
    #45 S = 1;
    #50 R = 1;
    join
    end
    always #1 clk =! clk;
    endmodule
    Output:
    D Latch using Behavioral model:

    module dlatchmod(e, d, q);


    input e;
    input d;
    output q;
    reg q;
    always @(e or d)
    begin
    if (e)
    q<=d;
    end
    endmodule

    module dlatcht_b;
    reg e;
    reg d;
    wire q;
    dlatchmod uut (.e(e),.d(d),.q(q) );
    initial begin
    d = 0;
    e = 0;
    end
    always #3 e=~e;
    always #5 d=~d;
    initial #1000 $stop;
    endmodule

    Output:

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