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    Lab 3

    Uploaded by

    tamlongnguyen2005

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Lab 3

    Uploaded by

    tamlongnguyen2005
    6 views5 pages

    Original Title

    lab-3

    Copyright

    © © All Rights Reserved

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    PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    6 views5 pages

    Lab 3

    Uploaded by

    tamlongnguyen2005

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    lab 3

    //ex1
    `timescale 1ns / 1ps

    module ex1(
    input wire clk, // 125 MHz clock
    output reg led_red,
    output reg led_blue
    );

    reg [26:0] counter; // 27-bit counter to count up to 62,500,


    000 (0.5 seconds at 125 MHz)

    // Initialize the registers


    initial begin
    counter = 0;
    led_red = 0;
    led_blue = 1; // Initial state: Red LED off, Blue LED on
    end

    // Main process to control LED blinking


    always @(posedge clk) begin
    if (counter == 62_500_000) begin
    counter <= 0;
    led_red <= ~led_red;
    led_blue <= ~led_blue;
    end else begin
    counter <= counter + 1;
    end
    end

    endmodule

    lab 3 1
    //ex2 module
    module ex2(
    input clk,
    input in,
    output reg out
    );

    reg q1, q2;

    always @(posedge clk) begin


    q1 <= in;
    q2 <= q1;
    out <= q1 & ~q2;
    end

    endmodule

    //tb
    module ex2_tb;
    reg clk;
    reg in;
    wire out;

    ex2 uut (
    .clk(clk),
    .in(in),
    .out(out)
    );

    initial begin
    clk = 0;
    forever #5 clk = ~clk; // 100 MHz clock
    end

    initial begin

    lab 3 2
    in = 0;
    #12 in = 1;
    #10 in = 0;
    #20 in = 1;
    #10 in = 0;
    #20 $stop;
    end
    endmodule

    //ex2 arty
    module ex2(
    input clk,
    input in,
    output reg [3:0] out
    );

    reg pre_in;
    reg q1, q2;
    initial begin
    out = 4'b0000;
    end

    always @(posedge clk) begin


    q1 <= in;
    q2 <= q1;
    pre_in = q1 & ~q2;
    if (pre_in) begin
    out <= out + 1;
    end
    end

    endmodule

    lab 3 3
    //ex3
    `timescale 1ns / 1ps
    module ex3(
    input clk,
    input [3:0] btn,
    output reg [3:0] led
    );

    initial begin
    led = 4'b0011;
    end

    reg [26:0] counter; // 27-bit counter to count up to 100,000,


    000 for 1 second interval
    reg shift_enable;
    reg [1:0] state; // State variable

    // State encoding
    localparam IDLE = 2'b00;
    localparam SHIFT_RIGHT = 2'b01;
    localparam SHIFT_LEFT = 2'b10;

    // Initialize counter and state


    initial begin
    counter = 0;
    shift_enable = 0;
    state = IDLE;
    end

    always @(posedge clk) begin


    if (counter == 100_000_000) begin
    counter <= 0;
    shift_enable <= 1;
    end else begin
    counter <= counter + 1;

    lab 3 4
    shift_enable <= 0;
    end
    end

    always @(posedge clk) begin


    if (btn[0]) begin
    led <= 4'b0011;
    state <= IDLE;
    end else if (btn[1]) begin
    state <= SHIFT_RIGHT;
    end else if (btn[2]) begin
    state <= SHIFT_LEFT;
    end else if (btn[3]) begin
    state <= IDLE;
    end

    case (state)
    IDLE: begin
    // Do nothing
    end
    SHIFT_RIGHT: begin
    if (shift_enable) begin
    led <= {led[2:0], led[3]}; // Shift right
    end
    end
    SHIFT_LEFT: begin
    if (shift_enable) begin
    led <= {led[0], led[3:1]}; // Shift left
    end
    end
    endcase
    end

    endmodule

    lab 3 5

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