Wolaita Sodo University: College of Engineering

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WOLAITA SODO UNIVERSITY

College Name:
College of Engineering
Name of Department: Electrical and Computer Engineering
Course Title:
Digital Logic Design
Course Code:
ECEG-3101
Target Group:
Electrical and computer Engineering Department 3rd- section 1,2 and 3
Instructor Name:
GORRE NARSIMHULU
Course Description

Introduction to Digital Systems


Basic and Derived Logic Gates;
Discreet Logic Gates Realization;
Digital Integrated Circuits and Logic Families;
Comparison of Common Logic Families;
Introduction to Switching Algebra;
Design of Logic Systems;
Design of Combinational Logic Systems;
Memory Elements;
Design of Sequential Logic Systems;

Course Objectives
Familiarize students with Number systems and conversions
Define common terminologies used in Boolean algebra and Define Logic Gates
Explain the steps in solving Karnaugh Maps and Minimising SOP and POS Expressions
Use the techniques to design Combinational and sequential logic Circuits
Explain the concepts of Latches, Flip-flops and recognize the differences between them
Analyze Counter timing Diagrams and circuits, Use up/down counters for generation of
binary sequences.
Identify forms of data movement in shift registers and explain how SISO, SIPO, PISO,
and PIPO operate.
Characteristics of Digital IC and explain the differences between all Logic Families
Utilize advanced concepts of Digital Electronics to provide better solutions

Students Roles
Active participation inside and outside the classroom.
1

Submit assignments and group works before the deadline.


Be competent in doing their exercises, quizzes and exam.

Course Outline
Contents
CHAPTER 1
Digital Concepts
1.1 Introduction to Digital Systems
1.2 Digital Vs. Analogue
1.3 Number Systems and Operations
Number system conversions and Complements

CHAPTER 6
Latches, Flip-flops and Timers
6.1 Latches
6.2 Flip-Flops
6.3 Types of Flip-flops
6.3.1. D Flip-flop
6.3.2. T Flip-flop
6.3.3. SR Flip-flop
6.3.4. JK Flip-flop
CHAPTER 7
Shift Registers
7.1 Basic Shift Register Functions
7.2 Types of Shift Registers
7.3 Shift Register Applications
7.4 Shift Register Counters

CHAPTER 2
Logic Gates and Boolean Algebra
2.1 Properties and Theorems of Boolean Algebra
2.2 Boolean Functions
2.3 Basic and Derived Logic Gates
- The Invertor
- The AND gate
- The OR Gate
- The NAND Gate
- The NOR Gate
- Exclusive Gates
CHAPTER 3
Simplification of Boolean Functions
3.1 Introduction
3.2 Karnaugh Maps
3.3 SOP Minimization
3.4 POS Minimization

CHAPTER 8
Digital ICs and Logic Families
8.1 Characteristics of Digital IC
8.2 Bipolar Transistor Characteristics
- RTL
- DTL
- TTL
8.3 Comparison of Different Logic Families

CHAPTER 4
Combinational Logic Analysis
4.1 Basic Combinational Logic Circuits (CLCs)
4.2 Decoders and Encoders
4.3 Multiplexers
4.4 De-Multiplexers

CHAPTER 9
Memory and Storage
9.1 RAMs
9.2 ROMs
9.3 Programmable ROMs
9.3.1 PLA
9.3.2 PAL

CHAPTER 5
Counters
5.1 Asynchronous Operation Counters
5.2 Synchronous Operation Counters
- Up/Down Counters
5.3 Cascaded Counters

Textbook:
Fundamentals of Digital Logic with Verilog Design, Brown and Vranesic, McGrawi-Hill Publ.
References:
Floyd, Digital Electronics (Ch: 1,2,3,6,7,9)
Digital Principles and Logic Design (Ch. 2,3,5,8)
Switching Theory and Automata, Kohavi
M. Morris Mano, Digital Design
Enoch O. Hwang, Digital Logic and Microprocessor Design with VHDL
CONTINUOUS ASSESSMENT ACTION PLAN FORMAT
Course title: Digital Logic Design

Course Code: ECEG-3101

Department: Electrical and Computer Engineering

Credit hrs. 5

S.
N
1
2
3
4
5
6

Kind of assessment
Attendance
Quiz 1,2
Assignment 1 , 2
Mid exam
Final Exam
Total

% of mark

Remark

5%
15%
20%
20%
40%
100%

Prepared by: Gorre Narsimhulu

Date: _______

Signature:

Approved by:_____________

Date:

Signature: _________

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