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    Handout 2016 PDF

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    Shubham Rohila
    This document provides details about the Digital Design course offered in the first semester of 2016-17, including: 1) The course number, title, instructor, team of instructors for lectures, tutorials, and practicals. 2) A description of the course content covering logic circuits, combinational and sequential logic, Verilog, and an introduction to computer organization. 3) The objectives, topics to be covered each week, textbooks, reference books, evaluation scheme, practical experiments, and notices about the course.

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    Handout 2016 PDF

    Uploaded by

    Shubham Rohila
    109 views4 pages
    This document provides details about the Digital Design course offered in the first semester of 2016-17, including: 1) The course number, title, instructor, team of instructors for lectures, tutorials, and practicals. 2) A description of the course content covering logic circuits, combinational and sequential logic, Verilog, and an introduction to computer organization. 3) The objectives, topics to be covered each week, textbooks, reference books, evaluation scheme, practical experiments, and notices about the course.

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    This document provides details about the Digital Design course offered in the first semester of 2016-17, including: 1) The course number, title, instructor, team of instructors for lectures, tutorials, and practicals. 2) A description of the course content covering logic circuits, combinational and sequential logic, Verilog, and an introduction to computer organization. 3) The objectives, topics to be covered each week, textbooks, reference books, evaluation scheme, practical experiments, and notices about the course.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    109 views4 pages

    Handout 2016 PDF

    Uploaded by

    Shubham Rohila
    This document provides details about the Digital Design course offered in the first semester of 2016-17, including: 1) The course number, title, instructor, team of instructors for lectures, tutorials, and practicals. 2) A description of the course content covering logic circuits, combinational and sequential logic, Verilog, and an introduction to computer organization. 3) The objectives, topics to be covered each week, textbooks, reference books, evaluation scheme, practical experiments, and notices about the course.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 4

    BITS, Pilani- K.K.

    Birla Goa Campus


    First Semester 2016-17
    Course Handout (Part-II)
    Date: 04/08/16
    In addition to Part I (General Handout for all the courses appended to the time table), this
    portion gives further specific details regarding the course.

    Course No. : CS /EEE /INSTR F215


    Course Title : Digital Design
    Instructor-in-charge : Dr. Anita Agrawal
    Team of Instructors :
    (i) For Lectures : Dr. Anita Agrawal, Dr. Anupama K.R.
    (ii) For Tutorials : Anita Agrawal, Anupama K.R., Neethu Robinson, Abhishek
    Joshi
    (iii)For Practicals : Anita Agrawal, Neethu Robinson, Jyotsna Kulkarni,
    Rajalekshmi Kishore, Abhishek Joshi, Vikas Khairnar,
    Chebyian Thumbidurai

    Course Description :This course covers the topics on logic circuits and
    minimization, Combinational and sequential logic circuits,
    Programmable Logic devices, State table and state diagrams,
    Digital ICs, Arithmetic operations and algorithms,
    Introduction to Computer organization, Algorithmic State
    Machines. It also introduces Verilog Hardware Descriptive
    Language and hands-on-experience on Reconfigurable devices
    such as Field Programmable Gate Array (FPGA)

    Scope and Objective : The objective of the course is to impart knowledge of the basic
    tools for the design of digital circuits and to provide methods
    and procedures suitable for a variety of digital design
    applications. The course also introduces fundamental concepts
    of computer organization. Laboratory exercises on
    Combination and Sequential logic design will be given as a
    part of the course.
    Self-Study: Q-M method

    Text Books:
    T1: M.Morris Mano and Michael D. Ciletti Digital Design, Pearson, 5th Edition, 2013

    Reference Books:
    R1: Donald D.Givone, Digital Principles and Design TMH, 2003
    R2: W. Stallings, Computer Organization and Architecture PHE, 9th Edition, 2012
    Course Plan:

    Lect. Reference to
    Learning Objectives Topics to be covered
    No. Text Book
    Introduction to Digital
    Systems and Digital Systems, Digital ICs 1.1,1.9, 2.8, 2.9,
    1-2
    Characteristics of Digital 10.1, 10.2
    ICs.
    * 1.2-1.8
    Codes, number systems Number systems and codes
    Boolean functions Canonical
    3 Boolean algebra 2.2-2.7
    forms
    K-Maps (2,3,4 & 5 variables),
    4-5 Simplification of Boolean
    Different types & levels of 3.1 - 3.9
    functions
    implementations, Q-M method
    Simulation and synthesis Hardware Description
    6 3.11
    basics Language (HDL)
    Combinational Logic,
    7-9 Adders, Subtractors Multipliers 4.1 - 4-7
    Arithmetic circuits
    Comparators, Decoders,
    10-12 MSI Components 4.8 - 4.11
    Encoders, MUXs, DEMUXs
    Simulation of
    13 Combinational Logic HDL for Combinational Logic 4.12
    Functions.
    Latches, Flip-Flops &
    14-16 Sequential Logic 5.1 - 5.4
    Characteristic tables
    Digital Integrated TTL, MOS Logic families and
    17-19 10.3 - 10.10
    Circuits their characteristics
    Analysis of clocked sequential
    Clocked Sequential
    20-22 circuits, state diagram and 5.5, 5.7, 5.8
    Circuits
    reduction
    Shift registers, Synchronous &
    6.1- 6.5
    23-25 Registers & Counters Asynchronous counters

    Simulation of Sequential HDL for Sequential Logic, HDL


    26 5.6, 6.6
    Logic Functions. for registers and counters
    Memory Organisation Memory hierarchy, different
    27-30 7.1 - 7.3, 7.5-7.8
    and PLDs types of memories and PLDs
    Analysis of arithmetic Multiplication & Division
    31-33 R2: 9.1-9.3
    units algorithms
    Modular approach for
    34 RTL, HDL description 8.1, 8.2
    CPU Design
    Design of Digital
    35-37 Systems Algorithmic State Machines R1: Chapter 8

    Design of Asynchronous
    38-40 Asynchronous Sequential Logic 9.1 9.4
    Circuits.

    * tutorial
    Evaluation Scheme:

    Maximum
    Marks (%
    Component Duration Date & Time Remarks
    wise
    weightage)
    19/09/16,
    Test I 1 hr 45 (15%) CB
    8:30 to 9:30 am.
    24/10/16
    Test II 1 hr 45 (15%) CB
    8:30 to 9:30 am.
    Assignments/Tutorials/Quiz
    20 (6.67%) ** OB
    /Project
    120, OB: 30
    Comprehensive Examination 3 hrs (10%) CB: 90 01/12/16 (FN) CB/OB
    (30%)
    Laboratory (Regularity, lab Regular lab
    30 (10%) OB
    Reports) sessions
    Lab Exam 20 (6.67%) ** CB
    On-line exam 20 (6.67%) ** CB

    Open book:
    Ass/tut/quiz/project: 6.67%
    Lab regularity: 10%
    Compre exam: 10%

    Total OB (%): 26.67

    ** To be announced later

    Practicals
    S.No. Name of experiment
    1. FAMILIARIZATION OF BENCH EQUIPMENTS
    2. IMPLEMENTATION OF BOOLEAN FUNCTIONS USING LOGIC GATES
    3. ADDERS AND SUBTRACTORS
    4. BCD ADDER
    5. DECODERS, MULTIPLEXERS AND DEMULTIPLEXERS
    6. COMPARATORS & ARITHMETIC LOGIC UNIT
    7. LATCHES & FLIP-FLOPS
    8. OPERATION OF 4-BIT COUNTER
    9. COUNTERS
    10. SHIFT REGISTERS
    11. SEQUENTIAL CIRCUITS

    Chamber Consultation Hour: To be announced in class


    Notices: All notices will be displayed on Wing A notice board and photon

    Make-up Policy: Make-up in any of the components may be granted only in extremely
    genuine cases and with prior permission of the IC.

    INSTRUCTOR-IN-CHARGE

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