HD61830/HD61830B

LCDC (LCD Timing Controller)

ADE-207-275(Z)
'99.9
Rev. 0.0
Description
The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the
display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal
driving signals.
It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on
liquid crystal display and a character mode in which characters are displayed by storing character codes in
the external RAM and developing them into the dot patterns with the internal character generator ROM.
Both modes can be provided for various applications.
The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS
microcontroller it can complete a liquid crystal display device with lower power dissipation.

Features
Dot matrix liquid crystal graphic display controller
Display control capacity
Graphic mode: 512k dots (216 bytes)
Character mode: 4096 characters (212 characters)
Internal character generator ROM: 7360 bits
160 types of 5 7 dot characters
32 types of 5 11 dot characters
Total 192 characters
Can be extended to 256 characters (4 kbytes max.) with external ROM

HD61830/HD61830B
Interfaces to 8-bit MPU
Display duty cycle (can be selected by a program)
Static to 1/128 duty cycle
Various instruction functions
Scroll, cursor on/off/blink, character blink, bit manipulation
Display method: Selectable A or B types
Internal oscillator (with external resistor and capacitor) HD61830
Operating frequency
1.1 MHz HD61830
2.4 MHz HD61830B
Low power dissipation
Power supply: Single +5 V 10%
CMOS process

HD61830/HD61830B
Differences between Products
HD61830 and HD61830B
HD61830

HD61830B

Oscillator

Internal or external

External only

Operating frequency

1.1 MHz

2.4 MHz

Pin arrangement
and signal name

Pin 6: C
Pin 7: R
Pin 9: CPO

Pin 6: CE
Pin 7: OE
Pin 9: NC

Package marking
to see figure

Package Marking

3D13
A

Lot No.

HD61830A00
JAPAN

3D13
B

Lot No.

HD61830B00
JAPAN

Ordering Information
Type No.

Package

HD61830A00H

60-pin plastic QFP (FP-60)

HD61830B00H

HD61830/HD61830B

MB

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

60

59

58

57

56

55

54

MA10

(CE) C

53

MA11

(OE) R

52

MA12

CR

51

MA13

(NC) CPO

50

MA14

FLM

10

49

MA15

CL1

11

48

D2

SYNC

12

47

D1

WE

13

46

CL2

RES

14

45

RD0

CS

15

44

RD1

16

43

RD2

R/W

17

42

RD3

RS

18

41

RD4

MA

19

40

RD5

GND

20

39

RD6

DB7

21

38

RD7

DB6

22

37

MD0

DB5

23

36

MD1

( ) is for HD61830B

Pin Arrangement

24

25

26

27

28

29

30

31

32

33

34

35

DB4

DB3

DB2

DB1

DB0

VCC

MD7

MD6

MD5

MD4

MD3

MD2

FP-60
(Top view)

HD61830/HD61830B
Terminal Functions
Symbol

Pin Number

I/O

Function

DB0DB7

2821

I/O

Data bus: Three-state I/O common terminal

Data is transferred to MPU through DB0 to DB7.

CS

15

Chip select: Selected state with CS = 0

R/W

17

Read/Write:R/W = 1: MPU HD61830

R/W = 0: MPU HD61830

RS

18

Register select: RS = 1: Instruction register

RS = 0: Data register

16

Enable: Data is written at the fall of E

Data can be read while E is 1

CR

CR oscillator (HD61830), External clock input (HD61830B)

CR oscillator to capacitor (HD61830 only)

CR oscillator to resistor (HD61830 only)

CPO

Clock signal for HD61830 in slave mode (HD61830 only)

CE

Chip enable (HD61830B only)

CE = 0: Chip enables make external RAM in active

OE

Output enable (HD61830B only)

OE = 1: Output enable informs external RAM that HD61830B requires
data bus

NC

Open Unused terminal. Dont connect any wires to this terminal

(HD61830B only)

MA0MA15

41, 6049

External RAM address output

In character mode, the line code for external CG is output through
MA12 to MA15 (0: Character 1st line, F: Character 16th line)

MD0MD7

3730

I/O

Display data bus: Three-state I/O common terminal

RD0RD7

4538

ROM data input: Dot data from external character generator is input

WE

13

Write enable: Write signal for external RAM

CL2

46

Display data shift clock for LCD drivers

CL1

11

Display data latch signal for LCD drivers

FLM

10

Frame signal for display synchronization

MA

19

Signal for converting liquid crystal driving signal into AC, A type

MB

Signal for converting liquid crystal driving signal into AC, B type

D1

47

D2

48

Display data serial output

D1: For upper half of screen
D2: For lower half of screen

SYNC

12

I/O

Synchronous signal for parallel operation

Three-state I/O common terminal (with pull-up MOS)
Master: Synchronous signal is output
Slave: Synchronous signal is input

RES

14

Reset: Reset = 0 results in display off, slave mode and Hp = 6

CS
E
RS
R/W
RES

DB0DB7

CL2

Busy
flag
(BF)

Rf

Cf

Oscillator
circuit

Instruction
register
(IR)

Data
output
register
(DOR)

Data
input
register
(DIR)

CPO

Control
signal

Mode
control
register
(MCR)

6
8

(CR)

Multiplexer

Parallel/serial
converter

Parallel/serial
converter

Multiplexer

Character
generator
ROM
(CGROM)

(OE)

(CE)

D2

D1

RD0RD7

Extended
external
ROM

MD0MD7

RAM

WE

( ) is for HD61830B

* When extended external ROM is used, MA0MA11

are applied to RAM, MA12 MA15 are applied to
extended external ROM.

Cursor
signal
generator

Line address
counter

Refesh address 16
counter (1)
(RAC1)
Refesh address 16
counter (2)
(RAC2)
Cursor address 16
counter
(CAC)

Oscillator
circuit

Control
signal

(CL2)

Dot registers
(DR)

Dot counter
(DC)

SYNC CL1 MA MB FLM

HD61830/HD61830B

Block Diagram

I/O interface circuit

HD61830/HD61830B
Block Functions
Registers
The HD61830/HD61830B has the five types of registers: instruction register (IR), data input register (DIR),
data output register (DOR), dot registers (DR), and mode control register (MCR).
The IR is a 4-bit register that stores the instruction codes for specifying MCR, DR, a start address register,
a cursor address register, and so on. The lower order 4 bits DB0 to DB3 of data buses are written in it.
The DIR is an 8-bit register used to temporarily store the data written into the external RAM, DR, MCR,
and so on.
The DOR is an 8-bit register used to temporarily store the data read from the external RAM. Cursor address
information is written into the cursor address counter (CAC) through the DIR. When the memory read
instruction is set in the IR (latched at the falling edge of E signal), the data of external RAM is read to DOR
by an internal operation. The data is transferred to the MPU by reading the DOR with the next instruction
(the contents of DOR are output to the data bus when E is at the high level).
The DR are registers used to store dot information such as character pitches and the number of vertical
dots, and so on. The information sent from the MPU is written into the DR via the DIR.
The MCR is a 6-bit register used to store the data which specifies states of display such as display on/off
and cursor on/off/blink. The information sent from the MPU is written in it via the DIR.
Busy Flag (BF)
The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot be
accepted. As shown in Control Instruction, read busy flag, the busy flag is output on DB7 under the
conditions of RS = 1, R/W = 1, and E = 1. Make sure the busy flag is 0 before writing the next instruction.
Dot Counters (DC)
The dot counters are counters that generate liquid crystal display timing according to the contents of DR.

HD61830/HD61830B
Refresh Address Counters (RAC1/RAC2)
The refresh address counters, RAC1 and RAC2, control the addresses of external RAM, character generator
ROM (CGROM), and extended external ROM. The RAC1 is used for the upper half of the screen and the
RAC2 for the lower half. In the graphic mode, 16-bit data is output and used as the address signal of
external RAM. In the character mode, the high order 4 bits (MA12MA15) are ignored. The 4 bits of line
address counter are output instead and used as the address of extended ROM.
Character Generator ROM
The character generator ROM has 7360 bits in total and stores 192 types of character data. A character code
(8 bits) from the external RAM and a line code (4 bits) from the line address counter are applied to its
address signals, and it outputs 5-bit dot data.
The character font is 5 7 (160 characters) or 5 11 (32 characters). The use of extended ROM allows 8
16 (256 characters max.) to be used.
Cursor Address Counter
The cursor address counter is a 16-bit counter that can be preset by instruction. It holds an address when the
data of external RAM is read or written (when display dot data or a character code is read or written). The
value of the cursor address counter is automatically increased by 1 after the display data is read or written
and after the set/clear bit instruction is executed.
Cursor Signal Generator
The cursor can be displayed by instruction in character mode. The cursor is automatically generated on the
display specified by the cursor address and cursor position.
Parallel/Serial Conversion
The parallel data sent from the external RAM, character generator ROM, or extended ROM is converted
into serial data by two parallel/serial conversion circuits and transferred to the liquid crystal driver circuits
for upper screen and lower screen simultaneously.

HD61830/HD61830B
Display Control Instructions
Display is controlled by writing data into the instruction register and 13 data registers. The RS signal
distinguishes the instruction register from the data registers. 8-bit data is written into the instruction register
with RS = 1, and the data register code is specified. After that, the 8-bit data is written in the data register
and the specified instruction is executed with RS = 0.
During the execution of the instruction, no new instruction can be accepted. Since the busy flag is set
during this, read the busy flag and make sure it is 0 before writing the next instruction.
1. Mode Control: (Execution time: 4 s) Code H'00 (hexadecimal) written into the instruction register
specifies the mode control register.
DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Mode control reg.

Mode data

Cursor/blink

CG

DB3

DB2

DB1

DB0

1/0

1/0

Cursor on

Cursor off, character blink

Cursor blink

Cursor on

Cursor off, character blink

Cursor blink

Master/slave

DB4

Display ON/OFF

DB5

Ext./Int. CG

DB7

Graphic/character
mode

RS

Cursor

R/W

Blink

Internal CG

Cursor off

Graphic/character
display
Character display
(Character mode)

Cursor off

External CG

Register

Graphic mode

1: Master mode
0: Slave mode
1: Display ON
0: Display OFF

HD61830/HD61830B
2. Set Character Pitch: (Execution time: 4 s) Vp indicates the number of vertical dots per character. The
space between the vertically-displayed characters is included in the determination. This value is meaningful
only during character display (in the character mode) and becomes invalid in the graphic mode.
H p indicates the number of horizontal dots per character in display, including the space between
horizontally-displayed characters. In the graphic mode, the Hp indicates the number of bits of 1-byte display
data to be displayed.
There are three Hp values (Table 1).
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Character pitch reg.

Table 1

(Vp 1) binary

Hp Values

Hp

DB2

DB1

DB0

Horizontal Character Pitch

10

(Hp 1) binary

HD61830/HD61830B
3. Set Number of Characters: (Execution time: 4 s) HN indicates the number of horizontal characters in
the character mode or the number of horizontal bytes in the graphic mode. If the total sum of horizontal
dots on the screen is taken as n,
n = Hp HN
HN can be set to an even number from 2 to 128 (decimal).
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Number-of-characters reg.

(HN 1) binary

4. Set Number of Time Divisions (Inverse of Display Duty Ratio): (Execution time: 4 s) NX indicates
the number of time divisions in multiplex display.
1/NX is the display duty ratio.
A value of 1 to 128 (decimal) can be set to NX.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Number-of-time-divisions reg.

(NX 1) binary

5. Set Cursor Position: (Execution time: 4 s) Cp indicates the position in a character where the cursor is
displayed in the character mode. For example, in 5 7 dot font, the cursor is displayed under a character by
specifying C p = 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch H p. A
value of 1 to 16 (decimal) can be set to Cp. If a smaller value than the vertical character pitch Vp is set (Cp
Vp), and a character overlaps with the cursor, the cursor has higher priority of display (at cursor display
on). If Cp is greater than Vp, no cursor is displayed. The cursor horizontal length is equal to Hp.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Cursor position reg.

(Cp 1) binary

11

HD61830/HD61830B
6. Set Display Start Low Order Address: (Execution time: 4 s) Cause display start addresses to be
written in the display start address registers. The display start address indicates a RAM address at which the
data displayed at the top left end on the screen is stored. In the graphic mode, the start address is composed
of high/low order 16 bits. In the character display, it is composed of the lower 4 bits of high order address
(DB3DB0) and 8 bits of low order address. The upper 4 bits of high order address are ignored.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Display start address reg.

(low order byte)

(Start low order address) binary

Set Display Start High Order Address

Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Display start address reg.

(high order byte)

(Start high order address) binary

7. Set Cursor Address (Low Order) (RAM Write Low Order Address): (Execution time: 4 s) Cause
cursor addresses to be written in the cursor address counters. The cursor address indicates an address for
sending or receiving display data and character codes to or from the RAM.
That is, data at the address specified by the cursor address are read/written. In the character mode, the
cursor is displayed at the character specified by the cursor address.
A cursor address consists of the low-order address (8 bits) and the high-order address (8 bits). Satisfy the
following requirements setting the cursor address (Table 2).
The cursor address counter is a 16-bit up-counter with set and reset functions. When bit N changes from 1
to 0, bit N + 1 is incremented by 1. When setting the low order address, the LSB (bit 1) of the high order
address is incremented by 1 if the MSB (bit 8) of the low order address changes from 1 to 0. Therefore, set
both the low order address and the high order address as shown in the Table 2.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Cursor address counter

(low order byte)

12

(Cursor low order address) binary

HD61830/HD61830B
Set Cursor Address (High Order) (RAM Write High Order Address)
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Cursor address counter

(high order byte)

Table 2

(Cursor high order address) binary

Cursor Address Setting

Condition

Requirement

When you want to rewrite (set ) both the low order

address and the high order address.

Set the low order address and then set the high
order address.

When you want to rewrite only the low order address. Do not fail to set the high order address again after
setting the low order address.
When you want to rewrite only the high order address. Set the high order address. You do not have to set
the low order address again.

13

HD61830/HD61830B
8. Write Display Data: (Execution time: 6 s) After the code $0C is written into the instruction register
with RS = 1, 8-bit data with RS = 0 should be written into the data register. This data is transferred to the
RAM specified by the cursor address as display data or character code. The cursor address is increased by 1
after this operation.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

RAM

MSB (pattern data, character code) LSB

9. Read Display Data: (Execution time: 6 s) Data can be read from the RAM with RS = 0 after writing
code $0D into the instruction register. Figure 1 shows the read procedure.
This instruction outputs the contents of data output register on the data bus (DB0 to DB7) and then
transfers RAM data specified by the cursor address to the data output register, also increasing the cursor
address by 1. After setting the cursor address, correct data is not output at the first read but at the second
one. Thus, make one dummy read when reading data after setting the cursor address.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

RAM

OB

MSB (pattern data, character code) LSB

CS
E
R/W
RS
B

DB

0A

Busy Cursor
check address
set
mode

Cursor
address

NL

Cursor Busy
low
check
order
address
write

Cursor
address
set
mode

NL

NU

Cursor Busy
high
check
order
address
write

0D
Data
read
mode

*
Dummy
read

Data output
register

(N)

(N+1)

Busy N
check address
data
read

Busy N + 1
check address
data
read

N+1

N+2

N+3

N address data N + 1 address data N + 2 ...

Figure 1 Read Procedure

14

HD61830/HD61830B
10. Clear Bit: (Execution time: 36 s) The clear/set bit instruction sets 1 bit in a byte of display data RAM
to 0 or 1, respectively. The position of the bit in a byte is specified by NB and RAM address is specified by
cursor address. After the execution of the instruction, the cursor address is automatically increased by 1. NB
is a value from 1 to 8. NB = 1 and NB = 8 indicates LSB and MSB, respectively.
Register

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Bit clear reg.

R/W

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction reg.

Bit set reg.

(NB 1) binary

Set Bit
Register

(NB 1) binary

11. Read Busy Flag: (Execution time: 0 s) When the read mode is set with RS = 1, the busy flag is
output to DB7. The busy flag is set to 1 during the execution of any of the other instructions. After the
execution, it is set to 0. The next instruction can be accepted. No instruction can be accepted when busy
flag = 1. Before executing an instruction or writing data, perform a busy flag check to make sure the busy
flag is 0. When data is written in the register (RS = 1), no busy flag changes. Thus, no busy flag check is
required just after the write operation into the instruction register with RS = 1.
The busy flag can be read without specifying any instruction register.
Register

R/W

RS

DB7

Busy flag

1/0

DB6

DB5

DB4

DB3

DB2

DB1

DB0

15

HD61830/HD61830B
Hp
RD7

NX

Cp

Vp

RD0

CURA
STA

HN (digit)

Symbol

Name

Meaning

Value

Hp

Horizontal character pitch

Horizontal character pitch

6 to 8 dots

HN

Number of horizontal
characters

Number of horizontal characters per

line (number of digits) in the character
mode or number of bytes per line in
the graphic mode

2 to 128 digits
(an even number)

Vp

Vertical character pitch

Vertical character pitch

1 to 16 dots

Cp

Cursor position

Line number on which the cursor

can be displayed

1 to 16 lines

NX

Number of time divisions

Inverse of display duty ratio

1 to 128 lines

Note: If the number of vertical dots on the screen is m, and the number of horizontal dots is n,
1/m = 1/NX = display duty ratio
n = Hp HN,
m/Vp = Number of display lines
Cp Vp

Figure 2 Display Variables

16

Character code
(8 bits)

Display pattern
(8 bits)

Graphic

Display Data
from MPU

Character
display

Display Mode

Start
address

Start
address

1 1 1 1 1 1 1 1

0 1 0 1 0 1 0 1

b7 b6 b5 b4 b3 b2 b1 b0

0 1 0 0 0 0 1 0

0 1 0 0 0 0 0 1

b7 b6 b5 b4 b3 b2 b1 b0

RAM

b0

Hp

8 dots

Hp: 8 dots

8 dots

b7

Hp: 6, 7, or 8 dots

Hp

Liquid Crystal
Display Panel

HD61830/HD61830B

Display Mode

17

HD61830/HD61830B
Internal Character Generator Patterns and Character Codes
Lower
4 bits

Higher
4 bits

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

xxxx1111

18

0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111

HD61830/HD61830B
Example of Correspondence between External CGROM Address Data and
Character Pattern
8 8 Dot Font
A10

A 9

A 8

A 7

A6 A5 A4 A3 A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07

8 16 Dot Font
A11
0
0
A10
0
0
A 9
0
0
A 8
0
1
A7 A6 A5 A4 A3 A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07
0

0 0 0 0

0 0 0 1

0 0 1 0
0 0 1 1

0 1 0 0

0
0
0
1

1
1
1
0

0
1
1
0

1
0
1
0

0
0

0
0
0
0

0
0
0
0

0
0
0

1
1
1
1
1

0
0
0
1
1

0
1
1
0
0

1
0
1
0
1

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

1 1 1 0
1 1 1 1
0 0 0 0

0
0
0

0
0
0

0
0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0
0
0

0
0
0
0

0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0
0

0
0

0
0
0

0
0
0
0

0
0

0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
1
0

19

HD61830/HD61830B
Example of Configuration
Graphic Mode or Character Mode (1) (Internal Character Generator)

HD61830
HD61830B

MPU

Liquid crystal
display module

MA0 MA15 at graphic mode,

MA0 MA11 at character mode

MD0MD7

RAM

Character Mode (2) (External Character Generator)

HD61830
HD61830B

MPU

MA12
RD0RD7 MA15
ROM

20

MD0
MD7

Liquid crystal
display module
MA0MA11

RAM

HD61830/HD61830B
Parallel Operation (HD61830)
(Master)
MPU

HD61830 (1)
CS CPO SYNC
RAM

Liquid crystal
Liquid crystal
display module (1) display module (2)
Driving both of two
module by same
common signal

CR SYNC
HD61830 (2)
CS (Slave)
RAM

Parallel Operation (HD61830B)

(Master)
MPU

HD61830B (1)
CS

SYNC
RAM

Liquid crystal
Liquid crystal
display module (1) display module (2)
Driving both of two
module by same
common signal

SYNC
HD61830B (2)
CS (Slave)
RAM

21

HD61830/HD61830B
HD61830 Application (Character Mode, External CG, Character Font 8 8)
HD61830

HD6800
A0
A12
A13
A14
A15
VMA
D0
to
D7
2

DB0
to
DB7
E

R/W

R/W

CS

A0A2

VCC

D1
FLM
MB
CL1
CL2
D2
MA

SYNC
CPO
RES
R

D0
to
D7

A3 A10

ROM
HN462716

OE
CE
D1
FLM
M
CL1
CL2
D2
+5 V
GND
5 V
V0

Open

CR
C

+5 V
GND
5 V

OE

RAM (2)
A0
HM6116
to
A10
CS

MA11
MA12
to
MA14
MA15
MD0
to
MD7
RD0
to
RD7

Open

WE

WE
OE
A0 RAM (1)
HM6116
to
A10
CS

WE
MA0
to
MA10

RS

LCD module

HD61830 Application (Graphic Mode)

DB0DB7
CS E
RS R/W
RES

HD61830
controller

D1
D2

Segment
driver

CL1, CL2
MB, FLM
MA0
MA15
MD0MD7

WE

RAM
16 kbits
CMOS

LCD

Segment
driver

GND
VDD (5 V)
VEE (5 V)

22

Segment
driver

Common
driver

HD6800
MPU

V1 V6
Power supply for
liquid crystal
display drive

Segment
driver

HD61830/HD61830B
HD61830B Application (Character Mode, External CG, Character Font 8 8)
HD6303

HD61830B
A0

RS

A1
to
A15

CS

OE
CE
MA11
MA12
to
MA15
MD0
to
MD7

Decoder
D0
to
D7

DB0
to
DB7
E

R/W

R/W

OE
WE
D0
A0 RAM (1) to
to HM6116 D7
A10
CS

WE
MA0
to
MA10

A0A3
RD0
to
RD7

Open
VCC
External
clock

D1
FLM
MB
CL1
CL2
D2
MA

SYNC
RES
CR

D0
to
D7

WE
A0 RAM (2)
HM6116
to
A10

OE
D0
to
D7
CS

A4A11

ROM
HN482732A

OE
CE
D1
FLM
M
CL1
CL2
D2
+5 V
GND
5 V

Open

LCD module

V0
+5 V
GND
5 V

HD61830B Application (Graphic Mode)

D1

DB0 DB7
HD61830B
controller

CS E
RS R/W
RES

Segment
driver

D2

Segment
driver

CL1, CL2
MB, FLM
MA0
MA15
OE

CE

MD0MD7

WE

RAM
16 kbits
CMOS

Common
driver

HD6303
MPU

LCD

Segment
driver

GND

Segment
driver

V1 V6
Power supply for
liquid crystal
display drive

VDD (5 V)
VEE (5 V)

23

HD61830/HD61830B
HD61830 Absolute Maximum Ratings
Item

Symbol

Value

Unit

Notes

Supply voltage

VCC

0.3 to +0.7

1, 2

Terminal voltage

VT

0.3 to VCC +0.3

1, 2

Operating temperature

Topr

20 to +75

Storage temperature

Tstg

55 to +125

Notes: 1. All voltages are referenced to GND = 0 V.

2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed.
We strongly recommend that you use the LSIs within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.

24

HD61830/HD61830B
HD61830 Electrical Characteristics (VCC = 5 V 10%, GND = 0 V, T a = 20 to
+75C)
Item

Symbol Min

Typ

Max

Unit

Test Condition Notes

Input high voltage (TTL)

VIH

2.2

VCC

Input low voltage (TTL)

VIL

0.8

Input high voltage

VIHR

3.0

VCC

Input high voltage (CMOS)

VIHC

0.7 VCC

VCC

Input low voltage (CMOS)

VILC

0.3 VCC

Output high voltage (TTL)

VOH

2.4

VCC

I OH = 0.6 mA

Output low voltage (TTL)

VOL

0.4

I OL = 1.6 mA

Output high voltage (CMOS)

VOHC

VCC 0.4

VCC

I OH = 0.6 mA

Output low voltage (CMOS)

VOLC

0.4

I OL = 0.6 mA

Input leakage current

I IN

VIN = 0 VCC

Three-state leakage current

I TSL

10

10

VOUT = 0 VCC 8

Power dissipation (1)

PW 1

10

15

mW

CR oscillation
f osc = 500 kHz

Power dissipation (2)

PW 2

20

30

mW

External clock
f cp = 1 MHz

Internal clock operation

(Clock oscillation frequency)

f osc

400

500

600

kHz

Cf = 15 pF 5% 10
Rf = 39 k 2%

External clock operation

(External clock operating frequency)

f cp

100

500

1100

kHz

11

External clock duty

Duty

47.5

50

52.5

11

External clock rise time

t rcp

0.05

11

External clock fall time

t fcp

0.05

11

Pull-up current

I PL

10

20

VIN = GND

12

Notes: The I/O terminals have the following configuration:

1. Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES.
2. Applied to input terminals and I/O common terminals, except terminals SYNC and CR.
3. Applied to terminal RES.
4. Applied to terminals SYNC and CR.
5. Applied to terminals DB0DB7, WE, MA0MA15, and MD0MD7.
6. Applied to terminals SYNC, CP0, FLM, CL1, CL2, D1, D2, MA, and MB.
7. Applied to input terminals.
8. Applied to I/O common terminals. However, the current which flows into the output drive MOS is
excluded.

25

HD61830/HD61830B

PW (mW)

9. The current which flows into the input and output circuits is excluded. When the input of CMOS is
in the intermediate level, current flows through the input circuit, resulting in the increase of power
supply current. To avoid this, input must be fixed at high or low.
The relationship between the operating frequency and the power dissipation is given below.
50
Max
40
30

Typ

20
10
0

250

500

750

1000

1250

1500

fOSC (kHz)
10. Applied to the operation of the internal oscillator when oscillation resistor Rf and oscillation
capacity Cf are used.
Cf = 15 pF 5%
Rf = 39 k 2%
(when fOSC =
500 kHz typ)

R
Rf

C
Cf
CR

The relationship among oscillation frequency, R f and Cf is given below.

Ta = 25C, VCC = 5 V

fOSC (kHz)
800
600
400

Cf = 10 pF
Cf = 15 pF

200
0

26

40

60

80

100

120

140

160

180
Rf (k)

HD61830/HD61830B
11. Applied to external clock operation.
TI

Th
Open

Open

Oscillator

0.7 VCC
0.5 VCC
0.3 VCC

CR
Duty cycle =
trcp

tfcp

Th
100%
Th + TI

12. Applied to SYNC, DB0DB7, and RD0RD7.

27

HD61830/HD61830B
Input Terminal
Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)
VCC
PMOS

NMOS

Applicable terminal: RD0RD7 (with pull-up MOS)

VCC
PMOS

VCC
PMOS

(Pull-up MOS)
NMOS

28

HD61830/HD61830B
Output Terminal
Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, CPO, MA0MA15
VCC
PMOS

NMOS

I/O Common Terminal

Applicable terminal: DB0DB7, SYNC, MD0MD7 (MD0MD7 have no pull-up MOS)
VCC
PMOS

VCC
PMOS

VCC

(Pull-up MOS)

Enable
NMOS

PMOS
Data

Input circuit

NMOS

Output circuit
(Three state)

29

HD61830/HD61830B
Timing Characteristics
HD61830 MPU Interface (V CC = 5 V 10%, GND = 0 V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Enable cycle time

t CYC

1.0

High level

t WEH

0.45

Low level

t WEL

0.45

Enable rise time

t Er

25

ns

Enable fall time

t Ef

25

ns

Setup time

t AS

140

ns

Data setup time

t DSW

225

ns

Data delay time

t DDR

225

ns *

Data hold time

t DHW

10

ns

Address hold time

t AH

10

ns

Output data hold time

t DH

20

ns

Enable pulse width

Note: * The following load circuit is connected for specification:

tCYC
tWEH

tWEL

2.2 V

0.8 V

tEr

tEf

tAS

tAH

2.2 V

CS, R/W, RS

0.8 V
tDSW

tDHW

2.2 V
0.8 V

DB0DB7
(MPUHD61830)

tDDR
DB0DB7
(MPUHD61830)

tDH

2.4 V
0.4 V
VCC
D1

RL

Test point
D2
R

30

D3
D4

RL = 2.4 k
R = 11 k
C = 130 pF (C includes jig capacitance)
Diodes D1 to D4 : 1S2074 H

HD61830/HD61830B
HD61830 External RAM and ROM Interface (VCC = 5 V 10%, GND = 0 V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

SYNC delay time

t DSY

200

ns

t WSY

900

ns

t CCPO

900

ns

High level

t WCPOH

450

ns

Low level

t WCPOL

450

ns

MA0 to MA15 refresh delay time

t DMAR

200

ns

MA0 to MA15 write address delay time

t DMAW

200

ns

MD0 to MD7 write data delay time

t DMDW

200

ns

MD0 to MD7, RD0 to RD7 setup time

t SMD

900

ns

Memory address setup time

t SMAW

250

ns

Memory data setup time

t SMDW

250

ns

WE delay time

t DWE

200

ns

WE pulse width (low level)

t WWE

450

ns

SYNC pulse width

Low level

CPO cycle time

CPO pulse width

SYNC
tDSY

1
V
2 CC
tWSY

tCCPO
1
V
2 CC

CPO
tWCPOL

tWCPOH
2.4 V
0.4 V

MA0MA15

tDMAR

tDMAR
MD0MD7

*
2.2 V
0.8 V
tSMD

RD0RD7

tDMAW

tSMAW

*
2.2 V
0.8 V
*

tDMDW

2.4 V
0.4 V
tSMDW

2.2 V
0.8 V
tSMD
*
2.4 V
0.4 V

WE
tDWE

tWWE

Notes: 1. No load is applied to all the output terminals.

2. * indicates the delay time of RAM and ROM.

31

HD61830/HD61830B
HD61830 LCD Driver Interface (VCC = 5 V 10%, GND = 0 V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Clock pulse width (high level)

t WCL1

450

ns

Clock delay time

t DCL2

200

ns

Clock cycle time

t WCL2

900

ns

High level

t WCH

450

ns

Low level

t WCL

450

ns

MA, MB delay time

t DM

300

ns

FLM delay time

t DF

300

ns

Data delay time

t DD

200

ns

Data setup time

t SD

250

ns

Clock pulse width

Note: No load is applied to all the output terminals (MA, MB, FLM, D1, and D2).

tWCL1

CL1

1V
2 CC
tWCL2

tDCL2

1V
2 CC

CL2

tWCH
1V
2 CC

MA, MB
tDM

tDF

FLM

1V
2 CC

D1
tDD
D2

32

tWCL

tSD
1V
2 CC

HD61830/HD61830B
HD61830B Absolute Maximum Ratings
Item

Symbol

Value

Unit

Notes

Supply voltage

VCC

0.3 to +0.7

1, 2

Terminal voltage

VT

0.3 to VCC +0.3

1, 2

Operating temperature

Topr

20 to +75

Storage temperature

Tstg

55 to +125

Notes: 1. All voltage is referred to GND = 0 V.

2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed.
We strongly recommend that you use the LSIs within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.

33

HD61830/HD61830B
HD61830B Electrical Characteristics (VCC = 5V 10%, GND = 0V, T a = 20 to
+75C)
Item

Symbol

Min

Typ

Max

Unit

Test Condition Notes

Input high voltage (TTL)

VIH

2.2

VCC

Input low voltage (TTL)

VIL

0.8

Input high voltage

VIHR

3.0

VCC

Input high voltage (CMOS)

VIHC

0.7 VCC

VCC

Input low voltage (CMOS)

VILC

0.3 VCC

Output high voltage (TTL)

VOH

2.4

VCC

I OH = 0.6 mA

Output low voltage (TTL)

VOL

0.4

I OL = 1.6 mA

Output high voltage (CMOS)

VOHC

VCC 0.4

VCC

I OH = 0.6 mA

Output low voltage (CMOS)

VOLC

0.4

I OI = 0.6 mA

Input leakage current

I IN

VIN = 0 VCC

Three-state leakage current

I TSL

10

10

VOUT = 0 VCC 8

Pull-up current

I PL

10

20

Vin = GND

Power dissipation

PW

50

mW

External clock
f cp = 2.4 MHz

10

Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES.
Applied to input terminals and I/O common terminals, except terminals SYNC and CR.
Applied to terminal RES.
Applied to terminals SYNC and CR.
Applied to terminals DB0DB7, WE, MA0MA15, OE, CE, and MD0MD7.
Applied to terminals SYNC, FLM, CL1, CL2, D1, D2, MA, and MB.
Applied to input terminals.
Applied to I/O common terminals. However, the current which flows into the output drive MOS is
excluded.
9. Applied to SYNC, DB0DB7, and RD0RD7.
10. The current which flows into the input and output circuits is excluded. When the input of CMOS is
in the intermediate level, current flows through the input circuit, resulting in the increase of power
supply current. To avoid this, input must be fixed at high or low.

Notes: 1.
2.
3.
4.
5.
6.
7.
8.

34

HD61830/HD61830B
Input Terminal
Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)
VCC
PMOS

NMOS

Applicable terminal: RD0RD7 (with pull-up MOS)

VCC
PMOS

VCC
PMOS

(Pull-up MOS)
NMOS

35

HD61830/HD61830B
Output Terminal
Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, OE, CE, MA0MA15
VCC
PMOS

NMOS

I/O Common Terminal

Applicable terminal: DB0DB7, SYNC, MD0MD7 (MD0MD7 have no pull-up MOS)
VCC

VCC
PMOS

PMOS

VCC

(Pull-up MOS)

Enable
PMOS
NMOS
Data
Input circuit

NMOS

Output circuit
(Three state)

36

HD61830/HD61830B
Timing Characteristics
HD61830B Clock Operation (V CC = 5 V 10%, GND = 0V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Notes

External clock operating frequency

f cp

100

2400

kHz

External clock duty

Duty

47.5

50

52.5

External clock rise time

t rcp

25.0

ns

External clock fall time

t fcp

25.0

ns

SYNC output hold time

t HSYO

30

ns

2, 3

SYNC output delay time

t DSY

210

ns

2, 3

SYNC input hold time

t HSYI

10

ns

SYNC input set-up time

t SSY

180

ns

Th

Tl

Notes: 1. Applied to external clock input terminal.

0.7 VCC
0.5 VCC
0.3 VCC
Oscillator

CR
tfcp

trcp

Duty cycle =

Th
Th + Tl

100%

2. Applied to SYNC terminal.

0.7 VCC
CR

0.3 VCC
tDSY
tHSYO

SYNC
(Output:
at master
mode)

SYNC
(Input:
at slave
mode)

tDSY
tHSYO

0.7 VCC
0.3 VCC
tHSYI

tSSY

tHSYI

tSSY

0.7 VCC
0.3 VCC

3. Testing load circuit.

Test point
CL

CL = 30 pF
(CL includes jig capacitance)

37

HD61830/HD61830B
HD61830B MPU Interface (VCC = 5V 10%, GND = 0V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Enable cycle time

t CYC

1.0

High level

t WEH

0.45

Low level

t WEL

0.45

Enable rise time

t Er

25

ns

Enable fall time

t Ef

25

ns

Setup time

t AS

140

ns

Data setup time

t DSW

225

ns

Data delay time

t DDR

225

ns *

Data hold time

t DHW

10

ns

Address hold time

t AH

10

ns

Output data hold time

t DH

20

ns

Enable pulse width

Note:

The following load circuit is connected for specification:

tCYC
tWEH

tWEL

2.2V

0.8V

tEr

tEf

tAS

tAH

2.2V

CS, R/W, RS

0.8V
tDSW

tDHW

2.2V
0.8V

DB0DB7
(MPUHD61830B)

tDDR
DB0DB7
(MPUHD61830B)

tDH

2.4V
0.4V

VCC
D1

RL

Test point
D2
R

D3
D4

38

RL = 2.4 k
R = 11 k
C = 130 pF (C includes jig capacitance)
Diodes D1 to D4 : 1S2074 H

HD61830/HD61830B
HD61830B External RAM and ROM Interface (VCC = 5V 10%, GND = 0V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Notes

MA0MA15 delay time

t DMA

300

ns

1, 2, 3

MA0MA15 hold time

t HMA

40

ns

1, 2, 3

CE delay time

t DCE

300

ns

1, 2, 3

CE hold time

t HCE

40

ns

1, 2, 3

OE delay time

t DOE

300

ns

1, 3

OE hold time

t HOE

40

ns

1, 3

MD output delay time

t DMD

150

ns

1, 3

MD output hold time

t HMDW

10

ns

1, 3

WE delay time

t DWE

150

ns

1, 3

WE clock pulse width

t WWE

150

ns

1, 3

MD output high impedance time (1)

t ZMDF

10

ns

1, 3

MD output high impedance time (2)

t ZMDR

50

ns

1, 3

RD data set-up time

t SRD

50

ns

RD data hold time

t HRD

40

ns

MD data set-up time

t SMD

50

ns

MD data hold time

t HMD

40

ns

Notes: 1. RAM write timing

T1

T2

T3

T1

0.7 VCC

CR

0.3 VCC
tHCE

CE

0.6V
tDMA
tHMA
2.4V
0.6V
tDOE
tHOE
2.4V
0.6V

tDMA
tHMA
MA0MA15
tDOE
tHOE
OE
tDWE
tZMDR

WE

tDMD

MD0MD7
(output)

tDWE

(High impedance)

2.4V
0.6V

2.4V
0.6V
tWWE
Valid
data

tZMDF

2.4V
0.6V

tHMDW
T1: Memory data refresh timing for upper screen
T2: Memory data refresh timing for lower screen
T3: Memory read/write timing

39

HD61830/HD61830B
2. ROM/RAM read timing
T1

T2

T3

T1

CR

(*1)
a
a

(*1)

tDCE
tHCE

tDCE
tHCE

tDCE
tHCE

2.4V

CE

0.6V

OE

MA0MA15

(*2)

0.6V

(*2)

tDMA
tHMA

tDMA
tHMA

2.4V

Address for
the lower screen

Address for upper screen

0.6V

tSMD
2.2V

MD0MD7
(input)

RD0RD7

tHMD

tSRD
2.2V

tHRD

Data for the upper screen

0.8V

tSMD

tSRD

tHMA
(*3)

tHMD

Data for
the lower screen

Data for the upper screen

0.8V

tDMA
tHMA

tSMD

tHMD

(*4)

tHRD

Data for the

lower screen

Invalid data

*1

This figures shows the timing for Hp = 8.

For Hp = 7, time shown by b becomes zero. For Hp = 6, time shown by a and b
become zero.
Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of Hp = 8,
Hp = 7, or Hp = 6 respectively.
*2
The waveform for instructions with memory read is shown with a dash line. In other cases,
the waveform shown with a solid line is generated.
*3
When an instruction with RAM read/write is executed, the value of cursor address is
output. In other cases, invalid data is output.
*4
When an instruction with RAM read is executed, HD61830B latches the data at this timing.
In other cases, this data is invalid.
3. Test load circuit
VCC
D1

RL

Test point
D2
R

D3
D4

40

RL = 2.4 k
R = 11 k
C = 50 pF (C includes jig capacitance)
Diodes D1 to D4 : 1S2074 H

HD61830/HD61830B
HD61830B LCD Driver Interface (VCC = 5V 10%, GND = 0V, Ta = 20 to +75C)
Item

Symbol

Min

Typ

Max

Unit

Notes

Clock cycle time

t WCL2

416

ns

1, 3

Clock pulse width(high level) t WCH

150

ns

1, 3

Clock pulse width(low level)

t WCL

150

ns

1, 3

Data delay time

t DD

50

ns

1, 3

Data hold time

t DH

100

ns

1, 3

Clock phase difference (1)

t CL1

100

ns

1, 3

Clock phase difference (2)

t CL2

100

ns

1, 3

Clock phase difference (3)

t CL3

100

ns

1, 3

MA, MB delay time

t DM

200

200

ns

1, 3

FLM set-up time

t SF

400

ns

2, 3

FLM hold time

t HF

1000

ns

2, 3

MA set-up time

t SMA

400

ns

2, 3

MA hold time

t HMA

1000

ns

2, 3

41

HD61830/HD61830B
Notes: 1.
tWCL2
tWCH

tWCL

0.7 VCC
0.3 VCC

CL2

tCL1

tCL2

tCL3

0.7 VCC
0.3 VCC t
WCH

CL1

tDH

tDD
D1, D2

0.7 VCC
0.3 VCC
tDM
0.7 VCC
0.3 VCC

MA, MB

2.
0.7 VCC
0.3 VCC

CL1
tSF

tHF

tSMA

tHMA

0.7 VCC
0.3 VCC

FLM

0.7 VCC
0.3 VCC

MA

3. Test load circuit

Test point
CL

42

CL = 100 pF
(CL includes jig capacitance)

HD61830/HD61830B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third partys rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachis sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachis sales office for any questions regarding this document or Hitachi semiconductor
products.

Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223

Hitachi Europe GmbH

Electronic components Group
Dornacher Strae 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX

Copyright Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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