GDM1602B

Features
1. 2. 3. 4. 5. 6. 5x8 dots with cursor Built-in controller (KS0066U or equivalent) +5V power supply (also available for =3.0V) 1/16 duty cycle BKL to be driven by pin1, pin2, or pin15, pin16 or A, K N.V. optional

SPECIFICATIONS OF LCD MODULE

Outline dimension

Absolute maximum ratings

(operating/storage temperature as 20~+70/-30~+80 )

GDM1602B
Block diagram

Interface pin description

Symbol VSS VDD V0

External connection
Power supply MPU MPU MPU MPU MPU LED BKL power supply

Function
Signal ground for LCM (GND) Power supply for logic (+5V) for LCM Contrast adjust Register select signal Read/write select signal Operation (data read/write) enable signal Four low order bi-directional three-state data bus lines. Used for data transfer between the MPU and the LCM. These four are not used during 4-bit operation. Four high order bi-directional three-state data bus lines. Used for data transfer between the MPU Power supply for BKL Power supply for BKL (GND)

Contrast adjust

VDD~V0 : LCD Driving voltage VR: 10k~20k

V: B

2/10

2002/03/15

GDM1602B
Optical characteristics
TN type display module (Ta=25 , VDD=5.0V) Item Symbol Condition Viewing angle Cr 4 Contrast ratio Response time (rise) Response time (fall) Cr Tr Tr Min. -25 -30 Typ. 2 120 120 Max. 30 150 150 Unit deg ms

STN type display module (Ta=25 , VDD=5.0V) Item Symbol Condition Viewing angle Cr 2 Contrast ratio Response time (rise) Response time (fall) Cr Tr Tr -

Min. -60
-40

Typ. 6 150 150

Max. 35 40 250 250

Unit deg ms

Electrical characteristics
DC characteristics Parameter
Supply voltage for LCD Input voltage Supply current Input leakage current H level input voltage L level input voltage H level output voltage L level output voltage Backlight supply voltage

Symbol VDD -V0 VDD IDD ILKG VIH VIL VOH VOL VF

Conditions
Ta =25 Ta=25 , VDD =5.0V

Min.
4.7 2.2 0 2.4 -

Typ.
4.6 1.5 -

Max.
5.5 2.5 1.0 VDD 0.6 0.4 -

Unit
V mA uA

Twice initial value or less LOH=-0.25mA LOH=1.6mA

Read cycle (Ta=25 , VDD=5.0V) Parameter Symbol Enable cycle time tc Enable pulse width tw Enable rise/fall time tr, tf RS; R/W setup time tsu RS; R/W address hold time th Read data output delay td Read data hold time tdh Write cycle (Ta=25 , VDD=5.0V) Parameter Symbol Enable cycle time tc Enable pulse width tw Enable rise/fall time tr, tf RS; R/W setup time tsu1 RS; R/W address hold time th1 Read data output delay tsu2 Read data hold time th2
V: B

Test pin
E RS; R/W RS; R/W DB0~DB7

Min.
500 300 100 10 60 20

Typ.
-

Max.
25 90 -

Unit

ns

Test pin
E RS; R/W RS; R/W DB0~DB7 3/10

Min.
500 300 100 10 60 10

Typ.
-

Max.
25 -

Unit

ns

2002/03/15

GDM1602B
Write mode timing diagram

Read mode timing diagram

Instruction description
Outline
To overcome the speed difference between the internal clock of KS0066U and the MPU clock, KS0066U performs internal operations by storing control in formations to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus (Refer to Table7). Instructions can be divided largely into four groups: 1) KS0066U function set instructions (set display methods, set data length, etc.) 2) Address set instructions to internal RAM 3) Data transfer instructions with internal RAM 4) Others The address of the internal RAM is automatically increased or decreased by 1. Note: during internal operation, busy flag (DB7) is read High. V: B 4/10

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GDM1602B
Busy flag check must be preceded by the next instruction.

Instruction Table
Instruction code Instruction Clear Display Return Home Entry mode Set Display ON/ OFF control Cursor or Display shift
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description
Write 20H to DDRA and set DDRAM address to 00H from AC Set DDRAM address to 00H From AC and return cursor to Its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction And blinking of entire display

Execution time (fosc= 270 KHZ

1.53ms

0 0

0 0

0 0

0 0

0 0

0 0

0 1

1 D

I/D C

SH B

39us

Function set Set CGRAM Address Set DDRAM Address Read busy Flag and Address Write data to Address Read data From RAM

0 0 0 0 1 1

0 0 0 1 0 1

0 0 1 BF D7 D7

0 1

Set display (D), cursor (C), and Blinking of cursor (B) on/off Control bit. Set cursor moving and display Shift control bit, and the 0 1 S/C R/L Direction, without changing of DDRAM data. Set interface data length (DL: 8Bit/4-bit), numbers of display 1 DL N F Line (N: =2-line/1-line) and, Display font type (F: 5x11/5x8) Set CGRAM address in address AC5 AC4 AC3 AC2 AC1 AC0 Counter. Set DDRAM address in address

39us

39us

39us 39us

AC6 AC5 AC4 AC3 AC2 AC1 AC0 Counter.

Whether during internal Operation or not can be known AC6 AC5 AC4 AC3 AC2 AC1 AC0 By reading BF. The contents of Address counter can also be read. Write data into internal RAM D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM).

0us

43us 43us

D6

D5

D4

D3

D2

D1

D0

Read data from internal RAM (DDRAM/CGRAM).

NOTE: When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2fosc is necessary for executing the next instruction by the falling edge of the E signal after the busy flag (DB7) goes to Low.

Contents
1) Clear display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1

Clear all the display data by writing 20H (space code) to all DDRAM address, and set DDRAM address to 00H into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on the fist line of the display. Make the entry mode increment (I/D=High).

V: B

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GDM1602B
2) Return home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 -

Return home is cursor return home instruction. Set DDRAM address to 00H into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. 3) Entry mode set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 SH

Set the moving direction of cursor and display. I/D: increment / decrement of DDRAM address (cursor or blink) When I/D=high, cursor/blink moves to right and DDRAM address is increased by 1. When I/D=Low, cursor/blink moves to left and DDRAM address is increased by 1. *CGRAM operates the same way as DDRAM, when reading from or writing to CGRAM. SH: shift of entire display When DDRAM read (CGRAM read/write) operation or SH=Low, shifting of entire display is not performed. If SH =High and DDRAM write operation, shift of entire display is performed according to I/D value. (I/D=high. shift left, I/D=Low. Shift right). 4) Display ON/OFF control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B

Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFF control bit When D=High, entire display is turned on. When D=Low, display is turned off, but display data remains in DDRAM. C: cursor ON/OFF control bit When D=High, cursor is turned on. When D=Low, cursor is disappeared in current display, but I/D register preserves its data. B: Cursor blink ON/OFF control bit When B=High, cursor blink is on, which performs alternately between all the High data and display characters at the cursor position. When B=Low, blink is off. 5) Cursor or display shift RS 0
V: B

R/W 0

DB7 0

DB6 0

DB5 0
6/10

DB4 1

DB3 S/C

DB2 R/L

DB1 -

DB0 2002/03/15

GDM1602B
Shifting of right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously in all the lines. When display data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of the address counter are not changed. Shift patterns according to S/C and R/L bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display

6) Function set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 F DB1 DB0 -

DL: Interface data length control bit When DL=High, it means 8-bit bus mode with MPU. When DL=Low, it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-but bus mode, it needs to transfer 4-bit data twice. N: Display line number control bit When N=Low, 1-line display mode is set. When N=High, 2-line display mode is set. F: Display line number control bit When F=Low, 5x8 dots format display mode is set. When F=High, 5x11 dots format display mode. 7) Set CGRAM address RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0

Set CGRAM address to AC. The instruction makes CGRAM data available from MPU. 8) Set DDRAM address RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0

Set DDRAM address to AC. This instruction makes DDRAM data available form MPU. When 1- line display mode (N=LOW), DDRAM address is form 00H to 4FH.In 2-line display mode (N=High), DDRAM address in the 1st line form 00H to 27H, and DDRAM address in the 2nd line is
V: B 7/10 2002/03/15

GDM1602B
from 40H to 67H. 9) Read busy flag & address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0

This instruction shows whether KS0066U is in internal operation or not. If the resultant BF is High, internal operation is in progress and should wait BF is to be LOW, which by then the nest instruction can be performed. In this instruction you can also read the value of the address counter. 10) Write data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0

Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation. The address is automatically increased/decreased by 1, according to the entry mode. 11) Read data from RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0

Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that has been read first is invalid, as the direction of AC is not yet determined. If RAM data is read several times without RAM address instructions set before, read operation, the correct RAM data can be obtained from the second. But the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction, it also transfers RAM data to output data register. After read operation, address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation. At this time, AC indicates next address position, but only the previous data can be read by the read instruction.

Display character address code:

1 00 40

2 01 41

3 02 42

4 03 43

5 04 44

6 05 45

7 06 46
8/10

8 07 47

9 08 48

10 09 49

11 12 13 14 15 16 0A 0B 0C 0D 0E 0F 4A 4B 4C 4D 4E 4F
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GDM1602B
Standard character pattern

V: B

9/10

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V: B 2002/03/15

10/10