VLSI Design

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INTRODUCTION TO VLSI DESIGN

1.1 INTRODUCTION
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The word digital has made a dramatic impact on our society. More significant is a
continuous trend towards digital solutions in all areas from electronic instrumentation,
control, data manipulation, signals processing, tele communications, etc., to consumer
electronics. Development of such solutions has been possible due to good digital system
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design and modeling techniques.
1.1.1 VLSI DESIGN

The complexity of VLSI being designed and designed and used today makes the manual
approach to design impractical. Design automation is the order of the day. With the rapid
technological developments in the last two decades, the status of VLSI technology is
characterized by the following:
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A steady increase in the size and hence the functionality of the ICs.
A steady reduction in feature size and hence increase in the speed of operation as
well as gate or transistor density.
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A steady improvement in the predictability of circuit behavior.

A steady increase in the variety and size of software tools for VLSI design.
1.1.2 VLSI DESIGN FLOW
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The above developments have resulted in a proliferation of approaches to VLSI design.
The design process, at various levels, is usually evolutionary in nature. It starts with a
given set of requirements. Initial design is to be developed and test impact analyst must
be considered. The Y-chart (first introduced by D. Gajski) is shown in below figure1

illustrates a design flow for most logic chips, using design activities on the three different
axes (domains). Y chart of three major domains, they are:
Structural domain
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Behavioral domain
Geometrical layout domain
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Typical VLSI design flow in three domains (Y-chart representation)
Figure 1
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The design flow starts from the algorithm that describes the behavior of the target chip.
The corresponding architecture of the processor is first defined. It is mapped onto the
chip surface by floor planning. The next design evolution in the behavioral domain
defines finite state machines (FSMs) which are structurally implemented with functional
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modules such as registers and arithmetic logic units (ALUs). These modules are then
geometrically placed onto the chip surface using CAD tools for automatic module
placement followed by routing, with a goal of minimizing interconnects area and signal
delays.
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The third evolution starts with a behavioral module description. Individual modules are
then implemented with leaf cells. At this stage the chip is described in terms of logic
gates (leaf cells), which can be placed and interconnected by using a cell placement &
routing program. The last evolution involves a detailed Boolean description of leaf cells
followed by a transistor level implementation of leaf cells and mask generation. In
standard-cell based design, leaf cells are already pre-designed and stored in a library for
logic design use.
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1.1.3 ABSTRACTION MODEL
The model divides the whole design cycle into various domains (see figure 2) with such
an abstraction through a division process the design is carried out in different layers. The
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designer at one layer can function without bothering about the layers above or below. The
thick horizontal lines separating the layers in the figure signify the compartmentalization.
As an example, le us consider design at the gate level. The circuit to be designed would
be described in terms of truth tables and static tables. With these as available inputs, he
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has to express them as Boolean logic equation and realize them i8n terms of gates and
flip-flops. In turn these form the inputs to the layer immediately below.
Compartmentalization of the approach to design in the manner described here is the
essence of abstraction; it is the basics for the development and d use of CAD tools in the
design at various levels.
1.1.4 ASIC DESIGN FLOW
As with any other technical activity, development of an ASIC starts with an idea and
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takes tangible shape through the stages of development as shown in figure 3 and shown
in detail in figure 4.The first step in the process is to expand the idea in terms of behavior
of the target circuit. Through stages of programming, the same is fully developed into a
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design description- in terms of well defined standard constructs and conventions.
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Design domain and levels of abstraction
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Figure 2
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Figure 3
Major activities in ASIC design
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The design is tested through a simulation process; it is to check, verify, and ensure that
what is wanted is what is described. Simulation is carried out through dedicated tools
.with every simulation results are studied to identify errors in the design description. The
errors are corrected and another simulation run is carried out. Simulation and changes to
design description together form a cyclic iterative process, repeated until an error free
design is evolved.
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Design description is an activity independent of the target technology or

manufacturer. It results in a description of the digital circuit. To translate it into a tangible
circuit, one goes through the physical design process. The same constitutes a set of
activities closely linked to the manufacturer and the target technology.
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1.1.5 DESIGN DESCRIPTION
The design is carried out in stages. The process of transforming the idea into a detailed
circuit description in terms of the elementary circuit components constitutes design
arrived in a step-by-step manner.
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description. The final circuit of such an IC can have up to a billion such components; it is
The first step in evolving the design description is to describe the
circuit in terms of its behavior. The description looks like a program in a high level
language like C. once the behavior level design description is ready, it is tested
extensively with the help of simulation tool; it checks and confirms that all the expected
functions are carried out satisfactorily. If necessary, this behavioral level routine is
edited, modified, and rerun all done manually. Finally, one has a design for the
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expected system- described at the behavioral level. The behavioral constructs not
supported by the synthesis tools replaced by data flow and gate level constructs. To
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surmise, the designer has to develop synthesizable codes for his design.
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ASIC design and development flow.
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Figure 4
The design at the behavioral level is to be elaborated in terms of known and
acknowledged functional blocks. It forms the next detailed level of design description.
Once again the design is to be tested through simulation and iteratively corrected for
errors. The elaboration can be continued one or two steps further. It leads to a detailed
design description in terms of logic gates and transistor switches.
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1.1.6
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OPTIMIZATION
The circuit at the gate level- in terms of the gates and flip-flops- can be redundant in
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nature. The same can be minimized with the help of minimization tools. The minimized
design is converted to a circuit in terms of the switch levels cells from standard libraries
provided by the foundries. The cell based designed generated by the tool is the last step in
1.1.7
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the design process; it forms the input to the first level of physical design.
POST LAYOUT SIMULATION
Once the placement and routing are completed the performance specifications like silicon
area, power consumed, path delays, can be computed. Equivalent circuit can be extracted
at the component level and the performance analysis carried out. This constitutes the final
stage called verification. One may have to go through the placement and routing
activity once again to improve performance.
CRITICAL SUBSYSTEMS
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1.1.8
The design may have critical subsystems. Their performance may be crucial to the overall
performance; in other words, to improve the system performance substantially, one may
have to design such subsystems afresh. The design here may imply redefinition of the
basic feature size of the component, component design, and placement of the
components, or routing done separately and specifically for the sub systems. A set of
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masks used in the foundry may have to be done a fresh for the purpose.
1.2 EMERGENCE OF HDLs

For a long time, programming languages such as FORTRAN, Pascal, and C were being
used to describe computer programs that were sequential in nature. Similarly, in the
digital design field, designers felt the need for a standard language to describe digital
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circuits. Thus, Hardware Description Languages (HDLs) come into existence. HDLs
allowed the designers to model the concurrency of process found in hardware elements.
1.2.1 IMPORTANCE OF HDLs
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Designers can be described at a very abstract level by use of HDLs. Designers can write
their RTL description without choosing a specific technology. Logic synthesis tools can
automatically convert the design to any fabrication technology.
By describing designs in HDLs, functional verification of the design can be done early in
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the design cycle. Since designers work at the RTL level, they can optimize and modify
the RTL description until it meets the desired functionality. Designing with HDLs is
analogous to computer programming. A textual description with comments is an easier
way to develop and debug circuits.
1.2.2 HARDWARE DESCRIPTIVE LANGUAGE:
There are two main hardware descriptive languages in use in the industry today for Very
Large Scale Integration (VLSI) of chips. They are:
Verilog HDL
VHDL
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1.2.3 OVERVIEW OF VERILOG HDL:
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Verilog HDL is a Hardware Description Language (HDL). A Hardware Description

Language is a language used to describe a digital system, for example, a computer or a
component of a computer. One may describe a digital system at several levels. For
example, an HDL might describe the layout of the wires, resistors and transistors on an
Integrated Circuit (IC) chip, i.e., and the switch level. Or, it might describe the logical
gates and flip flops in a digital system, i.e., the gate level.
An even higher level
describes the registers and the transfers of vectors of information between registers. This
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is called the Register Transfer Level (RTL). Verilog supports all of these levels. The
industry is currently split on which is better. Many feel that Verilog is easier to learn and
use than VHDL.
Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of
Cadence Design Systems, Inc.s Systems Division.
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Verilog HDL allows a hardware designer to describe designs at a high level of
abstraction such as at the architectural or behavioral level as well as the lower

implementation levels (i.e. , gate and switch levels) leading to Very Large Scale
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Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use
of HDLs is the simulation of designs before the designer must commit to fabrication.
1.2.4 POPULARITY OF VERILOG HDL:
Verilog HDL is a general purpose HDL that is easy to use and learn. It is similar
in syntax to the C programming language.
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Verilog HDL allows different levels of abstraction to be mixed in the same model.
Most popular logic synthesis tool support Verilog HDL. This makes it the
language of choice for designers.
All fabrication venders provide Verilog HDL libraries for post logic synthesis simulation.
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Thus, designing a chip in Verilog HDL allows the widest choice of venders.
1.2.5 OVERVIEW OF VHDL:
As the size and the complexity of digital system increases, more computer aided design
tools are introduced into the hardware design process. The early papered pencil design
methods have given way to sophisticated design entry, verification and automatic
hardware generation tools. The newest addition to this design methodologies the
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introduction of hardware description language (HDL).Actually the use of this language is

not new languages such as CDI, ISP and AHPL have been used for last some years.
However, their primary application has been the verification of designs architecture.
They do not have the capability to model design with a high degree of accuracy that is,
their timing model is not precise and/or their language construct implies a certain
and imply no particular hardware structure.
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hardware structure newer languages such as VHDL have more universal timing models
Hardware description languages have two main
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applications documenting a design and modeling it. Good documentation of a design
helps to ensure design accuracy and design portability. Since a simulator supports them
inherent in a HDL description can be used to validate a design. Prototyping of
complicated system is extremely expansive, and the goal of those concerned with the
development of hardware languages is to replace this prototyping process with validation

through simulation and silicon compilation.
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Once an entity has been modeled, it needs to be

validated by the VHDL system. A typical VHDL system consists of an analyzer and a
simulator. The analyzer reads in one or more design units contained in a single file and
compiles them into a design library after validating the syntax and performing some static
semantic checks. The design library is a place in the host environment where compiled
design units are stored.
The simulator simulates an entity, represented by an entity-architecture pair or by a
configuration, by reading in its compiled description from the design library & then
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performing the following steps:

1. Elaboration
2. Initialization
3. Simulation
VHDL is an acronym for VHSIC Hardware description language (VHSIC is an acronym

for very high speed integrated circuits). It is a hardware description language that can be
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used to model a digital system at many levels of abstraction, ranging from the algorithmic
level to the gate level.
The complexity of a digital system being modeled could vary from that of simple gate to
a complete digital electronic system, or anything in between.
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The digital system can also be described hierarchically. Timing can also be explicitly
modeled in the same description.
languages.
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The VHDL language can be regarded as an integrated amalgamation of the following
Sequential language.
Concurrent language.
Net list language.
Timing specifications.
Waveform generation language.
Therefore, the language has constructs that enable you to express the concurrent or
sequential behavior of a digital system as an interconnection of components. All the
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above constructs may be combined to provide a comprehensive description of the system

in a single model.
The language not only defines the syntax but also defines very clear simulation semantics
for each language construct. Therefore models written in this language can be verified
using a VHDL simulator. It inherits many of its features especially the sequential part,
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from the Ada programming language. Because VHDL provides an extensive range of
modeling capabilities, it is often difficult to understand, fortunately, it is possible to
quickly assimilate a core subset of the language that is both easy and simple to
understand without learning the more complex features. The complete language however
has sufficient power to capture the descriptions of the most complex chips to a complete
electronic system.
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1.3 BASIC CONCEPTS OF VERILOG:

1.3.1 LEXICAL CONVENTIONS
The basic lexical conventions used by Verilog HDL are similar to those in the c
programming language. Verilog contains a stream of tokens. Tokens can be comments,
language. All keywords are in low case.

WHITESPACE:
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1.3.2
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delimiters, numbers, string, identifiers, and keywords. Verilog HDL is a case-sensitive
Blank spaces (\b), tabs (\t) and newlines (\n) comprise the whitespace. Whitespace is
ignored by Verilog except when it separates tokens. Whitespace is not ignored in strings.
COMMENTS:
1.3.3
Comments can be inserted in the code for readability and documentation. There are two
ways to write comments. A one-line comment starts with //. Verilog skips from that
point to the end of line. A multiple-line comment starts with /* and ends with /*.
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Multiple-line comments cannot be nested.
1.3.4
OPERATORS:
Operators are of three types unary, binary, and ternary. Unary operators precede the
operand. Binary operators appear between two operands. Ternary operators have two
separate operators that separate three operands.
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NUMBER SPECIFICATION
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There are two types of number specification in verilog: sized and unsized.
Sized numbers
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Sized numbers are represented as <size> <base format> <number>.
<Size> is written only in decimal and specifies the number of bits in the number. Legal
base formats are decimal (d or D), hexadecimal (h or H), binary (b or B) and octal
or
O).
the
number
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specified
as
consecutive
digits
from
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0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular base.
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Uppercase letters are legal for number specification.
UNSIZED NUMBERS:
Numbers that are specified without a <base format > specification are decimal numbers
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by default. Numbers that are written without <size> specifications have a default number
of bits is simulator and machine specific (must be at least 32).
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X OR Z VALUES:
Verilog has two symbols for unknown and high impedance values. These values are very
important for modeling real circuits. An unknown value is denoted by an x. a high
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impedance value is denoted by z.
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An x or z values sets four bits for a number in the hexadecimal base, three bits for a
number in the octal base, and one bit for a number in the binary base. If the most
significant bit of a number is 0, x, z, the number is automatically extended to fill the most
significant bits, respectively, with 0, x, or z. This makes it easy to assign x or z to whole
vector. If the most significant digit is 1, then it is also zero extended.

NEGATIVE NUMBERS:
Negative numbers can be specified by putting a minus sign before the size for a constant
number. Size constants are always positive. It is illegal to have a minus sign between
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<base format > and <number>.
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UNDERSCORE CHARACTERS AND QUESTION MARKS:
An underscore character _ is allowed anywhere in a number except the first character.

Underscore character are allowed only to improve readability of number and are ignored
by Verilog.
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A question mark ? is the Verilog HDL alternative for z in the context of

numbers. The ? Is used to enhance readability in the case x and case z statements
1.3.6
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behavioral modeling, where the high impedance value is a dont acre condition.
STRINGS:
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A string is a sequence of character that is enclosed by double quotes. The restriction on a

string is that it must be contained on a single line, that is, without a carriage return. It
1.3.7
cannot be on multiple lines. Strings are treated as a sequence of one-byte ASCII values.
IDENTIFIERS AND KEYWORDS:
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Keywords are special identifiers reserved to define the language constructs. Keywords
are in lowercase. Identifiers are names given to objects so that they can be referenced in
the design. Identifiers are made up of alphanumeric characters, the underscore ( _ ) and
the dollar sign ($) and are low case sensitive. Identifier starts with an alphabetic character
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or an underscore. They cannot start with a number or a $ sign.
1.3.8
ESCAPED IDENTIFIERS:
Escaped identifiers begin with the backlash ( \ ) character and end with white space (
space, tab, or new line ).all characters between backlash and whitespace are processed
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literally. Any printable ASCII character can be included in escaped identifiers. The
1.4
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backlash or whitespace is not considered a part of the identifier.
DATA TYPES:
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1.4.1 VALUE SET
Verilog supports four values and eight strengths to model the functionality of real
hardware. The four value levels are listed in table 1.
Value levels
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Table 1
In addition to logic values, strength levels are often used to resolve conflicts between
drivers of different strengths in digital circuits. Value level 0 and 1 can have the strength
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levels listed in table 2.
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Strength levels
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Table 2
If two signal of unequal strength are driven on a wire, the stronger signal prevails. For
example, if two signals of strength strong 1 and weak 0 contend, the result is resolved as
a strong1. If two signals of equal strengths strong 1 and strong 0 conflict, the result is an
x. Strength levels are particularly useful for accurate modeling of signal contention, MOS
device, dynamic MOS, and low-level devices. Only trireg nets can have storage
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strengths large, medium, and small.
1.4.2
NETS:
Net represent connection between hardware elements. Just as in real circuits, nets have
values continuously driven on them by the outputs of devices that they are connected to.
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In figure 5 net a is connected to the output of and gate g1.net a will continuously assume
the value computed at the out put of gate g1, which is b & c.
Figure 5
Example of nets
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Nets are declared primarily with the keyword wire. Nets are one-bit values by default
unless they are declared explicitly as vectors. The term wire and net are often used
interchangeable. The default value of a net is z .nets get output value of their drivers. If a
REGISTERS:
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1.4.3
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net has no driver, it gets the value z.
Registers represent data storage elements. Registers retain until another value is placed
onto them. Do not confuse the term registers in Verilog with hardware registers from
edge-triggered flip-flops in real circuits. In Verilog, the term register merely means a
variable that can hold a value. Unlike a net, a register can be changed anytime in a
simulation by assigning a new value to the register.
Register data types are commonly declared by the keyword reg. the default value
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for a reg data type is x.
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Example 1
1.4.4
VECTORS:
Nets or reg data types can be declared as vectors. If bit width is not specified, the default
is scalar (1-bit).
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Vectors can be declared at [high#: low #] or [low#: high #]. But the left number in the
squared brackets is always the most significant bit of the vector. In the example shown
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STRINGS:
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above, bit 1 is the most significant bit of vector vitual_addr.
Strings can be stored in reg. the width of the register variables must be large enough to
hold the string. Each character in the string tales up 8 bits (1 byte). If the width of the
register is greater than the size of the string, Verilog fills bits to the left of the string with
zeros. If the register width is smaller than the string width, Verilog truncates the leftmost
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bits of the string. It is always safe to declare a string that is slightly wider than necessary.
Special characters serve a special purpose in displaying strings, such as newline, tabs, and
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displaying argument values. Special characters can be displayed in string only when they
are preceded by escape characters, as shown in the table 3.
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Special characters
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Table 3
SYSTEM TASKS & COMPILER DIRECTIVES:
1.5.1 SYSTEM TASKS:
Verilog provides standard system tasks to do certain routine operations. All system tasks
appear in the form $<keyword>. Operations such as displaying on the screen, monitoring
values of nets, stopping, and finishing are done by system tasks.
Displaying information
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$display is the main system task for displaying values of variables or strings or
expressions. This is one of the most useful tasks in Verilog.
Usage: $display (p1, p2, p3,, pn);
P1, p2, p3,., pn can be quoted strings or variables or expressions. The format of
$display is very similar to print f in c. A $display inserts a newline at the end of the
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string by default. Strings can be formatted by using the format specifications listed in
table 4.
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or
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Table 4 String format specifications
Monitoring information:
Verilog provides a mechanism to monitor when its value changes. This facility is
provided by the $monitor task.
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Usage: $monitor (p1, p2, p3.., pn);

The parameters p1, p2... pn can be variables, signal names, or quoted strings. Monitor
continuously monitors the values of the variables or signals specified in the parameter list
and display all parameters in the list whenever the value of any one variable or signal
changes. Unlike $display, $monitor needs to be invoked only once. Only one monitoring
list can be active at a time. If there is more than one $monitor statement in your
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simulation, the last $monitor statement will be the active statement.

Two tasks are used to switch monitoring on and off.
Usage: $monitor on;
$monitor off;
The $monitor on task enables monitoring and the $monitor off tasks disables
monitoring during a simulation. An example of monitor statement is given below.
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Stopping & finishing simulation:
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Example 1 monitor statement
The task $ stop is provided to stop during a simulation.
Usage: $ stop;
The $ stop task puts the simulation in an interactive model. The designer can then debug
the design from the interactive mode. The $stop task is used whenever the designer wants
to suspend the simulation and examine the values of signals in the design.
The $finish task terminates the simulation.
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Usage: $finish;
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Examples of $stop and $ finish are shown below in example 2.
Example 2
Stop and finish tasks
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1.5.2
COMPILER DIRECTIVES:
Complier directives are provided in Veriog. All compiler directives are defined by using
the `<keyword> construct. We deal with two most useful compiler directives.
`define:
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The `define directive is used to define text macros in Verilog. This is similar to # define
construct in C. The defined constants or text macros are used in the Verilog code by
preceding them with a ` (back tick). The Verilog compiler substitutes the text of the
` Define directive
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Example 3
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macro whenever it encounters a `<macro_name>.
`include:
The ` include directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation. This works similarly to the #include in the C
programming language. This directive is typically used to include header files, which
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typically contain global or commonly used definitions.

Example 4 ` include directive
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1.5.3
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MODULES:
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A module in Verilog consists of distinct parts, as shown in figure 6.
Figure 6 components of Verilog module
A module definition always begins with the keyword module. The module name, port
list, port declarations, and optional parameters must come first in a module definition.
Port list and port declarations are present are present only if the module has any ports to
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interact with the external environment. The five components within a module are
variable declarations, dataflow statements, instantiation of lower modules, behavioral
blocks, and tasks or functions. These components can be in any order and at any place in
the module definition. The end module statement must always come last in the module
definition .All components except module, module name, and end module are optional
and can be mixed and matched as per design needs. Verilog allows multiple modules to
be defined in a single file. The modules can be defined in any order in the file.
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1.5.4 PORTS:
Ports provide the interface by which a module can communicates with its environment.
For example, the input/output pins of an IC chip are its ports. The environment can
interact with the nodule only through its ports .the internals of the module are not visible
to the environment. This provides a very powerful flexibility to the designer. Ports are
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also referred as terminals.

1.5.5 PORT DECLARATION:
All ports in the list of ports must be declared in the module. ports can be declared as
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follows:
Each port in the lit is defined as input, output, or in out, based on the direction of the
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port signal. Thus, for the example of 4-bit full adder.
full adder (4-bit)
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Figure 7
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port declarations
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Example 5
Note that all ports declarations are implicitly declared as wire in verilog. Thus, if a port is
intended to be a wire, it is sufficient to declare it as output, input, or in out. Input or
outputs are normally declared as wires. However, if output ports hold their value they
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must be declared as reg.
1.5.6 PORT CONNECTION RULES:

One can visualize a port as consisting of two units, one unit that is internal to the module
another that is external to the module. The internal and external units are connected.
There are rules governing port connections when modules are initiated within other
modules. The Verilog simulator complains if any port connection rules are violated.
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These rules are summarized in figure 8.
Inputs
Internally, input ports must always be of the type net. Externally, the inputs can be
connected to a variable which is a reg or a net.
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port connection rules
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Figure 8
Outputs:
Internally, outputs port can be of the type reg or net. Externally, outputs must always
Inouts:
be connected to a net. They cannot be connected to a reg.
Internally, inout ports must always be of the type net. Externally, inout ports must
always be connected to a net.
Width watching:
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It is legal to connect internal and external items of different sizes when making intermodule port connections. However, a warning is typically issued that the widths do
not match.
Unconnected ports:
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Verilog allows ports to remain unconnected. For example, certain outputs ports might
be simply for debugging and you might not be interested in connecting them to the
external signals. You can let a port remain unconnected by instantiating module as
shown below.
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1.5.7 CONNECTING PORTS TO EXTERNAL SIGNALS:

There are two methods of making connections between signals specified in the module
instantiation and the ports in a module definition. These two methods cannot be mixed.
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These methods are discussed in the following sections.
Connecting by ordered list:
Connecting by ordered list is the most intuitive method for most beginners. The
signals to be connected must appear in the module instantiation in the same order as
or
the ports in the port list in the module definition. Once again, consider the module
fulladd4 defined in Example 5. To connect signals in module Top by ordered list, the
Verilog code is shown in Example 6. Notice that the external signals SUM, C_OUT,
A, B, and C_IN appear in exactly the same order as the ports sum, c_out, a, b, and
c_in in module definition of fulladd4.
Connection by order list
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Example 6
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Connecting ports by name:
or
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For large designs where modules have, say, 50 ports, remembering the order of the ports
in the module definition is impractical and error-prone. Verilog provides the capability to
connect external signals to ports by the port names, rather than by position. We could
connect the ports by name in Example 6 above by instantiating the module fulladd4, as
follows. Note that you can specify the port connections in any order as long as the port
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name in the module definition correctly matches the external signal.
Note that only those ports that are to be connected to external signals must be specified in
port connection by name. Unconnected ports can be dropped. For example, if the port
c_out were to be kept unconnected, the instantiation of fulladd4 would look as follows.
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The port c_out is simply dropped from the port list.
Another advantage of connecting ports by name is that as long as the port name is not
changed, the order of ports in the port list of a module can be rearranged without
changing the port connections in module instantiations.
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MODELING CONCEPTS
GATE-LEVEL MODELING:
ld
2.1 Gate Types:

A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates
as predefined primitives. These primitives are instantiated like modules except that they
are predefined in Verilog and do not need a module definition. All logic circuits can be
buf/not gates.
2.1.1 And/Or Gates:
or
designed by using basic gates. There are two classes of basic gates: and/or gates and
And/or gates have one scalar output and multiple scalar inputs. The first terminal in the
list of gate terminals is an output and the other terminals are inputs. The output of a gate
is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog
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are shown below.
The corresponding logic symbols for these gates are shown in Figure 9. We consider
gates with two inputs. The output terminal is denoted by out. Input terminals are denoted
by i1 and i2.
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These gates are instantiated to build logic circuits in Verilog. Examples of gate
instantiations are shown below. In Example , for all instances, OUT is connected to the
output out, and IN1 and IN2 are connected to the two inputs i1 and i2 of the gate
primitives.
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Basic gates
or
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Figure 9
More than two inputs can be specified in a gate instantiation. Gates with more than two
inputs are instantiated by simply adding more input ports in the gate instantiation (see
Example 7 ). Verilog automatically instantiates the appropriate gate.
Gate instantiation of and/or gates
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Example 7
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The truth tables for these gates define how outputs for the gates are computed from the
inputs. Truth tables are defined assuming two inputs. The truth tables for these gates are
shown in Table5. Outputs of gates with more than two inputs are computed by applying
Truth Table For and/Or gates
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or
Table 5
ld
the truth table iteratively.
2.1.2 Buf/Not Gates:
Buf/not gates have one scalar input and one or more scalar outputs. The last terminal in
the port list is connected to the input. Other terminals are connected to the outputs. We
will discuss gates that have one input and one output.
Two basic buf/not gate primitives are provided in Verilog.
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The symbols for these logic gates are shown in Figure 10.
Buf and Not Gates
ld
Figure 10
These gates are instantiated in Verilog as shown Example 8. That these gates can have
multiple outputs but exactly one input, which the last terminal in the port list is.
or
Gate Instant ion Of And/ Or gates
Example 8
The truth tables for these gates are very simple. Truth tables for gates with one input and
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one output are shown in Table 6.
Truth Tables for Buf /Not gates
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Table 6
2.1.3 Gate Level Modeling Examples:
4:1 Multiplexer:
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We will design a 4-to-1 multiplexer with 2 select signals. Multiplexers serve a useful
purpose in logic design. They can connect two or more sources to a single destination.
They can also be used to implement Boolean functions. We will assume for this example
that signals s1 and s0 do not get the value x or z. The I/O diagram and the truth table for
the multiplexer are shown in Figure 11. The I/O diagram will be useful in setting up the
ld
port list for the multiplexer.
4 to 1 multiplexer
or
Figure 11
We will implement the logic for the multiplexer using basic logic gates. The logic
diagram for the multiplexer is shown in Figure12.
Logic Diagram for Multiplexer
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Figure 12
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Two intermediate nets, s0n and s1n, are created; they are complements of input signals s1
and s0. Internal nets y0, y1, y2, y3 are also required. Note that instance names are not
specified for primitive gates, not, and, and or.
Verilog description of multiplexer
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or
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Example 9
This multiplexer can be tested with the stimulus shown in Example10. The stimulus
checks that each combination of select signals connects the appropriate input to the
output. The signal OUTPUT is displayed one time unit after it changes. System task
$monitor could also be used to display the signals when they change values.
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Stimulus for multiplexer
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or
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Example 10
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The output of the simulation is shown below.
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2.1.4 Gate Delays:

In real circuits, logic gates have delays associated with them. Gate delays allow the
Verilog user to specify delays through the logic circuits. Pin-to-pin delays can also be
specified in Verilog.
ld
Rise, fall, and Turn-off Delays:

There are three types of delays from the inputs to the output of a primitive gate.
Rise Delay
Fall Delay
or
The rise delay is associated with a gate output transition to a 1 from another value.
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The fall delay is associated with a gate output transition to a 0 from another value.
Turn-Off Delay
The turn-off delay is associated with a gate output transition to the high impedance value
(z) from another value.
If the value changes to x, the minimum of the three delays is considered. Three types of
delay specifications are allowed. If only one delay is specified, this value is used for all
transitions. If two delays are specified, they refer to the rise and fall delay values. The
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turn-off delay is the minimum of the two delays. If all three delays are specified, they
refer to rise, fall, and turn-off delay values. If no delays are specified, the default value is
zero.
2.1.5 Min/Typ/Max Values:
Verilog provides an additional level of control for each type of delay mentioned above.
ld
For each type of delayrise, fall, and turn-offthree values, min, typ, and max, can be
specified. Any one value can be chosen at the start of the simulation. Min/typ/max values
are used to model devices whose delays vary within a minimum and maximum range
or
because of the IC fabrication process variations.

Min value
The min value is the minimum delay value that the designer expects the gate to have.
Typ value
Max value
The typ value is the typical delay value that the designer expects the gate to have.
The max value is the maximum delay value that the designer expects the gate to have.
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2.1.6 DELAY EXAMPLE:
Let us consider a simple example to illustrate the use of gate delays to model timing in
the logic circuits. A simple module called D implements the following logic equations:
Out = (ab) + c
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The gate-level implementation is shown in Module D (Figure 13). The module contains
two gates with delays of 5 and 4 time units.
The module D is defined in Verilog as shown in Example 11.
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module D
or
ld
Figure 13
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Example 11 Verilog Definition for Module D Delay
The waveforms from the simulation are shown in Figure 14 to illustrate the effect of
specifying delays on gates. The waveforms are not drawn to scale. However, simulation
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time at each transition is specified below the transition.
The outputs E and OUT are initially unknown.
At time 10, after A, B, and C all transition to 1, OUT transitions to 1 after a delay
of 4 time units and E changes value to 1 after 5 time units.
At time 20, B and C transition to 0. E changes value to 0 after 5 time units and
OUT transitions to 0, 4 time units after E changes.
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Waveforms for Delay Simulation
2.2 DATAFLOW MODELING:

2.2.1 Continuous Assignment:
or
ld
Figure 14
A continuous assignment is the most basic statement in dataflow modeling, used to drive
a value onto a net. This assignment replaces gates in the description of the circuit and
describes the circuit at a higher level of abstraction. The assignment statement starts with
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the keyword assign. The syntax of an assign statement is as follows.
2.2.2 Implicit Continuous Assignment:
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Instead of declaring a net and then writing a continuous assignment on the net, Verilog
provides a shortcut by which a continuous assignment can be placed on a net when it is
declared. There can be only one implicit declaration assignment per net because a net is
declared only once.
In the example below, an implicit continuous assignment is contrasted with a regular
continuous assignment.
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ld
2.2.3 Implicit Net Declaration:

If a signal name is used to the left of the continuous assignment, an implicit net
declaration will be inferred for that signal name. If the net is connected to a module port,
or
the width of the inferred net is equal to the width of the module port.
2.2.4 Expressions, Operators & Operands:
Dataflow modeling describes the design in terms of expressions instead of primitive

gates. Expressions, operators, and operands form the basis of dataflow modeling.
Expressions:
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Expressions are constructs that combine operators and operands to produce a result.
Operands:
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Operands can be any one of the data types. Some constructs will take only certain types
of operands. Operands can be constants, integers, real numbers, nets, registers, times, bitselect (one bit of vector net or a vector register), part-select (selected bits of the vector net
or register vector), and memories or function calls.
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or
Operators:
Operators act on the operands to produce desired results. Verilog provides various types
of operators.
2.2.5 Operator Types:
Verilog provides many different operator types. Operators can be arithmetic, logical,
relational, equality, bitwise, reduction, shift, concatenation, or conditional. Some of these
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operators are similar to the operators used in the C programming language. Each operator
type is denoted by a symbol. Table 7 shows the complete listing of operator symbols
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classified by category.
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Operator Types and Symbols
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or
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Table 7
Concatenation Operator:
The concatenation operator ({,}) provides a mechanism to append multiple operands. The
operands must be sized. Unsized operands are not allowed because the size of each
operand must be known for computation of the size of the result.
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Concatenations are expressed as operands within braces, with commas separating the
operands. Operands can be scalar nets or registers, vector nets or registers, bit-select,
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part-select, or sized constants.
or
Replication Operator:
Repetitive concatenation of the same number can be expressed by using a replication

constant. A replication constant specifies how many times to replicate the number inside
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the brackets ( { } ).
Conditional Operator:
The conditional operator(?:) takes three operands.

Usage: condition_expr ? true_expr : false_expr ;
The condition expression (condition_expr) is first evaluated. If the result is true (logical
then the true_expr is evaluated. If the result is false (logical 0), then the false_expr is
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1),
evaluated. If the result is x (ambiguous), then both true_expr and false_expr are evaluated
and their results are compared, bit by bit, to return for each bit position an x if the bits are
different and the value of the bits if they are the same.
The action of a conditional operator is similar to a multiplexer. Alternately, it can be
compared to the if-else expression.
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or
Conditional operators are frequently used in dataflow modeling to model conditional
assignments. The conditional expression acts as a switching control.
2.3 Behavioral Modeling:
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2.3.1 Structured Procedures:
There are two structured procedure statements in Verilog: always and initial. These
statements are the two most basic statements in behavioral modeling. All other behavioral
statements can appear only inside these structured procedure statements.

Initial Statement:
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All statements inside an initial statement constitute an initial block. An initial
block starts at time 0, executes exactly once during a simulation, and then does not
execute again. If there are multiple initial blocks, each block starts to execute
concurrently at time 0. Each block finishes execution independently of other blocks.
Multiple behavioral statements must be grouped, typically using the keywords begin and
end.
If there is only one behavioral statement, grouping is not necessary. This is similar
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to the begin-end blocks in Pascal programming language or the { } grouping in the C

programming language. Example 12 illustrates the use of the initial statement.
Initial Statement
or
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Example 12
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In the above example, the three initial statements start to execute in parallel at time 0. If
delay #<delay> is seen before a statement, the statement is executed <delay> time units
after the current simulation time. Thus, the execution sequence of the statements inside
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the initial blocks will be as follows.
The initial blocks are typically used for initialization, monitoring, waveforms and
other processes that must be executed only once during the entire simulation run.
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Always Statement:
All behavioral statements inside an always statement constitute an always block. The
always
statement starts at time 0 and executes the statements in the always block
continuously in a looping fashion. This statement is used to model a block of activity that
is repeated continuously in a digital circuit. An example is a clock generator module that
ld
toggles the clock signal every half cycle. In real circuits, the clock generator is active
from time 0 to as long as the circuit is powered on. Example 13 illustrates one method to
model a clock generator in Verilog.
Always Statement
TU
or
Example 13
In Example 13 , the always statement starts at time 0 and executes the statement clock =
~clock every 10 time units. Notice that the initialization of clock has to be done inside a
separate initial statement. If we put the initialization of clock inside the always block,
clock will be initialized every time the always is entered. Also, the simulation must be
halted inside an initial statement. If there is no $stop or $finish statement to halt the
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simulation, the clock generator will run forever.
2.3.2
Procedural Assignments:
Procedural assignments update values of reg, integer, real, or time variables. The
value placed on a variable will remain unchanged until another procedural assignment
updates the variable with a different value. The syntax is shown below.
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There are two types of procedural assignment statements: blocking and nonblocking.
Blocking Assignment:
Blocking assignment statements are executed in the order they are specified in a
follow in a parallel block.

The = operator is used to specify blocking assignments.
or
Nonblocking Assignment:
ld
sequential block. A blocking assignment will not block execution of statements that
Nonblocking assignments allow scheduling of assignments without blocking execution of

the statements that follow in a sequential block. A <= operator is used to specify
nonblocking assignments. Note that this operator has the same symbol as a relational
operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an

expression and as an assignment operator in the context of a nonblocking assignment.
2.3.3
Multiway Branching:
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Case Statement:
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The keywords case, endcase, and default are used in the case statement..
Each of statement1, statement2 , default_statement can be a single statement or a block
of multiple statements. A block of multiple statements must be grouped by keywords

begin
and end.
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Case x , Case z Keywords:

There are two variations of the case statement. They are denoted by keywords, casex
and casez.
Casez treats all z values in the case alternatives or the case expression as don't
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cares. All bit positions with z can also represented by ? In that position.
Casex treats all x and z values in the case item or the case expression as don't
cares.
expression and the case alternatives.
2.3.4
Loops:
or
The use of casex and casez allows comparison of only non-x or -z positions in the case
There are four types of looping statements in Verilog: while, for, repeat, and forever. The
syntax of these loops is very similar to the syntax of loops in the C programming
language. All looping statements can appear only inside an initial or always block.
Loops may contain delay expressions.
While Loop:
TU
The keyword while is used to specify this loop. The while loop executes until the whileexpression is not true. If the loop is entered when the while-expression is not true, the
loop is not executed at all.
For Loop:
The keyword for is used to specify this loop. The for loop contains three parts:
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An initial condition
A check to see if the terminating condition is true

A procedural assignment to change value of the control variable
The initialization condition and the incrementing procedural assignment are included in
the for loop and do not need to be specified separately. Thus, the for loop provides a
more compact loop structure than the while loop.
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Repeat Loop:
The keyword repeat is used for this loop. The repeat construct executes the loop a
fixed number of times. A repeat construct cannot be used to loop on a general logical
expression. A while loop is used for that purpose. A repeat construct must contain a
number, which can be a constant, a variable or a signal value. However, if the number is
ld
a variable or signal value, it is evaluated only when the loop starts and not during the loop
execution.
Forever Loop:
or
The keyword forever is used to express this loop. The loop does not contain any
expression and executes forever until the $finish task is encountered. The loop is
equivalent to a while loop with an expression that always evaluates to true, e.g., while
(1). A forever loop can be exited by use of the disable statement.
A forever loop is typically used in conjunction with timing control constructs. If

timing control constructs are not used, the Verilog simulator would execute this statement
infinitely without advancing simulation time and the rest of the design would never be
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executed.
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8 Bit ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of
an instruction. Contains accumulator CPU registers and related logic such as arithmetic
and logic unit. ALU communicates with the internal registers and the external data bus by
Addition
Subtraction
Logical AND
Logical OR
Logical Exclusive OR
Compare
Left or Right Shifts or Rotate
Increment
Decrement
Set/Reset and Test Bit
3.1 Overview:
or

ld
using internal data bus. Functions performed by the ALU include:
The arithmetic logic unit (ALU) is the brain of the computer, the device that performs the
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arithmetic operations like addition, subtraction or logical operations like AND &OR.
Figure 15
ALU Symbol
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For this project I need to design 8-bit ALU to perform 16 operations:

ADD, SUB, Increment, Decrement, AND, CLEAR, NOT, Immediate OR, MOV, MOV
Word, Rotate Left, Rotate Right, SWAP, EX-OR, BCF, BSF. The ALU should have two
8-bit inputs s1 and s2, 4-bit ALU operation, output should be 8-bit result, 1-bit Zero
ld
signal, 1-bit Carry Out and 1-bit overflow output when an overflow is detected.
3.2 Project Requirements:
Design 8-bit ALU that has inputs s1 [7:0], s2 [7:0], m ALU operation [3:0] and outputs
operations.
3.3 Design Description:
3.3.1 1-bit ALU for the MSB:
or
Zero, Result [7:0], Overflow, Carry Out. The ALU should perform the above sixteen (16)
For the most significant bit (MSB) of my ALU I designed a special 1- bit ALU, which
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has overflow detection logic and a special output Set.
Figure 16 1-bit ALU for the Most Significant Bit (MSB)
3.3.2 Overflow Detection:
The overflow can be found when we compare the CarryIn and the CarryOut signal. If
they have different values, than overflow occurs; if both of them are 0s or 1s there is no
overflow. This logic can easily be represented by XOR on the two signals.
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or
Truth Table for XOR
Table 8
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3.3.3 Set Output:

This 1-bit ALU differs from the regular one not only by the overflow detection. It has an
extra output called Set used for the SLT operation. Set is the Sum output of the adder and
is connected to the Less input of the first 1-bit ALU.
3.4 Regular 1-bit ALU:
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My regular 1-bit ALU consists of 1-bit full adder, components for logical operations and
operation selector. This 1-bit ALU is used for the first 7 bits [6.0] of the 8-bit ALU.
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Figure 17 1-bit ALU
or
3.5 Full Adder:
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It can perform the following operations: AND, OR, addition of a & b. The adder has 3
Inputs - a, b, CarryIn; and 2 outputs - Sum and CarryOut and is also called (3,2). Adder
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with 2 inputs and 2 outputs is called half adder.
Figure 18
1-bit Full Adder
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Input & Output Specification of 1-bit Full Adder
Table 9
or
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3.6 Controls Of 1-bit ALU:
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Selecting the ALU operation to be performed is implemented with 4x1 multiplexer.
Figure 19 41 Multiplexer
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The 4x1 multiplexer is delivered with the logic of three 2x1 multiplexers as is shown on
Fig. 20. The data inputs are A, B, C and D control; signals are S0 and S1; output result is
E. The truth table on table 10 describes the logical functionality of 4x1 multiplexer. The
ld
code combination of the control signals S0, S1 will determinate which one of the data
signals A, B, C or D will appear at the output E. For example with combination S0=0 and
or
S1=0 the output signal E is A.
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Table 10 Truth Table for 41 Multiplexer
Figure 20 21 Multiplexer & Truth Table
3.7 Zero Detector:

It is needed to check if two registers are equal or not. We could say that they are equal if
a b = 0.
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The expression for the Zero signal is:
or
Figure 21 Zero Detectors
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Hard Ware Kit (Spartan -3A)

Description:
The Spartan-3A Evaluation Kit provides a platform for engineers designing
with the Xilinx Spartan-3A FPGA and/or Cypress PSoC Mixed Signal Array. The
these devices but
also
to implement
ld
board provides the necessary hardware to not only evaluate the advanced features of
user applications
using peripherals
and
expansion connectors on the Spartan-3A evaluation board. Figure 1 is a picture of the
the components and interconnects.

Features:
Clocks
Xilinx 3S400A-4FTG256C FPGA
or
Spartan-3A evaluation board; the block diagram in Figure 2 provides a high-level view of
16 MHz Oscillator (Maxim)
12 MHz Clock from PSoC device
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32 kHz Clock from PSoC device

Memory
32 Mb Page-Mode Flash Memory (Spansion)

128 Mb SPI Flash Memory (Spansion)
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Interfaces
USB 2.0 (PSoC)
JTAG Programming/Configuration Port

Temperature Sensor (Texas Instruments)
Buttons and switches

Four User LEDs
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Four PSoC Cap Sense capacitive switches

Four FPGA user pushbuttons (forwarded from PSoC Cap Sense switches)
Reset Push Button Switch
Digilent 6-pin header (2)
Configuration and Debug
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TU
JTAG
or
2x20 0.1 Expansion Connector
ld
User I/O and expansion
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TU
or
ld
Hardware Flow Diagram:
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Figure 22 Flow Diagram
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TU
or
ld
Spartan- 3A Evaluation Board Picture
Figure 23 Spartan-3A Evaluation Board
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Functional Description:
A Xilinx Spartan-3A (XC3S400A-4FTG256C) 400 K gate FPGA and a Cypress
Cy8C24894 PSoC Mixed-Signal Array are the primary components of the Avnet
Spartan-3A evaluation board.
In addition to on-board processing functions, the PSoC
device provides off- board communication via a USB 2.0 full-speed interface.
ld
Communication between the PSoC and FPGA is facilitated by a 3.3 V level RS-232
interface between the two devices. This, along with several GPIO lines interconnecting
the PSoC and FPGA, provide control and data-transfer mechanisms. A high-level block
or
diagram of the Spartan-3A evaluation board is shown in Figure 23. As can be seen in 2
Figure 23, the USB controller (PSoC), an SPI port, and an I^2C port provide off-board
communication mechanisms. On-board memory consists of a 128 Mbit SPI memory that
may be used by either the PSoC or the FPGA, with FPGA access controlled by the PSoC;
and 32 Mbit parallel Flash memory interfaced to the FPGA. Subsequent sections provide
details of the board design.
Xilinx Spartan-3A FPGA:
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The Xilinx XC3S400A-4FTG256C device designed onto the Spartan-3A evaluation

board provides four I/O banks with Vccaux and I/O voltage of all banks fixed at +3.3 V.
The ability to power Vcco and Vccaux from a common rail is a feature of the Spartan-3A
that allows a lower-cost board design. Note that because Vccaux is set at +3.3 V, each
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designs UCF must contain the statement:

CONFIG VCCAUX = 3.3;
The four I/O banks are described in Table 11 and detailed I/O pin usage is provided
throughout this document. Note that all pins utilized are bidirectional (regardless of
usage), the XC3S400A input-only pins are not utilized in this implementation.
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TU
or
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Block Diagram
Figure 24 Spartan-3A Block Diagram
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or
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Table 11 I/O Allocation
Cypress PSoC Mixed-Signal Array:
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The Cypress Cy8C24894 is a configurable device containing analog and digital blocks
and peripheral devices that allow the user to create customized configurations to support
different applications. As configured on the Spartan-3A evaluation board, the PSoC
provides a full-speed (12 Mbps) USB interface, RS-232, SPI and I^2C interfaces,
four capacitive touch-pads (the condition of which is sent to the FPGA), and 15 generalpurpose I/O lines (12 connected to the FPGA and three connected to header J9).A 6-pin
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header that is compatible with the Cypress Mini-Programmer allows configuration of

the PSoCs Flash program store. Additionally, the PSoC s JTAG interface may be
utilized to program the FPGA; e.g., the FPGA bit file transferred to the PSoC via
USB and the PSoC JTAG interface transfers the file into the FPGA.
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Memory:
The Spartan-3A evaluation board is populated with both parallel Flash memory (4
Mbytes) and 128 Mbit SPI Serial to support various types of applications. Both Parallel
Flash and SPI Serial Flash may be used for FPGA configuration. Figure 25 shows a
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or
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High-level block diagram of the memory interfaces on this board.
Figure 25
Memory Interfaces
Parallel Flash:
Parallel Flash memory consists of a single 32 Mbit Spansion S29GL032N in a TSOP-56
JN
package interfaced to the FPGA. This device (U22) may be utilized in a 4 M x 8 or a 2

M x 16 configuration by control of the Flash_BYTE# signal. Flash_BYTE# is pulled
low through a 10 K resistor to establish the 4 M x 8 default configuration that may
be used
for
FPGA configuration. Following configuration, the FPGA may drive
Flash_BYTE# high to establish the 2 M x 16 configuration. Jumper JP1 may be used to

write-protect the Flash memory by placing a shunt across pins 1 and 2; default setting is
JP1 open. Note the PCB layout also supports the same Spansion Flash device in a
TSSOP-48 package. Table 12 provides the FPGA/FLASH pinout.
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or
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Table 12 Parallel Flash Interface Pinout
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Serial SPI Flash:
128 Mbits of serial Flash memory is provided by a Spansion S25FL128P device (U19)
interfaced to the Spartan- 3A FPGA via its dedicated SPI interface, and to the Cypress
PSoC device via a 2:1 multiplexer (U20). This multiplexer is controlled by the PSoC,
JN
which is master of this SPI interface. There are two SPI modes as depicted in Figure 25;
PSoC/FPGASPI
Flash
(PSoC_SPI_MODE=0)
and
PSoCFPGA
(PSoC_SPI_MODE=1).
In the PSoC/FPGA SPI Flash mode, either the PSoC or the FPGA may access the
SPI Flash by driving its select line low. This is done through an AND gate (U21) that
will drive the SPI Flashs chip select line (SF_SEL#) low in response to a low s elect
signal from the FPGA (FPGA_SPI_SEL#) or the PSoC (PSoC_SPI_SEL). Note that the
SPI clock line (SPI_CLK) may be driven by either the PSOC or the FPGA. Since this
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configuration has the potential for conflict, if the PSoC intends to access the SPI Flash, it
must drive the FPGAs PROG_B pin low to place the FPGA in a reset state to prevent it
accessing the SPI Flash.
In the PSoC FPGA mode (PSoC_SPI_MODE=1) the multiplexer is configured to
interconnect the PSoC and FPGA SPI interfaces; the purpose of this is to enable slave
ld
serial configuration from PSoC to FPGA. In this mode the PSoC is master and the FPGA
will act as slave. Since the FPGAs SPI interface is only active during SPI boot mode,
implementation of the FPGAs slave interface must be accomplished via firmware.
While this configuration happens to share common pins with the FPGA SPI port, they
or
will function as slave serial in this mode. Table 13 provides the FPGAs SPI interface
pinout.
6-pin header J8 may be used to allow the PSoC to expand the SPI interface to an external
environment. Since the PSoCs SPI select signal (PSoC_SPI_SEL#) is common to the
SPI Flash as well as the SPI expansion interface, the default jumper on JP6 must be
removed prior to using the SPI expansion. Table 14 provides the J8 pinout.
Note that J8 pin 6 provides +3.3 V to another board; if that board is already powered then
JN
TU
J8 pin 6 must not be connected.
Table 13 SPI Interface Pinout
Table 14 SPI Header J8 Pinout
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Interfaces:
Interfaces on the Spartan-3A evaluation board consist of USB 2.0 via the PSoC, two 0.1
6-pin right-angle headers designed to T M interface to Digilent modules, a 0.1 2 x 20
header providing connectivity to available FPGA general-purpose I/O pins, a 0.1 1 x 6
header for SPI interface expansion, and a sensor providing temperature information via
ld
an I C interface.
USB 2.0:
or
USB Mini-AB connector P1 connects the PSoC device to a full-speed (12 Mbps) USB
host. Power supplied by the USB host via connector P1 (+5V_USB) may be used to
power the Spartan-3A evaluation board by jumpering JP2 1:2.
USB-UART:
The USB-UART interface is used for communication between the PSoC and the FPGA
but is not utilized externally (e.g., there is no RS-232 connector). This interface operates
at 3.3 V and is the mechanism by which the FPGA communicates via USB; e.g., the
TU
PSoC device provides UART/USB translation. Note that the net names UART_RXD and
UART_TXD on the schematic are named in terms of the PSoC connection.
Net
UART_RXD is an output from the FPGA and an input to the PSoC, as shown by the
direction of the off-page connectors on the schematic. The FPGA Tx signal is connected
to the PSoC Rx signal and then the PSoC re-broadcasts the data to the USB. For
incoming data from USB, the PSoC transmits on the UART_TXD net which is actually
JN
an Rx for the FPGA.
Table 15 USB-UART Signals
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Digilent Headers:
Two right-angles, 6-pin (1 x 6 female) Digilent headers (J6, J7) are interfaced to the
FPGA, with each header providing 3.3 V power, ground, and four I/Os. These headers
may be utilized as general-purpose I/Os or may be used to interface to Digilent modules.
J6 and J7 are placed in close proximity (09-centers) on the PCB in order to support dual
ld
Digilent modules. Figure 26 shows the pinout of the Digilent headers; Table 16 provides
or
the FPGA pinout.
TU
Figure 26 Digilent Header Pinout
Table 16 Connections
Miscellaneous I/O:
JN
Four user push button switches are provided via capacitive touch-pads connected to the
Cypress PSoC device. A touch at any of these four pads is sensed by the PSoC and
forwarded to the FPGA; these push buttons and their relationship to the FPGA are
depicted in Table 17. Note that FPGA_RESET is a soft reset intended for FPGA code
usage and does not perform any type of FPGA hardware reset.
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Table 17 Connections
ld
LEDs:
Four LEDs are provided for signaling purposes and connected to the FPGA as shown in
or
Table18. The corresponding FPGA pin must be driven high to light an LED.
Table 18 LED Assignment
GPIO Header (2 x 20):
Some unused FPGA pins are connected to 0.1 2 x 20-pin header J4. Signal names and
connector pin/FPGA pin connections are identified in Table 19. All I/Os are +3.3 V
JN
TU
CMOS.
Table 19 GPIO Pin Assignment
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ICTemperature Sensor:
A Texas Instruments TMP100 digital temperature sensor is interfaced to the PSoC via an
I C interface. The TMP100 has two 2 address pins to set the low-order I C slave address
bits; both pi ns are pulled low in this application providing an address of 0x90 (W) and
0x91 (R).The TMP100 will provide temperature readings over its specified operating
ld
temperature, -55 C to +125 C; well beyond the ability of the Spartan-3A evaluation
board to operate.
Module Clocks:
or
Three clocks are provided to the FPGA; 16.0 MHz from a Maxim MAX7381 CMOS
oscillator (U6), and 12.0 MHz and 32.0 kHz from the PSoC. Table 20 provides FPGA
connection details.
Table 20 Module Clocks
TU
Configuration:
The Spartan-3A evaluation board provides four mechanisms to program and
configure the FPGA; these are JTAG, Parallel Flash, Serial Flash, and the Cypress
PSoC. The storage devices (Flash and SPI) cannot be programmed via the JTAG
connector. The FPGA is the only thing in the JTAG chain on the Spartan-3A evaluation
board; however, depending on the setting of configuration jumpers M [2:0], any of these
JN
can be the configuration source. The serial Flash, Parallel Flash, and PSoC are described
earlier in this document.
Programming the Spartan-3A evaluation board via Boundary Scan requires that a JTAG
download cable be attached to the 14-pin 2 mm spaced header J5 (Figure 27) with a
ribbon cable or with flying leads. If the Xilinx Parallel Cable IV is used, the
ribbon cable connector mates with the keyed J5 connector.
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ld
Figure 27 Parallel IV Connector
Configuration Modes:
The following table shows the Spartan-3A evaluation board configuration modes
or
set by Jumper JP4. All mode jumpers (including the PUDC_B pin) are pulled high,
with jumper installation grounding the connection. Adding a jumper to the MODE pins
ties them to a pull-down that is stronger than the default pull-up. This is necessary in
order for the PSoC to overdrive the MODE jumpers regardless of whether or not the
jumpers are installed. Figure 6 depicts configuration jumper JP4; Table 21 provides the
various configuration settings at JP4, with recommended settings highlighted. A push
button labeled PROG (SW1) is pulled high and connected to the FPGA PROG
via AND gate U9; also connected to U9 is the PSoC (PSOC_FPGA_PROG).
Pushing SW1 (or driving PSOC_FPGA_PROG low) activates the FPGA programming
TU
mechanism. Upon releasing SW1 (or PSOC_FPGA_PROG going high), a reconfiguration is initiated based upon the setting of JP4. A blue LED (D7) should light
JN
when FPGA DONE is asserted.
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or
Table 21 JP4 Settings
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Figure 28 Configuration Jumper (JP4)
TU
Module Power:
The Spartan-3A evaluation board requires a +5 V input at barrel jack J3 or +5 V
via USB cable. Jumper JP2 is used to select between the barrel jack (JP2 = 2:3) or USB
power (JP2 = 1:2). LED D1 should be illuminated when power is applied. Jumper JP7
1:2 selects the barrel jack/USB input power; JP7 2:3 is not applicable.
Note that the
JN
barrel jack requires a 2.1 mm plug.
Application of 5 V power is sensed by a Texas Instruments TPS3809K33 Voltage

Supervisor. When power is above the TPS3809s threshold, its active-low reset output
is driven high supplying the enable for a Texas Instruments TPS62290 1A step-down
converter (U5) to supply the +3.3 V rail. The 3.3 V rail provides the enable (a Texas
Instruments TPS3106K33 Voltage Supervisor) to a second TPS62290 (U24) which
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supplies the +1.2 V rail. When the+1.2 V rail is above the TPS3106s threshold, its
active-low reset output is released allowing the power-on reset signal (PO_RESET#) to
go high. As mentioned above, pushbutton switch SW1 may be used to momentarily force
(via AND gate U23) PO_RESET# low.
ld
Note that 0-ohm jumper JT1 may be utilized to set the
operating mode of the TPS62290 converter; JT1 = 1:2 (default) sets fixed-
or
frequency PWM mode, JT1 2:3 sets power-save mode (automatic PFM/PWM switching).
Figures 29, 30 and 31, below, show details of the +3.3 V and
+1.2 V power supplies. Figure 29 shows that +1.2 V power (bottom trace) is delayed 114
ms from +3.3 V power. Using a finer scale, Figures 30 and 31 shows the rise of +3.3 V
JN
TU
and +1.2 V power (respectively) is monotonic and glitch-free.
Figure 29 Power Supply Sequencing
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JN
TU
Figure 30 +3.3v Power Supply Startup
Figure 31 +1.2v Power Supply Startup
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PCB Stackup:
Figure 32 shows 4-layer stacks up of the Spartan-3A Evaluation Kit Printed Circuit
Board (PCB). The PCB substrate is FR4- class epoxy glass with 1/2oz copper used for
or
ld
all layers.
JN
TU
Figure 32 PCB Layer Stack
77

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VLSI Design

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www.alljntuworld.

INTRODUCTION TO VLSI DESIGN

design and modeling techniques.

1.1.1 VLSI DESIGN

A steady improvement in the predictability of circuit behavior.

1.1.2 VLSI DESIGN FLOW

The above developments have resulted in a proliferation of approaches to VLSI design.

be considered. The Y-chart (first introduced by D. Gajski) is shown in below figure1

Geometrical layout domain

Typical VLSI design flow in three domains (Y-chart representation)

1.1.3 ABSTRACTION MODEL

design at various levels.

1.1.4 ASIC DESIGN FLOW

design description- in terms of well defined standard constructs and conventions.

Design domain and levels of abstraction

Major activities in ASIC design

Design description is an activity independent of the target technology or

1.1.5 DESIGN DESCRIPTION

arrived in a step-by-step manner.

The first step in evolving the design description is to describe the

ASIC design and development flow.

The design at the behavioral level is to be elaborated in terms of known and

1.2 EMERGENCE OF HDLs

1.2.1 IMPORTANCE OF HDLs

1.2.2 HARDWARE DESCRIPTIVE LANGUAGE:

1.2.3 OVERVIEW OF VERILOG HDL:

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description

An even higher level

Verilog HDL allows a hardware designer to describe designs at a high level of

abstraction such as at the architectural or behavioral level as well as the lower

1.2.4 POPULARITY OF VERILOG HDL:

introduction of hardware description language (HDL).Actually the use of this language is

and imply no particular hardware structure.

Hardware description languages have two main

applications documenting a design and modeling it. Good documentation of a design

development of hardware languages is to replace this prototyping process with validation

Once an entity has been modeled, it needs to be

performing the following steps:

VHDL is an acronym for VHSIC Hardware description language (VHSIC is an acronym

The VHDL language can be regarded as an integrated amalgamation of the following

Net list language.

Waveform generation language.

above constructs may be combined to provide a comprehensive description of the system

1.3 BASIC CONCEPTS OF VERILOG:

language. All keywords are in low case.

delimiters, numbers, string, identifiers, and keywords. Verilog HDL is a case-sensitive

Multiple-line comments cannot be nested.

Sized numbers are represented as <size> <base format> <number>.

0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular base.

Uppercase letters are legal for number specification.

impedance value is denoted by z.

vector. If the most significant digit is 1, then it is also zero extended.

<base format > and <number>.

UNDERSCORE CHARACTERS AND QUESTION MARKS:

An underscore character _ is allowed anywhere in a number except the first character.

A question mark ? is the Verilog HDL alternative for z in the context of

A string is a sequence of character that is enclosed by double quotes. The restriction on a

IDENTIFIERS AND KEYWORDS:

or an underscore. They cannot start with a number or a $ sign.