8086/8088 Architecture

Assembled by Aatif Shahbaz

Reference: Intel Microprocessor - Architecture, Programming and Interfacing by Barry B. Brey
In 1978, Intel released the 8086 microprocessor; a year or so later, it released the 8088. Both
devices are 16-bit microprocessors, which executed instructions in as little as 400 ns (2.5 MIPs,
or 2.5 millions of instructions per second). This represented a major improvement over the
execution speed of the 8085. In addition, the 8086 and 8088 addressed 1MB of memory,
which was 16 times more memory than the 8085. (A 1M-byte memory contains 1024K byte
sized memory locations or 1,048,576 bytes.)
The Programming Model:
The programming model of the 8086 through the Core2 is considered to be program visible
because its registers are used during application programming and are specified by the
instructions. Other registers, are considered to be program invisible because they are not
addressable directly during applications programming, but may be used indirectly during
system programming. Only the 80286 and above contain the program-invisible registers used
to control and operate the protected memory system and other features of the
microprocessor.
Figure illustrates the programming model of the 8086 through the Core2 microprocessor
including the 64-bit extensions. The earlier 8086, 8088, and 80286 contain 16-bit internal
architectures, a subset of the registers shown in Figure. The 80386 through the Core2
microprocessors contain full 32-bit internal architectures. The architectures of the earlier 8086
through the 80286 are fully upward-compatible to the 80386 through the Core2. The shaded
areas in this illustration represent registers that are found in early versions of the 8086, 8088,
or 80286 microprocessors and are provided on the 80386Core2 microprocessors for
compatibility to the early versions.

The programming model contains 8, 16, and 32-bit registers. The Pentium 4 and Core2 also
contain 64-bit registers when operated in the 64-bit mode as illustrated in the programming
model.
The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL and are referred to when an
instruction is formed using these two-letter designations. For example, an ADD AL,AH
instruction adds the 8-bit contents of AH to AL. (Only AL changes due to this instruction.)
The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, SS, FS, and GS.
Note that the first 4 registers contain a pair of 8-bit registers. An example is AX, which contains
AH and AL. The 16-bit registers are referenced with the two-letter designations such as AX. For
example, an ADD DX, CX instruction adds the 16-bit contents of CX to DX. (Only DX changes
due to this instruction.)
Some registers are general-purpose or multipurpose registers, while some have special
purposes. The multipurpose registers include AX, BX, CX, DX, BP, DI, and SI. These registers
hold various data sizes (bytes or words) and are used for almost any purpose, as dictated by a
program.

Multipurpose Registers:
AX(accumulator): AX is referenced as a 16-bit register, or as either of two 8-bit registers (AH
and AL). Note that if an 8-bit register is addressed, only that portion of the 16-bit register
changes without affecting the remaining bits. The accumulator is used for instructions such as
multiplication, division, and some of the adjustment instructions.

BX(base index): BX, BH, or BL register sometimes holds the offset address of a location in the
memory system in all versions of the microprocessor.
CX(count): CX, CH, or CL, is a general-purpose register that also holds the count for various
instructions. Instructions that use a count are the repeated string instructions
(REP/REPE/REPNE); and shift, rotate, and LOOP instructions.
DX(data): DX, DH, or DL, is a general-purpose register that holds a part of the result from a
multiplication or part of the dividend before a division. In the 80386
and above, this register can also address memory data.
BP(base pointer): BP, points to a memory location in all versions of the microprocessor for
memory data transfers.
DI(destination index): DI, often addresses string destination data for the string instructions.
SI(source index): The source index register often addresses source string data for the string
instructions.

Special-Purpose Registers:
The special-purpose registers include IP, SP, and FLAGS; and the segment registers include CS,
DS and ES.
IP(instruction pointer): IP addresses the next instruction in a section of memory defined as
a code segment. This register is IP (16 bits) when the microprocessor operates in the real
mode and EIP (32 bits) when the 80386 and above operate in the protected mode. Note that
the 8086, 8088, and 80286 do not contain an EIP register and only the 80286 and above
operate in the protected mode. The instruction pointer, which points to the next instruction in
a program, is used by the microprocessor to find the next sequential instruction in a program
located within the code segment. The instruction pointer can be modified with a jump or a call
instruction.
SP(stack pointer): SP addresses an area of memory called the stack. The stack memory
stores data through this pointer and is explained later in the text with the instructions that
address stack data. This register is referred to as SP.
FLAGS: FLAGS indicate the condition of the microprocessor and control its operation. Figure
shows the flag registers of all versions of the microprocessor. (Note the flags are upwardcompatible from the 8086/8088 through the Core2 microprocessors.) The 808680286 contain
a FLAG register (16 bits) and the 80386 and above contain an EFLAG register (32-bit extended
flag register). The 64-bit RFLAGS contain the EFLAG register, which is unchanged in the 64-bit
version.

The rightmost five flag bits and the overflow flag change after many arithmetic and logic
instructions execute. The flags never change for any data transfer or program control
operation. Some of the flags are also used to control features found in the microprocessor.
Following is a list of each flag bit, with a brief description of their function.
C (carry): Carry holds the carry after addition or the borrow after subtraction. Then carry flag
also indicates error conditions, as dictated by some programs and procedures.
P (parity): Parity is a logic 0 for odd parity and a logic 1 for even parity. Parity is the count of
ones in a number expressed as even or odd. For example, if a number contains three binary
one bits, it has odd parity. If a number contains no one bits, it has even parity. Today parity
checking is often accomplished by the data communications equipment instead of the
microprocessor.
A (auxiliary carry): The auxiliary carry holds the carry (half-carry) after addition or the borrow
after subtraction between bit positions 3 and 4 of the result. This highly specialized flag bit is
tested by the DAA and DAS instructions to adjust the value of AL after a BCD addition or
subtraction. Otherwise, the A flag bit is not used by the microprocessor or any other
instructions.
Z (zero): The zero flag shows that the result of an arithmetic or logic operation is zero. If , the
result is zero; if , the result is not zero. This may be confusing, but that is how Intel decided to
name this flag.
S (sign): The sign flag holds the arithmetic sign of the result after an arithmetic or logic
instruction executes. If , the sign bit (leftmost bit of a number) is set or negative; if , the sign
bit is cleared or positive.
T (trap): The trap flag enables trapping through an on-chip debugging feature. (A program is
debugged to find an error or bug.) If the T flag is enabled (1), the microprocessor interrupts the
flow of the program on conditions as indicated by the debug registers and control registers. If
the T flag is a logic 0, the trapping (debugging) feature is disabled. The Visual C++ debugging
tool uses the trap feature and debug registers to debug faulty software.

I (interrupt): The interrupt flag controls the operation of the INTR (interrupt request) input
pin. If , the INTR pin is enabled; if , the INTR pin is disabled. The state of the I flag bit is
controlled by the STI (set I flag) and CLI (clear I flag) instructions.
D (direction): The direction flag selects either the increment or decrement mode for the DI
and/or SI registers during string instructions. If , the registers are automatically decremented;
if , the registers are automatically incremented. The D flag is set with the STD (set direction)
and cleared with the CLD (clear direction) instructions.
O (overflow): Overflows occur when signed numbers are added or subtracted. An overflow
indicates that the result has exceeded the capacity of the machine. For example, if 7FH (+127 )
is addedusing an 8-bit additionto 01H (+1 ), the result is 80H (128). This result represents
an overflow condition indicated by the overflow flag for signed addition. For unsigned
operations, the overflow flag is ignored.

Segment Registers:
Additional registers, called segment registers, generate memory addresses when combined
with other registers in the microprocessor. There are either four or six segment registers in
various versions of the microprocessor. A segment register functions differently in the real
mode when compared to the protected mode operation of the microprocessor.
CS (code): The code segment is a section of memory that holds the code (programs and
procedures) used by the microprocessor. The code segment register defines the starting
address of the section of memory holding code. In real mode operation, it defines the start of
a 64K-byte section of memory; in protected mode, it selects a descriptor that describes the
starting address and length of a section of memory holding code. The code segment is limited
to 64K bytes in the 808880286, and 4G bytes in the 80386 and above when these
microprocessors operate in the protected mode.
DS (data): The data segment is a section of memory that contains most data used by a
program. Data are accessed in the data segment by an offset address or the contents of other
registers that hold the offset address. As with the code segment and other segments, the
length is limited to 64K bytes in the 808680286, and 4G bytes in the 80386 and above.
ES (extra): The extra segment is an additional data segment that is used by some of the string
instructions to hold destination data.
SS (stack): The stack segment defines the area of memory used for the stack. The stack entry
point is determined by the stack segment and stack pointer registers. The BP register also
addresses data within the stack segment.

Real Mode Memory Addressing:

The 80286 and above operate in either the real or protected mode. Only the 8086 and 8088
operate exclusively in the real mode. In the 64-bit operation mode of the Pentium 4 and
Core2, there is no real mode operation. Real mode operation allows the microprocessor to
address only the first 1M byte of memory spaceeven if it is the Pentium 4 or Core2
microprocessor. Note that the first 1M byte of memory is called the real memory,
conventional memory, or DOS memory system. The DOS operating system requires that the
microprocessor operates in the real mode. Windows does not use the real mode. Real mode
operation allows application software written for the 8086/8088, which only contains 1M byte
of memory, to function in the 80286 and above without changing the software. The upward
compatibility of software is partially responsible for the continuing success of the Intel family
of microprocessors. In all cases, each of these microprocessors begins operation in the real
mode by default whenever power is applied or the microprocessor is reset. Note that if the
Pentium 4 or Core2 operate in the 64-bit mode, it cannot execute real mode applications;
hence, DOS applications will not execute in the 64-bit mode unless a program that emulates
DOS is written for the 64-bit mode.
Segments and Offsets:
A combination of a segment address and an offset
address accesses a memory location in the real
mode. All real mode memory addresses must
consist of a segment address plus an offset
address. The segment address, located within one
of the segment registers, defines the beginning
address of any 64K-byte memory segment. The
offset address selects any location within the 64K
byte memory segment. Segments in the real mode
always have a length of 64K bytes. Figure shows
how the segment plus offset addressing scheme
selects a memory location. This illustration shows
a memory segment that begins at location 10000H
and ends at location 1FFFFH64K bytes in length.
It also shows how an offset address, sometimes
called a displacement, of F000H selects location
1F000H in the memory system. Note that the
offset or displacement is the distance above the
start of the segment, as shown in Figure.
The segment register in Figure contains 1000H, yet it addresses a starting segment at location
10000H. In the real mode, each segment register is internally appended with a 0H on its
rightmost end. This forms a 20-bit memory address, allowing it to access the start of a
segment. The microprocessor must generate a 20-bit memory address to access a location
within the first 1M of memory. For example, when a segment register contains 1200H, it
addresses a 64K-byte memory segment beginning at location 12000H. Likewise, if a segment

register contains 1201H, it addresses a memory segment beginning at location 12010H.

Because of the internally appended 0H, real mode segments can begin only at a 16-byte
boundary in the memory system. This 16-byte boundary is often called a paragraph.
Because a real mode segment of memory is
64K in length, once the beginning address is
known, the ending address is found by
adding FFFFH. For example, if a segment
register contains 3000H, the first address of
the segment is 30000H, and the last address
is 30000H + FFFFH or 3FFFFH. Table below
shows several examples of segment register
contents and the starting and ending
addresses of the memory segments
selected by each segment address.
The offset address is always added to the starting address of the segment to locate the data.
The segment and offset address is sometimes written as 1000:2000 for a segment address of
1000H with an offset of 2000H.
Default Segment and Offset Registers:
The microprocessor has a set of rules that apply to segments whenever memory is addressed.
These rules, which apply in the real and protected mode, define the segment register and
offset register combination. For example, the code segment register is always used with the
instruction pointer to address the next instruction in a program. This combination is CS:IP,
depending upon the microprocessors mode of operation. The code segment register defines
the start of the code segment and the instruction pointer locates the next instruction within
the code segment. This combination (CS:IP) locates the next instruction executed by the
microprocessor. For example, if CS=1400H and IP=1200H, the microprocessor fetches its next
instruction from memory location or 15200H.
Another of the default combinations is the stack. Stack data are referenced through the stack
segment at the memory location addressed by either the stack pointer (SP) or the pointer (BP).
These combinations are referred to as SS:SP or SS:BP. For example, if SS=2000H and
BP=3000H, the microprocessor addresses memory location 23000H for the stack segment
memory location. Note that in real mode, only the rightmost 16 bits of the extended register
address a location within the memory segment. Other defaults are shown in Table for
addressing memory using any Intel microprocessor with 16-bit registers.

Segment and Offset Addressing Scheme Allows Relocation:

The segment and offset addressing scheme seems unduly complicated. It is complicated, but it
also affords an advantage to the system. This complicated scheme of segment plus offset
addressing allows DOS programs to be relocated in the memory system. It also allows
programs written to function in the real mode to operate in a protected mode system. A relocatable program is one that can be placed into any area of memory and executed without
change. Re-locatable data are data that can be placed in any area of memory and used without
any change to the program. The segment and offset addressing scheme allows both programs
and data to be relocated without changing a thing in a program or data. This is ideal for use in
a general-purpose computer system in which not all machines contain the same memory
areas. The personal computer memory structure is different from machine to machine,
requiring re-locatable software and data.
Because memory is addressed within a segment by an offset address, the memory segment
can be moved to any place in the memory system without changing any of the offset
addresses. This is accomplished by moving the entire program, as a block, to a new area and
then changing only the contents of the segment registers. If an instruction is 4 bytes above the
start of the segment, its offset address is 4. If the entire program is moved to a new area of
memory, this offset address of 4 still points to 4 bytes above the start of the segment. Only the
contents of the segment register must be changed to address the program in the new area of
memory. Without this feature, a program would have to be extensively rewritten or altered
before it is moved. This would require additional time or many versions of a program for the
many different configurations of computer systems. This concept also applies to programs
written to execute in the protected mode for Windows. In the Windows environment all
programs are written assuming that the first 2G of memory are available for code and data.
When the program is loaded, it is placed in the actual memory, which may be anywhere and a
portion may be located on the disk in the form of a swap file.

Real Mode Segmented Model:

Real mode segmented model was mainstream programming model throughout the MSDOS era.
Program has access to 1MB of memory.
The CPU handles transformations of segment:offset combinations into a full 20-bit
address.
CS always points to the current code segment
The next instruction to be executed is pointed to by the CS:IP register pair.
Machine instructions called jumps can change CS to another code segment if necessary.
The program can span several code segments.
There is no direct CS manipulation to change from one code segment to another: when a
jump instruction needs to take execution into a different code segment, it changes CS
value for you.