ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays

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ULN2002A, ULN2003A, ULN2003AI

ULQ2003A, ULN2004A, ULQ2004A
SLRS027N DECEMBER 1976 REVISED JUNE 2015
ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays

1 Features
500-mA-Rated Collector Current (Single Output)

High-Voltage Outputs: 50 V
Output Clamp Diodes
Inputs Compatible With Various Types of Logic
Relay-Driver Applications
The ULx2004A devices have a 10.5-k series base

resistor to allow operation directly from CMOS
devices that use supply voltages of 6 V to 15 V. The
required input current of the ULx2004A device is
below that of the ULx2003A devices, and the required
voltage is less than that required by the ULN2002A
device.
.
2 Applications
Device Information(1)
Relay Drivers
Stepper and DC Brushed Motor Drivers
Lamp Drivers
Display Drivers (LED and Gas Discharge)
Line Drivers
Logic Buffers
3 Description
The ULx200xA devices are high-voltage, high-current
Darlington transistor arrays. Each consists of seven
NPN Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads.
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ULx200xD
SOIC (16)
9.90 mm 3.91 mm
ULx200xN
PDIP (16)
19.30 mm 6.35 mm
ULN200xNS
SOP (16)
10.30 mm 5.30 mm
ULN200xPW
TSSOP (16)
5.00 mm 4.40 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
.
.
Simplified Block Diagram
9
COM
The collector-current rating of a single Darlington pair

is 500 mA. The Darlington pairs can be paralleled for
higher current capability. Applications include relay
drivers, hammer drivers, lamp drivers, display drivers
(LED and gas discharge), line drivers, and logic
buffers. For 100-V (otherwise interchangeable)
versions of the ULx2003A devices, see the SLRS023
data sheet for the SN75468 and SN75469 devices.
The ULN2002A device is designed specifically for use
with 14-V to 25-V PMOS devices. Each input of this
device has a Zener diode and resistor in series to
control the input current to a safe limit. The
ULx2003A devices have a 2.7-k series base resistor
for each Darlington pair for operation directly with
TTL or 5-V CMOS devices.
16
1C
1B
2
15
2C
2B
3
14
3C
3B
4
13
4C
4B
5
12
5C
5B
6
11
6C
6B
7
7B
10
7C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
Absolute Maximum Ratings ......................................

ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: ULN2002A .......................
Electrical Characteristics: ULN2003A and
ULN2004A..................................................................
6.7 Electrical Characteristics: ULN2003AI ......................
6.8 Electrical Characteristics: ULN2003AI .....................
6.9 Electrical Characteristics: ULQ2003A and
ULQ2004A .................................................................
6.10 Switching Characteristics: ULN2002A, ULN2003A,
ULN2004A..................................................................
6.11 Switching Characteristics: ULN2003AI ..................
6.12 Switching Characteristics: ULN2003AI ..................
6.13 Switching Characteristics: ULQ2003A, ULQ2004A
6.14 Typical Characteristics ............................................
5
6
6
7
7
7
8
8
8
7
8
Parameter Measurement Information ................ 10

Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
13
Application and Implementation ........................ 14

9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
9.3 System Examples ................................................... 17
10 Power Supply Recommendations ..................... 18

11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19

12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................

Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
13 Mechanical, Packaging, and Orderable

Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (February 2013) to Revision N
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Deleted Ordering Information table. No specification changes. ............................................................................................. 1
Moved Typical Characteristics into Specifications section. ................................................................................................... 8
Changes from Revision L (April 2012) to Revision M
Page
Updated temperature rating for ULN2003AI in the ORDERING INFORMATION table ........................................................ 1
Changes from Revision K (August 2011) to Revision L
Page
Removed reference to obsolete ULN2001 device.................................................................................................................. 1
Submit Documentation Feedback
Copyright 19762015, Texas Instruments Incorporated
Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A

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5 Pin Configuration and Functions

D, N, NS, and PW Package
16-Pin SOIC, PDIP, SO, and TSSOP
Top View
1B
2B
3B
4B
5B
6B
7B
E
16
15
14
13
12
11
10
1C
2C
3C
4C
5C
6C
7C
COM
Pin Functions
PIN
NAME
1B
2B
3B
4B
5B
6B
7B
1C
10
2C
11
3C
12
4C
13
5C
14
6C
15
7C
16
COM
E
(1)
I/O (1)
NO.
DESCRIPTION
Channel 1 through 7 Darlington base input
Channel 1 through 7 Darlington collector output
I/O
Common cathode node for flyback diodes (required for inductive loads)
Common emitter shared by all channels (typically tied to ground)
I = Input, O = Output

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6 Specifications
6.1 Absolute Maximum Ratings
at 25C free-air temperature (unless otherwise noted) (1)
MIN
VCC
Collector-emitter voltage
Clamp diode reverse voltage
VI
IOK
(2)
50
V
V
Peak collector current, See Figure 4 and Figure 5
500
mA
Output clamp current
500
mA
Total emitter-terminal current
2.5
TJ
Operating virtual junction temperature
ULN200xA
20
70
ULN200xAI
40
105
ULQ200xA
40
85
ULQ200xAT
40
105
Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds
(2)
30
Operating free-air temperature range
(1)
UNIT
50
Input voltage (2)
TA
Tstg
MAX
Storage temperature
65
150
260
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
6.2 ESD Ratings

VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
VCC
Collector-emitter voltage (non-V devices)
TJ
Junction temperature
MIN
MAX
50
UNIT
V
40
125
6.4 Thermal Information

ULx200x
THERMAL METRIC (1)
D
(SOIC)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
73
67
64
108
C/W
UNIT
RJA
Junction-to-ambient thermal resistance
RJC(top)
Junction-to-case (top) thermal resistance
36
54
n/a
33.6
C/W
RJB
Junction-to-board thermal resistance
n/a
n/a
n/a
51.9
C/W
JT
Junction-to-top characterization parameter
n/a
n/a
n/a
2.1
C/W
JB
Junction-to-board characterization parameter
n/a
n/a
n/a
51.4
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics: ULN2002A

TA = 25C
PARAMETER
TEST FIGURE
VI(on)
ON-state input voltage
Figure 14
VCE = 2 V,
VOH
High-level output voltage after

switching
Figure 18
VS = 50 V, IO = 300 mA
VCE(sat)
Collector-emitter saturation
voltage
Figure 12
VF
Clamp forward voltage
ICEX
Collector cutoff current
ULN2002A
TEST CONDITIONS
MIN
TYP
IC = 300 mA
13
mV
IC = 100 mA
0.9
1.1
II = 350 A,
IC = 200 mA
1.3
II = 500 A,
IC = 350 mA
1.2
1.6
Figure 15
IF = 350 mA
Figure 9
VCE = 50 V,
II = 0
50
Figure 10
VCE = 50 V,
TA = 70C
II = 0
100
VI = 6 V
500
IC = 500 A
OFF-state input current
Figure 10
VCE = 50 V,
II
Input current
Figure 11
VI = 17 V
IR
Clamp reverse current
Figure 14
Ci
Input capacitance
VR = 50 V
1.7
50
V
A
A
65
0.82
1.25
TA = 70C
mA
100
VR = 50 V
VI = 0,
VS 20
II = 250 A,
II(off)
UNIT
MAX
50
f = 1 MHz
25
pF
6.6 Electrical Characteristics: ULN2003A and ULN2004A

TA = 25C
TEST
FIGURE
PARAMETER
TEST CONDITIONS
ULN2003A
MIN
TYP
ULN2004A
MAX
MIN
TYP
IC = 125 mA
VI(on)
ON-state input
voltage
Figure 14
VCE = 2 V
2.4
IC = 250 mA
2.7
IC = 275 mA
Figure 18
VCE(sat)
Collector-emitter
saturation voltage
Figure 13
ICEX
Collector cutoff
current
VS = 50 V, IO = 300 mA
8
VS 20
VS 20
IC = 100 mA
0.9
1.1
0.9
1.1
II = 350 A,
IC = 200 mA
1.3
1.3
II = 500 A,
IC = 350 mA
1.2
1.6
1.2
1.6
Figure 9
VCE = 50 V,
II = 0
50
50
Figure 10
VCE = 50 V,
TA = 70C
II = 0
100
100
Clamp forward
voltage
Figure 16
IF = 350 mA
II(off)
Off-state input
current
Figure 11
VCE = 50 V,
TA = 70C,
II
Input current
Figure 12
VI = 6 V
IC = 500 A
50
65
0.93
1.7
50
Ci
Input capacitance
Figure 15
VR = 50 V
VR = 50 V
TA = 70C
VI = 0,
f = 1 MHz
15
V
A
65
1.35
VI = 5 V
VI = 12 V
Clamp reverse
current
500
1.7
VI = 3.85 V
IR
mV
II = 250 A,
VF
IC = 350 mA
VOH
UNIT
IC = 200 mA
IC = 300 mA
High-level output
voltage after
switching
MAX
0.35
0.5
1.45
50
50
100
100
25
15
25
mA
A
pF

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6.7 Electrical Characteristics: ULN2003AI

TA = 25C
PARAMETER
VI(on)
VOH
VCE(sat)

switching
Collector-emitter saturation voltage
TEST FIGURE
Figure 14
Figure 18
Figure 13
ULN2003AI
TEST
CONDITIONS
VCE = 2 V
MIN
2.4
IC = 250 mA
2.7
IC = 300 mA
II = 250 A,
IC = 100 mA
II = 350 A,
II = 500 A,
II = 0
Figure 9
VCE = 50 V,
VF
Figure 16
IF = 350 mA
II(off)
Figure 11
VCE = 50 V,
II
Input current
Figure 12
VI = 3.85 V
IR
Figure 15
VR = 50 V
Ci
Input capacitance
VI = 0,
MAX
IC = 200 mA
VS = 50 V, IO = 300 mA
ICEX
TYP
VS 50
1.1
IC = 200 mA
1.3
IC = 350 mA
1.2
1.6
1.7
50
15
50
V
A
65
0.93
f = 1 MHz
mV
0.9
IC = 500 A
UNIT
1.35
mA
50
25
pF
6.8 Electrical Characteristics: ULN2003AI

TA = 40C to 105C
PARAMETER
VI(on)
VOH
VCE(sat)

switching
Collector-emitter saturation voltage
TEST FIGURE
Figure 14
Figure 18
Figure 13
TEST CONDITIONS
VCE = 2 V
II = 0
Figure 9
VCE = 50 V,
IF = 350 mA
II(off)
Figure 11
VCE = 50 V,
II
Input current
Figure 12
VI = 3.85 V
IR
Figure 15
VR = 50 V
Ci
Input capacitance
II = 500 A,
Figure 16
2.9
IC = 300 mA
II = 350 A,
VI = 0,
MAX
2.7
IC = 100 mA
TYP
IC = 250 mA
II = 250 A,
VF
MIN
IC = 200 mA
VS = 50 V, IO = 300 mA
ICEX
ULN2003AI
VS 50
1.2
IC = 200 mA
1.4
IC = 350 mA
1.2
1.7
1.7
30
15
100
2.2
1.35
mA
100
25
pF
65
0.93
f = 1 MHz
mV
0.9
IC = 500 A
UNIT

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6.9 Electrical Characteristics: ULQ2003A and ULQ2004A

over recommended operating conditions (unless otherwise noted)
TEST
FIGURE
PARAMETER
TEST CONDITIONS
ULQ2003A
MIN
TYP
ULQ2004A
MAX
MIN
TYP
MAX
IC = 125 mA
ON-state input
voltage
VI(on)
Figure 14
VCE = 2 V
IC = 200 mA
2.7
IC = 250 mA
2.9
IC = 275 mA
IC = 300 mA
High-level output
voltage after
switching
VCE(sat)
Collector-emitter
saturation voltage
Collector cutoff
current
ICEX
Figure 18
VS = 50 V, IO = 300 mA
8
VS 50
II = 350 A,
II = 500 A,
Figure 9
VCE = 50 V,
II = 0
Figure 10
VCE = 50 V,
TA = 70C
II = 0
100
VI = 6 V
500
Clamp forward
voltage
Figure 16
IF = 350 mA
II(off)
OFF-state input
current
Figure 11
VCE = 50 V,
TA = 70C,
0.9
1.2
IC = 200 mA
IC = 350 mA
1.2
Figure 12
0.9
1.1
1.4
1.3
1.7
1.2
1.6
100
1.7
IC = 500 A
VI = 3.85 V
Input current
mV
IC = 100 mA
VF
II
VS 50
II = 250 A,
Figure 13
2.3
1.7
65
0.93
Clamp reverse
current
Ci
Input capacitance
Figure 15
50
TA = 25C
VR = 50 V
VI = 0,
f = 1 MHz
15
V
A
65
1.35
VI = 5 V
VR = 50 V
50
0.35
0.5
1.45
VI = 12 V
IR
IC = 350 mA
VOH
UNIT
100
50
100
100
25
15
25
mA
A
pF
6.10 Switching Characteristics: ULN2002A, ULN2003A, ULN2004A

TA = 25C
PARAMETER
TEST CONDITIONS
ULN2002A, ULN2003A,
ULN2004A
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 17
0.25
tPHL
Propagation delay time, high- to low-level output
See Figure 17
0.25
6.11 Switching Characteristics: ULN2003AI

TA = 25C
PARAMETER
TEST CONDITIONS
ULN2003AI
MIN
TYP
MAX
UNIT
tPLH
See Figure 17
0.25
tPHL
See Figure 17
0.25

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6.12 Switching Characteristics: ULN2003AI

TA = 40C to 105C
PARAMETER
ULN2003AI
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
See Figure 17
10
tPHL
See Figure 17
10
6.13 Switching Characteristics: ULQ2003A, ULQ2004A

over recommended operating conditions (unless otherwise noted)
PARAMETER
ULQ2003A, ULQ2004A
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
See Figure 17
10
tPHL
See Figure 17
10
VCE(sat)
VCE(sat) - Collector-Emitter Saturation Voltage - V
2.5
TA = 25C
2
II = 250 A
II = 350 A
II = 500 A
1.5
0.5
0
0
100
200
300
400
500
600
700
IC - Collector Current - mA
Figure 1. Collector-Emitter Saturation Voltage

vs Collector Current (One Darlington)
800
VCE(sat)
VCE(sat) - Collector-Emitter Saturation Voltage - V
6.14 Typical Characteristics

2.5
TA = 25C
II = 250 A
2
II = 350 A
1.5
II = 500 A
1
0.5
0
0
100
200
300
400
500
600
700
800
IC(tot) - Total Collector Current - mA
Figure 2. Collector-Emitter Saturation Voltage

vs Total Collector Current (Two Darlingtons in Parallel)

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Typical Characteristics (continued)

600
500
450
IIC
C - Maximum Collector Current - mA
RL = 10
TA = 25C
IC
IC - Collector Current - mA
400
VS = 10 V
350
VS = 8 V
300
250
200
150
100
50
0
500
N=1
400
N=4
N=3
300
N=2
N=6
200 N = 7
N=5
100
TA = 70C
N = Number of Outputs
Conducting Simultaneously
25
50
75
100
125
150
200
175
10
20
30
40
II - Input Current - A
50
60
70
80
90 100
Duty Cycle - %
Figure 3. Collector Current vs Input Current
Figure 4. D Package Maximum Collector Current

vs Duty Cycle
600
2000
TJ = -40C to 105C
IIC
C - Maximum Collector Current - mA
1800
500
400
N=4
300
N=5
N=6
N=7
1600
Input Current A
N=1
N=3
N=2
200
1200
1000
Maximum
800
600
100
1400
400
TA = 85C
N = Number of Outputs
Conducting Simultaneously
0
10
20
30
40
50
60
70
Typical
200
80
90 100
2.5
3
3.5
4
Input Voltage V
Duty Cycle - %
4.5
Figure 6. Maximum and Typical Input Current

vs Input Voltage
Figure 5. N Package Maximum Collector Current

vs Duty Cycle
500
2.1
V CE = 2 V
TJ = -40C to 105C
TJ = -40C to 105C
450
400
Output Current mA
Maximum VCE(sat) Voltage V
1.9
1.7
1.5
Maximum
1.3
350
300
250
Minimum
200
1.1
150
Typical
0.9
100
200
300
400
500
Output Current mA
Figure 7. Maximum and Typical Saturated VCE

vs Output Current
100
250
350
450
550
650
Input Current A
Figure 8. Minimum Output Current vs Input Current

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7 Parameter Measurement Information

Open
Open
VCE
ICEX
ICEX
Open
VI
Figure 9. ICEX Test Circuit

Open
II(off)
Figure 10. ICEX Test Circuit

Open
VCE
II(on)
IC
Open
VI
Figure 11. II(off) Test Circuit
Figure 12. II Test Circuit
II is fixed for measuring VCE(sat), variable for measuring hFE.

Open
hFE =
II
VCE
Open
IC
II
Figure 13. hFE, VCE(sat) Test Circuit
10
VCE
IC
VI(on)
VCE
IC
Figure 14. VI(on) Test Circuit

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Parameter Measurement Information (continued)

VR
IR
VF
IF
Open
Open
Figure 15. IR Test Circuit
Figure 16. VF Test Circuit
Figure 17. Propagation Delay-Time Waveforms
200 W
10 ns
5 ns
90%
1.5 V
Input
VIH
(see Note C)
90%
1.5 V
10%
10%
0V
40 s
VOH
Output
VOL
VOLTAGE WAVEFORMS
The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 .
CL includes probe and jig capacitance.
For testing the ULN2003A device, ULN2003AI device, and ULQ2003A devices, VIH = 3 V; for the ULN2002A device,
VIH = 13 V; for the ULN2004A and the ULQ2004A devices, VIH = 8 V.
Figure 18. Latch-Up Test Circuit and Voltage Waveforms
11

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8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The ULN2003A device comprises seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULN2003A device has a series base resistor to each Darlington pair,
thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2003A
device offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and
LEDs. Applications requiring sink currents beyond the capability of a single output may be accommodated by
paralleling the outputs.
This device can operate over a wide temperature range (40C to 105C).
8.2 Functional Block Diagrams

All resistor values shown are nominal. The collector-emitter diode is a parasitic structure and should not be used
to conduct current. If the collectors go below GND, an external Schottky diode should be added to clamp
negative undershoots.
COM
7V
Output C
10.5 N
Input B
7.2 N
3 N
Figure 19. ULN2002A Block Diagram
COM
Output C
RB
2.7 N
Input B
Output C
RB
10.5 N
Input B
7.2 N
3 N
Figure 20. ULN2003A, ULQ2003A and ULN2003AI

Block Diagram
12
COM
7.2 N
3 N
Figure 21. ULN2004A and LQ2004A Block Diagram

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8.3 Feature Description

Each channel of the ULN2003A device consists of Darlington connected NPN transistors. This connection
creates the effect of a single transistor with a very high-current gain (2). This can be as high as 10,000 A/A at
certain currents. The very high allows for high-output current drive with a very low input current, essentially
equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-k resistor connected between the input and
base of the predriver Darlington NPN. The 7.2-k and 3-k resistors connected between the base and emitter of
each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
8.4 Device Functional Modes

8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2003A device is able to drive inductive loads and
suppress the kick-back voltage through the internal free-wheeling diodes.
8.4.2 Resistive Load Drive
When driving a resistive load, a pullup resistor is needed in order for ULN2003A device to sink current and for
there to be a logic high level. The COM pin can be left floating for these applications.
13

www.ti.com
9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

Typically, the ULN2003A device drives a high-voltage or high-current (or both) peripheral from an MCU or logic
device that cannot tolerate these conditions. This design is a common application of ULN2003A device, driving
inductive loads. This includes motors, solenoids and relays. Figure 22 shows a model for each load type.
9.2 Typical Application

ULN2003A
3.3-V Logic
3.3-V Logic
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
VSUP
3.3-V Logic
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
COM
VSUP
Figure 22. ULN2003A Device as Inductive Load Driver

9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
14
EXAMPLE VALUE
GPIO voltage
3.3 V or 5 V
Coil supply voltage
12 V to 48 V
Number of channels
Output current (RCOIL)
20 mA to 300 mA per channel
Duty cycle
100%

www.ti.com
9.2.2 Detailed Design Procedure

When using ULN2003A device in a coil driving application, determine the following:
Input voltage range
Temperature range
Output and drive current
Power dissipation
9.2.2.1 Drive Current
The coil voltage (VSUP), coil resistance (RCOIL), and low-level output voltage (VCE(SAT) or VOL) determine the coil
current.
ICOIL = (VSUP VCE(SAT)) / RCOIL
(1)
9.2.2.2 Low-Level Output Voltage

The low-level output voltage (VOL) is the same as VCE(SAT) and can be determined by, Figure 1, Figure 2, or
Figure 7.
9.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 4 or Figure 5.
For a more accurate determination of number of coils possible, use the below equation to calculate ULN2003A
device on-chip power dissipation PD:
N
PD = VOLi ILi
i=1
where
N is the number of channels active together

VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(2)
To ensure reliability of ULN2003A device and the system, the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 3.
PD(MAX) =
(T
J(MAX)
- TA )
qJA
where
TJ(max) is the target maximum junction temperature

TA is the operating ambient temperature
RJA is the package junction to ambient thermal resistance
(3)
Limit the die junction temperature of the ULN2003A device to less than 125C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
15

www.ti.com
9.2.3 Application Curves
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-0.004
14
12
Output voltage - V
Output voltage - V
The characterization data shown in Figure 23 and Figure 24 were generated using the ULN2003A device driving
an OMRON G5NB relay and under the following conditions: VIN = 5 V, VSUP= 12 V, and RCOIL= 2.8 k.
8
6
4
2
0.004
0.008
Time (s)
0.012
0
-0.004
0.016
D001
Figure 23. Output Response With Activation of Coil

(Turnon)
16
10
0.004
0.008
Time (s)
0.012
0.016
D001
Figure 24. Output Response With De-activation of Coil

(Turnoff)

www.ti.com
9.3 System Examples

ULN2002A
VSS
16
16
15
15
14
14
13
13
5
12
11
10
12
11
10
Lam
Test
TTL
Output
Figure 25. P-MOS to Load

ULN2004A
ULQ2004A
VDD
P-MOS
Output
ULQ2003A
VCC
Figure 26. TTL to Load

VCC
ULQ2003A
16
16
15
15
14
14
13
13
12
12
11
11
10
10
RP
CMOS
Output
TTL
Output
Figure 27. Buffer for Higher Current Loads
Figure 28. Use of Pullup Resistors to Increase

Drive Current
17

www.ti.com
10 Power Supply Recommendations

This device does not need a power supply. However, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to ensure that the output voltage does not heavily exceed the COM pin
voltage. This discrepancy heavily forward biases the fly-back diodes and causes a large current to flow into
COM, potentially damaging the on-chip metal or over-heating the device.
11 Layout
11.1 Layout Guidelines
Thin traces can be used on the input due to the low-current logic that is typically used to drive ULN2003A device.
Take care to separate the input channels as much as possible, as to eliminate crosstalk. TI recommends thick
traces for the output to drive whatever high currents that may be needed. Wire thickness can be determined by
the current density of the trace material and desired drive current.
Because all of the channels currents return to a common emitter, it is best to size that trace width to be very
wide. Some applications require up to 2.5 A.
11.2 Layout Example
GND
1B
2B
1
2
16
15
1C
2C
3B
14
3C
4B
5B
13
12
4C
5C
6B
5
6
11
6C
7B
7
8
10
9
7C
VCOM
Figure 29. Package Layout
18

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
SN7546x Darlington Transistor Arrays, SLRS023
12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ULN2002A
Click here
Click here
Click here
Click here
Click here
ULN2003A
Click here
Click here
Click here
Click here
Click here
ULN2003AI
Click here
Click here
Click here
Click here
Click here
ULN2004A
Click here
Click here
Click here
Click here
Click here
ULQ2003A
Click here
Click here
Click here
Click here
Click here
ULQ2004A
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
19
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
ULN2001AD
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
ULN2001ADR
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
ULN2001AN
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
ULN2002AD
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
ULN2002AN
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-20 to 70
ULN2002AN
ULN2002ANE4
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-20 to 70
ULN2002AN
ULN2003AD
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADE4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADG4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADR
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADRE4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADRG3
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ADRG4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003AID
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIDE4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIDG4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIDR
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIDRE4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIDRG4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
Addendum-Page 1
Samples
www.ti.com
5-May-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
ULN2003AIN
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU | CU SN
N / A for Pkg Type
-40 to 105
ULN2003AIN
ULN2003AINE4
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
ULN2003AIN
ULN2003AINSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
ULN2003AI
ULN2003AIPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
UN2003AI
ULN2003AIPWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
UN2003AI
ULN2003AIPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
UN2003AI
ULN2003AIPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 105
UN2003AI
ULN2003AIPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
UN2003AI
TBD
Call TI
Call TI
-55 to 125
25
Pb-Free
(RoHS)
CU NIPDAU | CU SN
N / A for Pkg Type
-20 to 70
ULN2003AN
ULN2003AJ
OBSOLETE
CDIP
16
ULN2003AN
ACTIVE
PDIP
16
ULN2003ANE3
PREVIEW
PDIP
16
TBD
Call TI
Call TI
-20 to 70
ULN2003AN
ULN2003ANE4
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-20 to 70
ULN2003AN
ULN2003ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ANSRE4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003ANSRG4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2003A
ULN2003APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
UN2003A
ULN2003APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
UN2003A
ULN2003APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-20 to 70
UN2003A
ULN2003APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
UN2003A
Addendum-Page 2
Samples
www.ti.com
5-May-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
ULN2004AD
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004ADE4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004ADG4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004ADR
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004ADRE4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004ADRG4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULN2004AN
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-20 to 70
ULN2004AN
ULN2004ANE4
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-20 to 70
ULN2004AN
ULN2004ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-20 to 70
ULN2004A
ULQ2003AD
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ULQ2003A
ULQ2003ADG4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULQ2003ADR
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULQ2003ADRG4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULQ2003AN
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
ULQ2003A
ULQ2004AD
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ULQ2004A
ULQ2004ADG4
ACTIVE
SOIC
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULQ2004ADR
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULQ2004ADRG4
ACTIVE
SOIC
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 3
ULQ2003A
-40 to 85
ULQ2003A
ULQ2003A
ULQ2004A
-40 to 85
ULQ2004A
ULQ2004A
Samples
www.ti.com
5-May-2015
Orderable Device
Status
(1)
ULQ2004AN
ACTIVE

Drawing
Qty
PDIP
16
25
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Op Temp (C)
Device Marking
(4/5)
-40 to 85
ULQ2004AN
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ULQ2003A, ULQ2004A :
Addendum-Page 4
Samples
www.ti.com
5-May-2015
Automotive: ULQ2003A-Q1, ULQ2004A-Q1

NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 5
PACKAGE MATERIALS INFORMATION

www.ti.com
20-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins

Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ULN2003ADR
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003ADR
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003ADRG3
SOIC
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003ADRG4
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003AIDR
SOIC
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003AIDRG4
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULN2003AIPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2003AIPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2003AIPWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2003APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2003APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2003APWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ULN2004ADR
SOIC
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
ULN2004ADRG4
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULN2004ADRG4
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULQ2003ADR
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
ULQ2003ADRG4
SOIC
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com
20-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ULN2003ADR
SOIC
16
2500
333.2
345.9
28.6
ULN2003ADR
SOIC
16
2500
367.0
367.0
38.0
ULN2003ADRG3
SOIC
16
2500
364.0
364.0
27.0
ULN2003ADRG4
SOIC
16
2500
333.2
345.9
28.6
ULN2003AIDR
SOIC
16
2500
364.0
364.0
27.0
ULN2003AIDRG4
SOIC
16
2500
333.2
345.9
28.6
ULN2003AIPWR
TSSOP
PW
16
2000
364.0
364.0
27.0
ULN2003AIPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
ULN2003AIPWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
ULN2003APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
ULN2003APWR
TSSOP
PW
16
2000
364.0
364.0
27.0
ULN2003APWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
ULN2004ADR
SOIC
16
2500
364.0
364.0
27.0
ULN2004ADRG4
SOIC
16
2500
333.2
345.9
28.6
ULN2004ADRG4
SOIC
16
2500
367.0
367.0
38.0
ULQ2003ADR
SOIC
16
2500
333.2
345.9
28.6
ULQ2003ADRG4
SOIC
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
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ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays

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ULN2002A, ULN2003A, ULN2003AI