Appendix B

Page 1 PIN ASSIGNMENT (TOP VIEWS)

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS

See page 3

See page 3

See page 7

See page 14

See page 9

See page 16

See page 10

TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).

Appendix B

Page 2

You can see more detailed versions of the following data sheets as PDF files at:

http://www2.eng.cam.ac.uk/~dmh/ptiialab/3B2

For further information and data sheets, point your browser at:
http://focus.ti.com/docs/logic/logichomepage.jhtml

TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).

Page 3

MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04 MM54C10 MM74C10 MM54C20 MM74C20

February 1988

Absolute Maximum Ratings

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 3V to VCC a 0 3V Voltage at Any Pin Operating Temperature Range 54C 74C Storage Temperature Range
b 55 C to a 125 C b 40 C to a 85 C b 65 C to a 150 C

Operating VCC Range Maximum VCC Voltage Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (Soldering 10 seconds)

3 0V to 15V 18V 700 mW 500 mW 300 C

MM54C00 MM54C02 MM54C04 MM54C10 MM54C20

MM74C00 Quad 2-Input NAND Gate MM74C02 Quad 2-Input NOR Gate MM74C04 Hex Inverter MM74C10 Triple 3-Input NAND Gate MM74C20 Dual 4-Input NAND Gate
Features
Y Y Y Y Y

DC Electrical Characteristics
Min Max limits apply across the guaranteed temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) Logical 1 Input Voltage VCC e 5 0V VCC e 10V Logical 0 Input Voltage VCC e 5 0V VCC e 10V Logical 1 Output Voltage VCC e 5 0V IO e b10 mA VCC e 10V IO e b10 mA Logical 0 Output Voltage VCC e 5 0V IO e 10 mA VCC e 10V IO e 10 mA Logical 1 Input Current Logical 0 Input Current Supply Current VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V 54C VCC e 4 5V 74C VCC e 4 75V Logical 0 Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V Logical 1 Output Voltage 54C VCC e 4 5V IO e b10 mA 74C VCC e 4 75V IO e b10 mA Logical 0 Output Voltage 54C VCC e 4 5V IO e 10 mA 74C VCC e 4 75V IO e 10 mA CMOS TO LOW POWER VIN(1) VIN(0) VOUT(1) VOUT(0) Logical 1 Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V Logical 0 Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V Logical 1 Output Voltage 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA Logical 0 Output Voltage 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA OUTPUT DRIVE (see 54C 74C Family Characteristics Data Sheet) TA e 25 C (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC e 5 0V VIN(0) e 0V VOUT e 0V VCC e 10V VIN(0) e 0V VOUT e 0V VCC e 5 0V VIN(1) e 5 0V VOUT e VCC VCC e 10V VIN(1) e 10V VOUT e VCC 2
b 1 75 b8 0 b1 0

Parameter

Conditions

Min

Typ

Max

Units

General Description
These logic gates employ complementary MOS (CMOS) to achieve wide power supply operating range low power consumption high noise immunity and symmetric controlled rise and fall times With features such as this the 54C 74C logic family is close to ideal for use in digital systems Function and pin out compatibility with series 54 74 devices minimizes design time for those designers already familiar with the standard 54 74 logic family All inputs are protected from damage due to static discharge by diode clamps to VCC and GND

Wide supply voltage range Guaranteed noise margin High noise immunity Low power consumption Low power TTL compatibility

3V to 15V 1V 0 45 VCC (typ ) 10 nW package (typ ) Fan out of 2 driving 74L

35 80 15 20 45 90 05 10 0 005
b 0 005

V V V V V V V V mA mA 15 mA V V 08 08 V V V V 04 04 V V

Connection Diagrams
Dual-In-Line Packages MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04

10

0 01 VCC b 1 5 VCC b 1 5

LOW POWER TO CMOS Logical 1 Input Voltage

44 44

TL F 58771

TL F 58772

TL F 58773

Top View Order Number MM54C00 or MM74C00 MM54C10 MM74C10

Top View Order Number MM54C02 or MM74C02

Top View Order Number MM54C04 or MM74C04 MM54C20 MM74C20

40 40 10 10 24 24 04 04

V V V V V V V V

TL F 58774

TL F 58775

Top View Order Number MM54C10 or MM74C10

Top View Order Number MM54C20 or MM74C20

mA mA mA mA

1 75 80

C1995 National Semiconductor Corporation

TL F 5877

RRD-B30M115 Printed in U S A

Page 4

AC Electrical Characteristics
Symbol Parameter

TA e 25 C CL e 50 pF unless otherwise specified Conditions VCC e 5 0V VCC e 10V (Note 2) (Note 3) Per Gate or Inverter VCC e 5 0V VCC e 10V (Note 2) (Note 3) Per Gate VCC e 5 0V VCC e 10V (Note 2) (Note 3) Per Gate Min Typ Max Units

Typical Performance Characteristics

Propagation Delay vs Ambient Temperature MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04

(Continued) Propagation Delay Time vs Load Capacitance MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04

MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04 tpd0 tpd1 Propagation Delay Time to Logical 1 or 0 Input Capacitance Power Dissipation Capacitance 50 30 60 12 90 60 ns ns pF pF

Propagation Delay vs Ambient Temperature MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04

CIN CPD

MM54C10 MM74C10 tpd0 tpd1 Propagation Delay Time to Logical 1 or 0 Input Capacitance Power Dissipation Capacitance 60 35 70 18 100 70 ns ns pF pF

CIN CPD

MM54C20 MM74C20 tpd0 tpd1 Propagation Delay Time to Logical 1 or 0 Input Capacitance Power Dissipation Capacitance 70 40 9 30 115 80 ns ns pF pF Propagation Delay Time vs Load Capacitance MM54C10 MM74C10 Propagation Delay Time vs Load Capacitance MM54C20 MM74C20
TL F 5877 7

CIN CPD

AC Parameters are guaranteed by DC correlated testing Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits The table of Electrical Characteristics provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90

Typical Performance Characteristics

Power Dissipation vs Frequency MM54C00 MM74C00 MM54C02 MM74C02 MM54C04 MM74C04
TL F 5877 8 TL F 5877 9

Gate Transfer Characteristics

Guaranteed Noise Margin Over Temperature vs VCC

Switching Time Waveforms and AC Test Circuit

CMOS to CMOS

TL F 5877 11 TL F 58776

TL F 5877 10

Note Delays measured with input tr tf s 20 ns

Page 5

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SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

Page 10
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1988, Texas Instruments Incorporated

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

Page 11
POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

Page 12
6

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

Page 13

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

POST OFFICE BOX 655303

x DALLAS, TEXAS 75265

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