Ds893 Virtex Ultrascale Data Sheet

Virtex UltraScale FPGAs Data Sheet:
DC and AC Switching Characteristics

DS893 (v1.2) July 27, 2015
Advance Product Specification
Summary
The Xilinx Virtex UltraScale FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the
highest performance. The -1L devices are screened for lower maximum static power. The speed
specification of a -1L device is the same as the -1 speed grade.
DC and AC characteristics are specified in commercial, extended, and industrial temperature ranges.
Except the operating temperature range or unless otherwise noted, all the DC and AC electrical
parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed
grade industrial device are the same as for a -1 speed grade commercial device). However, only selected
speed grades and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications are representative of worst-case conditions.
The parameters included are common to popular designs and typical applications.
This data sheet, part of an overall set of documentation on the UltraScale architecture-based devices, is
available on the Xilinx website at www.xilinx.com/ultrascale.
DC Characteristics
Table 1: Absolute Maximum Ratings(1)
Symbol
Description
Min
Max
Units
FPGA Logic
VCCINT
Internal supply voltage
0.500
1.100
VCCINT_IO(2)
Internal supply voltage for the I/O banks
0.500
1.100
VCCAUX
Auxiliary supply voltage
0.500
2.000
VCCBRAM
Supply voltage for the block RAM memories
0.500
1.100
Output drivers supply voltage for HR I/O banks
0.500
3.400
Output drivers supply voltage for HP I/O banks
0.500
2.000
VCCAUX_IO(3)
Auxiliary supply voltage for the I/O banks
0.500
2.000
VREF
Input reference voltage
0.500
2.000
I/O input voltage for HR I/O banks(5)
0.400
VCCO + 0.550
I/O input voltage for HP I/O banks
0.550
VCCO + 0.550
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O
standards except TMDS_33(8)
0.400
2.625
Key memory battery backup supply
0.500
2.000
VCCO
VIN(4)(6)(7)
VBATT
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Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings(1) (Contd)
Symbol
Description
Min
Max
Units
IDC
Available output current at the pad
20
20
mA
IRMS
Available RMS output current at the pad
20
20
mA
GTH or GTY Transceiver

VMGTAVCC
Analog supply voltage for the GTH or GTY transmitter and

receiver circuits
0.500
1.100
VMGTAVTT

receiver termination circuits
0.500
1.320
VMGTVCCAUX
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTH or
GTY transceivers
0.500
1.935
VMGTREFCLK
GTH or GTY transceiver reference clock absolute input voltage
0.500
1.320
VMGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the

GTH or GTY transceiver column
0.500
1.320
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input

voltage
0.500
1.260
IDCIN-FLOAT
DC input current for receiver input pins DC coupled RX

termination = floating
10
mA
IDCIN-MGTAVTT

termination = VMGTAVTT
0(9)
mA
IDCIN-GND

termination = GND
0(9)
mA
IDCIN-PROG

termination = Programmable
0(9)
mA
IDCOUT-FLOAT
DC output current for transmitter pins DC coupled RX

termination = floating
10
mA
IDCOUT-MGTAVTT
DC output current for transmitter pins DC coupled RX

termination = VMGTAVTT
mA
System Monitor
VCCADC
System Monitor supply relative to GNDADC
0.500
2.000
VREFP
System Monitor reference input relative to GNDADC
0.500
2.000
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Table 1: Absolute Maximum Ratings(1) (Contd)
Symbol
Description
Min
Max
Units
65
150
260
125
Temperature
TSTG
Storage temperature (ambient)
TSOL
Maximum soldering
Tj
Maximum junction
temperature(10)
temperature(10)
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might
affect device reliability.
2. VCCINT_IO must be connected to VCCINT.
3. VCCAUX_IO must be connected to VCCAUX.
4. The lower absolute voltage specification always applies.
5. If VCCO is 3.3V, the maximum voltage is 3.4V.
6. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
7. The maximum limit applied to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and
Table 5.
8. See Table 12 for TMDS_33 specifications.
9. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH Transceiver
User Guide (UG576) or the UltraScale Architecture GTY Transceiver User Guide (UG578)
10. For soldering guidelines and thermal considerations, see the Kintex UltraScale and Virtex UltraScale FPGAs Packaging and
Pinout Specifications (UG575).
Table 2: Recommended Operating Conditions(1)(2)

Symbol
Description
Min
Typ
Max
Units
Internal supply voltage
0.922
0.950
0.979
For -3 (1.0V only) devices: Internal supply voltage
0.970
1.000
1.030
Internal supply voltage for the I/O banks
0.922
0.950
0.979
For -3 (1.0V only) devices: internal supply voltage for the

I/O banks
0.970
1.000
1.030
Block RAM supply voltage
0.922
0.950
0.979
For -3 (1.0V only) devices: block RAM supply voltage
0.970
1.000
1.030
Auxiliary supply voltage
1.746
1.800
1.854
Supply voltage for HR I/O banks
1.140
3.400
Supply voltage for HP I/O banks
0.950
1.890
Auxiliary I/O supply voltage
1.746
1.800
1.854
0.200
VCCO + 0.200
FPGA Logic
VCCINT
VCCINT_IO
(3)
VCCBRAM
VCCAUX
VCCO(4)(5)
VCCAUX_IO
(6)
I/O input voltage

VIN(7)
I/O input voltage (when VCCO = 3.3V) for VREF and

differential I/O standards except TMDS_33(8).
0.400
2.625
IIN(9)
Maximum current through any pin in a powered or

unpowered bank when forward biasing the clamp diode.
10.000
mA
VBATT(10)
Battery voltage
1.000
1.890
GTH or GTY Transceiver

VMGTAVCC(11)
Analog supply voltage for the GTH or GTY transceiver
0.970
1.000
1.030
VMGTAVTT(11)

receiver termination circuits
1.170
1.200
1.230
VMGTVCCAUX(11)
Auxiliary analog QPLL voltage supply for the transceivers
1.750
1.800
1.850
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Table 2: Recommended Operating Conditions(1)(2) (Contd)
Symbol
Description
Min
Typ
Max
Units
VMGTAVTTRCAL(11)
Analog supply voltage for the resistor calibration circuit of

the GTH or GTY transceiver column
1.170
1.200
1.230
VCCADC
SYSMON supply relative to GNDADC
1.746
1.800
1.854
VREFP
Externally supplied reference voltage
1.200
1.250
1.300
Junction temperature operating range for commercial (C)

temperature devices
85
Junction temperature operating range for extended (E)

temperature devices
100
Junction temperature operating range for industrial (I)

temperature devices
40
100
SYSMON
Temperature
Tj
Notes:
1.
2.
3.
4.
All voltages are relative to ground.

For the design of the power distribution system consult UltraScale Architecture PCB Design Guide (UG583).
VCCINT_IO must be connected to VCCINT.
For VCCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After
configuration, data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only) at 5%, and 3.3V (HR I/O only) at
+3/5%.
6. VCCAUX_IO must be connected to VCCAUX.
7. The lower absolute voltage specification always applies.
8. See Table 12 for TMDS_33 specifications.
9. A total of 200 mA per 52-pin bank should not be exceeded.
10. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
11. Each voltage listed requires filtering as described in UltraScale Architecture GTH Transceiver User Guide (UG576) or
UltraScale Architecture GTY Transceiver User Guide (UG578).
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Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Typ(1)
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration

data might be lost)
0.82
VDRAUX
Data retention VCCAUX voltage (below which configuration

data might be lost)
1.50
IREF
VREF leakage current per pin
15
IL
Input or output leakage current per pin (sample-tested)
15(2)
Die input capacitance at the pad (HP I/O)
3.75
pF
Die input capacitance at the pad (HR I/O)
7.00
pF
Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V
75
175
50
169
60
678
30
450
10
262
Pad pull-down (when selected) at VIN = 3.3V
60
190
Pad pull-down (when selected) at VIN = 1.8V
29
685
CIN(3)
IRPU
IRPD
ICCADC
Analog supply current, analog circuits in powered up state
19.2
mA
IBATT(4)
Battery supply current
150
nA
Calibrated programmable on-die termination (DCI) in HP I/O banks(6) (measured per JEDEC specification)
R(7)
Thevenin equivalent resistance of programmable input

termination to VCCO/2 where ODT = RTT_40
10%(5)
40
+10%(5)

10%(5)
48
+10%(5)

10%(5)
60
+10%(5)
Programmable input termination to VCCO where

ODT = RTT_40
10%(5)
40
+10%(5)

ODT = RTT_48
10%(5)
48
+10%(5)

ODT = RTT_60
10%(5)
60
+10%(5)

ODT = RTT_120
10%(5)
120
+10%(5)

ODT = RTT_240
10%(5)
240
+10%(5)
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Table 3: DC Characteristics Over Recommended Operating Conditions (Contd)
Symbol
Description
Min
Typ(1)
Max
Units
Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)
R(7)

50%
40
50%

50%
48
50%

50%
60
50%

ODT = RTT_40
50%
40
50%

ODT = RTT_48
50%
48
50%

ODT = RTT_60
50%
60
50%

ODT = RTT_120
50%
120
50%

ODT = RTT_240
50%
240
50%
Uncalibrated programmable on-die termination in HR I/O banks (measured per JEDEC specification)
R(7)

50%
40
50%

50%
48
50%

50%
60
50%
50% VCCO
VCCO x
0.49
VCCO x
0.50
VCCO x
0.51
70% VCCO
VCCO x
0.69
VCCO x
0.70
VCCO x
0.71
Internal VREF
Differential
termination
Programmable differential termination (TERM_100)
100
Temperature diode ideality factor
1.002
Temperature diode series resistance
Notes:
1.
2.
3.
4.
5.
6.
7.
Typical values are specified at nominal voltage, 25C.

For HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 A.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25C.
If VRP resides at a different bank (DCI cascade), the range increases to 15%.
VRP resistor tolerance is (240 1%).
On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
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Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)
AC Voltage Overshoot % of UI at 40C to 100C AC Voltage Undershoot % of UI at 40C to 100C
VCCO + 0.30
100%
0.30
100%
VCCO + 0.35
100%
0.35
70.00%
VCCO + 0.40
100%
0.40
27.00%
VCCO + 0.45
100%
0.45
10.00%
VCCO + 0.50
85.00%
0.50
5.00%
VCCO + 0.55
70.00%
0.55
2.10%
VCCO + 0.60
46.60%
0.60
1.50%
VCCO + 0.65
21.20%
0.65
1.10%
VCCO + 0.70
9.75%
0.70
0.60%
VCCO + 0.75
4.55%
0.75
0.45%
VCCO + 0.80
2.15%
0.80
0.20%
VCCO + 0.85
1.00%
0.85
0.10%
VCCO + 0.90
0.50%
0.90
0.05%
Notes:
1.
A total of 200 mA per bank should not be exceeded.
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2)
AC Voltage Overshoot % of UI at 40C to 100C AC Voltage Undershoot % of UI at 40C to 100C
VCCO + 0.05
100%
0.05
100%
VCCO + 0.10
100%
0.10
100%
VCCO + 0.15
100%
0.15
100%
VCCO + 0.20
100%
0.20
100%
VCCO + 0.25
100%
0.25
100%
VCCO + 0.30
100%
0.30
100%
VCCO + 0.35
92.00%
0.35
92.00%
VCCO + 0.40
70.00%
0.40
40.00%
VCCO + 0.45
30.00%
0.45
15.00%
VCCO + 0.50
15.00%
0.50
10.00%
VCCO + 0.55
10.00%
0.55
4.00%
VCCO + 0.60
8.00%
0.60
0.00%
VCCO + 0.65
6.00%
0.65
0.00%
VCCO + 0.70
4.00%
0.70
0.00%
VCCO + 0.75
2.00%
0.75
0.00%
VCCO + 0.80
2.00%
0.80
0.00%
VCCO + 0.85
2.00%
0.85
0.00%
Notes:
1.
2.
A total of 200 mA per bank should not be exceeded.

For UI smaller than 20 s.
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Table 6: Typical Quiescent Supply Current(1)(2)(3)
Speed Grade
Symbol
ICCINTQ
ICCINT_IOQ
ICCOQ
ICCAUXQ
ICCAUX_IOQ
Description
Device
Quiescent VCCINT supply current
Quiescent current for VCCINT_IO supply
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Quiescent VCCAUX_IO supply current
DS893 (v1.2) July 27, 2015

1.0V
0.95V
Units
-3
-2
-1/-1L
XCVU065
1581
1437
1437
mA
XCVU080
2309
2100
2100
mA
XCVU095
2309
2100
2100
mA
XCVU125
3161
2875
2875
mA
XCVU160
4742
4312
4312
mA
XCVU190
4742
4312
4312
mA
XCVU440
7988
7264
7264
mA
XCVU065
100
89
89
mA
XCVU080
161
143
143
mA
XCVU095
161
143
143
mA
XCVU125
200
178
178
mA
XCVU160
299
266
266
mA
XCVU190
299
266
266
mA
XCVU440
299
266
266
mA
XCVU065
mA
XCVU080
mA
XCVU095
mA
XCVU125
mA
XCVU160
mA
XCVU190
mA
XCVU440
mA
XCVU065
187
187
187
mA
XCVU080
273
273
273
mA
XCVU095
273
273
273
mA
XCVU125
373
373
373
mA
XCVU160
560
560
560
mA
XCVU190
560
560
560
mA
XCVU440
1009
1009
1009
mA
XCVU065
74
74
74
mA
XCVU080
124
124
124
mA
XCVU095
124
124
124
mA
XCVU125
148
148
148
mA
XCVU160
223
223
223
mA
XCVU190
223
223
223
mA
XCVU440
223
223
223
mA
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Table 6: Typical Quiescent Supply Current(1)(2)(3) (Contd)
Speed Grade
Symbol
ICCBRAMQ
Description
Quiescent VCCBRAM supply current
Device
1.0V
0.95V
Units
-3
-2
-1/-1L
XCVU065
89
81
81
mA
XCVU080
122
111
111
mA
XCVU095
122
111
111
mA
XCVU125
178
162
162
mA
XCVU160
267
243
243
mA
XCVU190
267
243
243
mA
XCVU440
178
162
162
mA
Notes:
1.
2.
3.
Typical values are specified at nominal voltage, 85C junction temperatures (Tj) with single-ended SelectIO resources.
Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins
are 3-state and floating.
Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power
consumption for conditions other than those specified.
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Power-On/Off Power Supply Sequencing

The recommended power-on sequence is VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to
achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended
power-off sequence is the reverse of the power-on sequence. If VCCINT/VCCINT_IO and VCCBRAM have the
same recommended voltage levels, they can be powered by the same supply and ramped simultaneously.
VCCINT_IO must be connected to VCCINT. If VCCAUX/VCCAUX_IO and VCCO have the same recommended
voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO
must be connected together.
The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceivers
is VCCINT, VMGTAVCC, V MGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for
VMGTVCCAUX . Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off
sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from V MGTAVTT can be higher than
specifications during power-up and power-down.
When the current minimums are met, the device powers on after all five supplies have passed through
their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied.
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10

Table 7 shows the minimum current, in addition to I CCQ, that are required by Virtex UltraScale FPGAs for
proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the
device powers on after all four supplies have passed through their power-on reset threshold voltages. The
device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx
Power Estimator (XPE) tools to estimate current drain on these supplies.
Table 7: Power-on Current by Device
Device
ICCINTMIN + ICCINT_IOMIN
ICCO
ICCAUXMIN + ICCAUX_IOMIN
ICCBRAMMIN
Units
XCVU065
ICCINTQ + ICCINT_IOQ + 2199
ICCOQ + 40
ICCAUXQ + ICCAUX_IOQ + 267
ICCBRAMQ + 100
mA
XCVU080
ICCOQ + 40
ICCBRAMQ + 125
mA
XCVU095
ICCOQ + 40
ICCBRAMQ + 150
mA
XCVU125
ICCOQ + 54
ICCBRAMQ + 200
mA
XCVU160
ICCOQ + 69
ICCBRAMQ + 259
mA
XCVU190
ICCOQ + 80
ICCBRAMQ + 300
mA
XCVU440
ICCINTQ + ICCINT_IOQ + 15549 ICCOQ + 189 ICCAUXQ + ICCAUX_IOQ + 1885
ICCBRAMQ + 707
mA
Table 8 shows the power supply ramp time.

Table 8: Power Supply Ramp Time
Symbol
Description
Min
Max
Units
TVCCINT
Ramp time from GND to 95% of VCCINT
0.2
40
ms
TVCCINT_IO
Ramp time from GND to 95% of VCCINT_IO
0.2
40
ms
TVCCO
Ramp time from GND to 95% of VCCO
0.2
40
ms
TVCCAUX
Ramp time from GND to 95% of VCCAUX
0.2
40
ms
TVCCBRAM
Ramp time from GND to 95% of VCCBRAM
0.2
40
ms
TMGTAVCC
Ramp time from GND to 95% of VMGTAVCC
0.2
40
ms
TMGTAVTT
Ramp time from GND to 95% of VMGTAVTT
0.2
40
ms
TMGTVCCAUX
Ramp time from GND to 95% of VMGTVCCAUX
0.2
40
ms
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11
DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for I OL and I OH are guaranteed over the
recommended operating conditions at the VOL and VOH test points. Only selected standards are tested.
These are chosen to ensure that all standards meet their specifications. The selected standards are tested
at a minimum VCCO with the respective V OL and VOH voltage levels shown. Other standards are sample
tested.
Table 9: SelectIO DC Input and Output Levels For HR I/O Banks(1)(2)
I/O
Standard
VIL
V, Min
V, Max
VIH
V, Min
V, Max
VOL
VOH
IOL
IOH
V, Max
V, Min
mA
mA
HSTL_I
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
8.0
8.0
HSTL_I_18
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
8.0
8.0
HSTL_II
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
16.0
16.0
HSTL_II_18
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
16.0
16.0
HSUL_12
0.300 VREF 0.130 VREF + 0.130 VCCO + 0.300
20% VCCO
80% VCCO
0.1
0.1
LVCMOS12
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.400
VCCO 0.400
Note 3
Note 3
LVCMOS15
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
Note 4
Note 4
LVCMOS18
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
Note 4
Note 4
LVCMOS25
0.300
0.700
1.700
VCCO + 0.300
0.400
VCCO 0.400
Note 4
Note 4
LVCMOS33
0.300
0.800
2.000
3.400
0.400
VCCO 0.400
Note 4
Note 4
LVTTL
0.300
0.800
2.000
3.400
0.400
2.400
Note 4
Note 4
SSTL12
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 0.150 VCCO/2 + 0.150
14.25
14.25
SSTL135
13.0
13.0
SSTL135_R
8.9
8.9
SSTL15
13.0
13.0
SSTL15_R
8.9
8.9
SSTL18_I
8.0
8.0
SSTL18_II
13.4
13.4
Notes:
1.
2.
3.
4.
Tested according to relevant specifications.

Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
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Table 10: SelectIO DC Input and Output Levels for HP I/O Banks(1)(2)(3)
I/O
Standard
VIH
VIL
V, Min
V, Max
V, Min
V, Max
VOL
VOH
IOL
IOH
V, Max
V, Min
mA
mA
HSTL_I
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
5.8
5.8
HSTL_I_12
0.300 VREF 0.080 VREF + 0.080 VCCO + 0.300
25% VCCO
75% VCCO
4.1
4.1
HSTL_I_18
0.300 VREF 0.100 VREF + 0.100 VCCO + 0.300
0.400
VCCO 0.400
6.2
6.2
HSUL_12
0.300 VREF 0.130 VREF + 0.130 VCCO + 0.300
20% VCCO
80% VCCO
0.1
0.1
LVCMOS12
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.400
VCCO 0.400
Note 4
Note 4
LVCMOS15
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
Note 5
Note 5
LVCMOS18
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
Note 5
Note 5
LVDCI_15
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
7.0
7.0
LVDCI_18
0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO 0.450
7.0
7.0
SSTL12
8.0
8.0
SSTL135
9.0
9.0
SSTL15
10.0
10.0
SSTL18_I
7.0
7.0
Notes:
1.
2.
3.
4.
5.

POD10 and POD12 DC input and output levels are shown in Table 11, Table 16, and Table 17.
Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.
Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.
Table 11: DC Input Levels for Single-ended POD10 and POD12 I/O Standards(1)(2)
I/O
Standard
VIL
VIH
V, Min
V, Max
V, Min
V, Max
POD10
0.300
VREF 0.068
VREF + 0.068
VCCO + 0.300
POD12
0.300
VREF 0.068
VREF + 0.068
VCCO + 0.300
Notes:
1.
2.

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Table 12: Differential SelectIO DC Input and Output Levels
VICM (V)(1)
I/O
Standard
Typ
Max
Min
VOCM(V)(3)
Typ Max
VOD(V)(4)
Min
Typ
Max
1.250
Note 5
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600
1.000
1.200
1.485
0.300 0.450 0.600
SUB_LVDS
0.500 0.900 1.300 0.070
0.700
0.900
1.100
0.100 0.150 0.200
LVPECL
0.300 1.200 1.425 0.100 0.350 0.600
PPDS_25
0.200 0.900 VCCAUX 0.100 0.250 0.400
0.500
0.950
1.400
0.100 0.250 0.400
RSDS_25
0.300 0.900 1.500 0.100 0.350 0.600
1.000
1.200
1.485
0.100 0.350 0.600
SLVS_400_18
0.070 0.200 0.330 0.140
0.450
SLVS_400_25
0.070 0.200 0.330 0.140
0.450
TMDS_33
2.700 2.965 3.230 0.150 0.675 1.200 VCCO 0.405 VCCO 0.300 VCCO 0.190 0.400 0.600 0.800
BLVDS_25
Min
VID(V)(2)
0.300 1.200 1.425 0.100
Min
Typ
Max
Notes:
1.
2.
3.
4.
5.
6.
7.
VICM is the input common mode voltage.

VID is the input differential voltage (Q Q).
VOCM is the output common mode voltage.
VOD is the output differential voltage (Q Q).
VOD for BLVDS will vary significantly depending on topology and loading.
LVDS_25 is specified in Table 18.
LVDS is specified in Table 19.
Table 13: Complementary Differential SelectIO DC Input and Output Levels for HR I/O Banks
I/O Standard
VICM (V)(1)
Min
Typ
Max
VID (V)(2)
Min
VOL (V)(3)
VOH (V)(4)
IOL
IOH
Max
Max
Min
mA
mA
DIFF_HSTL_I
0.300 0.750 1.125 0.100
0.400
VCCO 0.400
8.0
8.0
DIFF_HSTL_I_18
0.300 0.900 1.425 0.100
0.400
VCCO 0.400
8.0
8.0
DIFF_HSTL_II
0.300 0.750 1.125 0.100
0.400
VCCO 0.400
16.0
16.0
DIFF_HSTL_II_18
0.300 0.900 1.425 0.100
0.400
VCCO 0.400
16.0
16.0
DIFF_HSUL_12
0.300 0.600 0.850 0.100
20% VCCO
80% VCCO
0.1
0.1
DIFF_SSTL12
0.300 0.600 0.850 0.100
(VCCO/2) 0.150 (VCCO/2) + 0.150
14.25
14.25
DIFF_SSTL135
0.300 0.675 1.000 0.100
(VCCO/2) 0.150 (VCCO/2) + 0.150
13.0
13.0
DIFF_SSTL135_R
0.300 0.675 1.000 0.100
(VCCO/2) 0.150 (VCCO/2) + 0.150
8.9
8.9
DIFF_SSTL15
0.300 0.750 1.125 0.100
(VCCO/2) 0.175 (VCCO/2) + 0.175
13.0
13.0
DIFF_SSTL15_R
0.300 0.750 1.125 0.100
(VCCO/2) 0.175 (VCCO/2) + 0.175
8.9
8.9
DIFF_SSTL18_I
0.300 0.900 1.425 0.100
(VCCO/2) 0.470 (VCCO/2) + 0.470
8.0
8.0
DIFF_SSTL18_II
0.300 0.900 1.425 0.100
(VCCO/2) 0.600 (VCCO/2) + 0.600
13.4
13.4
Notes:
1.
2.
3.
4.

VID is the input differential voltage.
VOL is the single-ended low-output voltage.
VOH is the single-ended high-output voltage.
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Table 14: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks(1)
VOL (V)(4)
VOH (V)(5)
IOL
IOH
Max
Max
Min
mA
mA
VCCO/2 (VCCO/2) + 0.150 0.100
0.400
VCCO 0.400
5.8
5.8
VCCO/2
0.100
0.250 x VCCO
0.750 x VCCO
4.1
4.1
DIFF_HSTL_I_18
(VCCO/2) 0.175 VCCO/2 (VCCO/2) + 0.175 0.100
0.400
VCCO 0.400
6.2
6.2
DIFF_HSUL_12
(VCCO/2) 0.120 VCCO/2 (VCCO/2) + 0.120 0.100
20% VCCO
80% VCCO
0.1
0.1
DIFF_SSTL12
(VCCO/2) 0.150 VCCO/2 (VCCO/2) + 0.150 0.100
(VCCO/2) 0.150 (VCCO/2) + 0.150
8.0
8.0
DIFF_SSTL135
(VCCO/2) 0.150 VCCO/2 (VCCO/2) + 0.150 0.100
(VCCO/2) 0.150 (VCCO/2) + 0.150
9.0
9.0
DIFF_SSTL15
(VCCO/2) 0.175 VCCO/2 (VCCO/2) + 0.175 0.100
(VCCO/2) 0.175 (VCCO/2) + 0.175 10.0 10.0
DIFF_SSTL18_I
(VCCO/2) 0.175 VCCO/2 (VCCO/2) + 0.175 0.100
(VCCO/2) 0.470 (VCCO/2) + 0.470
I/O Standard
DIFF_HSTL_I
VICM (V)(2)
Min
0.680
DIFF_HSTL_I_12
0.400 x VCCO
Typ
VID (V)(3)
Max
0.600 x VCCO
Min
7.0
7.0
Notes:
1.
2.
3.
4.
5.
DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 15, Table 16, and Table 17.
VID is the input differential voltage.
VOL is the single-ended low-output voltage.
VOH is the single-ended high-output voltage.
Table 15: DC Input Levels for Differential POD10 and POD12 I/O Standards(1)(2)
I/O Standard
VICM (V)
VID (V)
Min
Typ
Max
Min
Max
DIFF_POD10
0.63
0.70
0.77
0.14
DIFF_POD12
0.76
0.84
0.92
0.16
Notes:
1.
2.

Table 16: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards(1)(2)
Symbol
Description
VOUT
Min
Typ
Max
Units
ROL
Pull-down resistance
VOM_DC (as described in Table 17)
36
40
44
ROH
Pull-up resistance
VOM_DC (as described in Table 17)
36
40
44
Notes:
1.
2.

Table 17: Table 16 Definitions for DC Output Levels for POD Standards
Symbol
VOM_DC
Description
DC output Mid measurement level (for IV curve linearity)
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LVDS DC Specifications (LVDS_25)

The LVDS_25 standard is available in the HR I/O banks. See the UltraScale Architecture SelectIO Resources
User Guide (UG571) for more information.
Table 18: LVDS_25 DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
2.375
2.500
2.625
247
350
600
mV
1.250
1.485
100
350
600(2)
mV
VCCO
Supply voltage
VODIFF(1)
Differential Output Voltage:

(Q Q), Q = High
(Q Q), Q = High
RT = 100 across Q and Q signals
VOCM(1)
Output Common-Mode Voltage
RT = 100 across Q and Q signals 1.000
VIDIFF
Differential Input Voltage:

(Q Q), Q = High
(Q Q), Q = High
VICM_DC(3)
Input Common-Mode Voltage (DC Coupling)
0.300
1.200
1.500
VICM_AC(4)
Input Common-Mode Voltage (AC Coupling)
0.600
1.100
Notes:
1.
2.
3.
4.
VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.

Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only
when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0,
EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
LVDS DC Specifications (LVDS)

The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User
Guide (UG571) for more information.
Table 19: LVDS DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
1.710
1.800
1.890
247
350
600
mV
1.250
1.425
100
350
600(2)
mV
VICM_DC(3) Input Common-Mode Voltage (DC Coupling)
0.300
1.200
1.425
VICM_AC(4)
0.600
1.100
VCCO
Supply voltage
VODIFF(1)
Differential Output Voltage

(Q Q), Q = High
(Q Q), Q = High
RT = 100 across Q and Q signals
VOCM(1)
Output Common-Mode Voltage
RT = 100 across Q and Q signals 1.000
VIDIFF
Differential Input Voltage

(Q Q), Q = High
(Q Q), Q = High
Input Common-Mode Voltage (AC Coupling)
Notes:
1.
2.
3.
4.
VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.

Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only
when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0,
EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
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AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the Vivado Design
Suite as outlined in Table 20.
Table 20: Speed Specification Version By Device
2015.2
1.16
Device
XCVU065, XCVU080, XCVU095, XCVU125, XCVU160, XCVU190, XCVU440
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as follows:

These specifications are based on simulations only and are typically available soon after device design
specifications are frozen. Although speed grades with this designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a better indication of the expected performance
of production silicon. The probability of under-reporting delays is greatly reduced as compared to
Advance data.
Product Specification
These specifications are released once enough production silicon of a particular device family member has
been characterized to provide full correlation between specifications and devices over numerous
production lots. There is no under-reporting of delays, and customers receive formal notification of any
subsequent changes. Typically, the slowest speed grades transition to production before faster speed
grades.
Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching
characteristics are representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static
timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all
Virtex UltraScale FPGAs.
Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to
another depends completely on the status of the fabrication process for each device. Table 21 correlates
the current status of the Virtex UltraScale FPGAs on a per speed grade basis.
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Table 21: Virtex UltraScale FPGAs Speed Grade Designations
Device

Advance
XCVU065
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU080
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU095
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU125
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU160
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU190
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
XCVU440
-3 (1.0V), -2 (0.95V), -1 (0.95V),

and -1L (0.95V)
Preliminary
Production
Production Silicon and Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed
specification is released with the correct label (Advance, Preliminary, Production). Any labeling
discrepancies are corrected in subsequent speed specification releases.
Table 22 lists the production released Virtex UltraScale FPGAs, speed grade, and the minimum
corresponding supported speed specification version and Vivado software revisions. The Vivado software
and speed specifications listed are the minimum releases required for production. All subsequent releases
of software and speed specifications are valid.
Table 22: Virtex UltraScale FPGAs Device Production Software and Speed Specification Release
Device
1.0V
-3E
0.95V
-2E, -2I
-1C, -1I, -1LI
XCVU065
XCVU080
XCVU095
XCVU125
XCVU160
XCVU190
XCVU440
Notes:
1.
Blank entries indicate a device and/or speed grade in Advance or Preliminary status.
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Performance Characteristics
This section provides the performance characteristics of some common functions and designs
implemented in Virtex UltraScale FPGAs. These values are subject to the same guidelines as the AC
Switching Characteristics, page 17. In each table, the I/O bank type is either high performance (HP) or high
range (HR).
Table 23: LVDS Component Mode Performance
Description
LVDS TX DDR (OSERDES 4:1, 8:1)

LVDS TX SDR (OSERDES 2:1, 4:1)
LVDS RX DDR (ISERDES 1:4, 1:8)(1)
LVDS RX SDR (ISERDES 1:2, 1:4)(1)
Speed Grade
I/O Bank
Type
1.0V
-3
-2E
-2I
-1/-1L
HP
1250
1250
1250
1250
Mb/s
HR
1250
1250
1250
1000
Mb/s
HP
625
625
625
625
Mb/s
HR
625
625
625
500
Mb/s
HP
1250
1250
1250
1250
Mb/s
HR
1250
1250
1250
1000
Mb/s
HP
625
625
625
625
Mb/s
HR
625
625
625
500
Mb/s
0.95V
Units
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
Table 24: LVDS Native Mode Performance(1)

Description
LVDS TX DDR (TX_BITSLICE 4:1, 8:1)

LVDS TX SDR (TX_BITSLICE 2:1, 4:1)
LVDS RX DDR (RX_BITSLICE 1:4, 1:8)(2)
LVDS RX SDR (RX_BITSLICE 1:2, 1:4)(2)
Speed Grade
I/O Bank
Type
1.0V
-3
-2E
-2I
-1/-1L
HP
1600
1600
1600
1400
HR
1250
1250
1250
1250
Mb/s
HP
800
800
800
700
Mb/s
HR
625
625
625
625
Mb/s
HP
1600
1600
1600
1400
Mb/s
HR
1250
1250
1250
1250
Mb/s
HP
800
800
800
700
Mb/s
HR
625
625
625
625
Mb/s
0.95V
Units
Mb/s
Notes:
1.
2.
Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
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Table 25: LVDS Native-Mode 1000BASE-X Support(1)
Speed Grade
Description
I/O Bank Type
1000BASE-X
HP
1.0V
0.95V
-3
-2E
-2I
-1/-1L
Yes
Yes
Yes
Yes
Notes:
1.
1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE
Std 802.3-2008).
Table 26 provides the maximum data rates for applicable memory standards using the Virtex UltraScale
FPGAs memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards
supported and detailed specifications. The final performance of the memory interface is determined
through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale
Architecture PCB Design Guide (UG583), electrical analysis, and characterization of the system.
Table 26: Maximum Physical Interface (PHY) Rate for Memory Interfaces
Memory
Standard
Speed Grade
I/O Bank Type
DRAM Type
1.0V
Single rank component

DDR4
HP
DDR3
HR
DDR3L
QDRII+
HP
Units
-3E
-2E
-2I
-1/-1L
2400
2400
2400
2133
Mb/s
1 rank
DIMM(1)(2)
2133
2133
2133
1866
Mb/s
2 rank
DIMM(1)(3)
1866
1866
1866
1600
Mb/s
4 rank
DIMM(1)(4)
1333
1333
1333
NA
Mb/s

HP
0.95V
2133
2133
2133
1866
Mb/s
1 rank
DIMM(1)(2)
1866
1866
1866
1600
Mb/s
2 rank
DIMM(1)(3)
1600
1600
1600
1333
Mb/s
4 rank
DIMM(1)(4)
1066
1066
1066
800
Mb/s
1333
1333
1333
1066
Mb/s
1866
1866
1866
1600
Mb/s
1 rank
DIMM(1)(2)
1600
1600
1600
1333
Mb/s
2 rank
DIMM(1)(3)
1333
1333
1333
1066
Mb/s
4 rank
DIMM(1)(4)
800
800
800
606
Mb/s
HR
1066
1066
1066
800
Mb/s
All
633
600
600
550
MHz
800(5)
800(5)
667(5)
MHz
1066
1066
933
MHz
QDRIV
HP
800(5)
RLDRAM III
HP
1066
Notes:
1.
2.
3.
4.
5.
Dual in-line memory module (DIMM) includes RDIMM, SODIMM, and UDIMM.
Includes: 1 rank 1 slot, DDP 2 rank.
Includes: 2 rank 1 slot, 1 rank 2 slot.
Includes: 2 rank 2 slot, 4 rank 1 slot.
These memory interface values are pending characterization.
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IOB Pad Input, Output, and 3-State

Table 27 (high-range IOB (HR)) and Table 28 (high-performance IOB (HP)) summarizes the values of
standard-specific data input delay adjustments, output delays terminating at pads (based on standard)
and 3-state delays.
TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The
delay varies depending on the capability of the SelectIO input buffer.
TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB
pad. The delay varies depending on the capability of the SelectIO output buffer.
TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB
pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output
buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than
TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. In HR I/O banks, the on-die termination
turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the INTERMDISABLE pin is used.
Table 27: IOB High Range (HR) Switching Characteristics

TINBUF_DELAY_PAD_I
I/O Standards
1.0V
TOUTBUF_DELAY_O_PAD
0.95V
1.0V
0.95V
TOUTBUF_DELAY_TD_PAD
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
BLVDS_25
0.46
0.58
0.64
1.25
1.37
1.62
1.27
1.40
1.66
ns
DIFF_HSTL_I_18_F
0.42
0.53
0.57
0.65
0.71
0.90
0.75
0.82
1.06
ns
DIFF_HSTL_I_18_S
0.42
0.53
0.57
0.77
0.83
1.02
0.89
0.94
1.16
ns
DIFF_HSTL_I_F
0.42
0.53
0.57
0.66
0.73
0.92
0.80
0.90
1.14
ns
DIFF_HSTL_I_S
0.42
0.53
0.57
0.71
0.77
0.96
0.85
0.98
1.23
ns
DIFF_HSTL_II_18_F
0.42
0.53
0.57
0.72
0.80
0.99
0.85
0.98
1.23
ns
DIFF_HSTL_II_18_S
0.42
0.53
0.57
0.77
0.83
1.03
0.90
1.03
1.28
ns
DIFF_HSTL_II_F
0.42
0.53
0.57
0.63
0.71
0.91
0.77
0.87
1.11
ns
DIFF_HSTL_II_S
0.42
0.53
0.57
0.74
0.80
0.99
0.91
0.96
1.20
ns
DIFF_HSUL_12_F
0.42
0.53
0.57
0.66
0.73
0.92
0.66
0.73
0.92
ns
DIFF_HSUL_12_S
0.42
0.53
0.57
0.75
0.82
1.01
0.75
0.82
1.01
ns
DIFF_SSTL12_F
0.42
0.53
0.57
0.63
0.70
0.89
0.72
0.81
1.02
ns
DIFF_SSTL12_S
0.42
0.53
0.57
0.97
1.04
1.26
0.97
1.04
1.26
ns
DIFF_SSTL135_F
0.42
0.53
0.57
0.63
0.70
0.88
0.76
0.87
1.09
ns
DIFF_SSTL135_S
0.42
0.53
0.57
0.71
0.77
0.96
0.87
0.94
1.18
ns
DIFF_SSTL135_R_F
0.42
0.53
0.57
0.65
0.72
0.91
0.76
0.84
1.06
ns
DIFF_SSTL135_R_S
0.42
0.53
0.57
0.74
0.80
1.00
0.88
0.93
1.17
ns
DIFF_SSTL15_F
0.42
0.53
0.57
0.59
0.66
0.85
0.72
0.82
1.05
ns
DIFF_SSTL15_S
0.42
0.53
0.57
0.72
0.78
0.98
0.88
0.96
1.20
ns
DIFF_SSTL15_R_F
0.42
0.53
0.57
0.66
0.73
0.92
0.78
0.86
1.09
ns
DIFF_SSTL15_R_S
0.42
0.53
0.57
0.74
0.81
1.01
0.89
0.94
1.18
ns
DIFF_SSTL18_I_F
0.42
0.53
0.57
0.68
0.74
0.94
0.85
0.93
1.18
ns
DIFF_SSTL18_I_S
0.42
0.53
0.57
0.78
0.86
1.05
0.78
0.86
1.05
ns
DIFF_SSTL18_II_F
0.42
0.53
0.57
0.64
0.71
0.90
0.77
0.88
1.11
ns
DS893 (v1.2) July 27, 2015

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Table 27: IOB High Range (HR) Switching Characteristics (Contd)
TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
DIFF_SSTL18_II_S
0.42
0.53
0.57
0.76
0.83
1.03
0.89
1.04
1.29
ns
HSTL_I_18_F
0.44
0.55
0.59
0.67
0.73
0.93
0.77
0.84
1.08
ns
HSTL_I_18_S
0.44
0.55
0.59
0.79
0.85
1.05
0.91
0.96
1.18
ns
HSTL_I_F
0.44
0.55
0.59
0.68
0.75
0.94
0.82
0.92
1.16
ns
HSTL_I_S
0.44
0.55
0.59
0.73
0.79
0.98
0.87
1.00
1.25
ns
HSTL_II_18_F
0.44
0.55
0.59
0.74
0.82
1.01
0.87
1.00
1.25
ns
HSTL_II_18_S
0.44
0.55
0.59
0.79
0.85
1.05
0.92
1.05
1.30
ns
HSTL_II_F
0.44
0.55
0.59
0.65
0.73
0.93
0.79
0.90
1.13
ns
HSTL_II_S
0.44
0.55
0.59
0.76
0.82
1.01
0.93
0.98
1.22
ns
HSUL_12_F
0.44
0.55
0.59
0.68
0.75
0.94
0.68
0.75
0.94
ns
HSUL_12_S
0.44
0.55
0.59
0.77
0.84
1.04
0.96
0.97
1.15
ns
LVCMOS12_F_12
0.68
0.95
0.95
0.87
0.95
1.16
0.87
0.95
1.16
ns
LVCMOS12_F_4
0.68
0.95
0.95
1.02
1.16
1.39
1.02
1.16
1.39
ns
LVCMOS12_F_8
0.68
0.95
0.95
0.92
0.97
1.19
0.92
0.97
1.19
ns
LVCMOS12_S_12
0.68
0.95
0.95
0.99
1.06
1.28
0.99
1.06
1.28
ns
LVCMOS12_S_4
0.68
0.95
0.95
1.15
1.36
1.60
1.15
1.36
1.60
ns
LVCMOS12_S_8
0.68
0.95
0.95
1.03
1.10
1.32
1.03
1.10
1.32
ns
LVCMOS15_F_12
0.60
0.82
0.87
0.92
0.96
1.18
0.92
0.96
1.18
ns
LVCMOS15_F_16
0.60
0.82
0.87
0.86
0.94
1.15
0.88
0.94
1.17
ns
LVCMOS15_F_4
0.60
0.82
0.87
1.06
1.15
1.38
1.06
1.15
1.38
ns
LVCMOS15_F_8
0.60
0.82
0.87
0.96
1.02
1.24
0.96
1.02
1.24
ns
LVCMOS15_S_12
0.60
0.82
0.87
1.01
1.07
1.29
1.01
1.07
1.29
ns
LVCMOS15_S_16
0.60
0.82
0.87
0.99
1.04
1.26
0.99
1.04
1.26
ns
LVCMOS15_S_4
0.60
0.82
0.87
1.16
1.29
1.53
1.16
1.29
1.53
ns
LVCMOS15_S_8
0.60
0.82
0.87
1.05
1.11
1.34
1.05
1.11
1.34
ns
LVCMOS18_F_12
0.55
0.76
0.79
0.99
1.04
1.25
0.99
1.04
1.25
ns
LVCMOS18_F_16
0.55
0.76
0.79
0.95
1.00
1.21
0.95
1.00
1.21
ns
LVCMOS18_F_4
0.55
0.76
0.79
1.13
1.17
1.41
1.13
1.17
1.41
ns
LVCMOS18_F_8
0.55
0.76
0.79
1.05
1.10
1.33
1.05
1.10
1.33
ns
LVCMOS18_S_12
0.55
0.76
0.79
1.06
1.11
1.34
1.06
1.11
1.34
ns
LVCMOS18_S_16
0.55
0.76
0.79
1.03
1.11
1.34
1.03
1.11
1.34
ns
LVCMOS18_S_4
0.55
0.76
0.79
1.20
1.32
1.58
1.20
1.32
1.58
ns
LVCMOS18_S_8
0.55
0.76
0.79
1.10
1.18
1.38
1.10
1.18
1.38
ns
LVCMOS25_F_12
0.74
0.85
0.90
1.45
1.54
1.81
1.45
1.54
1.81
ns
LVCMOS25_F_16
0.74
0.85
0.90
1.43
1.59
1.88
1.43
1.59
1.88
ns
LVCMOS25_F_4
0.74
0.85
0.90
2.18
2.24
2.56
2.18
2.24
2.56
ns
LVCMOS25_F_8
0.74
0.85
0.90
1.60
1.67
1.95
1.60
1.67
1.95
ns
LVCMOS25_S_12
0.74
0.85
0.90
1.90
2.14
2.47
1.90
2.14
2.47
ns
DS893 (v1.2) July 27, 2015

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TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
LVCMOS25_S_16
0.74
0.85
0.90
1.70
1.89
2.19
1.71
1.89
2.19
ns
LVCMOS25_S_4
0.74
0.85
0.90
3.02
3.27
3.68
3.02
3.27
3.68
ns
LVCMOS25_S_8
0.74
0.85
0.90
1.95
2.15
2.47
1.95
2.15
2.47
ns
LVCMOS33_F_12
0.87
0.97
1.03
1.98
1.98
2.24
1.98
1.98
2.24
ns
LVCMOS33_F_16
0.87
0.97
1.03
1.79
1.79
2.09
1.79
1.79
2.09
ns
LVCMOS33_F_4
0.87
0.97
1.03
2.34
2.34
2.63
2.34
2.34
2.63
ns
LVCMOS33_F_8
0.87
0.97
1.03
2.05
2.05
2.32
2.05
2.05
2.32
ns
LVCMOS33_S_12
0.87
0.97
1.03
2.09
2.13
2.48
2.09
2.13
2.48
ns
LVCMOS33_S_16
0.87
0.97
1.03
2.11
2.11
2.43
2.11
2.11
2.43
ns
LVCMOS33_S_4
0.87
0.97
1.03
3.08
3.23
3.67
3.08
3.23
3.67
ns
LVCMOS33_S_8
0.87
0.97
1.03
2.15
2.28
2.55
2.66
2.67
2.78
ns
LVDS_25
0.44
0.58
0.62
0.71
0.83
0.95
105.73
105.74
105.85
ns
LVPECL
0.42
0.57
0.62
N/A
N/A
N/A
N/A
N/A
N/A
ns
LVTTL_F_12
0.94
1.04
1.05
1.83
1.83
2.10
1.83
1.83
2.10
ns
LVTTL_F_16
0.94
1.04
1.05
1.79
1.79
2.06
1.79
1.79
2.06
ns
LVTTL_F_4
0.94
1.04
1.05
2.34
2.34
2.63
2.34
2.34
2.63
ns
LVTTL_F_8
0.94
1.04
1.05
1.97
1.97
2.22
1.97
1.97
2.22
ns
LVTTL_S_12
0.94
1.04
1.05
1.90
1.90
2.19
1.96
1.97
2.19
ns
LVTTL_S_16
0.94
1.04
1.05
2.07
2.07
2.40
2.07
2.07
2.40
ns
LVTTL_S_4
0.94
1.04
1.05
3.08
3.23
3.67
3.08
3.23
3.67
ns
LVTTL_S_8
0.94
1.04
1.05
2.22
2.22
2.47
2.22
2.37
2.50
ns
MINI_LVDS_25
0.44
0.58
0.62
0.71
0.83
0.95
105.73
105.74
105.85
ns
PPDS_25
0.44
0.58
0.62
0.71
0.83
0.95
105.73
105.74
105.85
ns
RSDS_25
0.44
0.58
0.62
0.71
0.83
0.95
105.73
105.74
105.85
ns
SLVS_400_25
0.44
0.58
0.62
N/A
N/A
N/A
N/A
N/A
N/A
ns
SSTL12_F
0.44
0.55
0.59
0.65
0.72
0.91
0.74
0.83
1.04
ns
SSTL12_S
0.44
0.55
0.59
0.70
0.78
0.97
0.80
0.88
1.11
ns
SSTL135_F
0.44
0.55
0.59
0.65
0.72
0.90
0.78
0.89
1.11
ns
SSTL135_S
0.44
0.55
0.59
0.70
0.77
0.97
0.86
0.94
1.18
ns
SSTL135_R_F
0.44
0.55
0.59
0.67
0.74
0.93
0.78
0.86
1.08
ns
SSTL135_R_S
0.44
0.55
0.59
0.76
0.82
1.02
0.90
0.96
1.19
ns
SSTL15_F
0.44
0.55
0.59
0.61
0.68
0.87
0.74
0.84
1.07
ns
SSTL15_S
0.44
0.55
0.59
0.74
0.80
1.00
0.90
0.99
1.23
ns
SSTL15_R_F
0.44
0.55
0.59
0.68
0.75
0.94
0.80
0.89
1.11
ns
SSTL15_R_S
0.44
0.55
0.59
0.76
0.83
1.04
0.91
0.96
1.20
ns
SSTL18_I_F
0.44
0.55
0.59
0.70
0.76
0.96
0.87
0.95
1.21
ns
SSTL18_I_S
0.44
0.55
0.59
0.80
0.88
1.08
0.80
0.88
1.08
ns
SSTL18_II_F
0.44
0.55
0.59
0.66
0.73
0.92
0.79
0.90
1.14
ns
DS893 (v1.2) July 27, 2015

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TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
SSTL18_II_S
0.44
0.55
0.59
0.78
0.85
1.05
0.91
1.06
1.32
ns
SUB_LVDS
0.44
0.58
0.62
0.71
0.83
0.95
105.73
105.74
105.85
ns
TMDS_33
0.57
0.65
0.73
0.71
0.83
0.95
105.73
105.74
105.85
ns
DS893 (v1.2) July 27, 2015

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Table 28: IOB High Performance (HP) Switching Characteristics
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
TOUTBUF_DELAY_O_PAD
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
DIFF_HSTL_I_12_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSTL_I_12_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSTL_I_12_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_HSTL_I_18_F
0.43
0.48
0.55
0.45
0.49
0.53
0.53
0.61
0.68
ns
DIFF_HSTL_I_18_M
0.43
0.48
0.55
0.50
0.55
0.59
0.59
0.68
0.76
ns
DIFF_HSTL_I_18_S
0.43
0.48
0.55
0.56
0.62
0.67
0.67
0.77
0.86
ns
DIFF_HSTL_I_DCI_12_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSTL_I_DCI_12_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSTL_I_DCI_12_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_HSTL_I_DCI_18_F
0.43
0.48
0.55
0.45
0.49
0.53
0.53
0.61
0.68
ns
DIFF_HSTL_I_DCI_18_M
0.43
0.48
0.55
0.50
0.55
0.59
0.59
0.68
0.76
ns
DIFF_HSTL_I_DCI_18_S
0.43
0.48
0.55
0.56
0.62
0.67
0.67
0.77
0.86
ns
DIFF_HSTL_I_DCI_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSTL_I_DCI_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSTL_I_DCI_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_HSTL_I_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSTL_I_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSTL_I_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_HSUL_12_DCI_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSUL_12_DCI_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSUL_12_DCI_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_HSUL_12_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_HSUL_12_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_HSUL_12_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_POD10_DCI_F
0.43
0.48
0.55
0.46
0.50
0.55
0.58
0.65
0.73
ns
DIFF_POD10_DCI_M
0.43
0.48
0.55
0.52
0.58
0.63
0.62
0.71
0.79
ns
DIFF_POD10_DCI_S
0.43
0.48
0.55
0.61
0.68
0.74
0.69
0.79
0.88
ns
DIFF_POD10_F
0.43
0.48
0.55
0.46
0.50
0.55
0.58
0.65
0.73
ns
DIFF_POD10_M
0.43
0.48
0.55
0.52
0.58
0.63
0.62
0.71
0.79
ns
DIFF_POD10_S
0.43
0.48
0.55
0.61
0.68
0.74
0.69
0.79
0.88
ns
DIFF_POD12_DCI_F
0.43
0.48
0.55
0.46
0.50
0.55
0.58
0.65
0.73
ns
DIFF_POD12_DCI_M
0.43
0.48
0.55
0.52
0.58
0.63
0.62
0.71
0.79
ns
DIFF_POD12_DCI_S
0.43
0.48
0.55
0.61
0.68
0.74
0.69
0.79
0.88
ns
DIFF_POD12_F
0.43
0.48
0.55
0.46
0.50
0.55
0.58
0.65
0.73
ns
DIFF_POD12_M
0.43
0.48
0.55
0.52
0.58
0.63
0.62
0.71
0.79
ns
DIFF_POD12_S
0.43
0.48
0.55
0.61
0.68
0.74
0.69
0.79
0.88
ns
DIFF_SSTL12_DCI_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_SSTL12_DCI_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DS893 (v1.2) July 27, 2015

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25

Table 28: IOB High Performance (HP) Switching Characteristics (Contd)
TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
DIFF_SSTL12_DCI_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL12_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_SSTL12_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_SSTL12_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL135_DCI_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.69
ns
DIFF_SSTL135_DCI_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_SSTL135_DCI_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL135_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.69
ns
DIFF_SSTL135_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_SSTL135_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL15_DCI_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_SSTL15_DCI_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_SSTL15_DCI_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL15_F
0.43
0.48
0.55
0.46
0.50
0.54
0.54
0.62
0.68
ns
DIFF_SSTL15_M
0.43
0.48
0.55
0.50
0.55
0.60
0.60
0.68
0.76
ns
DIFF_SSTL15_S
0.43
0.48
0.55
0.56
0.61
0.67
0.67
0.76
0.85
ns
DIFF_SSTL18_I_DCI_F
0.43
0.48
0.55
0.45
0.49
0.53
0.53
0.61
0.68
ns
DIFF_SSTL18_I_DCI_M
0.43
0.48
0.55
0.50
0.55
0.59
0.59
0.68
0.76
ns
DIFF_SSTL18_I_DCI_S
0.43
0.48
0.55
0.56
0.62
0.67
0.67
0.77
0.86
ns
DIFF_SSTL18_I_F
0.43
0.48
0.55
0.45
0.49
0.53
0.53
0.61
0.68
ns
DIFF_SSTL18_I_M
0.43
0.48
0.55
0.50
0.55
0.59
0.59
0.68
0.76
ns
DIFF_SSTL18_I_S
0.43
0.48
0.55
0.56
0.62
0.67
0.67
0.77
0.86
ns
HSLVDCI_15_F
0.43
0.46
0.52
0.48
0.53
0.56
0.57
0.64
0.71
ns
HSLVDCI_15_M
0.43
0.46
0.52
0.53
0.57
0.62
0.62
0.71
0.79
ns
HSLVDCI_15_S
0.43
0.46
0.52
0.58
0.64
0.69
0.70
0.79
0.88
ns
HSLVDCI_18_F
0.43
0.46
0.52
0.48
0.53
0.57
0.57
0.65
0.71
ns
HSLVDCI_18_M
0.43
0.46
0.52
0.52
0.57
0.62
0.62
0.71
0.79
ns
HSLVDCI_18_S
0.43
0.46
0.52
0.58
0.64
0.69
0.70
0.80
0.90
ns
HSTL_I_12_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
HSTL_I_12_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_12_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
HSTL_I_18_F
0.43
0.46
0.52
0.47
0.51
0.55
0.55
0.63
0.70
ns
HSTL_I_18_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_18_S
0.43
0.46
0.52
0.58
0.63
0.69
0.69
0.78
0.88
ns
HSTL_I_DCI_12_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
HSTL_I_DCI_12_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_DCI_12_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
HSTL_I_DCI_18_F
0.43
0.46
0.52
0.47
0.51
0.55
0.55
0.63
0.70
ns
DS893 (v1.2) July 27, 2015

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TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
HSTL_I_DCI_18_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_DCI_18_S
0.43
0.46
0.52
0.58
0.63
0.69
0.69
0.78
0.88
ns
HSTL_I_DCI_F
0.43
0.46
0.52
0.47
0.52
0.56
0.56
0.63
0.70
ns
HSTL_I_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_DCI_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
HSTL_I_F
0.43
0.46
0.52
0.47
0.52
0.56
0.56
0.63
0.70
ns
HSTL_I_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSTL_I_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
HSUL_12_DCI_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
HSUL_12_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSUL_12_DCI_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
HSUL_12_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
HSUL_12_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
HSUL_12_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
LVCMOS12_F_2
0.56
0.66
0.74
0.67
0.73
0.79
0.67
0.73
0.79
ns
LVCMOS12_F_4
0.56
0.66
0.74
0.63
0.68
0.73
0.63
0.68
0.73
ns
LVCMOS12_F_6
0.56
0.66
0.74
0.59
0.64
0.69
0.59
0.65
0.72
ns
LVCMOS12_F_8
0.56
0.66
0.74
0.57
0.63
0.67
0.59
0.66
0.72
ns
LVCMOS12_M_2
0.56
0.66
0.74
0.72
0.79
0.85
0.72
0.79
0.85
ns
LVCMOS12_M_4
0.56
0.66
0.74
0.66
0.71
0.77
0.66
0.71
0.77
ns
LVCMOS12_M_6
0.56
0.66
0.74
0.62
0.67
0.72
0.62
0.69
0.75
ns
LVCMOS12_M_8
0.56
0.66
0.74
0.62
0.67
0.72
0.64
0.71
0.78
ns
LVCMOS12_S_2
0.56
0.66
0.74
0.77
0.89
0.96
0.77
0.89
0.96
ns
LVCMOS12_S_4
0.56
0.66
0.74
0.68
0.74
0.79
0.68
0.74
0.79
ns
LVCMOS12_S_6
0.56
0.66
0.74
0.66
0.72
0.78
0.66
0.72
0.79
ns
LVCMOS12_S_8
0.56
0.66
0.74
0.66
0.72
0.77
0.67
0.74
0.82
ns
LVCMOS15_F_12
0.45
0.52
0.58
0.61
0.66
0.71
0.66
0.73
0.81
ns
LVCMOS15_F_2
0.45
0.52
0.58
0.73
0.77
0.83
0.73
0.77
0.83
ns
LVCMOS15_F_4
0.45
0.52
0.58
0.69
0.73
0.78
0.69
0.73
0.78
ns
LVCMOS15_F_6
0.45
0.52
0.58
0.63
0.68
0.73
0.63
0.70
0.77
ns
LVCMOS15_F_8
0.45
0.52
0.58
0.61
0.66
0.72
0.63
0.71
0.78
ns
LVCMOS15_M_12
0.45
0.52
0.58
0.63
0.69
0.75
0.67
0.77
0.85
ns
LVCMOS15_M_2
0.45
0.52
0.58
0.77
0.80
0.86
0.77
0.80
0.86
ns
LVCMOS15_M_4
0.45
0.52
0.58
0.72
0.76
0.82
0.72
0.76
0.82
ns
LVCMOS15_M_6
0.45
0.52
0.58
0.67
0.72
0.78
0.67
0.74
0.82
ns
LVCMOS15_M_8
0.45
0.52
0.58
0.65
0.71
0.76
0.65
0.76
0.83
ns
LVCMOS15_S_12
0.45
0.52
0.58
0.65
0.70
0.75
0.67
0.75
0.83
ns
LVCMOS15_S_2
0.45
0.52
0.58
0.78
0.85
0.91
0.78
0.85
0.91
ns
DS893 (v1.2) July 27, 2015

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TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
LVCMOS15_S_4
0.45
0.52
0.58
0.74
0.78
0.84
0.74
0.78
0.84
ns
LVCMOS15_S_6
0.45
0.52
0.58
0.72
0.76
0.82
0.72
0.76
0.84
ns
LVCMOS15_S_8
0.45
0.52
0.58
0.68
0.73
0.79
0.68
0.75
0.83
ns
LVCMOS18_F_12
0.43
0.49
0.54
0.67
0.72
0.78
0.72
0.81
0.90
ns
LVCMOS18_F_2
0.43
0.49
0.54
0.94
1.07
1.15
0.94
1.07
1.15
ns
LVCMOS18_F_4
0.43
0.49
0.54
0.78
0.82
0.89
0.78
0.82
0.89
ns
LVCMOS18_F_6
0.43
0.49
0.54
0.72
0.77
0.83
0.72
0.79
0.88
ns
LVCMOS18_F_8
0.43
0.49
0.54
0.70
0.75
0.81
0.72
0.81
0.89
ns
LVCMOS18_M_12
0.43
0.49
0.54
0.70
0.76
0.81
0.74
0.83
0.92
ns
LVCMOS18_M_2
0.43
0.49
0.54
0.99
1.10
1.19
0.99
1.10
1.19
ns
LVCMOS18_M_4
0.43
0.49
0.54
0.82
0.86
0.92
0.82
0.86
0.92
ns
LVCMOS18_M_6
0.43
0.49
0.54
0.75
0.80
0.87
0.75
0.81
0.90
ns
LVCMOS18_M_8
0.43
0.49
0.54
0.73
0.78
0.85
0.73
0.83
0.92
ns
LVCMOS18_S_12
0.43
0.49
0.54
0.74
0.78
0.84
0.76
0.83
0.92
ns
LVCMOS18_S_2
0.43
0.49
0.54
1.05
1.16
1.25
1.05
1.16
1.25
ns
LVCMOS18_S_4
0.43
0.49
0.54
0.83
0.86
0.93
0.83
0.86
0.93
ns
LVCMOS18_S_6
0.43
0.49
0.54
0.79
0.82
0.89
0.79
0.82
0.90
ns
LVCMOS18_S_8
0.43
0.49
0.54
0.75
0.80
0.86
0.75
0.82
0.90
ns
LVDCI_15_F
0.45
0.52
0.58
0.48
0.53
0.56
0.57
0.64
0.71
ns
LVDCI_15_M
0.45
0.52
0.58
0.53
0.57
0.62
0.62
0.71
0.79
ns
LVDCI_15_S
0.45
0.52
0.58
0.58
0.64
0.69
0.70
0.79
0.88
ns
LVDCI_18_F
0.43
0.49
0.54
0.48
0.53
0.57
0.57
0.65
0.71
ns
LVDCI_18_M
0.43
0.49
0.54
0.52
0.57
0.62
0.62
0.71
0.79
ns
LVDCI_18_S
0.43
0.49
0.54
0.58
0.64
0.69
0.70
0.80
0.90
ns
LVDS
0.42
0.46
0.51
0.57
0.67
0.72
890.24
890.26
890.28
ns
POD10_DCI_F
0.43
0.46
0.52
0.48
0.52
0.56
0.59
0.67
0.74
ns
POD10_DCI_M
0.43
0.46
0.52
0.54
0.60
0.65
0.64
0.73
0.81
ns
POD10_DCI_S
0.43
0.46
0.52
0.63
0.69
0.76
0.71
0.81
0.89
ns
POD10_F
0.43
0.46
0.52
0.48
0.52
0.56
0.59
0.67
0.74
ns
POD10_M
0.43
0.46
0.52
0.54
0.60
0.65
0.64
0.73
0.81
ns
POD10_S
0.43
0.46
0.52
0.63
0.69
0.76
0.71
0.81
0.89
ns
POD12_DCI_F
0.43
0.46
0.52
0.48
0.52
0.56
0.59
0.67
0.74
ns
POD12_DCI_M
0.43
0.46
0.52
0.54
0.60
0.65
0.64
0.73
0.81
ns
POD12_DCI_S
0.43
0.46
0.52
0.63
0.69
0.76
0.71
0.81
0.89
ns
POD12_F
0.43
0.46
0.52
0.48
0.52
0.56
0.59
0.67
0.74
ns
POD12_M
0.43
0.46
0.52
0.54
0.60
0.65
0.64
0.73
0.81
ns
POD12_S
0.43
0.46
0.52
0.63
0.69
0.76
0.71
0.81
0.89
ns
SLVS_400_18
0.42
0.46
0.51
N/A
N/A
N/A
N/A
N/A
N/A
ns
DS893 (v1.2) July 27, 2015

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28

TOUTBUF_DELAY_O_PAD
TINBUF_DELAY_PAD_I
I/O Standards
1.0V
0.95V
1.0V
0.95V
1.0V
0.95V
Units
-3
-2
-1/-1L
-3
-2
-1/-1L
-3
-2
-1/-1L
SSTL12_DCI_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
SSTL12_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL12_DCI_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL12_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.63
0.70
ns
SSTL12_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL12_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL135_DCI_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.64
0.70
ns
SSTL135_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL135_DCI_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL135_F
0.43
0.46
0.52
0.48
0.52
0.56
0.56
0.64
0.70
ns
SSTL135_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL135_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL15_DCI_F
0.43
0.46
0.52
0.47
0.52
0.56
0.56
0.63
0.70
ns
SSTL15_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL15_DCI_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL15_F
0.43
0.46
0.52
0.47
0.52
0.56
0.56
0.63
0.70
ns
SSTL15_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL15_S
0.43
0.46
0.52
0.57
0.63
0.68
0.69
0.78
0.87
ns
SSTL18_I_DCI_F
0.43
0.46
0.52
0.47
0.51
0.55
0.55
0.63
0.70
ns
SSTL18_I_DCI_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL18_I_DCI_S
0.43
0.46
0.52
0.58
0.63
0.69
0.69
0.78
0.88
ns
SSTL18_I_F
0.43
0.46
0.52
0.47
0.51
0.55
0.55
0.63
0.70
ns
SSTL18_I_M
0.43
0.46
0.52
0.52
0.57
0.61
0.61
0.70
0.78
ns
SSTL18_I_S
0.43
0.46
0.52
0.58
0.63
0.69
0.69
0.78
0.88
ns
SUB_LVDS
0.42
0.46
0.51
0.57
0.67
0.72
890.24
890.26
890.28
ns
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Table 29 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O. TOUTBUF_DELAY_TE_PAD is the
delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e.,
a high impedance state). TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output. In HP I/O
banks, the internal DCI termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the
DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always
faster than TOUTBUF_DELAY_TE_PAD when the INTERMDISABLE pin is used.
Table 29: IOB 3-state Output Switching Characteristics
Speed Grade
Symbol
TOUTBUF_DELAY_TE_PAD(1)
TINBUF_DELAY_IBUFDIS_O
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
T input to pad high-impedance for HR I/O banks
1.37
1.52
1.69
ns
T input to pad high-impedance for HP I/O banks
0.62
0.71
0.78
ns
IBUF turn-on time from IBUFDISABLE to O output for

HR I/O banks
0.47
0.65
0.68
ns
IBUF turn-on time from IBUFDISABLE to O output for

HP I/O banks
1.06
1.21
1.49
ns
Notes:
1.
The TOUTBUF_DELAY_TE_PAD values are applicable to single-ended I/O standards. For true differential standards, the values
are larger. Use the Vivado timing report for the most accurate timing values for your configuration.
I/O Standard Adjustment Measurement Methodology

Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay.
Table 30: Input Delay Measurement Methodology
Description
I/O Standard
Attribute
VL(1)(2)
VH(1)(2)
VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
LVCMOS, 1.2V
LVCMOS12
0.1
1.1
0.6
LVCMOS, LVDCI, HSLVDCI, 1.5V
LVCMOS15,
LVDCI_15,
HSLVDCI_15
0.1
1.4
0.75
LVCMOS, LVDCI, HSLVDCI, 1.8V
LVCMOS18,
LVDCI_18,
HSLVDCI_18
0.1
1.7
0.9
LVCMOS, 2.5V
LVCMOS25
0.1
2.4
1.25
LVCMOS, 3.3V
LVCMOS33
0.1
3.2
1.75
LVTTL, 3.3V
LVTTL
0.1
3.2
1.75
HSTL (high-speed transceiver logic),

Class I, 1.2V
HSTL_I_12
VREF 0.5
VREF + 0.5
VREF
0.60
HSTL, Class I and II, 1.5V
HSTL_I, HSTL_II
VREF 0.65
VREF + 0.65
VREF
0.75
HSTL, Class I and II, 1.8V
HSTL_I_18,
HSTL_II_18
VREF 0.8
VREF + 0.8
VREF
0.90
HSUL (high-speed unterminated logic), 1.2V HSUL_12
VREF 0.5
VREF + 0.5
VREF
0.60
SSTL (stub series terminated logic), 1.2V
SSTL12
VREF 0.5
VREF + 0.5
VREF
0.60
SSTL, 1.35V
SSTL135, SSTL135_R VREF 0.575 VREF + 0.575
VREF
0.675
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Table 30: Input Delay Measurement Methodology (Contd)
Description
I/O Standard
Attribute
VL(1)(2)
VH(1)(2)
VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
VREF 0.65
VREF + 0.65
VREF
0.75
SSTL, 1.5V
SSTL15, SSTL15_R
SSTL, Class I and II, 1.8V
SSTL18_I, SSTL18_II
VREF 0.8
VREF + 0.8
VREF
0.90
POD10, 1.0V
POD10
VREF 0.6
VREF + 0.6
VREF
0.70
POD12, 1.2V
POD12
VREF 0.74
VREF + 0.74
VREF
0.84
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL_I_12
0.6 0.125
0.6 + 0.125
0(6)
DIFF_HSTL, Class I and II,1.5V
DIFF_HSTL_I,
DIFF_HSTL_II
0(6)
DIFF_HSTL, Class I and II, 1.8V
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 0.125
0.9 + 0.125
0(6)
DIFF_HSUL, 1.2V
DIFF_HSUL_12
0.6 0.125
0.6 + 0.125
0(6)
0.6 0.125
0.6 + 0.125
0(6)
0.675
0.125
0.675 +
0.125
0(6)
0(6)
0(6)
0.75 0.125 0.75 + 0.125
DIFF_SSTL, 1.2V
DIFF_SSTL12
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL135,
DIFF_SSTL135_R
DIFF_SSTL15,
DIFF_SSTL15_R
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
DIFF_POD10, 1.0V
DIFF_POD10
0.70 0.125 0.70 + 0.125
0(6)
DIFF_POD12, 1.2V
DIFF_POD12
0.84 0.125 0.84 + 0.125
0(6)
LVDS (low-voltage differential signaling),

1.8V
LVDS
0(6)
LVDS_25, 2.5V
LVDS_25
0(6)
0.9 + 0.125
0(6)
0.9 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
1.25 0.125 1.25 + 0.125
0(6)
0(6)
SUB_LVDS, 1.8V
SLVS, 1.8V
SLVS, 2.5V
LVPECL, 2.5
BLVDS_25, 2.5V
MINI_LVDS_25, 2.5V
PPDS_25
RSDS_25
TMDS_33
SUB_LVDS
SLVS_400_18
SLVS_400_25
LVPECL
BLVDS_25
MINI_LVDS_25
PPDS_25
RSDS_25
TMDS_33
0.75 0.125 0.75 + 0.125

0.9 0.125
0.9 0.125
0.9 + 0.125
0.9 + 0.125
1.25 0.125 1.25 + 0.125

0.9 0.125
0.9 0.125
3 0.125
3 + 0.125
Notes:
1.
2.
3.
4.
5.
6.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same
voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the
same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
Input waveform switches between VLand VH.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these
measurements. VREF values listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted
in Figure 1.
The value given is the differential input voltage.
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31
Output Delay Measurements

Output delays are measured with short output traces. Standard termination was used for all testing. The
propagation delay of the trace is characterized separately and subtracted from the final measurement, and
is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
X-Ref Target - Figure 1
VREF
Output
RREF
VMEAS (voltage level when taking delay measurement)

CREF (probe capacitance)
DS893_01_051415
Figure 1: Single-Ended Test Setup

Output
+
CREF
RREF VMEAS
DS893_02_051415
Figure 2: Differential Test Setup

Parameters VREF, R REF, C REF, and V MEAS fully describe the test conditions for each I/O standard. The most
accurate prediction of propagation delay in any given application can be obtained through IBIS
simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 31.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS
model or capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual
propagation delay of the PCB trace.
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Table 31: Output Delay Measurement Methodology
Description
I/O Standard Attribute
RREF CREF(1) VMEAS

()
(pF)
(V)
VREF
(V)
LVCMOS, 1.2V
LVCMOS12
1M
0.6
LVCMOS 1.5V
LVCMOS15
1M
0.75
LVCMOS 1.8V
LVCMOS18
1M
0.9
LVCMOS, 2.5V
LVCMOS25
1M
1.25
LVCMOS, 3.3V
LVCMOS33
1M
1.65
LVTTL, 3.3V
LVTTL
1M
1.65
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
50
VREF
0.75
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
50
VREF
0.9
HSTL (high-speed transceiver logic), Class I, 1.2V
HSTL_I_12
50
VREF
0.6
HSTL, Class I, 1.5V
HSTL_I
50
VREF
0.75
HSTL, Class II, 1.5V
HSTL_II
25
VREF
0.75
HSTL, Class I, 1.8V
HSTL_I_18
50
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
VREF
0.9
HSUL (high-speed unterminated logic), Class I, 1.2V HSUL_12
50
VREF
0.6
SSTL12, 1.2V
SSTL12
50
VREF
0.6
SSTL135/SSTL135_R, 1.35V
SSTL135, SSTL135_R
50
VREF
0.675
SSTL15/SSTL15_R, 1.5V
SSTL15, SSTL15_R
50
VREF
0.75
SSTL (stub series terminated logic),

Class I and Class II, 1.8V
SSTL18_I, SSTL18_II
50
VREF
0.9
POD10, 1.0V
POD10
50
VREF
1.0
POD12, 1.2V
POD12
50
VREF
1.2
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL_I_12
50
VREF
0.6
DIFF_HSTL_I, DIFF_HSTL_II
50
VREF
0.75
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
50
VREF
0.9
DIFF_HSUL_12, 1.2V
DIFF_HSUL_12
50
VREF
0.6
DIFF_SSTL12, 1.2V
DIFF_SSTL12
50
VREF
0.6
DIFF_SSTL135,
DIFF_SSTL135_R
50
VREF
0.675
DIFF_SSTL15,
DIFF_SSTL15_R
50
VREF
0.75
DIFF_SSTL18, Class I and II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
50
VREF
0.9
DIFF_POD10, 1.0V
DIFF_POD10
50
VREF
1.0
DIFF_POD12, 1.2V
DIFF_POD12
50
VREF
1.2
0(2)
0(2)
0(2)
0(2)
0(2)
0(2)
LVDS (low-voltage differential signaling), 1.8V

LVDS, 2.5V
BLVDS (Bus LVDS), 2.5V
Mini LVDS, 2.5V
PPDS_25
RSDS_25
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LVDS_25
BLVDS_25
MINI_LVDS_25
PPDS_25
RSDS_25
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100
100
100
100
100
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Table 31: Output Delay Measurement Methodology (Contd)
Description
I/O Standard Attribute
RREF CREF(1) VMEAS

()
(pF)
(V)
VREF
(V)
SUB_LVDS
SUB_LVDS
100
0(2)
TMDS_33
TMDS_33
50
0(2)
3.3
Notes:
1.
2.
CREF is the capacitance of the probe, nominally 0 pF.

The value given is the differential output voltage.
Block RAM and FIFO Switching Characteristics

Table 32: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-3
-2
-1/-1L
Units
Maximum Frequency
FMAX_WF_NC
Block RAM
(WRITE_FIRST and NO_CHANGE modes).
660
585
525
MHz
FMAX_RF
Block RAM (READ_FIRST mode)
575
510
460
MHz
FMAX_FIFO
FIFO in all modes without ECC.
660
585
525
MHz
Block RAM and FIFO in ECC configuration without

PIPELINE.
530
450
390
MHz
Block RAM and FIFO in ECC configuration with

PIPELINE and Block RAM in WRITE_FIRST or
NO_CHANGE mode.
660
585
525
MHz
Block RAM in ECC configuration in READ_FIRST

mode with PIPELINE.
575
510
460
MHz
FMAX_ADDREN_RDADDRCHANGE
Block RAM with address enable and read address

change compare turned on.
575
510
460
MHz
TPW_WF_NC(1)
Block RAM in WRITE_FIRST and NO_CHANGE

modes and FIFO. Clock High/Low pulse width.
758
855
952
ps, Min
TPW_RF(1)
Block RAM in READ_FIRST modes.

Clock High/Low pulse width.
870
980
1087
ps, Min
FMAX_ECC
Notes:
1.
The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse width requirements at the higher
frequencies.
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Input/Output Delay Switching Characteristics

Table 33: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-3
REFCLK frequency (component mode)
FREFCLK
REFCLK frequency (native mode)
TMINPER_RST
Minimum reset pulse width
TIDELAY_RESOLUTION/
TODELAY_RESOLUTION
IDELAY/ODELAY chain resolution
0.95V
-2
Units
-1/-1L
200 to 800
200 to 2400
MHz
200 to 2400
200 to 2133
MHz
52.00
ns
2.5 to 15
ps
DSP48 Slice Switching Characteristics

Table 34: DSP48 Slice Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-3
-2
-1/-1L
Units
Maximum Frequency
FMAX
With all registers used
741
661
594
MHz
FMAX_PATDET
With pattern detector
687
581
512
MHz
FMAX_MULT_NOMREG
Two register multiply without MREG
462
429
361
MHz
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG with

pattern detect
428
387
326
MHz
FMAX_PREADD_NOADREG
Without ADREG
468
429
358
MHz
FMAX_NOPIPELINEREG
Without pipeline registers (MREG, ADREG)
335
312
260
MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG, ADREG) with

pattern detect
316
286
238
MHz
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Clock Buffers and Networks

Table 35: Clock Buffers Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
850
725
630
MHz
850
725
630
MHz
850
725
630
MHz
850
725
630
MHz
512
MHz
Global Clock Switching Characteristics (Including BUFGCTRL)

FMAX
Maximum frequency of a global clock tree (BUFG)
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)

FMAX
Maximum frequency of a global clock buffer with input divide

capability (BUFGCE_DIV)
Global Clock Buffer with Clock Enable (BUFGCE)

FMAX
Maximum frequency of a global clock buffer with clock enable

(BUFGCE)
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)

FMAX
Maximum frequency of a leaf clock buffer with clock enable

(BUFCE_LEAF)
GTH/GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
FMAX
Maximum frequency of a serial transceiver clock buffer with clock

enable and clock input divide capability
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512
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MMCM Switching Characteristics

Table 36: MMCM Specification
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
MMCM_FINMAX
Maximum input clock frequency
1066
933
800
MHz
MMCM_FINMIN
Minimum input clock frequency
10
10
10
MHz
MMCM_FINJITTER
Maximum input clock period jitter
MMCM_FINDUTY
< 20% of clock input period or 1 ns Max
Input duty cycle range: 1049 MHz
2575
3070
3565
4060
Input duty cycle range: >500 MHz
4555
MMCM_FMIN_PSCLK
Minimum dynamic phase shift clock frequency
0.01
0.01
0.01
MHz
MMCM_FMAX_PSCLK
Maximum dynamic phase shift clock frequency
550
500
450
MHz
MMCM_FVCOMIN
Minimum MMCM VCO frequency
600
600
600
MHz
MMCM_FVCOMAX
Maximum MMCM VCO frequency
MMCM_FBANDWIDTH
Low MMCM bandwidth at

High MMCM bandwidth at
1600
1440
1200
MHz
typical(1)
1.00
1.00
1.00
MHz
typical(1)
4.00
4.00
4.00
MHz
0.12
0.12
0.12
ns
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM

MMCM_TOUTJITTER
MMCM_TOUTDUTY
outputs(2)
MMCM output jitter
Note 3
0.165
0.20
0.20
ns
MMCM maximum lock time for MMCM_FPFDMIN

frequencies above 20 MHz
100
100
100
MMCM maximum lock time for MMCM_FPFDMIN

frequencies from 10 MHz to 20 MHz
200
200
200
MMCM_FOUTMAX
MMCM maximum output frequency
850
725
630
MHz
MMCM_FOUTMIN
MMCM minimum output frequency(4)(5)
4.69
4.69
4.69
MHz
MMCM_TEXTFDVAR
External clock feedback variation
MMCM_RSTMINPULSE
5.00
5.00
5.00
ns
MMCM_FPFDMAX
Maximum frequency at the phase frequency

detector
550
500
450
MHz
MMCM_FPFDMIN
Minimum frequency at the phase frequency

detector
10
10
10
MHz
MMCM_TFBDELAY
Maximum delay in the feedback path
MMCM_TLOCKMAX
MMCM output clock duty cycle
precision(4)
5 ns Max or one clock cycle
Notes:
1.
2.
3.
4.
5.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter
frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
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PLL Switching Characteristics

Table 37: PLL Specification(1)
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
PLL_FINMAX
Maximum input clock frequency
1066
933
800
MHz
PLL_FINMIN
Minimum input clock frequency
70
70
70
MHz
PLL_FINJITTER
Maximum input clock period jitter
PLL_FINDUTY
3565
4060
Input duty cycle range: >500 MHz
4555
PLL_FVCOMIN
Minimum PLL VCO frequency
600
600
600
MHz
PLL_FVCOMAX
Maximum PLL VCO frequency
1335
1335
1200
MHz
PLL_TSTATPHAOFFSET
Static phase offset of the PLL outputs(2)
0.12
0.12
0.12
ns
PLL_TOUTJITTER
PLL output jitter
PLL_TOUTDUTY
PLL CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B
duty-cycle precision(4)
0.20
ns
PLL_TLOCKMAX
PLL maximum lock time
PLL_FOUTMAX
Note 3
0.165
0.20
100
PLL maximum output frequency at

CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B
850
725
630
MHz
PLL maximum output frequency at CLKOUTPHY
2670
2670
2400
MHz
PLL minimum output frequency at

CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B(5)
4.69
4.69
4.69
MHz
PLL_FOUTMIN
PLL minimum output frequency at CLKOUTPHY
PLL_RSTMINPULSE
PLL_FPFDMAX
2 x VCO mode: 1200

1 x VCO mode: 600
0.5 x VCO mode: 300
MHz
5.00
5.00
5.00
ns
Maximum frequency at the phase frequency

detector
667.5
667.5
600
MHz
PLL_FPFDMIN
Minimum frequency at the phase frequency

detector
70
70
70
MHz
PLL_FBANDWIDTH
PLL bandwidth at typical
15
15
15
MHz
Notes:
1.
2.
3.
4.
5.
The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
The static offset is measured between any PLL outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
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Device Pin-to-Pin Output Parameter Guidelines

The pin-to-pin numbers in Table 38 through Table 41 are based on the clock root placement in the center
of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 38: Global Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-3
0.95V
-2
Units
-1/-1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without
MMCM/PLL.
TICKOF
Global clock input and output flip-flop without

MMCM/PLL (near clock region).
XCVU065
4.87
5.72
6.76
ns
XCVU080
5.10
6.01
7.07
ns
XCVU095
5.10
6.01
7.07
ns
XCVU125
4.87
5.72
6.76
ns
XCVU160
4.87
5.72
6.76
ns
XCVU190
4.87
5.72
6.76
ns
XCVU440
5.93
6.97
8.21
ns
Notes:
1.
This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
Table 39: Global Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-3
0.95V
-2
Units
-1/-1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without
MMCM/PLL.
TICKOF_FAR
Global clock input and output flip-flop without

MMCM/PLL (far clock region).
XCVU065
5.30
6.25
7.36
ns
XCVU080
5.52
6.58
7.64
ns
XCVU095
5.52
6.58
7.64
ns
XCVU125
5.30
6.25
7.36
ns
XCVU160
5.30
6.25
7.36
ns
XCVU190
5.30
6.25
7.36
ns
XCVU440
6.26
7.36
8.64
ns
Notes:
1.
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Table 40: Global Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
1.0V
-3
0.95V
-2
Units
-1/-1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
TICKOFMMCMCC Global clock input and output flip-flop with
MMCM.
XCVU065
1.54
1.54
1.88
ns
XCVU080
1.53
1.53
1.81
ns
XCVU095
1.53
1.53
1.81
ns
XCVU125
1.54
1.54
1.88
ns
XCVU160
1.54
1.54
1.88
ns
XCVU190
1.54
1.54
1.88
ns
XCVU440
1.55
1.55
1.83
ns
Notes:
1.
2.
MMCM output jitter is already included in the timing calculation.
Table 41: Global Clock Input to Output Delay With PLL

Speed Grade
Symbol
Description
Device
1.0V
-3
0.95V
-2
Units
-1/-1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
TICKOF_PLL_CC Global clock input and output flip-flop with
PLL.
XCVU065
4.93
5.28
6.16
ns
XCVU080
5.15
5.62
6.43
ns
XCVU095
5.15
5.62
6.43
ns
XCVU125
4.93
5.28
6.16
ns
XCVU160
4.93
5.28
6.16
ns
XCVU190
4.93
5.25
6.16
ns
XCVU440
5.89
6.39
7.44
ns
Notes:
1.
2.
PLL output jitter is already included in the timing calculation.
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Device Pin-to-Pin Input Parameter Guidelines

The pin-to-pin numbers in Table 42 and Table 43 are based on the clock root placement in the center of
the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 42: Global Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
1.0V
-3
0.95V
-2
Units
-1/-1L
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)
TPSMMCMCC_VU065
TPHMMCMCC_VU065
Global clock input and input

flip-flop (or latch) with
MMCM.
Setup
Hold
TPSMMCMCC_VU080
Setup
TPHMMCMCC_VU080
Hold
TPSMMCMCC_VU095
Setup
TPHMMCMCC_VU095
Hold
TPSMMCMCC_VU125
Setup
TPHMMCMCC_VU125
Hold
TPSMMCMCC_VU160
Setup
TPHMMCMCC_VU160
Hold
TPSMMCMCC_VU190
Setup
TPHMMCMCC_VU190
Hold
TPSMMCMCC_VU440
Setup
TPHMMCMCC_VU440
Hold
XCVU065
XCVU080
XCVU095
XCVU125
XCVU160
XCVU190
XCVU440
2.14
2.23
2.52
ns
0.48
0.48
0.48
ns
2.15
2.25
2.55
ns
0.46
0.46
0.46
ns
2.15
2.25
2.55
ns
0.46
0.46
0.46
ns
2.14
2.23
2.52
ns
0.46
0.48
0.48
ns
2.13
2.23
2.52
ns
0.47
0.47
0.47
ns
2.14
2.23
2.52
ns
0.48
0.48
0.48
ns
2.21
2.31
2.68
ns
0.42
0.42
0.42
ns
Notes:
1.
2.
3.
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Table 43: Global Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-3
-2
Units
-1/-1L
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)
TPSPLLCC_VU065
TPHPLLCC_VU065
Global clock input and input

flip-flop (or latch) with PLL.
Setup
XCVU065
Hold
TPSPLLCC_VU080
Setup
TPHPLLCC_VU080
Hold
TPSPLLCC_VU095
Setup
TPHPLLCC_VU095
Hold
TPSPLLCC_VU125
Setup
TPHPLLCC_VU125
Hold
TPSPLLCC_VU160
Setup
TPHPLLCC_VU160
Hold
TPSPLLCC_VU190
Setup
TPHPLLCC_VU190
Hold
TPSPLLCC_VU440
Setup
TPHPLLCC_VU440
Hold
XCVU080
XCVU095
XCVU125
XCVU160
XCVU190
XCVU440
0.71
0.71
0.71
ns
2.26
2.26
2.61
ns
0.95
0.95
0.95
ns
2.35
2.35
2.69
ns
0.95
0.95
0.95
ns
2.35
2.35
2.69
ns
0.71
0.71
0.71
ns
2.26
2.26
2.61
ns
0.71
0.71
0.71
ns
2.26
2.26
2.61
ns
0.71
0.71
0.71
ns
2.26
2.26
2.61
ns
1.22
1.22
1.22
ns
3.29
3.38
3.89
ns
Notes:
1.
2.
3.
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 44: Sampling Window

Speed Grade
Description
1.0V
0.95V
Units
-3
-2E
-2I
-1/-1L
TSAMP_BUFG(1)
510
560
610
610
ps
TSAMP_NATIVE_DPA
100
100
100
125
ps
TSAMP_NATIVE_BISC
60
60
60
85
ps
Notes:
1.
This parameter indicates the total sampling error of the Virtex UltraScale FPGAs DDR input registers, measured across
voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers
edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase
shift resolution. These measurements do not include package or clock tree skew.
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Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for clock
transmitter and receiver data-valid windows.
Table 45: Package Skew
Symbol
Description
Device
XCVU065
XCVU080
XCVU095
PKGSKEW
Package Skew
XCVU125
XCVU160
XCVU190
XCVU440
Package
Value
Units
FFVC1517
ps
FFVC1517
ps
FFVD1517
ps
FFVB1760
ps
FFVA2104
ps
FFVB2104
ps
FFVC1517
ps
FFVD1517
ps
FFVB1760
ps
FFVA2104
ps
FFVB2104
ps
FFVC2104
ps
FLVD1517
ps
FLVB1760
ps
FLVA2104
ps
FLVB2104
ps
FLVC2104
ps
FLGB2104
ps
FLGC2104
ps
FLGB2104
ps
FLGC2104
ps
FLGA2577
ps
FLGB2377
ps
FLGA2892
ps
Notes:
1.
2.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest
delay from die pad to ball.
Package delay information is available for these device/package combinations. This information can be used to deskew the
package.
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GTH Transceiver Specifications

GTH Transceiver DC Input and Output Levels
Table 46 summarizes the DC specifications of the GTH transceivers in Virtex UltraScale FPGAs. Consult the
UltraScale Architecture GTH Transceiver User Guide (UG576) for further details.
Table 46: GTH Transceiver DC Specifications
Symbol
DC Parameter
Differential peak-to-peak input
voltage (external AC coupled)
DVPPIN
Conditions
Min
Typ
Max
Units
>10.3125 Gb/s
150
1250
mV
6.6 Gb/s to 10.3125 Gb/s
150
1250
mV
6.6 Gb/s
150
2000
mV
VIN
Single-ended input voltage.

Voltage measured at the pin
referenced to GND.
DC coupled
VMGTAVTT = 1.2V
400
VMGTAVTT
mV
VCMIN
Common mode input voltage
DC coupled
VMGTAVTT = 1.2V
2/3 VMGTAVTT
mV
DVPPOUT
Differential peak-to-peak output

voltage(1)
Transmitter output swing

is set to 1100
800
mV
When remote RX is
terminated to GND
Common mode output voltage:
DC coupled (equation based)
VCMOUTDC
When remote RX
termination is floating
When remote RX is
terminated to VRX_TERM(2)
VMGTAVTT/2 DVPPOUT/4
mV
VMGTAVTT DVPPOUT/2
mV
MGTAVTT
D
V
V
VPPOUT
MGTAVTT
RX_TERM
---------------------- ------------------------------------------------------
4
2
VMGTAVTT DVPPOUT/2
mV
VCMOUTAC
Common mode output voltage: AC coupled (equation based)
mV
RIN
Differential input resistance
100
ROUT
Differential output resistance
100
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew

(All packages)
ps
CEXT
Recommended external AC coupling capacitor(3)
100
nF
Notes:
1.
2.
3.
The output swing and pre-emphasis levels are programmable using the attributes discussed in the UltraScale Architecture
GTH Transceiver User Guide (UG576), and can result in values lower than reported in this table.
VRX_TERM is the remote RX termination voltage.
Other values can be used as appropriate to conform to specific protocols and standards.
+V
P
Single-Ended
Peak-to-Peak
Voltage
N
0
ds893_03_120314
Figure 3: Single-Ended Peak-to-Peak Voltage
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+V
Differential
Peak-to-Peak
Voltage
PN
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
ds893_04_120314
Figure 4: Differential Peak-to-Peak Voltage

Table 47 summarizes the DC specifications of the clock input of the GTH transceivers in Virtex UltraScale
FPGAs. Consult the UltraScale Architecture GTH Transceiver User Guide (UG576) for further details.
Table 47: GTH Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Min
Typ
Max
Units
250
2000
mV
VIDIFF
Differential peak-to-peak input voltage
RIN
100
CEXT
Required external AC coupling capacitor
10
nF
Table 48: GTH Transceiver Clock Output Level Specification

Symbol
Description
Conditions
Min
Typ
Max
Units
VOL
Output high voltage for P and N
RT = 100 across P and N signals
400
mV
VOH
Output low voltage for P and N
760
mV
VDDOUT
Differential output voltage

(PN), P = High
(NP), N = High
360
mV
VCMOUT
Common mode voltage
580
mV
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GTH Transceiver Switching Characteristics

Consult the UltraScale Architecture GTH Transceiver User Guide (UG576) for further information.
Table 49: GTH Transceiver Performance
Symbol
Speed Grade
Output
Divider
Description
1.0V
0.95V
Units
-3E
-2E, -2I
-1C,-1I,-1LI
FGTHMAX
GTH maximum line rate
16.375
16.375
12.5
Gb/s
FGTHMIN
GTH minimum line rate
0.5
0.5
0.5
Gb/s
FGTHCRANGE
CPLL line rate range(1)
Min
Max
Min
Max
Min
4.0
12.5
4.0
12.5
4.0
8.5
Gb/s
2.0
6.25
2.0
6.25
2.0
4.25
Gb/s
1.0
3.125
1.0
3.125
1.0
2.125
Gb/s
0.5
1.5625
0.5
1.5625
0.5
1.0625
16
FGTHQRANGE1 QPLL0 line rate range(2)
FGTHQRANGE2 QPLL1 line rate range(3)
Max
N/A
Gb/s
Gb/s
Min
Max
Min
Max
Min
Max
9.8
16.375
9.8
16.375
9.8
12.5
Gb/s
4.9
8.1875
4.9
8.1875
4.9
8.1875
Gb/s
2.45
4.0938
2.45
4.0938
2.45
4.0938
Gb/s
1.225
2.0469
1.225
2.0469
1.225
2.0469
Gb/s
16
0.6125
1.0234
0.6125
1.0234
0.6125
1.0234
Gb/s
Min
Max
Min
Max
Min
Max
8.0
13.0
8.0
13.0
8.0
12.5
Gb/s
4.0
6.5
4.0
6.5
4.0
6.5
Gb/s
2.0
3.25
2.0
3.25
2.0
3.25
Gb/s
1.0
1.625
1.0
1.625
1.0
1.625
Gb/s
16
0.5
0.8125
0.5
0.8125
0.5
0.8125
Gb/s
Min
Max
Min
Max
Min
Max
FCPLLRANGE
CPLL frequency range
2.0
6.25
2.0
6.25
2.0
4.25
GHz
FQPLL0RANGE
QPLL0 frequency range
9.8
16.375
9.8
16.375
9.8
16.375
GHz
FQPLL1RANGE
8.0
13.0
8.0
13.0
8.0
13.0
GHz
Notes:
1.
2.
3.
The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.
The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.
Table 50: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTHDRPCLK
Description
GTHDRPCLK maximum frequency
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Units
250
MHz
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Table 51: GTH Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Units
Min
Typ
Max
60
820
MHz
FGCLK
Reference clock frequency range
TRCLK
Reference clock rise time
20% 80%
200
ps
TFCLK
Reference clock fall time
80% 20%
200
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
40
50
60
Units
TRCLK
80%
20%
TFCLK
ds893_05_120314
Figure 5: Reference Clock Timing Parameters

Table 52: GTH Transceiver Reference Clock Selection Phase Noise Mask
Symbol
QPLLREFCLKMASK(1)(2)
CPLLREFCLKMASK(1)(2)
Offset
Frequency
Description
QPLL0/QPLL1 reference clock select
phase noise mask at
REFCLK frequency = 312.5 MHz.
Min
Typ
Max
10 KHz
105
100 KHz
124
1 MHz
130
10 KHz
105
124
130
140
100 KHz
CPLL reference clock select phase noise
mask at REFCLK frequency = 312.5 MHz. 1 MHz
50 MHz
dBc/Hz
dBc/Hz
Notes:
1.
2.
For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 x Log(N/312.5) where N
is the new reference clock frequency in MHz.
This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a
supported protocol, e.g., PCIe.
Table 53: GTH Transceiver PLL/Lock Time Adaptation

Symbol
Description
Conditions
TLOCK
Initial PLL lock
TDLOCK
Clock recovery phase acquisition and After the PLL is locked to

adaptation time for decision
the reference clock, this is
feedback equalizer (DFE).
the time it takes to lock
Clock recovery phase acquisition and the clock data recovery
adaptation time for low-power mode (CDR) to the data present
at the input.
(LPM) when the DFE is disabled.
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Units
Min
Typ
Max
ms
50,000
37 x 106
UI
50,000
2.3 x 106
UI
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Table 54: GTH Transceiver User Clock Switching Characteristics(1)
Symbol
Description
Data Width Conditions

(Bit)
Internal
Logic
Interconnect
Logic
Speed Grade
1.0V
0.95V
-3E
-2E, -2I
-1C, -1I,
-1LI
Units
FTXOUTPMA
TXOUTCLK maximum frequency sourced from

OUTCLKPMA
511.719
511.719
390.625
MHz
FRXOUTPMA
RXOUTCLK maximum frequency sourced from

OUTCLKPMA
511.719
511.719
390.625
MHz
FTXOUTPROGDIV

TXPROGDIVCLK
511.719
511.719
511.719
MHz
FRXOUTPROGDIV

RXPROGDIVCLK
511.719
511.719
511.719
MHz
FTXIN
TXUSRCLK
maximum
frequency
FRXIN
FTXIN2
FRXIN2
RXUSRCLK
maximum
frequency
TXUSRCLK2
maximum
frequency
RXUSRCLK2
maximum
frequency
16
16, 32
511.719
511.719
390.625
MHz
32
32, 64
511.719
511.719
390.625
MHz
20
20, 40
409.375
409.375
312.500
MHz
40
40, 80
409.375
409.375
312.500
MHz
16
16, 32
511.719
511.719
390.625
MHz
32
32, 64
511.719
511.719
390.625
MHz
20
20, 40
409.375
409.375
312.500
MHz
40
40, 80
409.375
409.375
312.500
MHz
16
16
511.719
511.719
390.625
MHz
16, 32
32
511.719
511.719
390.625
MHz
32
64
255.860
255.860
195.313
MHz
20
20
409.375
409.375
312.500
MHz
20, 40
40
409.375
409.375
312.500
MHz
40
80
204.688
204.688
156.250
MHz
16
16
511.719
511.719
390.625
MHz
16, 32
32
511.719
511.719
390.625
MHz
32
64
255.860
255.860
195.313
MHz
20
20
409.375
409.375
312.500
MHz
20, 40
40
409.375
409.375
312.500
MHz
40
80
204.688
204.688
156.250
MHz
Notes:
1.
Clocking must be implemented as described in UltraScale Architecture GTH Transceiver User Guide (UG576).
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Table 55: GTH Transceiver Transmitter Switching Characteristics
Symbol
Description
FGTHTX
Serial data rate range
TRTX
TX rise time
TFTX
TX fall time
Condition
Min
Typ
Max
Units
0.500
FGTHMAX
Gb/s
20%80%
40
ps
80%20%
40
ps
TLLSKEW
TX lane-to-lane
skew(1)
500
ps
VTXOOBVDPP
Electrical idle amplitude
15
mV
TTXOOBTRANSITION
Electrical idle transition time
140
ns
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.33
UI
0.17
UI
0.28
UI
0.17
UI
0.28
UI
0.17
UI
0.33
UI
0.17
UI
0.28
UI
0.17
UI
0.33
UI
0.17
UI
0.32
UI
0.17
UI
0.30
UI
0.15
UI
0.30
UI
0.15
UI
0.30
UI
0.15
UI
0.32
UI
0.16
UI
TJ16.3_QPLL
DJ16.3_QPLL
TJ15_QPLL
DJ15_QPLL
TJ14.1_QPLL
DJ14.1_QPLL
TJ14.025_QPLL
DJ14.025_QPLL
TJ13.1_QPLL
DJ13.1_QPLL
TJ12.5_QPLL
DJ12.5_QPLL
TJ12.5_CPLL
DJ12.5_CPLL
TJ11.3_QPLL
DJ11.3_QPLL
TJ10.3_QPLL
DJ10.3_QPLL
TJ10.3_CPLL
DJ10.3_CPLL
TJ9.8_QPLL
DJ9.8_QPLL
TJ9.8_CPLL
DJ9.8_CPLL
TJ8.0_CPLL
DJ8.0_CPLL
TJ6.6_CPLL
DJ6.6_CPLL
TJ5.0
DJ5.0
TJ4.25
DJ4.25
TJ4.0L
DJ4.0L
Total
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
Deterministic
Total
jitter(3)(4)
jitter(3)(4)
Deterministic
Total
jitter(3)(4)
jitter(3)(4)
Deterministic
Total
jitter(3)(4)
jitter(3)(4)
Deterministic
Total
jitter(3)(4)
jitter(3)(4)
Deterministic
Total
jitter(2)(4)
jitter(3)(4)
Deterministic
Total
jitter(3)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(3)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(3)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(3)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(3)(4)
jitter(3)(4)
Deterministic
DS893 (v1.2) July 27, 2015

jitter(3)(4)
16.3 Gb/s
15.0 Gb/s
14.1 Gb/s
14.025 Gb/s
13.1 Gb/s
12.5 Gb/s
12.5 Gb/s
11.3 Gb/s
10.3 Gb/s
10.3 Gb/s
9.8 Gb/s
9.8 Gb/s
8.0 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
4.0 Gb/s(5)
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Table 55: GTH Transceiver Transmitter Switching Characteristics (Contd)
Symbol
Description
TJ3.2
Total jitter(3)(4)
DJ3.2
Deterministic jitter(3)(4)
TJ2.5
Total jitter(3)(4)
DJ2.5
TJ1.25
Total jitter(3)(4)
DJ1.25
TJ500
Total jitter(3)(4)
DJ500
Deterministic
Condition
3.2 Gb/s(6)
2.5 Gb/s(7)
1.25 Gb/s(8)
500 Mb/s(9)
jitter(3)(4)
Min
Typ
Max
Units
0.20
UI
0.10
UI
0.20
UI
0.10
UI
0.15
UI
0.06
UI
0.10
UI
0.03
UI
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Using same REFCLK input with TX phase alignment enabled for up to four fully populated GTH Quads at maximum line rate.
Using QPLL_FBDIV = 40, 40-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
Using CPLL_FBDIV = 2, 40-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
All jitter values are based on a bit-error ratio of 10-12.
CPLL frequency at 2.0 GHz and TXOUT_DIV = 1.
Table 56: GTH Transceiver Receiver Switching Characteristics

Symbol
Description
Condition
FGTHRX
Serial data rate
TRXELECIDLE
Time for RXELECIDLE to respond to loss or restoration of

data
RXOOBVDPP
OOB detect threshold peak-to-peak
RXSST
Receiver spread-spectrum tracking(1) Modulated at 33 kHz
RXRL
Run length (CID)
Data/REFCLK PPM offset tolerance
RXPPMTOL
SJ Jitter
Min
Typ
Max
Units
0.500
FGTHMAX
Gb/s
10
ns
60
150
mV
5000
ppm
256
UI
Bit rates 6.6 Gb/s
1250
1250
ppm
Bit rates > 6.6 Gb/s

and 8.0 Gb/s
700
700
ppm
200
200
ppm
Tolerance(2)
JT_SJ16.3
Sinusoidal jitter (QPLL)(3)
16.3 Gb/s
0.30
UI
JT_SJ15
15.0 Gb/s
0.30
UI
JT_SJ14.1
14.1 Gb/s
0.30
UI
JT_SJ13.1
13.1 Gb/s
0.30
UI
JT_SJ12.5
12.5 Gb/s
0.30
UI
JT_SJ11.3
11.3 Gb/s
0.30
UI
JT_SJ10.3_QPLL
10.3 Gb/s
0.30
UI
JT_SJ10.3_CPLL
Sinusoidal jitter (CPLL)(3)
10.3 Gb/s
0.30
UI
JT_SJ9.8
9.8 Gb/s
0.30
UI
JT_SJ8.0_QPLL
8.0 Gb/s
0.44
UI
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Table 56: GTH Transceiver Receiver Switching Characteristics (Contd)
Symbol
Description
JT_SJ8.0_CPLL
JT_SJ6.6_CPLL
JT_SJ5.0
Min
Typ
Max
Units
8.0 Gb/s
0.42
UI
6.6 Gb/s
0.44
UI
5.0 Gb/s
0.44
UI
JT_SJ4.25
4.25 Gb/s
0.44
UI
JT_SJ4.0L
4.0 Gb/s(4)
0.45
UI
JT_SJ3.75
3.75 Gb/s
0.44
UI
JT_SJ3.2
3.2 Gb/s(5)
0.45
UI
JT_SJ2.5
Sinusoidal jitter
(CPLL)(3)
Gb/s(6)
0.50
UI
JT_SJ1.25
1.25 Gb/s(7)
0.50
UI
JT_SJ500
500 Mb/s
0.40
UI
3.2 Gb/s
0.70
UI
6.6 Gb/s
0.70
UI
3.2 Gb/s
0.10
UI
6.6 Gb/s
0.10
UI
SJ Jitter Tolerance with Stressed

JT_TJSE3.2
JT_TJSE6.6
JT_SJSE3.2
JT_SJSE6.6
Condition
2.5
Eye(2)
Total jitter with stressed eye(8)

Sinusoidal jitter with stressed eye(8)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using RXOUT_DIV = 1, 2, and 4.

All jitter values are based on a bit error ratio of 1012.
The frequency of the injected sinusoidal jitter is 10 MHz.
CPLL frequency at 2.0 GHz and RXOUT_DIV = 1.
Composite jitter with RX equalizer enabled. DFE disabled.
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GTH Transceiver Electrical Compliance

The UltraScale Architecture GTH Transceiver User Guide (UG576) contains recommended use modes that
ensure compliance for the protocols listed in Table 57. The transceiver wizard provides the recommended
settings for those use cases and for protocol specific characteristics.
Table 57: GTH Transceiver Protocol List
Protocol
Specification
Serial Rate (Gb/s)
Electrical
Compliance
CAUI-10
IEEE 802.3-2012
10.3125
Compliant
nPPI
IEEE 802.3-2012
10.3125
Compliant
10GBASE-KR
IEEE 802.3-2012
10.3125
Compliant
SFP+
SFF-8431 (SR and LR)
9.9532811.10
Compliant
XFP
INF-8077i, revision 4.5
10.3125
Compliant
RXAUI
CEI-6G-SR
6.25
Compliant
XAUI
IEEE 802.3-2012
3.125
Compliant
1000BASE-X
IEEE 802.3-2012
1.25
Compliant
OTU2
ITU G.8251
10.709225
Compliant
OTU4 (OTL4.10)
OIF-CEI-11G-SR
11.180997
Compliant
OC-3/12/48/192
GR-253-CORE
0.15559.956
Compliant
Interlaken
OIF-CEI-6G, OIF-CEI-11G-SR
4.2512.5
Compliant
PCIe Gen1, 2, 3
PCI Express Base 3.0
2.5, 5.0, and 8.0
Compliant
SDI
SMPTE 424M-2006
0.272.97
Compliant
Hybrid Memory Cube (HMC)
HMC-15G-SR
12.5 and 15.0
Compliant
CPRI
CPRI_v_6_1_2014-07-01
0.614412.165
Compliant
Passive Optical Network (PON)
10G-EPON, 1G-EPON, NG-PON2, XG-PON,

and 2.5G-PON
0.15510.3125
Compliant
JESD204a/b
OIF-CEI-6G, OIF-CEI-11G
3.12512.5
Compliant
Serial RapidIO
RapidIO Specification 3.1
1.2510.3125
Compliant
DisplayPort (Source Only)
DP 1.2B CTS
1.625.4
Compliant
Fibre Channel
FC-PI-4
1.062514.025
Compliant
SATA Gen1, 2, 3
Serial ATA Revision 3.0 Specification
1.5, 3.0, and 6.0
Compliant
SAS Gen1, 2, 3
T10/BSR INCITS 519
3.0, 6.0, and 12.0
Compliant
SFI-5
OIF-SFI5-01.0
0.62512.5
Compliant
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GTH Transceiver Protocol Jitter Characteristics

For Table 58 through Table 63, the UltraScale Architecture GTH Transceiver User Guide (UG576) contains
recommended settings for optimal usage of protocol specific characteristics.
Table 58: Gigabit Ethernet Protocol Characteristics (GTH Transceivers)
Description
Line Rate (Mb/s)
Min
Max
Units
1250
0.24
UI
0.749
UI
Line Rate (Mb/s)
Min
Max
Units
3125
0.35
UI
3125
0.65
UI
Gigabit Ethernet Transmitter Jitter Generation

Total transmitter jitter (T_TJ)
Gigabit Ethernet Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance
1250
Table 59: XAUI Protocol Characteristics (GTH Transceivers)

Description
XAUI Transmitter Jitter Generation
XAUI Receiver High Frequency Jitter Tolerance

Table 60: PCI Express Protocol Characteristics (GTH Transceivers)(1)

Standard
Description
Condition
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation

PCI Express Gen 1
Total transmitter jitter
2500
0.25
UI
PCI Express Gen 2
5000
0.25
UI
31.25
ps
12
ps
0.65
UI
0.40
UI
0.30
UI
1.00
UI
Note 3
UI
0.10
UI
PCI Express Gen 3(2)
Total transmitter jitter uncorrelated

Deterministic transmitter jitter uncorrelated
8000
PCI Express Receiver High Frequency Jitter Tolerance

PCI Express Gen 1
PCI Express Gen 2(2)
PCI Express Gen
3(2)

Receiver inherent timing error
Receiver inherent deterministic timing error
Receiver sinusoidal
jitter tolerance
2500
5000
0.03 MHz1.0 MHz

1.0 MHz10 MHz
10 MHz100 MHz
8000
Notes:
1.
2.
3.
Tested per card electromechanical (CEM) methodology.

Using common REFCLK.
Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
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Table 61: CEI-6G and CEI-11G Protocol Characteristics (GTH Transceivers)
Description
Line Rate (Mb/s)
Interface
Min
Max
Units
CEI-6G-SR
0.3
UI
CEI-6G-LR
0.3
UI
CEI-6G-SR
0.6
UI
CEI-6G-LR
0.95
UI
CEI-11G-SR
0.3
UI
CEI-11G-LR/MR
0.3
UI
CEI-11G-SR
0.65
UI
CEI-11G-MR
0.65
UI
CEI-11G-LR
0.825
UI
CEI-6G Transmitter Jitter Generation

Total transmitter jitter(1)
49766375
CEI-6G Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance(1)
49766375

995011100

995011100
Notes:
1.
2.
Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference
clock.
Table 62: SFP+ Protocol Characteristics (GTH Transceivers)

Description
Line Rate (Mb/s)
Min
Max
Units
0.28
UI
0.7
UI
SFP+ Transmitter Jitter Generation

9830.40(1)
9953.00
10312.50
10518.75
11100.00
SFP+ Receiver Frequency Jitter Tolerance

9830.40(1)
9953.00
10312.50
10518.75
11100.00
Notes:
1.
Line rated used for CPRI over SFP+ applications.
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Table 63: CPRI Protocol Characteristics (GTH Transceivers)
Description
Line Rate (Mb/s)
Min
Max
Units
614.4
0.35
UI
1228.8
0.35
UI
2457.6
0.35
UI
3072.0
0.35
UI
4915.2
0.3
UI
6144.0
0.3
UI
9830.4
Note 1
UI
614.4
0.65
UI
1228.8
0.65
UI
2457.6
0.65
UI
3072.0
0.65
UI
4915.2
0.95
UI
6144.0
0.95
UI
9830.4
Note 1
UI
CPRI Transmitter Jitter Generation
CPRI Receiver Frequency Jitter Tolerance
Notes:
1.
Tested per SFP+ specification, see Table 62.
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GTY Transceiver Specifications

GTY Transceiver DC Input and Output Levels
Table 64 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale FPGAs. Consult
www.xilinx.com/products/technology/high-speed-serial for further details.
Table 64: GTY Transceiver DC Specifications
Symbol
DC Parameter
Differential peak-to-peak input
voltage (external AC coupled)
DVPPIN
Conditions
Min
Typ
Max
Units
>10.3125 Gb/s
150
1250
mV
6.6 Gb/s to 10.3125 Gb/s
150
1250
mV
6.6 Gb/s
150
2000
mV
VIN
Single-ended input voltage.

Voltage measured at the pin
referenced to GND.
DC coupled
VMGTAVTT = 1.2V
400
VMGTAVTT
mV
VCMIN
Common mode input voltage
DC coupled
VMGTAVTT = 1.2V
2/3 VMGTAVTT
mV
DVPPOUT
Differential peak-to-peak output

voltage(1)
Transmitter output swing

is set to 0x1F
800
mV
VCMOUTDC

DC coupled
Equation based
VMGTAVTT DVPPOUT/4
mV
VCMOUTAC

AC coupled
Equation based
VMGTAVTT DVPPOUT/2
mV
RIN
100
ROUT
Differential output resistance
100
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
ps
100
nF
CEXT
Recommended external AC coupling
capacitor(2)
Notes:
1.
2.
The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes and can result in values
lower than reported in this table.
Other values can be used as appropriate to conform to specific protocols and standards.
+V
P
Single-Ended
Peak-to-Peak
Voltage
N
0
ds893_03_120314
Figure 6: Single-Ended Peak-to-Peak Voltage
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+V
Differential
Peak-to-Peak
Voltage
PN
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
ds893_04_120314
Figure 7: Differential Peak-to-Peak Voltage

Table 65 summarizes the DC specifications of the clock input of the GTY transceivers in Virtex UltraScale
FPGAs. Consult www.xilinx.com/products/technology/high-speed-serial for further details.
Table 65: GTY Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Min
Typ
Max
Units
250
2000
mV
VIDIFF
Differential peak-to-peak input voltage
RIN
100
CEXT
Required external AC coupling capacitor
10
nF
GTY Transceiver Switching Characteristics

Consult www.xilinx.com/products/technology/high-speed-serial for further information.
Table 66: GTY Transceiver Performance
Symbol
Description
Speed Grade
Output
Divider
1.0V
0.95V
Units
-3E
-2E, -2I
-1C,-1I,-1LI
FGTYMAX
GTY maximum line rate
30.5
28.21
12.5
Gb/s
FGTYMIN
GTY minimum line rate
0.5
0.5
0.5
Gb/s
FGTYCRANGE
FGTYQRANGE1
CPLL line rate

range(1)
QPLL0 line rate

range
DS893 (v1.2) July 27, 2015

Min
Max
Min
Max
Min
Max
4.0
12.5
4.0
12.5
4.0
8.5
Gb/s
2.0
6.25
2.0
6.25
2.0
4.25
Gb/s
1.0
3.125
1.0
3.125
1.0
2.125
Gb/s
0.5
1.5625
0.5
1.5625
0.5
1.0625
Gb/s
16
N/A
Gb/s
32
N/A
Gb/s
Min
Max
Min
Max
Min
Max
1(2)
19.6
30.5(3)
19.6
28.21
N/A
N/A
Gb/s
1(4)
9.8
16.375
9.8
16.375
9.8
12.5
Gb/s
2(4)
4.9
8.1875
4.9
8.1875
4.9
8.1875
Gb/s
4(4)
2.45
4.09375
2.45
4.09375
2.45
4.09375
Gb/s
8(4)
1.225
2.04688
1.225
2.04688
1.225
2.04688
Gb/s
16(4)
0.6125
1.02344
0.6125
1.02344
0.6125
1.02344
Gb/s
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Table 66: GTY Transceiver Performance (Contd)
Symbol
FGTYQRANGE2
Speed Grade
Output
Divider
Description
QPLL1 line rate

range
1.0V
0.95V
-3E
Units
-2E, -2I
-1C,-1I,-1LI
Min
Max
Min
Max
Min
Max
1(5)
16.0
26.0
16.0
26.0
N/A
N/A
Gb/s
1(6)
8.0
13.0
8.0
13.0
8.0
12.5
Gb/s
2(6)
4.0
6.5
4.0
6.5
4.0
6.5
Gb/s
4(6)
2.0
3.25
2.0
3.25
2.0
3.25
Gb/s
8(6)
1.0
1.625
1.0
1.625
1.0
1.625
Gb/s
16(6)
0.5
0.8125
0.5
0.8125
0.5
0.8125
Gb/s
Min
Max
Min
Max
Min
Max
FCPLLRANGE
CPLL frequency range
2.0
6.25
2.0
6.25
2.0
4.25
GHz
FQPLL0RANGE
9.8
16.375
9.8
16.375
9.8
16.375
GHz
FQPLL1RANGE
8.0
13.0
8.0
13.0
8.0
13.0
GHz
Notes:
1.
2.
3.
4.
5.
6.
The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
The values listed are the rounded results of the calculated equation (2 x QPLL0_Frequency)/Output_Divider. These values
are for line rates greater than 16.375 Gb/s.
This value is limited by FGTYMAX.
The values listed are rounded results from calculated equation (QPLL0_Frequency)/Output_Divider.
The values listed are the rounded results of the calculated equation (2 x QPLL1_Frequency)/Output_Divider. These values
are for line rates greater than 16.375 Gb/s.
The values listed are rounded results from calculated equation (QPLL1_Frequency)/Output_Divider.
Table 67: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTYDRPCLK
Description
All Speed Grades
Units
250
MHz
GTYDRPCLK maximum frequency
Table 68: GTY Transceiver Reference Clock Switching Characteristics

Symbol
Description
Conditions
All Speed Grades
Units
Min
Typ
Max
60
820
MHz
FGCLK
Reference clock frequency range
TRCLK
Reference clock rise time
20% 80%
200
ps
TFCLK
Reference clock fall time
80% 20%
200
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
40
50
60
TRCLK
80%
20%
TFCLK
ds893_05_120314
Figure 8: Reference Clock Timing Parameters
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Table 69: GTY Transceiver PLL/Lock Time Adaptation
Symbol
Description
All Speed Grades
Conditions
TLOCK
Initial PLL lock
TDLOCK
Clock recovery phase acquisition and After the PLL is locked to

adaptation time for decision
the reference clock, this is
feedback equalizer (DFE).
the time it takes to lock
Clock recovery phase acquisition and the clock data recovery
adaptation time for low-power mode (CDR) to the data present
at the input.
(LPM) when the DFE is disabled.
Units
Min
Typ
Max
ms
50,000
37 x 106
UI
50,000
2.3 x 106
UI
Table 70: GTY Transceiver User Clock Switching Characteristics(1)
Symbol
Description

(Bit)
Internal
Logic
Interconnect
Logic
Speed Grade
1.0V
0.95V
-3E
-2E, -2I
-1C, -1I,
-1LI
Units
FTXOUTPMA

OUTCLKPMA
511.719
511.719
390.625
MHz
FRXOUTPMA

OUTCLKPMA
511.719
511.719
390.625
MHz
FTXOUTPROGDIV

TXPROGDIVCLK
511.719
511.719
511.719
MHz
FRXOUTPROGDIV

RXPROGDIVCLK
511.719
511.719
511.719
MHz
FTXIN
FRXIN
FTXIN2
TXUSRCLK
maximum
frequency
RXUSRCLK
maximum
frequency
TXUSRCLK2
maximum
frequency
DS893 (v1.2) July 27, 2015

16
16, 32
511.719
511.719
390.625
MHz
32
32, 64
511.719
511.719
390.625
MHz
64
64, 128
476.563
440.781
195.313
MHz
20
20, 40
409.375
409.375
312.500
MHz
40
40, 80
409.375
409.375
312.500
MHz
80
80, 160
381.250
352.625
156.250
MHz
16
16, 32
511.719
511.719
390.625
MHz
32
32, 64
511.719
511.719
390.625
MHz
64
64, 128
476.563
440.781
195.313
MHz
20
20, 40
409.375
409.375
312.500
MHz
40
40, 80
409.375
409.375
312.500
MHz
80
80, 160
381.250
352.625
156.250
MHz
16
16
511.719
511.719
390.625
MHz
20
20
409.375
409.375
312.500
MHz
16, 32
32
511.719
511.719
390.625
MHz
20, 40
40
409.375
409.375
312.500
MHz
32, 64
64
476.563
440.781
195.313
MHz
40, 80
80
381.250
352.625
156.250
MHz
64
128
238.281
220.391
97.656
MHz
80
160
190.625
176.313
78.125
MHz
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Table 70: GTY Transceiver User Clock Switching Characteristics(1)
Symbol
FRXIN2
Speed Grade

(Bit)
Description
RXUSRCLK2
maximum
frequency
1.0V
0.95V
Units
Internal
Logic
Interconnect
Logic
-3E
-2E, -2I
-1C, -1I,
-1LI
16
16
511.719
511.719
390.625
MHz
20
20
409.375
409.375
312.500
MHz
16, 32
32
511.719
511.719
390.625
MHz
20, 40
40
409.375
409.375
312.500
MHz
32, 64
64
476.563
440.781
195.313
MHz
40, 80
80
381.250
352.625
156.250
MHz
64
128
238.281
220.391
97.656
MHz
80
160
190.625
176.313
78.125
MHz
Notes:
1.
Clocking must be implemented as described in the UltraScale Architecture GTY Transceiver User Guide (UG578).
Table 71: GTY Transceiver Transmitter Switching Characteristics

Symbol
Description
FGTYTX
Serial data rate range
TRTX
TX rise time
TFTX
TX fall time
Condition
Min
Typ
Max
Units
0.500
FGTYMAX
Gb/s
20%80%
40
ps
80%20%
40
ps
TLLSKEW
TX lane-to-lane
skew(1)
500
ps
VTXOOBVDPP
Electrical idle amplitude
15
mV
TTXOOBTRANSITION
Electrical idle transition time
140
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
TJ30.5
DJ30.5
TJ16.375
DJ16.375
TJ12.5
DJ12.5
TJ11.3
DJ11.3
TJ10.3125_QPLL
DJ10.3125_QPLL
TJ10.3125_CPLL
DJ10.3125_CPLL
TJ9.953
DJ9.953
TJ9.8
DJ9.8
TJ8.0_QPLL
DJ8.0_QPLL
Total
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(3)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(3)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
Deterministic
Total
jitter(2)(4)
jitter(2)(4)
jitter(2)(4)
Deterministic
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30.5 Gb/s
16.375 Gb/s
12.5 Gb/s
11.3 Gb/s
10.3125 Gb/s
10.3125 Gb/s
9.953 Gb/s
9.8 Gb/s
8.0 Gb/s
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Table 71: GTY Transceiver Transmitter Switching Characteristics (Contd)
Symbol
Description
TJ8.0_CPLL
Total jitter(3)(4)
DJ8.0_CPLL
TJ6.6_CPLL
Total jitter(3)(4)
DJ6.6_CPLL
TJ5.0
Total jitter(3)(4)
DJ5.0
TJ4.25
Total jitter(3)(4)
DJ4.25
TJ3.75
Total jitter(3)(4)
DJ3.75
jitter(3)(4)
TJ3.20
Total
DJ3.20
TJ3.20L
Total jitter(3)(4)
jitter(3)(4)
DJ3.20L
Deterministic
TJ2.5
Total jitter(3)(4)
DJ2.5
jitter(3)(4)
TJ1.25
Total
DJ1.25
TJ500
Total jitter(3)(4)
DJ500
Condition
8.0 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s(5)
3.20 Gb/s(6)
2.5 Gb/s(7)
1.25 Gb/s(8)
500 Mb/s
Min
Typ
Max
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using same REFCLK input with TX phase alignment enabled for up to four fully-populated GTY Quads at maximum line rate.
Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
All jitter values are based on a bit-error ratio of 10-12.
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Table 72: GTY Transceiver Receiver Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
Units
0.500
FGTYMAX
Gb/s
10
ns
60
150
mV
5000
ppm
256
UI
Bit rates 6.6 Gb/s
1250
1250
ppm

and 8.0 Gb/s
700
700
ppm
200
200
ppm
FGTYRX
Serial data rate
TRXELECIDLE
Time for RXELECIDLE to respond to loss or restoration of

data
RXOOBVDPP
OOB detect threshold peak-to-peak
RXSST
Receiver spread-spectrum
RXRL
Run length (CID)
RXPPMTOL
tracking(1)
Data/REFCLK PPM offset tolerance
Modulated at 33 kHz
SJ Jitter Tolerance(2)
JT_SJ30.5
30.5 Gb/s
UI
JT_SJ16.375
16.375 Gb/s
UI
JT_SJ12.5
12.5 Gb/s
UI
JT_SJ11.3
11.3 Gb/s
UI
JT_SJ10.32_QPLL
10.32 Gb/s
UI
JT_SJ10.32_CPLL
10.32 Gb/s
UI
JT_SJ9.8
9.8 Gb/s
UI
JT_SJ8.0_QPLL
8.0 Gb/s
UI
JT_SJ8.0_CPLL
8.0 Gb/s
UI
JT_SJ6.6_CPLL
6.6 Gb/s
UI
JT_SJ5.0
5.0 Gb/s
UI
JT_SJ4.25
4.25 Gb/s
UI
JT_SJ3.75
3.75 Gb/s
UI
JT_SJ3.2
3.2 Gb/s(4)
UI
JT_SJ3.2L
3.2 Gb/s(5)
UI
JT_SJ2.5
2.5 Gb/s(6)
UI
JT_SJ1.25
1.25 Gb/s(7)
UI
JT_SJ500
500 Mb/s
UI
3.2 Gb/s
UI
6.6 Gb/s
UI
3.2 Gb/s
UI
6.6 Gb/s
UI
SJ Jitter Tolerance with Stressed Eye(2)

JT_TJSE3.2
JT_TJSE6.6
JT_SJSE3.2
JT_SJSE6.6
Total jitter with stressed eye(8)

Sinusoidal jitter with stressed eye(8)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using RXOUT_DIV = 1, 2, and 4.

All jitter values are based on a bit error ratio of 1012.
The frequency of the injected sinusoidal jitter is 80 MHz.
Composite jitter with RX equalizer enabled. DFE disabled.
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GTY Transceiver Electrical Compliance

The UltraScale Architecture GTY Transceiver User Guide (UG578) contains recommended use modes that
ensure compliance for the protocols listed in Table 73. The transceiver wizard provides the recommended
settings for those use cases and for protocol specific characteristics.
Table 73: GTY Transceiver Protocol List
Protocol
Specification
Serial Rate
(Gb/s)
Electrical
Compliance
CAUI-4
IEEE 802.3-2012
25.78125
Compliant
28 Gb/s Backplane
CEI-25G-LR
2528.05
Compliant
Interlaken
OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR 4.2525.78125
100GBASE-KR4
IEEE 802.3bj-2014, CEI-25G-LR
25.78125
OTU4 (OTL4.4)
OIF-CEI-28G-VSR
27.952493
Compliant
CAUI-10
IEEE 802.3-2012
10.3125
Compliant
nPPI
IEEE 802.3-2012
10.3125
Compliant
10GBASE-KR
IEEE 802.3-2012
10.3125
Compliant
SFP+
SFF-8431 (SR and LR)
9.9532811.10
Compliant
XFP
INF-8077i, Revision 4.5
10.3125
Compliant
RXAUI
CEI-6G-SR
6.25
Compliant
XAUI
IEEE 802.3-2012
3.125
Compliant
1000BASE-X
IEEE 802.3-2012
1.25
Compliant
OTU2
ITU G.8251
10.709225
Compliant
OTU4 (OTL4.10)
OIF-CEI-11G-SR
11.180997
Compliant
OC-3/12/48/192
GR-253-CORE
0.15559.956
Compliant
PCIe Gen1, 2, 3
PCI Express Base 3.0
2.5, 5.0, and 8.0
Compliant
SDI
SMPTE 424M-2006
0.272.97
Compliant
Hybrid Memory Cube (HMC)
HMC-15G-SR
12.5 and 15.0
Compliant
CPRI
CPRI_v_6_1_2014-07-01
0.614412.165
Compliant
Passive Optical Network (PON)
10G-EPON, 1G-EPON, NG-PON2, XG-PON, and

2.5G-PON
0.15510.3125
Compliant
JESD204a/b
OIF-CEI-6G, OIF-CEI-11G
3.12512.5
Compliant
Serial RapidIO
RapidIO Specification 3.1
1.2510.3125
Compliant
DisplayPort (Source Only)
DP 1.2B CTS
1.625.4
Compliant
Fibre Channel
FC-PI-4
1.062514.025
Compliant
SATA Gen1, 2, 3
Serial ATA Revision 3.0 Specification
1.5, 3.0, and 6.0
Compliant
SAS Gen1, 2, 3
T10/BSR INCITS 519
3.0, 6.0, and 12.0
Compliant
SFI-5
OIF-SFI5-01.0
0.625 - 12.5
Compliant
Compliant
Compliant(1)
Notes:
1.
25 dB loss at Nyquist without FEC.
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GTY Transceiver Protocol Jitter Characteristics

For Table 74 through Table 78, the UltraScale Architecture GTY Transceiver User Guide (UG578) contains
recommended settings for optimal usage of protocol specific characteristics.
Table 74: Gigabit Ethernet Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
Min
Max
Units
1250
0.24
UI
0.749
UI
Line Rate (Mb/s)
Min
Max
Units
3125
0.35
UI
3125
0.65
UI
Gigabit Ethernet Transmitter Jitter Generation

Gigabit Ethernet Receiver High Frequency Jitter Tolerance

1250
Table 75: XAUI Protocol Characteristics (GTY Transceivers)

Description
XAUI Transmitter Jitter Generation
XAUI Receiver High Frequency Jitter Tolerance

Table 76: CEI-6G and CEI-11G Protocol Characteristics (GTY Transceivers)

Description
Line Rate (Mb/s)
Interface
Min
Max
Units
CEI-6G-SR
0.3
UI
CEI-6G-LR
0.3
UI
CEI-6G-SR
0.6
UI
CEI-6G-LR
0.95
UI
CEI-11G-SR
0.3
UI
CEI-11G-LR/MR
0.3
UI
0.65
UI

49766375

49766375

995011100

CEI-11G-SR
995011100
CEI-11G-MR
0.65
UI
CEI-11G-LR
0.825
UI
Notes:
1.
2.
Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference
clock.
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Table 77: SFP+ Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
Min
Max
Units
0.28
UI
0.7
UI
Line Rate (Mb/s)
Min
Max
Units
614.4
0.35
UI
1228.8
0.35
UI
2457.6
0.35
UI
3072.0
0.35
UI
4915.2
0.3
UI
6144.0
0.3
UI
9830.4
Note 1
UI
614.4
0.65
UI
1228.8
0.65
UI
2457.6
0.65
UI
3072.0
0.65
UI
4915.2
0.95
UI
6144.0
0.95
UI
9830.4
Note 1
UI
SFP+ Transmitter Jitter Generation

9830.40(1)
9953.00
10312.50
10518.75
11100.00
SFP+ Receiver Frequency Jitter Tolerance

9830.40(1)
9953.00
10312.50
10518.75
11100.00
Notes:
1.
Line rated used for CPRI over SFP+ applications.
Table 78: CPRI Protocol Characteristics (GTY Transceivers)

Description
CPRI Transmitter Jitter Generation
CPRI Receiver Frequency Jitter Tolerance
Notes:
1.
Tested per SFP+ specification, see Table 77.
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Integrated Interface Block for Interlaken

More information and documentation on solutions using the integrated interface block for Interlaken can
be found at www.xilinx.com/technology/protocols/interlaken.htm. The UltraScale Architecture and Product
Overview (DS890) lists the Virtex UltraScale FPGAs that include this block.
Table 79: Maximum Performance for Interlaken Designs
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
FRX_SERDES_CLK Receive serializer/ deserializer clock
402.84
402.84
195.32
MHz
FTX_SERDES_CLK Transmit serializer/ deserializer clock
402.84
402.84
195.32
MHz
FDRP_CLK
250.00
250.00
250.00
MHz
Dynamic reconfiguration port clock
Min
300.00(1)
FCORE_CLK
Interlaken core clock
FLBUS_CLK
Interlaken local bus clock
412.50(2)
300.00
Max
Min
429.69
300.00(1)
412.50(2)
349.52
300.00
Max
Min
Max
429.69 300.00 322.27
MHz
349.52 300.00 322.27
MHz
Notes:
1.
2.
The minimum value for CORE_CLK is 300 MHz for the 12 x 12.5G Interlaken configuration.
The minimum value for CORE_CLK is 412.5 MHz for the 6 x 25.78125G Interlaken configuration. This 6 x 25.78125G
configuration is not supported in the lane logic-only mode.
Integrated Interface Block for 100G Ethernet MAC and PCS

More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be
found at www.xilinx.com/technology/protocols/100g-ethernet.htm.
Table 80: Maximum Performance for 100G Ethernet Designs
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
FTX_CLK
Transmit clock
322.27
322.27
322.27
MHz
FRX_CLK
Receive clock
322.27
322.27
322.27
MHz
FRX_SERDES_CLK
Receive serializer/deserializer clock
322.27
322.27
322.27
MHz
FDRP_CLK
Dynamic reconfiguration port clock
250.00
250.00
250.00
MHz
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Integrated Interface Block for PCI Express Designs

More information and documentation on solutions for PCI Express designs can be found at:
www.xilinx.com/technology/protocols/pciexpress.htm.
Table 81: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
FPIPECLK
Description
1.0V
Pipe clock maximum frequency
0.95V
Units
-3
-2
-1
-1L
250.00
250.00
250.00
250.00
MHz
250.00
MHz
FCORECLK
Core clock maximum frequency
500.00
500.00
500.00(1)
FUSERCLK
User clock maximum frequency
250.00
250.00
250.00
250.00
MHz
FDRPCLK
DRP clock maximum frequency
250.00
250.00
250.00
250.00
MHz
Notes:
1.
PCI Express x8 Gen3 operation is supported in -2 and -3 speed grades. Refer to the UltraScale Architecture Gen3
Integrated Block for PCI Express v4.0 User Guide (PG156) for information regarding x8 Gen 3 operation in the -1 speed
grade.
System Monitor Specifications

Table 82: SYSMON Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V 3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = 40C to 100C, typical values at Tj = 40C
ADC Accuracy(1)
Resolution
10
Bits
LSBs
No missing codes, guaranteed

monotonic
LSBs
Offset calibration enabled
LSBs
Gain error
0.4
Sample rate
0.2
MS/s
External 1.25V reference
LSBs
On-chip reference
LSBs
(Tj = 55C to 125C)
10
Bits
Integral
nonlinearity(2)
Differential nonlinearity
INL
DNL
Offset error
RMS code noise
ADC Accuracy at Extended Temperatures

Resolution
Integral nonlinearity
INL
(Tj = 55C to 125C)
Differential nonlinearity
DNL
No missing codes, guaranteed

monotonic. (Tj = 55C to 125C)
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Table 82: SYSMON Specifications (Contd)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
0.5
+0.5
Unipolar common mode range (FS input)
+0.5
Bipolar common mode range (FS input)
+0.5
+0.6
Adjacent channels set within these

ranges should not corrupt
measurements on adjacent channels
0.1
VCCADC
Tj = 40C to 100C (with external REF)
4.5
Tj = 40C to 100C (with internal REF)
6.5
1.5
2.5
Analog Inputs(2)
Unipolar operation
Bipolar operation
ADC input ranges
Maximum external channel input

ranges
On-Chip Sensor Accuracy
Temperature sensor error(1)
Supply sensor error(3)
Conversion
Rate(4)
Conversion timecontinuous tCONV
Number of ADCCLK cycles
26
32
Cycles
Conversion timeevent
tCONV
Number of ADCCLK cycles
21
Cycles
DRP clock frequency
DCLK
DRP clock frequency
250
MHz
ADC clock frequency
ADCCLK Derived from DCLK
5.2
MHz
40
60
1.20
1.25
1.30
Ground VREFP pin to AGND,

-2 and -3 speed grades
Tj = 40C to 100C
1.2375
1.25
1.2625

-1 and -1L speed grades
Tj = 40C to 100C
1.23125
1.25
1.26875

Tj = 55C to 125C
1.225
1.25
1.275
DCLK duty cycle
SYSMON
Reference(5)
External reference
On-chip reference
VREFP
Externally supplied reference voltage
Notes:
1.
2.
3.
4.
5.
ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when
this feature is enabled.
See the Analog Input section in the UltraScale Architecture System Monitor User Guide (UG580).
Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values
are specified for when this feature is enabled.
See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580).
Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the
ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power
supply). However, for external ratiometric type applications allowing reference to vary by 4% is permitted.
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I2C Interfaces
Table 83: I2C Fast Mode Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
TDCFCLK
SCL duty cycle
50
TFCKO
SDAO clock-to-out delay
900
ns
TFDCK
SDAI setup time
100
ns
FFCLK
SCL clock frequency
400
kHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
SCL
TFDCK
SDAI
TFCKO
SDAO
DS893_06_120314
Figure 9: I2C Fast Mode Interface Timing Diagram

Table 84: I2C Standard Mode Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
TDCSCLK
SCL duty cycle
50
TSCKO
SDAO clock-to-out delay
3450
ns
TSDCK
SDAI setup time
250
ns
FSCLK
SCL clock frequency
100
kHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
SCL
TSDCK
SDAI
TSCKO
SDAO
DS893_07_120314
Figure 10: I2C Standard Mode Interface Timing Diagram
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Configuration Switching Characteristics

Table 85: Configuration Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
Program latency
7.5
7.5
7.5
ms, Max
Power-on reset
(40 ms maximum ramp rate time)
57
57
57
ms, Max
ms, Min
Power-on reset with POR override

(2 ms maximum ramp rate time)
15
15
15
ms, Max
ms, Min
250
250
250
ns, Min
Power-up Timing Characteristics

TPL
TPOR
TPROGRAM
Program pulse width
CCLK Output (Master Mode)

TICCK
Master CCLK output delay from INIT_B
150
150
150
ns, Min
TMCCKL
Master CCLK clock Low time duty cycle
40/60
40/60
40/60
%, Min/Max
TMCCKH
Master CCLK clock High time duty cycle
40/60
40/60
40/60
%, Min/Max
SPI x2/x4/x8
BPI
150.00
150.00
150.00
MHz, Max
SPI x1 serial
SLR-based devices
125.00
125.00
125.00
MHz, Max
SPI x1 serial
All other devices
150.00
150.00
150.00
MHz, Max
SelectMAP
125.00
125.00
125.00
MHz, Max
FMCCK
Master CCLK frequency
FMCCK_START
Master CCLK frequency at start of configuration
3.00
3.00
3.00
MHz, Typ
FMCCKTOL
Frequency tolerance, master mode with respect to

nominal CCLK
35
35
35
%, Max
CCLK Input (Slave Modes)

TSCCKL
Slave CCLK clock minimum Low time
2.5
2.5
2.5
ns, Min
TSCCKH
Slave CCLK clock minimum High time
2.5
2.5
2.5
ns, Min
Serial
SLR-based devices
125.00
125.00
125.00
MHz, Max
Serial
All other devices
150.00
150.00
150.00
MHz, Max
SelectMAP
125.00
125.00
125.00
MHz, Max
FSCCK
Slave CCLK frequency
EMCCLK Input (Master Mode)

TEMCCKL(1)
External master CCLK Low time
2.50
2.50
2.50
ns, Min
TEMCCKH(1)
External master CCLK High time
2.50
2.50
2.50
ns, Min
125.00
125.00
125.00
MHz, Max
150.00
150.00
150.00
MHz, Max
125.00
125.00
125.00
MHz, Max
Serial
SLR-based devices
FEMCCK
External master CCLK frequency Serial

All other devices
SelectMAP
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Table 85: Configuration Switching Characteristics (Contd)
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
Master SLR ICAP

accessing the entire
device
125.00
125.00
125.00
MHz, Max
SLR ICAP accessing

the local SLR
200.00
200.00
200.00
MHz, Max
All other devices
200.00
200.00
200.00
MHz, Max
3.0/0
3.0/0
3.0/0
ns, Min
8.0
8.0
8.0
ns, Max
3.5/0
3.5/0
3.5/0
ns, Min
4.0/0
4.0/0
4.0/0
ns, Min
10.0/0
10.0/0
10.0/0
ns, Min
Internal Configuration Access Port
FICAPCK
Internal configuration access

port (ICAPE3)
Master/Slave Serial Mode Programming Switching

TDCCK/TCCKD
DIN setup/hold
TCCO
DOUT clock to out
SelectMAP Mode Programming Switching

TSMDCCK/TSMCCKD
D[31:00] setup/hold
TSMCSCCK/TSMCCKCS CSI_B setup/hold

TSMWCCK/TSMCCKW
RDWR_B setup/hold
TSMCKCSO
CSO_B clock to out (330 pull-up resistor required)
7.0
7.0
7.0
ns, Max
TSMCO
D[31:00] clock to out in readback
8.0
8.0
8.0
ns, Max
FRBCCK
Readback frequency
SLR-based devices
All other devices
MHz, Max
125.00
125.00
125.00
MHz, Max
Boundary-Scan Port Timing Specifications

SLR-based devices
TTAPTCK/TTCKTAP
TMS and TDI setup/hold
TTCKTDO
TCK falling edge to TDO output
FTCK
TCK frequency
All other devices
ns, Min
3.0/2.0
3.0/2.0
3.0/2.0
SLR-based devices
All other devices
ns, Min
ns, Max
7.0
7.0
7.0
ns, Max
SLR-based devices
20.00
20.00
20.00
MHz, Max
All other devices
66.00
66.00
66.00
MHz, Max
BPI Master Flash Mode Programming Switching

TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B

clock to out
10.0
10.0
10.0
ns, Max
TBPIDCC/TBPICCD
D[15:00] setup/hold
3.5/0
3.5/0
3.5/0
ns, Min
SPI Master Flash Mode Programming Switching

TSPIDCC/TSPICCD
D[03:00] setup/hold
3.0/0
3.0/0
3.0/0
ns, Min
TSPIDCC/TSPICCD
D[07:04] setup/hold
3.5/0
3.5/0
3.5/0
ns, Min
TSPICCM
MOSI clock to out
8.0
8.0
8.0
ns, Max
TSPICCFC
FCS_B clock to out
8.0
8.0
8.0
ns, Max
200.00
200.00
200.00
MHz, Max
DNA Port Switching

FDNACK
DNA port frequency
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Table 85: Configuration Switching Characteristics (Contd)
Speed Grade
Symbol
Description
1.0V
0.95V
Units
-3
-2
-1/-1L
STARTUPE3 Ports
TUSRCCLKO
STARTUPE3 USRCCLKO input port to CCLK pin output

delay
1.00/
6.00
1.00/
6.70
1.00/
7.50
ns, Min/Max
TDO
DO[3:0] ports to D03-D00 pins output delay
1.00/
6.70
1.00/
7.70
1.00/
8.40
ns, Min/Max
TDTS
DTS[3:0] ports to D03-D00 pins 3-state delays
1.00/
7.30
1.00/
8.30
1.00/
9.00
ns, Min/Max
TFCSBO
FCSBO port to FCS_B pin output delay
1.00/
6.90
1.00/
8.00
1.00/
8.60
ns, Min/Max
TFCSBTS
FCSBTS port to FCS_B pin 3-state delay
1.00/
6.90
1.00/
8.00
1.00/
8.60
ns, Min/Max
TUSRDONEO
USRDONEO port to DONE pin output delay
1.00/
8.50
1.00/
9.60
1.00/
10.40
ns, Min/Max
TUSRDONETS
USRDONETS port to DONE pin 3-state delay
1.00/
8.50
1.00/
9.60
1.00/
10.40
ns, Min/Max
TDI
D03-D00 pins to DI[3:0] ports input delay
0.5/2.6
0.5/3.1
FCFGMCLK
STARTUPE3 CFGMCLK output frequency
50.00
50.00
50.00
MHz, Typ
FCFGMCLKTOL
STARTUPE3 CFGMCLK output frequency tolerance
15
15
15
%, Max
0.5/3.5 ns, Min/Max
Notes:
1.
When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet these low
time and high time requirements.
eFUSE Programming Conditions

Table 86: eFUSE Programming Conditions(1)
Symbol
Description
IFS
VCCAUX supply current
Tj
Temperature range
Min
Typ
Max
Units
115
mA
40
125
Notes:
1.
Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when
readback CRC is active).
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Revision History
The following table shows the revision history for this document.
Date
Version
Description of Revisions
07/27/2015
1.2
In Table 18 and Table 19 updated Note 2, Note 3, and Note 4.

Updated Table 20 and Table 38 through Table 43 with speed specifications for Vivado
Design Suite 2015.2 v1.16.
Updated the STARTUPE3 Ports descriptions in Table 85. Updated Note 1 in Table 86.
05/29/2015
1.1
Entire data sheet is updated. Some of the highlights are noted in this revision history
although it is not comprehensive.
Updated Note 2 and Note 3 in Table 1 and Note 3, Note 4, and Note 6 in Table 2. Added
data and Note 2 to Table 3. Updated Note 3 in Table 6. Revised the Power-On/Off Power
Supply Sequencing section. Updated the descriptions in Table 8. Revised the VOCM
maximum for MINI_LVDS_25 and RSDS_25 in Table 12. Revised the VICM specifications
in Table 14. Removed rows from Table 16 and Table 17. Removed VOH and VOL rows,
revised the VOCM maximum, and revised VICM in Table 18. Removed VOH and VOL rows
and revised VICM in Table 19. Updated Table 20, Table 27, and Table 28 with speed
specifications for Vivado Design Suite 2015.1 v1.15. Added Note 1 to Table 29.
Added the section: I/O Standard Adjustment Measurement Methodology. Updated
FREFCLK in Table 33. Revised MMCM_FINMAX and MMCM_TLOCKMAX in Table 36. Updated the
descriptions and PLL_FINMAX in Table 37. Added a discussion on the data in the device
pin-to-pin parameter tables on page 39 and page 41. Updated Table 44. Updated the
package information in Table 45. Updated VCMOUTDC and added Note 2 in Table 46. Added
Table 48 and Table 52. Updated both Table 55 and Table 56. Updated and combined the
protocol characteristic sections into the GTH Transceiver Electrical Compliance section.
Updated some of the maximum values for FGTYMAX, FGTYQRANGE1, and FGTYQRANGE2 in
Table 66. Updated FRXIN2 (data width conditions for internal logic) in Table 70. Updated
and combined the protocol characteristic sections into the GTY Transceiver Electrical
Compliance section. Revised the values for FLBUS_CLK in Table 79. Revised FCORECLK and
Note 1 in Table 81. Updated the On-Chip Sensor Accuracy, On-chip reference, and Note 5
in Table 82. In Table 85, added more speed specifications, updated TPOR, TPL, FMCCKTOL,
and FRBCCK, added the STARTUPE3 Ports section, and added Note 1.
07/10/2014
1.0
Initial Xilinx release.
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The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect,
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been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to
notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display
the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinxs limited warranty,
please refer to Xilinxs Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty
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Automotive Applications Disclaimer

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS
THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO
IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD
TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN
SUCH APPLICATIONS.
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Virtex UltraScale FPGAs Data Sheet:

DC and AC Switching Characteristics

Advance Product Specification

Internal supply voltage

Internal supply voltage for the I/O banks

Auxiliary supply voltage

Supply voltage for the block RAM memories

Output drivers supply voltage for HR I/O banks

Output drivers supply voltage for HP I/O banks

Auxiliary supply voltage for the I/O banks

Input reference voltage

I/O input voltage for HR I/O banks(5)

I/O input voltage for HP I/O banks

Key memory battery backup supply

DS893 (v1.2) July 27, 2015

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics

Available output current at the pad

Available RMS output current at the pad

GTH or GTY Transceiver

Analog supply voltage for the GTH or GTY transmitter and

Analog supply voltage for the GTH or GTY transmitter and

GTH or GTY transceiver reference clock absolute input voltage

Analog supply voltage for the resistor calibration circuit of the

Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input

DC input current for receiver input pins DC coupled RX

DC input current for receiver input pins DC coupled RX

DC input current for receiver input pins DC coupled RX

DC input current for receiver input pins DC coupled RX

DC output current for transmitter pins DC coupled RX

DC output current for transmitter pins DC coupled RX

System Monitor supply relative to GNDADC

System Monitor reference input relative to GNDADC

DS893 (v1.2) July 27, 2015

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics

Storage temperature (ambient)

Table 2: Recommended Operating Conditions(1)(2)

Internal supply voltage

For -3 (1.0V only) devices: Internal supply voltage

Internal supply voltage for the I/O banks

For -3 (1.0V only) devices: internal supply voltage for the

Block RAM supply voltage

For -3 (1.0V only) devices: block RAM supply voltage

Auxiliary supply voltage

Supply voltage for HR I/O banks

Supply voltage for HP I/O banks

Auxiliary I/O supply voltage

I/O input voltage

I/O input voltage (when VCCO = 3.3V) for VREF and

Maximum current through any pin in a powered or

GTH or GTY Transceiver

Analog supply voltage for the GTH or GTY transceiver

Analog supply voltage for the GTH or GTY transmitter and

Auxiliary analog QPLL voltage supply for the transceivers

DS893 (v1.2) July 27, 2015

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics

Analog supply voltage for the resistor calibration circuit of

SYSMON supply relative to GNDADC

Externally supplied reference voltage

Junction temperature operating range for commercial (C)

Junction temperature operating range for extended (E)