Draw The Block Diagram of Von Neumann Architecture and Explain About Its Parts in Brief Answer
Draw The Block Diagram of Von Neumann Architecture and Explain About Its Parts in Brief Answer
Draw The Block Diagram of Von Neumann Architecture and Explain About Its Parts in Brief Answer
Answer
Arithmetic and
Logic unit
I/O Equipment
Main Memory
Main memory:
Main memory stores both instructions and data
Arithmetic logic unit (ALU):
Capable of operating on binary data i.e. performs all the arithmetic operations
Control unit:
Control unit interprets the instructions in memory and causes them to be executed
I/O equipment:
Input/output equipment unit operated by the control unit.
CPU
PC
MAR
MBR
IR
I/O AR
ALU
I/O BR
Draw the block diagram of Intel 8085 CPU organization and explain the different flag bits supported by the
8085 CPU
Answer
Internal CPU Bus
Accumulator
Temp reg
Flags
Instruction
register
ALU
Control
Unit
B reg
C reg
D reg
E reg
H reg
L reg
Stack pointer
Program counter
Address
buffer
Address/ data
buffer
Address Bus
Address/data bus
Control Bus
Explain direct addressing mode and Register addressing Mode with example
Answer
Direct addressing mode: algorithm defined as EA = A , where EA= actual address of the location containing the
reference operand. And A = contents of the address field in the instruction.
In direct addressing mode address fiels contains address of operand
e.g ADD A
Add contents of cell A to accumulator.
Look in the memory at address A for operand
It gives single memory reference to access data
Limited address space.
M1
MA
M2
MD
MA
M3
MD
MA
M4
MD
MA
MD
As from the figure main memory is divided into 4 different modules. When an instruction FETCH is issued by
processor, a memory access circuit creates four consecutive addresses and places them in four MARs. A
memory read command reads all the four modules simultaneously and retrieves four instructions. These are
sent to processor. Thus each FETCH instruction fetches 4 consecutive instructions.
S1
S2
Sk
Output
Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. Pipelining
is the key implantation technique used to make fast CPUs.
To achieve pipelining , one must subdivide the input task (process) into a sequence of subtasks , each of which
can be executed by a specialized hardware stage that operates concurrently with other stage in the pipeline.
As from above figure : the pipeline consist of a cascade of processing stages . the stages are pure combinational
circuits performing arithmetic or logical operations over the data stream flowing through the pipe. The stages
are separated high speed interface latches separate the stages. The latches are fast registers for holding the
intermediate results between the stages. Information that flows between adjacent stages are under the control
of a common clock applied to all the latches simultaneously.
Draw the I/O module of computer system and explain its functions
Answer
System Bus interface
Data register
Data Lines
Status/control register
Address
lines
Data
Lines
Data
Status
Control
Input/Output
Logic
External
Device
interface
logic
Data
Status
Control
It is an entity within a computer that is responsible for the control of one or more external devices and
exchange of data between those devices and main memory or CPU.I/O module may control more than one
external device. We usually refer to each of the interface of the external device as a port. I/O modules also
sends interrupt signal to the CPU.
Following are the sequence of operation:
CPU checks I/O module device status
I/O module returns device status
If ready , CPU requests data transfer
I/O module gets data from device
I/O module transfers data to CPU
Status register
Mask register
DMA Channel
Base count
Current count
CPU
Base address
Current
address
Bus request
Bus grant
DACKX
DRQX
TC
PC BUS
A DMA controller is a device, usually peripheral to a computer CPU that is programmed to perform a sequence
of data transfer on behalf of the CPU. A DMA controller can directly access memory and is used to transfer data
from one memory location to another or from an I/O device to memory and vice-versa. A DMA controller
manages several DMA channels, each of which can be programmed to perform a sequence of these DMA
transfers. A DMA request signal for each channel is routed to the DMA controller. This signal is monitored and
responded in same way as the processor handles the interrupts. When DMA controller sees DMA requests, the
DMA controller responds by performing one or many data transfers that I/O device into system memory or
vice-versa. Channel must be enabled by the processor for the DMA controller to respond to DMA requests. The
number of transfer performed, transfer modes used and memory location accessed depends on how the DMA
channel is programmed.
A DMA controller shares the system memory and I/O bus with the CPU and has both bus master and slave
capability. In master mode DMA controller acquires the system bus from the CPU to perform DMA transfers. In
slave mode DMA controller is accessed by the CPU, which programs the DMA controllers internal registers to
set up DMA transfers. Internal registers consist of source and destination address registers and transfer count
registers for each DMA channel, as well as control and status registers for initiating, monitoring and sustaining
the operation of the DMA controller.