Tsl1401r LF B

TSL1401RLF
128 1 LINEAR SENSOR ARRAY WITH HOLD
r
r
D
D
D
D
D
D
D
D
D
D
D
D
TAOS076B APRIL 2007
128 1 Sensor-Element Organization

400 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor Required
Replacement for TSL1401 and TSL1401R
RoHS Compliant
DIP PACKAGE
(TOP VIEW)
SI 1
8 NC
CLK 2
7 GND
AO 3
6 GND
VDD 4
5 NC
NC No internal connection
Description
The TSL1401RLF linear sensor array consists of a 128 1 array of photodiodes, associated charge amplifier
circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for
all pixels. The pixels measure 63.5 m (H) by 55.5 m (W) with 63.5-m center-to-center spacing and 8-m
spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI)
signal and a clock.
Functional Block Diagram

Pixel 1
S1
Pixel
2
1 Integrator
Reset
2
Pixel
3
Pixel
128
4
Analog
Bus
3
Output
Buffer
VDD
AO
S2
Sample/Hold/
Output
6, 7
GND
Switch Control Logic
Hold
CLK
SI
Q1
Q2
Q3
Q128
Gain
Trim
128-Bit Shift Register
The LUMENOLOGY r Company
Copyright E 2007, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.

1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
www.taosinc.com
TSL1401RLF
TAOS076B APRIL 2007
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AO
Analog output.
CLK
Clock. The clock controls charge transfer, pixel output, and reset.
GND
6, 7
Ground (substrate). All voltages are referenced to the substrate.
NC
5, 8
No internal connection.
SI
Serial input. SI defines the start of the data-out sequence.
VDD
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the
rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors
to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is
clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a
high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and
return the internal logic to a known state. If a minimum integration time is desired, the next SI pulse may be
presented after a minimum delay of tqt (pixel charge transfer time) after the 129th clock pulse.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee)(tint)
where:
Vout
Vdrk
Re
Ee
tint
is the analog output voltage for white condition

is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(J/cm2)
is the incident irradiance in W/cm2
is integration time in seconds
A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device.
The TSL1401RLF is intended for use in a wide variety of applications, including: image scanning, mark and
code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and
optical linear and rotary encoding.
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TSL1401RLF
TAOS076B APRIL 2007
Absolute Maximum Ratings

Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . 0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25C to 85C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25C to 85C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Not recommended for solder reflow.
Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN
NOM
MAX
Supply voltage, VDD
5.5
Input voltage, VI
High-level input voltage, VIH
VDD
VDD
Low-level input voltage, VIL
0.8
400
1000
Wavelength of light source,

Clock frequency, fclock
Sensor integration time, tint (see Note 1)

Setup time, serial input, tsu(SI)
0.03375
UNIT
nm
8000
kHz
100
ms
20
ns
Hold time, serial input, th(SI) (see Note 2)
ns
Operating free-air temperature, TA
70
NOTES: 1. Integration time is calculated as follows:

tint(min) = (128 18) y clock period + 20 ms
where 128 is the number of pixels in series, 18 is the required logic setup clocks, and 20 ms is the pixel charge transfer time (tqt)
2. SI must go low before the rising edge of the next clock pulse.
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TSL1401RLF
TAOS076B APRIL 2007
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25C, p = 640 nm, tint = 5 ms,
RL = 330 , Ee = 11 W/cm2 (unless otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
2.4
0.1
0.2
4%
7.5%
Vout
Analog output voltage (white, average over 128 pixels)
See Note 4
Vdrk
Analog output voltage (dark, average over 128 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Note 5
Nonlinearity of analog output voltage
See Note 6
0.4%
Output noise voltage
See Note 7
Re
Responsivity
See Note 8
25
35
Vsat
Analog output saturation voltage
VDD = 5 V, RL = 330
4.5
4.8
VDD = 3 V, RL = 330
2.5
2.8
SE
Saturation exposure
DSNU
Dark signal nonuniformity
All pixels, Ee = 0, See Note 10
IL
Image lag
See Note 11
IDD
Supply current
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
Ci
Input capacitance
VDD = 5 V, See Note 9
136
VDD = 3 V, See Note 9
78
0.02
UNIT
FS
mVrms
45
V/
(J/cm 2)
V
nJ/cm 2
0.05
0.5%
VDD = 5 V, Ee = 0
2.8
4.5
VDD = 3 V, Ee = 0
2.6
4.5
mA
pF
NOTES: 3. All measurements made with a 0.1 F capacitor connected between VDD and ground.
4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. Re(min) = [Vout(min) Vdrk(max)] (Ee tint)
9. SE(min) = [Vsat(min) Vdrk(min)] Ee tint) [Vout(max) Vdrk(min)]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out (IL) * V drk
IL +
100
V out (white) * V drk
Timing Requirements (see Figure 1 and Figure 2)

MIN
tsu(SI)
Setup time, serial input (see Note 12)
th(SI)
Hold time, serial input (see Note 12 and Note 13)
tw
Pulse duration, clock high or low
50
tr, tf
Input transition (rise and fall) time
tqt
Pixel charge transfer time
NOM
MAX
UNIT
20
ns
ns
ns
500
20
ns
s
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 7 and 8)
PARAMETER
ts
Analog output settling time to 1%
TEST CONDITIONS
RL = 330 ,
CL = 10 pF
MIN
TYP
120
MAX
UNIT
ns
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TSL1401RLF
TAOS076B APRIL 2007
TYPICAL CHARACTERISTICS
CLK
tqt
SI
Internal
Reset
Integration
18 Clock Cycles
tint
Not Integrating
Integrating
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
tw
128
129
2.5 V
CLK
5V
0V
tsu(SI)
SI
5V
50%
0V
th(SI)
ts
AO
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
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TSL1401RLF
TAOS076B APRIL 2007
NORMALIZED IDLE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PHOTODIODE SPECTRAL RESPONSIVITY

1
2
IDD Normalized Idle Supply Current
TA = 25C
Relative Responsivity
0.8
0.6
0.4
0.2
0
300
1.5
0.5
0
400
500
600
700
800
900
1000 1100
10
20
Figure 3
50
60
70
Figure 4
DARK OUTPUT VOLTAGE
vs
WHITE OUTPUT VOLTAGE

vs
2
0.10
VDD = 5 V
tint = 0.5 ms to 15 ms
tint = 0.5 ms
tint = 1 ms
VDD = 5 V
0.09
1.5
Vout Output Voltage
Vout Output Voltage V
40
TA Free-Air Temperature C
Wavelength nm
0.5
0.08
tint = 15 ms
tint = 5 ms
tint = 2.5 ms
0.07
0.06
0
10
20
30
40
60
50
70
10
20
30
40
60
50
70
Figure 6
Figure 5
30
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TSL1401RLF
TAOS076B APRIL 2007
SETTLING TIME
vs.
LOAD
600
SETTLING TIME
vs.
LOAD
600
VDD = 3 V
Vout = 1 V
500
470 pF
Settling Time to 1% ns
Settling Time to 1% ns
500
400
220 pF
300
200
100 pF
100
VDD = 5 V
Vout = 1 V
200
400
600
800
RL Load Resistance W
400
220 pF
300
200
100 pF
100
10 pF
470 pF
1000
10 pF
200
400
600
800
RL Load Resistance W
Figure 7
1000
Figure 8
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TSL1401RLF
TAOS076B APRIL 2007
APPLICATION INFORMATION
Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on
each pixels integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature
of the TAOS TSL14xx linear array family. By changing the integration time, a desired output voltage can be
obtained on the output pin while avoiding saturation for a wide range of light levels.
The integration time is the time between the SI (Start Integration) positive pulse and the HOLD positive pulse
minus the 18 setup clocks. The TSL14xx linear array is normally configured with the SI and HOLD pins tied
together. This configuration will be assumed unless otherwise noted. Sending a high pulse to SI (observing
timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. However,
a minimum of (n+1) clocks, where n is the number of pixels, must occur before the next high pulse is applied
to SI. It is not necessary to send SI immediately on/after the (n+1) clocks. A wait time adding up to a maximum
total of 100 ms between SI pulses can be added to increase the integration time creating a higher output voltage
in low light applications.
Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity
to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the
Functional Block Diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing
switch S1 (position 2).
At SI input, all of the pixel voltages are simultaneously scanned and held by moving S2 to position 2 for all pixels.
During this event, S2 for pixel 1 is in position 3. This makes the voltage of pixel 1 available on the analog output.
On the next clock, S2 for pixel 1 is put into position 2 and S2 for pixel 2 is put into position 3 so that the voltage
of pixel 2 is available on the output.
Following the SI pulse and the next 17 clocks after the SI pulse is applied, the S1 switch for all pixels remains
in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle.
On the rising edge of the 19th clock, the S1 switch for all the pixels is put into position 1 and all of the pixels begin
a new integration cycle.
The first 18 pixel voltages are output during the time the integrating capacitor is being reset. On the 19th clock
following an SI pulse, pixels 1 through 18 have switch S2 in position 1 so that the sampling capacitor can begin
storing charge. For the period from the 19th clock through the nth clock, S2 is put into position 3 to read the output
voltage during the nth clock. On the next clock the previous pixel S2 switch is put into position 1 to start sampling
the integrating capacitor voltage. For example, S2 for pixel 19 moves to position 1 on the 20th clock. On the n+1
clock, the S2 switch for the last (nth) pixel is put into position 1 and the output goes to a high-impedance state.
If a SI was initiated on the n+1 clock, there would be no time for the sampling capacitor of pixel n to charge to
the voltage level of the integrating capacitor. The minimum time needed to guarantee the sampling capacitor
for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 s.
Therefore, after n+1 clocks, an extra 20 s wait must occur before the next SI pulse to start a new integration
and output cycle.
The minimum integration time for any given array is determined by time required to clock out all the pixels
in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant.
Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels
in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level
for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum
clock frequency of 8 MHz.
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TSL1401RLF
TAOS076B APRIL 2007
APPLICATION INFORMATION
The minimum integration time can be calculated from the equation:
T int(min) +
1
maximum clock
frequency
(n * 18) pixels ) 20ms
where:
n
is the number of pixels
In the case of the TSL1401RLF with the maximum clock frequency of 8 MHz, the minimum integration time
would be:
T int(min) + 0.125 ms
(128 * 18) ) 20ms + 33.75ms
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
It should be noted that the data from the light sampled during one integration period is made available on the
analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock
period. In other words, at any given time, two groups of data are being handled by the linear array: the previous
measured light data is clocked out as the next light sample is being integrated.
Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
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TSL1401RLF
TAOS076B APRIL 2007
MECHANICAL INFORMATION
This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated in an electrically
nonconductive clear plastic compound.
0.440 (11,18)
0.420 (10,67)
Centerline of Pin 1 Nominally
Lies Between Pixels 4 and 5.
Pin 1 C
L
Pixel Coverage
(Note C)
0.310 (7,87)
0.290 (7,37)
0.260 (6,60)
0.240 (6,10)
C
L Package
1
j 0.03 (0,76) NOM
0.075 (1,91)
0.060 (1,52)
0.017 (0,43)
+ 0.004 (0,1)
0.260 (6,60)
0.240 (6,10)
200 mm Typical
Pixel 1 C
L
C
7 L 6
C
L Pin 1
0.016 (0,41)
0.014 (0,36)
Die Thickness
0.10 (2,54)
8
10
0.130 (3,30)
0.120 (3,05)
0.175 (4,45)
0.155 (3,94)
Seating Plane
100
90
0.012 (0,30)
0.008 (0,20)
0.060 (1,52)
0.040 (1,02)
NOTES: A.
B.
C.
D.
E.
0.053 (1,35)
0.043 (1,09)
0.025 (0,64)
0.015 (0,38)
0.150 (3,81)
0.125 (3,18)
Pb
All linear dimensions are in inches and (millimeters).

Index of refraction of clear plastic is 1.55.
Center of pixel active areas typically located under this line.
Lead finish is NiPd.
This drawing is subject to change without notice.
Figure 9. Packaging Configuration
10
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TSL1401RLF
TAOS076B APRIL 2007
PRODUCTION DATA information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT

Pb-Free (RoHS) TAOS terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMERS RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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TAOS076B APRIL 2007
12
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TSL1401RLF

128 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS076B APRIL 2007

128 1 Sensor-Element Organization

Functional Block Diagram

Switch Control Logic

128-Bit Shift Register

The LUMENOLOGY r Company

Copyright E 2007, TAOS Inc.

Texas Advanced Optoelectronic Solutions Inc.

Ground (substrate). All voltages are referenced to the substrate.

Serial input. SI defines the start of the data-out sequence.

is the analog output voltage for white condition

Copyright E 2007, TAOS Inc.

The LUMENOLOGY r Company

Absolute Maximum Ratings

Recommended Operating Conditions (see Figure 1 and Figure 2)

Supply voltage, VDD

Low-level input voltage, VIL

Wavelength of light source,

Sensor integration time, tint (see Note 1)

Hold time, serial input, th(SI) (see Note 2)

Operating free-air temperature, TA

NOTES: 1. Integration time is calculated as follows:

The LUMENOLOGY r Company

Copyright E 2007, TAOS Inc.

Analog output voltage (white, average over 128 pixels)

Analog output voltage (dark, average over 128 pixels)

Pixel response nonuniformity

Nonlinearity of analog output voltage

Output noise voltage

Analog output saturation voltage

Dark signal nonuniformity

All pixels, Ee = 0, See Note 10

High-level input current

Low-level input current

VDD = 5 V, See Note 9

VDD = 3 V, See Note 9

Timing Requirements (see Figure 1 and Figure 2)

Setup time, serial input (see Note 12)

Hold time, serial input (see Note 12 and Note 13)

Pulse duration, clock high or low

Input transition (rise and fall) time

Pixel charge transfer time

Analog output settling time to 1%

Copyright E 2007, TAOS Inc.

The LUMENOLOGY r Company

129 Clock Cycles

Figure 1. Timing Waveforms

Figure 2. Operational Waveforms

The LUMENOLOGY r Company

Copyright E 2007, TAOS Inc.

PHOTODIODE SPECTRAL RESPONSIVITY

WHITE OUTPUT VOLTAGE

Vout Output Voltage V

Copyright E 2007, TAOS Inc.

The LUMENOLOGY r Company

The LUMENOLOGY r Company

Copyright E 2007, TAOS Inc.