Chapter 5 - Analog Integrated Circuit Design by John Choma

LECTURE SUPPLEMENT #5 . . .
[LS #5]
CHAPTER #05

MOSFET Biasing Networks

Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 900890271
2137404692 [USC Office]
2137407581 [USC Fax]
8183841552 [Cell]
[email protected]

PRELUDE:
This chapter establishes the circuit concepts and circuit design strategies that underpin practical
biasing networks suitable for use in high performance, MOSFET technology analog integrated
circuits. We shall begin with an abridged review of the preceding chapter so that a strong tech-
nical foundation is forged to support the development of a family of practical biasing networks.
We shall see that these structures range from simple voltage references and current mirrors to
networks boasting biasing that is rendered nominally independent of supply voltages. Included
among the topical issues addressed in this chapter are conventional and low voltage reference
circuits, traditional and advanced high performance current sources and sinks, regulated current
sinks, and networks that feature constant or electronically tunable forward transconductances.
July 2013
Chapter 5 MOSFET Biasing

- 405 -
5.1.0. INTRODUCTION
As we have noted with BJT technology, biasing is a fundamental and often challenging
design task that pervades all analog circuit design initiatives. Biasing subcircuits establish the
necessary quiescent operating conditions that allow an active network comprised of intercon-
nected and inherently nonlinear transistors and other active devices to deliver nominally linear
input/output (I/O) performance for given input signal environments and output load conditions.
Biasing networks are also designed to deliver the static transistor currents and voltages that are
deemed essential to support gain, bandwidth, linearity, I/O impedances, transient settling time,
standby power dissipation, and other targeted performance objectives.
In a reliable and reproducible analog network, the desired characteristics of the biasing
circuit must be sustained despite unavoidable changes in semiconductor operating temperatures
and the non-ideal nature of the utilized power supplies. For example, even relatively small drain
currents conducted by deep submicron MOSFETs can give rise to large device current densities
that foster significant internal device heating. The preceding chapter taught us to appreciate the
effects of the temperature sensitivities of carrier mobilities, threshold potentials, and other
transistor variables and parameters. As a result, it is only logical to expect the quiescent currents
and voltages established in our biasing networks to be vulnerable to temperature fluctuations un-
less we take care to implement creative and reliable thermal compensation schema. Moreover,
the portability culture in which we reside makes us mindful that batteries serving as the power
line voltage are not ideal sources of constant voltage. These battery voltages degrade quickly
with time, especially if the networks in which these batteries are deployed conduct relatively
large standby currents. Since it is an annoyance to be compelled to replace or recharge batteries
as soon as their voltages decrease by 10%, 20%, or even 50%, we must be prepared to design
biasing circuits whose static responses are not overly sensitive to voltage supply levels. Stated in
another way, our biasing designs must boast sufficiently high power supply rejection, or PSR.
Yet another issue that responsible circuit designers must address is that the quiescent cur-
rents and voltages forged by our biasing structures must be impervious to a plethora of engineer-
ing uncertainties. Such uncertainties include those that are associated with the physical and
geometric parameters implicit to the mathematical models of our active devices. To wit, a
reference output voltage that is directly proportional to carrier mobility is a less than laudable
accomplishment because mobilities are temperature dependent. Moreover, an accurate numeri-
cal delineation of carrier mobilities at any specific operating temperature or voltage is a chal-
lenge because of their functional dependence on numerous semiconductor variables that are ob-
scure, nebulous, or simply difficult to monitor or measure. Additionally, manufacturing and
processing uncertainties plague passive circuit components, the matching accuracy among simi-
lar active devices produced by foundry processes, and the lossy parasitics associated with circuit
layout and packaging.
This chapter explores biasing cells that are commonly used in high performance analog
integrated circuits. Our discussion begins with an analysis of a simple voltage reference scheme
that is often adopted in conjunction with the realization of high impedance current sinks and
sources. We shall examine the viability of this and alternative schemes to function as a reliable
and predictable voltage and current references for arbitrary load terminations. The simple vol-
tage reference configuration is subsequently extended to embrace the design requirements of mi-
nimal quiescent operating point sensitivity to temperature and variations in power line (battery)
voltages. Circuits that reliably bias transistors for constant and predictable forward transconduc-

- 406 -
tance are addressed, as are topologies boasting improved current source and current sink imped-
ance properties.
As a foundational prelude to our bias circuit discussions, the salient features of the
static volt-ampere characteristics of MOSFETs, which we addressed in the preceding chapter, are
reviewed. The analytical comfort level that hopefully derives from this review is indispensable
because mathematically tractable analyses serving to complement ultimate computer-aided cir-
cuit studies demand reasonable and insightfully understood device modeling approximations.
We shall also focus on the transient responses of biasing networks subjected to the sudden
application or removal of static power. This focus is important because the transients associated
with circuit startup or even shutdown can prove to be destructive to sensitive, deep submicron
transistors.
5.2.0. STATIC MODEL OF A MOSFET
Figure (5.1) gives the circuit schematic symbol of both n-channel and p-channel transis-
tors. In this diagram, we explicitly show the bulk terminals appropriately connected so that bulk-
source and bulk-drain PN junctions intrinsic to the utilized transistors are reverse biased. In
other schematic representations, we may choose not to show these bulk terminal connections.
Regardless and unless stipulated otherwise, we presume that bulk connections are made to ensure
the reverse biasing of PN junctions internal to the transistor.

Figure (5.1). (a). Schematic symbol of an NMOS transistor in which the positive
reference polarity convention for drain current and both gate-source
and drain-source voltages are delineated. (b). Schematic symbol of
a counterpart PMOS transistor. In both diagrams, the bulk substrate
terminals are presumed incident with signal ground.
Figure (5.1a) delineates the positive reference polarity conventions for the drain cur-
rent, I
d
, the gate-source voltage, V
gs
, the drain-source voltage, V
ds
, and the gate-drain voltage,
V
gd
, are indicated. Unless otherwise specified, we assume that the substrate terminals of the p-
type bulk of NMOS devices are connected to the smallest of available circuit potentials, which
we indicate in the figure as Min. B. If these minimal and possibly negative circuit potentials
are constant, the bulk terminals lie at signal ground. For the p-channel device in Figure (5.1b), it
is more convenient to cast the static volt-ampere characteristics in terms of the source-gate vol-
tage, V
sg
, the source-drain voltage, V
sd
, and the drain-gate voltage, V
dg
. We assume that the sub-
strate terminals of the n-type bulk of all PMOS devices are incident with the most positive of
available circuit potentials, which we delineate in the figure as Max. B+. To the extent that
these maximum potentials are constant, the bulk nodes of PMOS transistors, like those of NMOS
devices, are connected to signal ground. At this point in our electronic circuit travels, we should
easily remember that positive drain current flows into an NMOS device, while positive drain cur-
+
V
gs
+
V
ds
I
d
I
d
(a).
+
V
dg
(b).
+
V
sd
+
V
sg
+
V
gd
To Min.
B
To Max.
B

- 407 -
rent flows out of a PMOS transistor.
In Figure (5.1a), let V
hn
designate the threshold voltage of the NMOS transistor. If the
transistor is biased for operation in its saturation regime where V
ds
V
dsat
V
gs
V
hn
, the simple
square law, Schichman-Hodges model relating the drain current to the applied gate-source vol-
tage is
( ) ( )
2 2
no ox n
d gs hn gs hn
C K W W
I V V V V ,
2 L 2 L
| | | | | | | |
= =
| | | |
\ . \ . \ . \ .
(5-1)
where
no
is the mobility of free electrons in the inverted channel immediately below the oxide-
semiconductor interface. Specifically,
no
is the carrier mobility when lateral electric field
intensities induced in the channel by applied drain-source voltages are much smaller than the
critical field intensity, which is in the neighborhood of 5 V/m. Continuing, (W/L) is the gate
width to drawn channel length ratio, or simply, gate aspect ratio. Parameter C
ox
symbolizes the
density of the capacitance associated with the gate oxide layer, is
ox ox ox
C T . = (5-2)
In (5-2),
ox
is the dielectric constant of silicon dioxide (345 fF/cm), while T
ox
is the average
thickness of the insulating gate oxide.
The companion volt-ampere relationship for the saturated p-channel transistor in Figure
(5.1b) is
( ) ( )
2 2
po ox p
d sg hp sg hp
C K
W W
I V V V V ,
2 L 2 L
| | | |
| | | |
= =
| |
| |
\ . \ .
\ . \ .
(5-3)
which requires V
sd
V
sg
V
h
. In this relationship,
po
is the low field value of the mobility of
free holes in the inverted channel. Note that the gate-source voltage, V
gs
, in (5-1) is replaced by
the source-gate voltage, V
sg
. The replacement of V
gs
by V
sg
allows threshold voltages V
hn
in (5-1)
and V
hp
in (5-3) to be couched as positive voltages. We recall that the threshold voltage in MOS-
FETs operated without the source terminal connected directly to the bulk terminal modulates
minimally for thin gate oxide layers.
It is expedient for us to write the volt-ampere equations in (5-1) and (5-3) in the forms,
( )
( )
2
d n gs hn
2
d p sg hp
I V V for NMOS
,
I V V for PMOS
=
=
(5-4)
where
no ox n
n
po ox p
p
C K W W
for NMOS
2 L 2 L
.
C K
W W
for PMOS
2 L 2 L
| | | |
= =
| |
\ . \ .
| | | |
= =
| |
\ . \ .
(5-5)
We observe that the introduced transconductance coefficient parameters,
n
and
p
, which have
dimensional units of mhos/volt, scale linearly with gate aspect ratio, W/L.
The compact static volt-ampere equations in (5-4) show that for given threshold vol-
tage, gate aspect ratio, gate oxide capacitance density, and channel carrier mobility, the drain
current is determined exclusively by one voltage variable; namely, gate-source voltage V
gs
in
NMOS and source-gate voltage V
sg
in PMOS. The lack of drain current dependence on drain-

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source or source-drain voltage means that the electrical characteristics of the drain-source port of
a MOSFET are modeled as an ideal current source. In other words, (5-4) suggests that the drain
current can be represented as an ideal, albeit nonlinear, voltage controlled current source, with
either V
gs
or V
sg
serving as the controlling voltage. Since the gate terminal is incident with an
insulating oxide layer serving as an interface between the gate contact metallization (or polysili-
con) and the semiconductor surface, the gate conducts zero static current. Accordingly, the
drain-source terminal pair emulates an ideal voltage controlled current source, as inferred by the
simple models offered in Figure (5.2). In short, the simple static model of (5-4) stipulates that
when MOSFETs operate in their saturation regions, their drain currents are functionally depen-
dent, albeit to first order, on only gate-source voltages. Conversely, a current forced to flow in
the MOSFET drain establishes, by virtue of (5-4), a unique gate-source potential. We should
note further that if both the NMOS and PMOS devices are operated to conduct a fixed static
drain current, progressively larger gate aspect ratios result in a gate-source (or a source-gate) vol-
tage that approaches threshold value.

Figure (5.2). (a). Simplified static model of an NMOS transistor biased for operation in satura-
tion. The drain current, I
d
, is exclusively a function of the gate-source voltage,
V
gs
. (b). Simplified static model of a PMOS transistor biased for operation in
saturation. To first order the drain current, I
d
, is exclusively a function of the
source-gate voltage, V
sg
. The ground connection at the bulk terminals of both de-
vices indicates signal ground only.
5.2.1. TEMPERATURE SENSITIVITY
In contrast to a BJT, whose static collector current exhibits positive temperature coeffi-
cient, the static volt-ampere characteristics of a MOSFET display negative temperature sensitiv-
ity. In other words, for constant gate-source or source-gate voltages, the observed drain current
decreases with increasing interfacial operating temperatures. Two principle phenomenological
reasons contribute to the negative temperature coefficient of a MOSFET. The first of these de-
rives from the fact that the carrier mobility in the inverted channel of a transistor decreases nomi-
nally as a three-halves power law of absolute temperature. In particular,
+
V
gs
+
V
ds
I
d
I
d
(a).
+
V
dg
(b).
+
V
sd
+
V
sg
+
V
gd
Drain
Gate
Source
Source
Gate
Drain
+
V
gs
+
V
ds
+
V
dg
+
V
sd
+
V
sg
+
V
gd
Drain
Gate
Source
Source
Gate
Drain
I

=

(
V

V
)
d
n

g
s
h
n

2
I

=

(
V

V
)
d
p

s
g
h
p

2

- 409 -
3 2
o
o
T
(T) (T ) ,
T
| |
=
|
\ .
(5-6)
where (T) designates electron mobility
no
in NMOS or hole mobility
po
in PMOS at any arbi-
trary absolute temperature, T. On the other hand T
o
is the reference temperature at which the
reference mobility value, (T
o
), is extracted. Since parameters
n
and
p
in (5-5), to which the
drain currents in (5-4) are proportional, are linear functions of carrier mobility, the immediate
effect of increased operating temperature is clearly a diminished drain current.
In addition to a temperature-induced degradation of mobility, the threshold voltage of a
MOS technology transistor increases with temperature. This threshold potential increase further
diminishes the drain current observed for a given gate-source voltage at increasing operating
temperatures. The positive temperature coefficient of threshold voltage derives from its intimate
dependence on the Fermi potential, which effectively defines the oxide-semiconductor interface
potential corresponding to the onset of channel inversion in a MOSFET. To first order,
h o ho o
h h o F
F o
V (T ) V T T
V (T) V (T ) 2 V ,
2V T
| | (
| ( ~ + +
|
(
\ .
(5-7)
where V
h
(T) is the threshold voltage value of either NMOS or PMOS at absolute temperature T,
and the Fermi potential, V
F
, is given by
sub
F T
i
N
V V .
n
ln
| |
=
|
\ .
(5-8)
In the last expression, N
sub
denotes the impurity concentration in the substrate (acceptor
concentration for NMOS and donor concentration for PMOS), n
i
is the intrinsic carrier
concentration of silicon, and V
T
is the familiar Boltzmann voltage. But V
F
itself varies with
temperature owing to two well-known facts. In particular, V
T
is linearly dependent on absolute
temperature and n
i
nominally increases by as much as two to four fold for each 10 C increase in
operating temperature. When due consideration is given to mobility and threshold effects, the
sensitivity of the drain current to absolute temperature is found to be
d
0.25
I
d d F
T
o d
I I 4V 3 T
S .
T T 2 T I
(
| | c
(
~ +
|
( c
\ .

(5-9)
In (5-9), =
n
for NMOS, =
p
for PMOS, and it is understood that V
F
, I
d
, and in the brack-
eted factor on the right hand side are each evaluated at the reference temperature, T
o
. The first
term in the bracketed quantity derives from the temperature dependence of carrier mobility,
while the second term within the bracketed quantity reflects threshold voltage sensitivity to
temperature. Accordingly, the per-unit, or percentage, change in drain current induced by a
specified percentage change in operating temperature is negative and larger in magnitude than
1.50. We note, however, that for progressively larger drain currents, the temperature sensitivity
of drain current tends toward a constant of (1.50).
EXAMPLE #5.1:
In an attempt to dramatize the foregoing temperature issues, consider an
NMOS MOSFET having a substrate impurity concentration of N
sub
= 10
15

atoms/cm
3
. At a reference temperature of T
o
= 27 C = 300.16 K, the
MOSFET, which is biased for a drain current of I
d
= 1 mA, delivers
n
=

- 410 -
50 mmhos/volt, and a threshold voltage of V
hn
= 400 mV. Assume a refer-
ence temperature intrinsic carrier concentration of 10
10
atoms/cm
3
. Deter-
mine the requisite gate-source voltage, V
gs
, such that the room tempera-
ture, 1 mA value of drain current is sustained at an elevated operating
temperature of 75 C.
SOLUTION #5.1:
(1). From (5-4), the gate-source voltage commensurate with 1 mA of drain current at 27 C is,
with
n
= 50 mmhos/volt and V
hn
= 400 mV, V
gs
= 541.4 mV. Also, at T
o
= 27 C = 300.16
K, the Boltzmann voltage, V
T
, is
o
T
kT
V 25.88 mV ,
q
= = (E1-1)
where k = 1.38(10
23
) joules/K is Boltzmanns constant, and q = 1.6(10
19
) coulombs is the
magnitude of electron charge. For N
sub
= 10
15
atoms/cm
3
and n
i
= 10
10
atoms/cm
3
at 27 C,
the Fermi potential in (5-8) is V
F
= 297.9 mV at the reference temperature.
(2). Using (5-7), the threshold voltage increases to V
hn
= 495.3 mV at T = 75 C = 348.16 K,
which is an increase of almost 24%. Appealing to (5-6), the ratio of the carrier mobility at
348 K to the carrier mobility at 300 K is
3 2 3 2
o
o
T (T) 300
1 1.249 .
(T ) T 348
| | | |
= = =
| |
\ . \ .
(E1-2)
Since parameter
n
is directly proportional to carrier mobility,
n
decreases by a factor of
1.249 to a 75 C value of
n
= 40.02 mmhos/volt.
(3). If a biasing circuit were to be implemented to deliver constant gate-source voltage to the
transistor of present interest,
n
= 40.02 mmhos/volt, V
hn
= 495.3 mV, and V
gs
= 541.4 mV
(the gate-source voltage value computed at 27 C), the drain current in (5-4) becomes I
d
=
85.03 A. This revised current level is a decrease from the original drain current value by a
whopping factor of almost 12! On the other hand, sustaining a 1 mA drain current in the face
of the foregoing temperature-induced perturbations in parameter
n
and threshold voltage V
hn

requires an updated gate-source voltage of V
gs
= 653.4 volts. In other words, the gate-source
voltage must increase by 20.7% over the 48 C increase in operating temperature.
ENGINEERING COMMENTARY:
This example teaches that the temperature-induced effects on the drain current conducted by
a MOSFET biased in saturation can be substantial. In the present case, the factor of 12 de-
crease in quiescent drain current is certainly large enough to motivate significant concern as
to the ability of the circuit in which the considered MOSFET is embedded to sustain perfor-
mance specifications over the stipulated 48 C rise in operating temperature. The design les-
son learned is that if the desired signal performance of a circuit is critically dependent on
quiescent current level, constant gate-source voltage is not a prudent bias design strategy.
In the present case, the gate-source voltage that sets the drain current on the subject transistor
must increase by 20.7% over the 48 C rise in temperature. While this requirement may ap-
pear foreboding, it reflects realistic biasing compensation. To place this contention into
engineering perspective, the requisite increase in gate-source voltage, say AV
gs
, is AV
gs
=
V
gs
(75 C) V
gs
(27 C) = 112.0 mV, which amounts to an average temperature rate of vol-
tage increase of 2.33 mV/C. Thus, the incorporated biasing compensation must sense
temperature (perhaps by sensing current). In response to this sensing, it must then increase
the gate-source bias by about 2.33 mV for every degree centigrade increase in temperature.
This mandated average increase is indeed a reasonable design goal for properly designed
biasing compensation. As a general rule, the majority of MOSFETs achieve nominally

- 411 -
temperature invariant drain current when the applied gate-source voltage is made to increase
at a rate in the range of 1.5 mV/C to 2.5 mV/C. Interestingly enough, the +2.33 mV/C
requirement computed in this example differs only slightly from the average temperature rate
at which the base-emitter biasing voltage applied to a BJT must decrease to preserve constant
static collector current.
5.2.2. IMPROVED STATIC MODELS
We should remain mindful of the fact that the static volt-ampere characteristics given
by (5-4), which we shall invoke habitually in our first order, design-oriented circuit analyses, are
only first order approximations of the static characteristics we actually observe and monitor in
the laboratory. Unfortunately, the deviations between first order theoretic predilections and
engineering observations are aggravated as devices are scaled to deep submicron dimensions.
The primary shortfalls implicit to (5-4), insofar as static circuit responses of minimal geometry
transistors are concerned, are the neglect of channel length modulation (CLM), bulk-induced
threshold modulation (body effect or BITM), carrier mobility degradation induced by lateral
electric fields, and, to a somewhat lesser extent, drain induced barrier lowering (DIBL). The cir-
cuit level influence of these and other high order MOSFET phenomena are best studied via
computer-aided investigations that exploit device models more advanced than are those premised
on long channel simplifications. But it is important that we perform these computer-based stu-
dies only after we execute an insightfully understood manual analysis with our relatively simple,
first order transistor models so that we can understand and appreciate the quantitative impact of
high order phenomenology. Such understanding and appreciation are vital prerequisites for
enabling our creative abilities that implement circuit compensation or outright circuit architec-
tural changes. In effect, the fundamental goal of such circuit enhancements and alterations is to
render high order, and generally poorly controlled, phenomenology inconsequential to the task of
meeting our design targets.
Although we have pondered the aforementioned modeling shortfalls in the preceding
chapter, it is prudent to itemize their respective circuit level effects before undertaking our de-
sign-oriented investigation of MOSFET biasing networks.
5.2.2.1. Channel Length Modulation
Three fundamental effects of CLM are observed in short channel MOS technology
transistors. The first of these is a slight positive slope to the saturated volt-ampere characteris-
tics, which is rendered transparent by Figure (4.17). This slope is inversely proportional to the
channel length modulation voltage, V
, and thus, it is functionally related to the drawn channel

length, L. It manifests a drain current that is slightly larger than the drain current predicted by
the square law model in (5-4). The additional drain current is a nominally linear function of the
excess drain-source voltage, (V
ds
V
dsat
)
1
; in particular for NMOS,
( )
2
ds dsat
d n gs hn
V V
I V V 1 .
V
|
| |
| ~ +
|
\ .
(5-10)

1
The focus here is on NMOS transistors. But similar statements apply to PMOS transistors, where we could
minimize the impact of channel length modulation by setting the source-drain biasing voltage, V
sd
, to a value that is
close to the source-drain saturation voltage. While we shall generally address modeling issues in the context of
NMOS transistors, we shall understand that, subject to minor notational differences, our assertions apply equally
well to PMOS transistors.

- 412 -
We understand by (5-10) that biasing an NMOS transistor at a drain-source voltage
that is only slightly larger than its drain-saturation voltage minimizes the circuit-level impact of
CLM. Of course, setting the drain-source voltage close to the drain saturation voltage limits the
amount of signal swing that can be tolerated at the drain port while maintaining a specified
linearity target. Alternatively, CLM is inconsequential in transistors featuring long channel
lengths. To be sure, long channel lengths generally require correspondingly large gate widths,
which combine with these long channel lengths to produce increased device capacitances and
therefore, potentially reduced circuit bandwidths. But in biasing circuits, which operate in the
steady state at zero frequency, bandwidth is not an important metric. Indeed constrained band-
widths in biasing structures often prove advantageous from the viewpoint of avoiding exces-
sively underdamped biasing responses to a bus line voltage that is applied suddenly.
The second effect of CLM is that the large signal model evidenced at the drain-source
port of a MOSFET is no longer an ideal current source controlled nonlinearly by applied gate-
source voltage. Instead, the output port now appends a shunting resistive branch across the sub-
ject voltage controlled current source. Unfortunately, the appended resistance is nonlinearly re-
lated to both drain-source and gate-source voltages, which generally motivates our defaulting to
computer-aided analysis whenever CLM looms significant. However, the appended resistance is
large in devices that have large channel lengths and/or operate at low saturation currents.
Finally, CLM alters the small signal performance of a MOSFET by imposing a channel
resistance (r
o
) across the drain-source port of a MOS technology transistor. As is confirmed in
the preceding chapter, this resistance shunts the drain-source signal current source, which is con-
trolled by applied gate-source signal voltage. The resistance shunting impinges on small signal
MOSFET performance in two ways. First, it reduces the achievable I/O gain because the ap-
pended resistance places an additional load between drain and source terminals in an amplifier.
Second, it establishes a finite resistance at the drain output port, as opposed to the infinitely large
driving point output resistance manifested at the drain port by the long channel approximation.
Thus, while the Schichman-Hodges model affords a common source amplifier that behaves as an
ideal transconductor, in the senses of infinitely large input and output impedances at low signal
frequencies, CLM brings such a transconductor into non-ideal state of engineering reality.
5.2.2.2. Bulk-Induced Threshold Modulation
Bulk-induced threshold modulation (BITM) incurs both large signal and small signal
effects. From the large signal perspective, the body effect increases the threshold voltage of a
MOSFET as a nonlinear function of the reverse bias imposed across the bulk-source PN junc-
tion. In extreme situations, this means that if the subject reverse bias includes a signal compo-
nent, it is possible that sufficiently large signals can incur intermittent or aperiodic cutoff of the
transistor. Such an extreme can materialize, for example, if the gate aspect ratio is so large that a
desired drain current can be sustained when the gate-source voltage is ever so slightly above the
threshold potential. At a minimum, threshold voltage perturbations induced by large signal
swings can exacerbate nonlinearity problems, despite the care ostensibly taken to pin the quies-
cent operating point of the transistor in a reasonably linear region of its characteristics curves.
We remember that BITM is minimal for thin gate oxide layers.
From a small signal perspective, Figure (4.22), with the help of (4-172) and (4-173),
confirms that the body effect establishes a controlled current source in shunt with the drain-
source terminals of a MOSFET. Depending on the nature of the bulk-source signal voltage, this
additional controlled source changes the I/O gain of an amplifier. And if the bulk-source signal

- 413 -
voltage is nonzero, it can alter appreciably the driving point output impedance seen looking into
the transistor drain. We note again from (4-173) that a thin gate oxide reduces the net
transconductance associated with the additional voltage controlled current source in the drain cir-
cuit. But an even more important observation is that if this additional controlled source is
significant to the enumeration of gain and/or output impedance, there is cause for design
concern. In particular, a significant effect on the small signal characteristics implies that body
effect has a similarly significant influence on static MOSFET responses, which bodes poorly
from an I/O linearity perspective.
5.2.2.3. Carrier Mobility Degradation
The immediate impact of carrier mobility degradation induced by the lateral electric
fields caused by drain-source voltages is a reduction of the drain saturation voltage. This effect
is highlighted and analytically addressed by (4-130) through (4-133). These relationships show
that the reduction in drain saturation current is minimal for long channel lengths. A reduced
drain saturation voltage is actually good news in that it enables us to bias the transistor at
progressively smaller drain-source voltages while sustaining saturation regime operation. But
carrier mobility degradation reduces the drain current, which is to say that progressively larger
gate-source biases are required to offset this current reduction. Obviously, increased gate-source
voltage causes an increase in drain saturation voltage.
5.3.0. CURRENT SINKS AND SOURCES
Current sinks and sources are ubiquitous in analog networks. One reason that
underpins the popularity of these subcircuits is that the forward transconductance, drain-source
channel resistance, and several other low and high frequency parameters in the small signal
transistor model are dependent on quiescent transistor currents. In an attempt to minimize
network nonlinearities, it is incumbent on us to keep quiescent variables as constant as possible,
which is to say that it is desirable to derive critical static currents from nominally ideal sources or
sinks of constant current. Additionally, and as we witnessed in the preceding chapter, a constant
tail current in a balanced differential amplifier not only keeps pertinent small signal transistor
parameters constant, but its value also sets the allowable input signal amplitude that affords
acceptable linearity.
5.3.1. SIMPLE CURRENT MIRROR
We commence our present discussion by studying the current mirrors offered in Figure
(5.3). We shall analyze only the NMOS mirror in Figure (5.3a). The analysis of the PMOS mir-
ror in Figure (5.3b) proceeds along the same lines as that of its NMOS counterpart and is left as
an exercise for the reader.
In both of the two circuit diagrams before us, input current I
ref
is often realized as an off
chip current source. In light of the design flexibilities afforded by discrete, off the shelf compo-
nents, we can view this branch element as an ideal, constant current source having infinitely
large terminal impedance. While voltage V
dd
is presumably larger than node voltage V
kk
, we as-
sume V
kk
is large enough to ensure that transistor M2 operates in its saturation domain. In the
case of transistor M1, saturation is assured because of the indicated electrical connection of its
gate and drain terminals. From a cataloguing perspective, we usually think of the NMOS mirror
as a current sink in that the drain current, I
k
, flows into ground from a general branch element

- 414 -
that is not delineated in the figure. On the other hand, the PMOS mirror is viewed as a current
source since drain current I
k
flows into a general branch element, which is also not delineate din
the subject figure.

Figure (5.3). (a). Schematic diagram of an NMOS current mirror. (b). The PMOS counter-
part to the NMOS current mirror. In both diagrams, the gate aspect ratio of
transistor M2 is larger than that of transistor M1 by a factor of k
21
.
In Figure (5.3a), the drain-source voltage, V
ds
, of transistor M1 is identical to its gate-
source bias, which we indicate as V
ref
. This means that the drain saturation voltage of this
transistor, V
dsat1
, is V
dsat1
= (V
ref
V
hn
) = (V
ds1
V
hn
). Note that as we inferred in the preceding
paragraph, this transistor operates in saturation in that the inequality, V
ds1
> V
dsat1
= (V
gs1
V
hn
)
= (V
ds1
V
hn
), is clearly satisfied. Because the gate of a MOSFET conducts no quiescent cur-
rent, I
ref
is identical to the drain current, I
d1
of M1. Accordingly, (5-10) yields
( )
2
hn
d1 ref n1 ref hn
V
I I V V 1 ,
V
|
| |
| = ~ +
|
\ .
(5-11)
where we have not bothered to differentiate between the two transistor threshold voltages and the
two channel length modulation voltages. We have adopted this tack because the two NMOS de-
vices are monolithic transistors that are physically identical. We include identical channel
lengths in this physical restriction, but we do allow geometrical differences between their respec-
tive gate widths and thus, their corresponding gate aspect ratios. In case before us, the gate as-
pect ratio of transistor M2 is k
21
-times the gate aspect ratio of M1. Moreover, both transistors
return their source and bulk terminals to ground, thereby negating BITM. Thus, the two transis-
tors function with the same threshold voltages. Since drain induced barrier lowering (DIBL) af-
fects the threshold voltage, the latter statement presumes negligible or identical DIBL in both
transistors.
We note now that the circuit architecture forces the gate-source voltage, V
gs2
, of transis-
tor M2 to be identical to V
gs1
, which is, of course, the previously introduced voltage, V
ref
. Thus,
( )
2
kk ref hn
d2 k n2 ref hn
V V V
I I V V 1 ,
V
|
+ | |
|
= ~ +
|
\ .
(5-12)
But from (5-5),
n2
21
n1
k .
|
|
= (5-13)
It follows from (5-11) and (5-12) that
M1
M2
x k
21
+V
dd
V
dd
I
ref
+V
kk
V
ref
V
ref
I
k
I
d1
I
d1
M1
M2
x k
21
I
ref
V
kk
I
k
(a). (b).

R
out
R
out
x 1
x 1

- 415 -
kk ref hn
k 21 ref
hn
V V V
1
V
I k I .
V
1
V
+ | |
|
+
|
=
|
|
+
|
|
\ .
(5-14)
In earlier chapters, we repeatedly asserted that the fundamental purpose of circuit
analysis is not necessarily to arrive at an accurate response result. Instead, we advanced the
pedagogy that the fundamental purpose of circuit analysis is to arrive at tractable results that pro-
vide insights as to how the considered circuit might be designed to deliver consistently reliable
and reproducible high quality responses. To these ends, the work we executed to generate (5-14)
comprises an excellent example of the engineering assessment task that will consistently con-
front us as we consider subsequent, and inevitably more complex, networks.
To the foregoing end, (5-14) is hardly a precise result for output current I
k
, since we
have invoked a simple square law model for MOSFET volt-ampere characteristics, embellished
only for a first order account of channel length modulation. We do notice, however, that for
large V
, which is achieved for long drawn channel lengths, current I

k
collapses approximately to
k
21
I
ref
. This means that since k
21
is a reliably deterministic ratio of device gate aspect ratios, I
k

mirrors constant current I
ref
within a predictable scale factor of k
21
. In a word, as long as the off
chip reference current, I
ref
, remains constant, output current I
k
stays constant, independent of
power line voltage V
dd
, transistor threshold voltage, and all other transistor parameters and
operating temperature. In turn, the numerical value of current I
k
is set by a reliable and predicta-
ble ratio of gate aspect ratios.
Unfortunately, there are potential issues concerning scale factor k
21
, which derives di-
rectly from (5-13). In particular, the transconductance coefficient,
n
, is directly proportional to
carrier mobility. As we witnessed in the preceding chapter, the mobility of carriers in the in-
verted channel of an NMOS transistor is determined by the intensity of the drain to source elec-
tric field, which in turn is a monotonically increasing function of the applied drain-source vol-
tage. In Figure (5.3a), the drain-source (as well as gate-source) voltage applied to transistor M1
is the voltage, V
ref
, while for M2, the drain-source bias is an invariably larger voltage, V
kk
. If in-
deed V
kk
> V
ref
, the electric field intensity in the drain-source channel of M2 exceeds the electric
field intensity in which the inverted channel of transistor M1 is immersed. This means that the
carrier mobilities in M1 and M2 are not identical, thereby rendering (5-13) an approximation. A
reasonable rectification of this dilemma does not necessarily require that V
kk
be identical to vol-
tage V
ref
, for carrier mobility is not overtly sensitive to voltage. But it is only sensible for us to
attempt to ensure that voltage V
kk
is not excessively larger than V
ref
. In addition to reducing the
disparity between carrier mobilities in the two NMOS transistors, a secondary benefit of securing
V
kk
in the neighborhood of V
ref
is that the parenthesized quantity on the right hand side of (5-14)
collapses nearly to one. In short, channel length modulation phenomena are rendered virtually
inconsequential.
Another valuable metric for assessing the quality of a current source or current sink is
the output resistance, R
out
, which it presents to its output port. This output resistance is founda-
tional to an assessment of the power supply rejection of a current sink. It tells us the amount, say
AI
k
, by which the presumably constant current, I
k
, changes when applied voltage V
kk
is perturbed
by the amount, AV
kk
. The voltage fluctuation may be the result of signal spurs, electrical noise,
poor regulation, or other offending conditions that contaminate the line supporting voltage V
kk
.

- 416 -
Moreover, if AV
kk
and AI
k
are small, which we expect them to be in a well-designed biasing
environment, we can stipulate the linear constraint,
kk
k
out
V
I .
R
=
A
A (5-15)
Equation (5-15) boasts two important engineering ramifications. The first of these is that if out-
put resistance R
out
is known, the perturbation, AI
k
in current caused by a given change (parasitic
or otherwise), AV
kk
, in voltage can be straightforwardly enumerated. The second ramification is
that if AV
kk
and AI
k
are small, output resistance R
out
derives from a simple, low frequency, small
signal analysis that culminates in the computation of the voltage to current ratio, AV
kk
/AI
k
. Be-
cause of our presumed linearity between AV
kk
and AI
k
, we note that this ratio does not rely on an
explicit awareness of either AV
kk
or AI
k
. Clearly, R
out
= is the ideal circumstance in that it en-
sures AI
k
= 0 for all AV
kk
. We therefore deem it productive to embark on the task of determining
output resistance R
out
for the NMOS sink in Figure (5.3a).
We can conduct a circuit analysis that leads to an expression for the desired output
resistance, R
out
, simply by straightforwardly examining the entire network in Figure (5.3a) with
each transistor supplanted by its small signal model. Although there is nothing philosophically
wrong with this solution tack, we shall adopt a slightly more creative analytical strategy. In
particular, we must begin to prepare ourselves for complicated analytical projects. In these ad-
vanced projects, replacing each active device by an equivalent circuit is likely to provoke inordi-
nately cumbersome, tedious, and even annoying mathematics that accomplish little more than to
mask the design insights we are attempting to glean.

Figure (5.4). (a). Subcircuit comprised of diode-connected transistor M1 that drives the gate of transistor
M2 in Figure (5.3a). (b). Low frequency, small signal model of the subcircuit in (a). (c). Cir-
cuit used to evaluate the Thvenin output resistance, V
y
/I
y
= r
d
, of the subcircuit in (a). (d).
The Thvenin equivalent source circuit seen by the gate of transistor M2 in Figure (5.3a).
In order to initiate our design-oriented analysis, let us replace the diode-connected
subcircuit to the left of the M2 gate in Figure (5.3a) by its Thvenin equivalent circuit. Such a
M1
+V
dd
I
ref 0
V
ref
I
d1
(a).
To Gate
Of M2
(b).
r
o1
g V
m1 1

b1 m1 2
g V
V
1
V
2
To Gate
Of M2
To Gate
Of M2
(c).
r
o1
g V
m1 1
V
1
V
y
I
y
(d).
r
o1
1/g
m1
r
d

- 417 -
replacement demands that the subject subcircuit be electrically represented by a small signal, and
therefore linear, equivalent circuit since Thvenin displayed neither interest in, nor compassion
for, nonlinear circuits. Figure (5.4a) displays the subcircuit partitioned from the remaining
components of the current mirror we are investigating. In Figure (5.4b), we exploit the low fre-
quency, small signal transistor model we produced as Figure (4.22a) to delineate the pertinent
equivalent circuit of the reference subcircuit in Figure (5.4a). In this model, we have replaced
the power line voltage, V
dd
, by a short circuit since the small signal voltage value of a source of
constant voltage is a null voltage. As it turns out, the present replacement of V
dd
by a short cir-
cuit carries no engineering significance since the small signal model of the constant current
source, I
ref
, to which V
dd
is applied as a series element, is an open circuit. To this end, we depict
current source I
ref
by its replacement small signal source. Given that current I
ref
is a constant, its
small signal current has zero value, which of course reflects an open circuit. If we had accounted
for a finite terminal resistance associated with I
ref
, the small signal model of the subject source
would have been its presumably large two-terminal shunting resistance, as opposed to the im-
plied open circuit.
The short circuiting of voltage source V
dd
and the open circuiting of current source I
ref
,
precludes any signal source from being applied to the biasing subcircuit. This situation imme-
diately leads us to conclude that the Thvenin signal voltage activating the gate of transistor M2
is zero. If, however, we had observed a small fluctuation in I
ref
and/or a small fluctuation in V
dd

under the condition of a finite current source resistance, the subcircuit at hand would have re-
sponded by delivering a presumably small, but nonzero, Thvenin voltage at its open circuited
output port.
With zero Thvenin voltage observed at the output port of the M1 biasing subcircuit,
the Thvenin equivalent of this subcircuit collapses to a simple Thvenin resistance. We can
determine this resistance with the help of the model shown in Figure (5.4c). The latter model
derives directly from the network in Figure (5.4b), where we have dispensed with the short cir-
cuit replacement of line voltage V
dd
because of the open circuit replacement of reference current
I
ref
. Additionally, we observe that since the bulk and source terminals of transistor M1 are
grounded, no bulk-source signal voltage, shown as voltage V
2
in Figure (5.4b), is established.
Thus, the bulk transconductance current,
b1
g
m1
V
2
, which quantifies the dependence of signal
drain current on signal bulk-source voltage, vanishes. We can then determine the Thvenin out-
put resistance, say r
d
, in a conceptual manner that mirrors how an ohmmeter determines the
resistance between any two terminals of a linear network. In particular, an ohmmeter squirts a
small amount of current, say I
y
in the present case, into the port of interest (the model output
port). In response to this applied current, the ohmmeter measures the voltage V
y
, which is the
voltage across, and in disassociated polarity with, the injected small current, I
y
2
. The ohmmeter
then displays voltage V
y
normalized to current I
y
on the ohmmeter display; that is, it effectively
measures the resistance of interest by displaying the voltage to current ratio, V
y
/I
y
. We show the
mathematical form of this ohmmeter in the small signal model of Figure (5.4c).
In the aforementioned diagram, the ohmmeter voltage, V
y
, happens to be identical to the
gate-source signal voltage, V
1
, which controls the current source, g
m1
V
1
. In other words, current
g
m
V
1
is the same as g
m1
V
y
. But voltage V
y
appears directly across, and in associated polarity
with, the controlled source, g
m1
V
y
. We therefore argue that the branch conducting current g
m1
V
y

2
A branch voltage is said to be in disassociated polarity with its branch current if said branch current flows toward
the plus end of the branch voltage. On the other hand, a branch voltage is in associated polarity with its branch
current if the branch current is directed toward the minus end of the voltage.

- 418 -
is equivalent to a branch resistance, V
y
/g
m1
V
y
= 1/g
m1
, as we depict in our final form subcircuit
model of Figure (5.4d). Without even writing an equilibrium Kirchhoff equation, we can then
conclude that the Thvenin resistance, r
d
, presented to the gate of transistor M2 by the M1 subcir-
cuit is
o1
d o1
m1 m1 o1 m1
r
1 1
r r ,
g 1 g r g
= = ~
+
(5-16)
where the indicated approximation reflects the strong prospects that g
m1
r
o1
>> 1. For large gate
aspect ratio and/or a relatively large reference current, I
ref
, g
m1
is reasonably large (tens of
millimhos). In turn, the resistance seen at the output port of the diode-connected network is, as is
the resistance of a conventional PN junction diode, relatively small (high tens to a few hundreds
of ohms in the case of a diode-connected MOSFET).
The discovery that the small signal model of the diode-connected transistor, M1, is a
simple resistance is hardly revolutionary. In particular, transistor M1 functions effectively as a
two terminal branch element since its gate and drain terminals are connected together, as are its
bulk and source terminals. Accordingly, when we replace the subject transistor by its low fre-
quency (and therefore memoryless), small signal equivalent circuit, we clearly end up with a li-
near, two terminal network that has no implicit energy storage elements. But a linear, two ter-
minal, memoryless, network is, by definition, a two terminal linear resistance in that its terminal
voltage is necessarily linearly related to its terminal current in a fashion that is prescribed by the
adopted linear model.
Figure (5.5) is the small signal schematic diagram of the entire NMOS current mirror in
Figure (5.3a), wherein the gate circuit of transistor M2 is supplanted by our Thvenin equivalent
representation of this M1 subcircuit. Of course, we have determined that this Thvenin
representation consists only of a simple two-terminal resistance, r
d
, as stipulated by (5-16).
Moreover, our mathematical ohmmeter, comprised now of the independent current source, I
x
,
and its companion terminal voltage V
x
, is appended to the output port of the mirror. Since there
is no Thvenin voltage driving the gate of transistor M2, the gate-source signal voltage, V
a
, ap-
plied to M2 is zero. This zero signal voltage renders g
m2
V
a
= 0
3
, whence, and again by inspec-
tion, we see that output resistance R
out
is

Figure (5.5). Low frequency, small signal model used to compute the output resistance, R
out
, of the NMOS
current mirror. In terms of mathematical ohmmeter variables, this resistance is R
out
= V
x
/I
x
.

3
A controlled current or a controlled voltage source must not be set to zero indiscriminately when evaluating a
circuit resisitance. As in the present case, such a controlled source may assume a null value, but only if network
conditions compel the source current (or voltage) to vanish.
r
o2
r
d
g V
m2 a
V
a
V
x
I
x
R
out
M1
M2
x k
21
+V
dd
I
ref
+V
kk
V
ref
I
k
I
d1
R
out

- 419 -
x
out o2
x
V
R r .
I
= = (5-17)
As noted earlier, we should like to have R
out
large. Since R
out
in this case is merely the drain-
source channel resistance of transistor M2, large R
out
requires that M2 have a long channel length
and/or M2 should conduct a relatively small quiescent drain current.
We note, perhaps with some chagrin, that the effort we expended to determine the
Thvenin network driving the M2 gate turned out to be inconsequential in that R
out
is indepen-
dent of the electrical properties observed at the gate of transistor M2. Resistance R
out
is
understandably independent of gate parameters, because the gate of a MOSFET conducts no
static current. Moreover, no excitation prevailed at the M2 gate site. However, our efforts have
not been expended in vain, for we shall commonly encounter diode-connected transistors to
which we can directly apply the fruits of the aforementioned analysis.
EXAMPLE #5.2:
In the NMOS current mirror of Figure (5.3a), spurious signals perturb the
voltages, V
dd
and V
kk
, in the respective amounts of AV
dd
and AV
kk
. The
reference current source, I
ref
, which can be presumed constant, has a ter-
minal resistance of R
r
. Determine the approximate resultant change, say
AI
k
in the quiescent current, I
k
, established by the mirror. Explain all
approximations, and offer suggestions as to how the spurious signal-in-
duced output current fluctuation can be minimized in view of the stipu-
lated voltage changes.
SOLUTION #5.2:

Figure (5.6). (a). Low frequency, small signal model of the M1 subcircuit for the NMOS current mirror of
Figure (5.3a). The model is used in Example #5.2. (b). Low frequency, small signal model of
the NMOS current mirror of Figure (5.3a). This model is also used in Example #5.2.
(1). We begin by determining the Thvenin equivalent circuit driving the gate of transistor M2.
Unlike the discussion of the preceding section, this Thvenin representation embraces a
Thvenin voltage owing to the non-ideal nature of current source I
ref
and the stipulated
change, AV
dd
, in power line voltage. To this end, Figure (5.6a) depicts the small signal model
of the M1 subcircuit. Rather than representing transistor M1 by its small signal model, we
rely on our recent experience, which affirms that a diode-connected transistor (M1) can be re-
placed by a two-terminal resistance of value r
d
, as defined in (5-16). Resistance R
r
accounts
for the finite terminal resistance associated with current source I
ref
, while the perturbation,
r
o2
g V
m2 a
V
a
+
R
r
r
d
V
t1
R
t1
R
t1
V
dd k V
d1 dd
V
kk
I
k
(a). (b).

- 420 -
AV
dd
, in voltage V
dd
can be viewed as a small signal voltage source. Recall that in the preced-
ing section, AV
dd
is effectively expunged because V
dd
is taken as an ideal, constant voltage
source. Moreover, R
r
in the previous section of material is infinitely large owing to the pre-
sumed ideal nature of current source I
ref
. The subject model produces a Thvenin voltage,
V
t1
, at the output port of the M1 subcircuit of
d
t1 dd d1 dd
d r
r
V V k V ,
r R
| |
= =
|
+
\ .
(E2-1)
where k
d1
, the voltage divider in (E2-1), is
d d
d1
d r r m1 r
r r 1
k .
r R R g R
= ~ ~
+
(E2-2)
The indicated approximation exploits our awareness that the resistance, r
d
, of a diode-con-
nected MOSFET is small and approximately equal to 1/g
m1
, while we expect a reasonably
well designed current source to exude a large current source terminal resistance, R
r
.
The Thvenin scenario is finalized by determining the Thvenin output resistance at the drain
port of transistor M1. The simplicity of the network before us obviates the need to exploit
our mathematical ohmmeter here. In particular, we always set to zero all independent energy
sources in the process of evaluating a network resistance. In this case, there is only one such
independent source; namely, AV
dd
. With AV
dd
clamped to zero, inspection alone dictates a
Thvenin resistance, R
t1
, of
o1
t1 d r r r
m1 o1 m1 m1
r 1 1
R r R R R ,
1 g r g g
| | | |
= = ~ ~
| |
+
\ . \ .
(E2-3)
where the approximations reflect large R
r
and g
m1
r
o1
>> 1. It follows that this Thvenin
resistance is essentially determined by the terminal resistance associated with the diode-con-
nected first transistor.
(2). Figure (5.6b) offers the small signal model of the entire NMOS mirror. In this model, we
have exploited the facts that the bulk-source signal voltage for M2 is zero, the gate of transis-
tor M2 is driven by the Thvenin model deduced in the preceding part of this solution, and
the spurious change, AV
kk
, behaves as a small signal voltage source applied with respect to
ground at the drain terminal of transistor M2. Since the considered network is linear,
superposition theory can be invoked to determine the net change, AI
k
, in current, I
k
. In
particular, with AV
kk
= 0, we see that the control voltage, V
a
, is V
a
= k
d1
AV
dd
; hence AI
k
=
g
m2
V
a
= g
m2
k
d1
AV
dd
. On the other hand, AV
dd
= 0 constrains voltage V
a
to zero. Resultantly,
AI
k
= AV
kk
/r
o2
. It follows that
kk
k m2 d1 dd
o2
V
I g k V .
r
= + (E2-4)
Recalling (E2-2), we can write
m2
m2 d1
m1 r
g
g k .
g R
~ (E2-5)
But, transistor M2 has a gate aspect ratio that exceeds the gate aspect ratio of transistor M1 by
a factor of k
21
. Additionally, the drain current flowing in M2 is a factor of k
21
larger than the
drain current of M1. Since the forward transconductance of a saturated MOSFET is propor-
tional to the square root of the product of gate aspect ratio and quiescent drain current,
m2 21
m2 d1
m1 r r
g k
g k .
g R R
~ = (E2-6)
We conclude that the perturbation in drain current I
k
is given by

- 421 -
kk 21 dd kk
k m2 d1 dd
o2 r o2
V k V V
I g k V .
r R r
= + ~ +
(E2-7)
The result in (E2-7) tends to mirror expectations. In particular, the closer I
ref
is to an ideal
current source and the closer transistor M2 emulates an ideal controlled current source at its
drain port, the less sensitive current I
k
is to perturbations in the voltages, V
dd
and V
kk
. Ideality
with respect to I
ref
means resistance R
r
is infinity, in which case, the first term on the right
hand side of (E2-7) vanishes. If the drain port of M2 emulates an ideal (controlled) current
source, r
o2
is infinitely large, and the second term on the right hand side of (E2-7) goes to
zero. We also note that too large of a current mirroring factor, k
21
, aggravates the sensitivity
of current I
k
with respect to the power bus voltage, V
dd
. The latter situation also reflects
engineering expectation for if V
dd
fluctuates, I
ref
is perturbed (assuming I
ref
is a practical cur-
rent source). Once I
ref
fluctuates, I
k
necessarily changes for the current gain, I
k
/I
ref
, is directly
proportional to k
21
. Indeed, I
k
/I
ref
k
21
if channel length modulation in transistor M2 is
minimal.
5.3.2. CURRENT MIRROR WITH SOURCE DEGENERATION
[1]

The current mirrors in Figure (5.3) offer limited design flexibility with respect to the
output resistance, R
out
. Recall from (5-15) that this output resistance establishes the sensitivity of
output current, I
k
, with respect to small perturbations in the applied voltage, V
kk
. In particular, a
targeted small sensitivity to applied voltage mandates a large output resistance. If we appeal to
(5-17), we see that R
out
in Figure (5.3a) is determined exclusively by the channel resistance, r
o2
,
implicit to NMOS transistor M2. Thus, the only direct means afforded us to adjust, or to tune,
R
out
is to change current I
k
(smaller I
k
for larger R
out
). Unfortunately, this design degree of free-
dom may not be available, for current mirrors are often implemented to establish a required cur-
rent, I
k
, which is presumably optimal, or at least preferred, for a particular application. Yet
another problem arises when the application to which the design effort is focused requires that
deep submicron transistors be utilized in the mirror. We recall that very small drawn channel
lengths beget proportionately small channel length modulation voltages, which in turn result in
small drain-source channel resistances at given quiescent drain currents. We therefore expect
that low bias current sensitivity to applied voltage is a challenge for deep submicron technolo-
gies.

Figure (5.7). Schematic diagram of a source-degenerated NMOS
current mirror. An analogous source-degenerated
PMOS mirror can also be forged.
M2
x k
21
M1
R
ss
R /k
ss 21
+V
dd
I
ref
+V
kk
I
k
R
out

- 422 -
A viable mitigation of the foregoing dilemma is offered by the so-called source-degene-
rated NMOS current mirror offered in Figure (5.7). The schematic diagram is similar to that of
the simple NMOS mirror in Figure (5.3a), save for the insertion of resistances, R
ss
and R
ss
/k
21
, in
the transistor source terminals. These resistances are called source degeneration elements for, as
we shall witness when we address MOSFET amplifiers, they reduce, or degenerate, the for-
ward transconductances, and thus the overall I/O gain, of their respective transistors. We are
also about to see that if the source degeneration resistances are selected in accordance with the
elemental stipulations in the subject circuit schematic diagram, k
21
must necessarily equate to the
ratio of the gate aspect ratio of transistor M2 to the transistor M1 gate aspect ratio. If I
k
= k
21
I
ref
,
the gate-source voltage, V
gs2
, of transistor M2 is forced to replicate the gate-source voltage, V
gs1
,
of M1. This declaration follows from the Kirchhoff equilibrium relationship,
ss
gs1 ref ss gs2 k
21
R
V I R V I ,
k
| |
| + = +
|
\ .
(5-18)
whence, with I
k
= k
21
I
ref
,
k
gs1 gs2 ref ss
21 ref
I
V V I R 1 0 .
k I
| |
|
= =
|
\ .
(5-19)
Of course, the Schichman-Hodges model affirms that if V
gs1
= V
gs2
produces I
k
= k
21
I
ref
, parame-
ter k
21
is the ratio of the gate aspect ratio of transistor M2 to the gate aspect ratio of M1.
There is another important ramification to the source degeneration resistances deployed
in the mirror of Figure (5.7). In particular, if V
gs1
= V
gs2
, (5-18) confirms that the drop, I
ref
R
ss
,
across the source degeneration resistance, R
ss
, for transistor M1 is identical to the voltage drop,
I
k
R
ss
/k
21
, across the source degeneration resistance, R
ss
/k
21
, used for transistor M2. The equal
resistive drops means that the quiescent voltages established with respect to ground at each
transistor source node are the same. In turn, equal source terminal voltages manifest equal bulk-
source biases since both transistors have their respective bulk terminals returned to circuit
ground. We can therefore conclude that the threshold voltages, V
hn1
and V
hn2
, of M1 and M2,
respectively, while subject to bulk-induced threshold modulation, are, at least in theory, identi-
cally equal to a potential that is somewhat greater than the zero bias value of transistor threshold
voltage.
With V
gs1
= V
gs2
A V
gs
, V
hn1
= V
hn2
A V
hn
(inclusive of body effect) and V
1
= V
2
A V
,
(5-10) yields
( )
( )
2
hn
ref n gs hn
2
kk ref ss dsat
k 21 n gs hn
V
I V V 1
V
.
V I R V
I k V V 1
V
|
|
| |
| ~ +
|
\ .
| |
|
~ +
|
\ .
(5-20)
These two relationships lead to

- 423 -
kk ref ss dsat
k 21 ref
hn
V I R V
1
V
I k I ,
V
1
V
| |
|
+
|
=
|
|
+
|
|
\ .
(5-21)
which is similar in form to (5-14) for the simple (non-degenerated) NMOS current mirror. Since
V
dsat
= (V
gs
V
hn
), selecting V
kk
in the neighborhood of (I
ref
R
ss
+ V
gs
) mitigates channel length
modulation. Alternatively, large V
, which requires a suitably long drawn channel, likewise off-

sets channel length modulation. Thus, if we satisfy one or both of these design targets, we
achieve I
k
k
21
I
ref
, which is indicative of an ideal current mirror.
If the shunt resistance associated with the reference current source, I
ref
, is infinitely
large, current I
k
proudly boasts no sensitivity to power line voltage V
dd
. In other words, an ideal
current source, I
ref
, implements infinitely large power supply rejection with respect to V
dd
. On
the other hand, the sensitivity of I
k
to voltage V
kk
is determined by output resistance R
out
in accor-
dance with the generality set forth by (5-15). Deducing an analytical expression for R
out
initiates
with our determining the Thvenin voltage and the Thvenin resistance associated with the gate-
drain output port of the M1 subcircuit. In this case, we can claim immediately that the Thvenin
voltage driving the gate terminal of transistor M2 is zero owing to the fact that the constant and
ideal current source, I
ref
, presents zero signal value to the mirror. Equivalently, we may assert
that a small signal open circuit prevails in the network branch that interconnects voltage V
dd
with
the gate-drain terminal of transistor M1. Moreover, the Thvenin output resistance of the M1
subcircuit bodes no significance in that the gate of transistor M2 conducts no static current and
therefore, no voltage is dropped across this resistance. Accordingly, we can presumably concen-
trate on the small signal analysis of only the M2 subcircuit of the mirror, with the understanding
that zero signal voltage is applied to its gate.
True enough! But nonetheless, we shall proceed with finding the Thvenin resistance
at the output port of the M1 subcircuit for two reasons. First, high frequency currents are con-
ducted by MOSFET gates, whereupon it may be that the subject Thvenin resistance establishes
a critical time constant with an M1 device capacitance. Second, we shall encounter source-
degenerated, diode-connected transistors as building block components in our future network
deliberations, so we are well advised to execute and file for future reference in our design note-
books the pertinent circuit analysis and its results.
Figure (5.8) is the small signal model for determining the M1 Thvenin resistance, R
t1
,
which we shall calculate as the ratio, V
y
/I
y
, of mathematical ohmmeter variables. We recall our
modeling experience with the diode-connected transistor in the conventional NMOS mirror of
Figure (5.3a). This modeling experience suggests that the M1 diode-connected unit we are pre-
sently examining establishes a drain to source resistance of 1/g
m1
, if channel resistance r
o1
is
large. In turn, our first blush estimate of the Thvenin output resistance is R
t1
= 1/g
m1
+ R
ss
. In-
deed, this is a reasonably accurate first order estimate of R
t1
, but it is not strictly correct in that
body effect prevails herewith. In support of this contention, we note that unlike the network in
Figure (5.3a), which grounds both the source and the bulk terminals of transistor M1, the dia-
gram in Figure (5.7) portends only the grounding of the bulk terminal for transistor M1. It fol-
lows that the model shown in Figure (5.8) properly incorporates a bulk transconductance effect
of
b1
g
m1
V
2
, where V
2
symbolizes the signal component of the bulk-source voltage applied to
transistor M1. In general, we recall that a very thin gate oxide, T
ox
, begets very small
b
. Of

- 424 -
course,
b
=0 implies no bulk-induced transconductance.

Figure (5.8). Small signal model used to determine the Thvenin output resistance, R
t1
, presented at the output
port of the M1 subcircuit in the source degenerated mirror of Figure (5.7).
In the small signal model of Figure (5.8), we have delineated key branch currents in or-
der to facilitate the construction of the requisite Kirchhoff equations. In particular,
1 y y ss
2 y ss
V V I R
,
V I R
=
=
(5-22)
and
( )
y y m1 1 b1 m1 2 o1 y ss
V I g V g V r I R . = + (5-23)
Upon substituting (5-22) into (5-23), followed by the obligatory rearrangement of terms, we find
that
( )
y
b1 m1 o1
t1 o1 ss
y m1 m1 o1
V
1 1 g r
1
R r R .
I g 1 g r
(
+ +
(
= = +
(
+
(

(5-24)
The first term on the right hand side of this expression represents our familiar small signal resis-
tance of a diode-connected transistor. Our inspection of the last term, which accounts for the
resistance, R
ss
, placed in the source lead of transistor M1, suggests that the immediate effect of
BITM is to increase very slightly the witnessed value of this series resistance. Nevertheless, our
first order estimate of the value of Thvenin resistance R
t1
is apparently spot on. In particular, if
g
m1
r
o1
>> 1 (which is almost always true) and
b1
<< 1 (which is true for thin gate oxide layers),
( )
b1 m1 o1
t1 o1 ss ss
m1 m1 o1 m1
1 1 g r
1 1
R r R R .
g 1 g r g
(
+ +
(
= + ~ +
(
+
(

(5-25)
Our analytical task is completed by applying the low frequency, small signal MOSFET
model to the M2 subcircuit of the source degenerated current mirror. We display this model in
Figure (5.9), where we have once again identified relevant branch currents. The model, which
includes the inconsequential Thvenin resistance, R
t1
, disclosed above, projects
M1
R
ss
R
ss
+V
dd
I
ref
r
o1
g V
m1 1

b1 m1 2
g V
V
1
V
2
I
y
I
y
V
y
R
t1
R
t1
I g V g V
y m1 1 b1 m1 2


- 425 -

Figure (5.9). Small signal model used to determine the Thvenin output resistance, R
out
,
presented at the output port of the source degenerated mirror in Figure (5.7).
ss
a b x
21
R
V V I ,
k
| |
| = =
|
\ .
(5-26)
and
( )
ss
x x m2 a b2 m2 b o2 x
21
R
V I g V g V r I .
k
| |
| = +
|
\ .
(5-27)
Subsequent to our inserting (5-26) into (5-27), we find that
( )
x ss ss
out b2 m2 o2
x 21 21
V R R
R 1 1 g r .
I k k
( | |
( | = = + + +
|
(
\ .
(5-28)
For g
m2
r
o2
>> 1 and
b2
<< 1,
( )
ss ss ss
out b2 m2 o2 m2 o2
21 21 21
R R R
R 1 1 g r 1 g r .
k k k
( ( | | | |
( ( | | = + + + ~ +
| |
( (
\ . \ .
(5-29)
Since transistor M2 has a gate aspect ratio that exceeds the gate aspect ratio of M1 by a factor of
k
21
, and since M2 conducts a static current that is larger than the static current of M1 by the same
factor (k
21
), g
m2
/g
m1
= k
21
. It follows that (5-29) can be simplified to the form,
( )
out m1 ss o2
R 1 g R r . ~ + (5-30)
It is now safe to say that the source degenerated current mirror of Figure (5.7) proac-
tively addresses the output resistance shortfall we identified in the conventional mirror of Figure
(5.3a). In particular, the present output resistance embellishes the M2 channel resistance, r
o2
,
which we recall as the actual output resistance of the original current mirror, by an approximate
factor of (1 + g
m1
R
ss
). In a word, the degenerated mirror improves on the current sensitivity of
the original mirror by the factor, (1 + g
m1
R
ss
). But as is perennially the case whenever we suc-
ceed in enhancing or optimizing circuit performance, engineering prices are paid. In the present
case, two prices surface. The first is increased power dissipation. Whereas power needs to be
supplied to only the two transistors embedded in the conventional mirror, power in the degene-
rated version must be supplied to the same two transistors and additionally, two circuit resis-
tances; namely, the resistances, R
ss
, and R
ss
/k
21
. If power dissipation is a critical issue, it clearly
behooves us to keep resistance R
ss
as small as practicable. The second price is the need for an
R /k
ss 21
R
t1
r
o2
g V
m2 a

b2 m2 b
g V
V
a
V
b
I
x
I
x
V
x
R
out
I g V g V
x m2 a b2 m2 b


- 426 -
increased voltage, V
kk
. In the present case, V
kk
must bias the drain-source terminals of transistor
M2, and it must establish a suitable voltage across the circuit resistance, R
ss
/k
21
. We can alterna-
tively state that for fixed V
kk
, the second problem amounts to a constrained voltage swing at the
drain-source port of transistor M2. The latter contention impinges at least indirectly on the de-
gree of achievable circuit linearity in the source degenerated current mirror.
5.3.3. CASCODE CURRENT MIRROR
When the source degeneration resistance, R
ss
/k
21
, in Figure (5.7) is supplanted by a
transistor that is biased at its gate with a diode-connected transistor, similar to the biasing of
transistor M2 in Figure (5.7), the source degenerated current mirror is transformed into what is
known as a cascode current mirror. The cascode mirror is depicted schematically in Figure
(5.10), where all transistor bulk terminals are grounded
4
. We note that since the source and bulk
terminals of transistors M3 and M4 are connected to circuit ground, no BITM occurs in these
devices. But threshold modulation in transistors M1 and M2 can be an issue since the source
terminals of these transistors are not grounded. We also note that transistors M1 and M3 have
the same gate aspect ratios, and transistors M2 and M4 also have equal gate aspect ratios But the
latter ratios are a factor of k-times larger than the gate aspect ratios of M1 and M2.
In Figure (5.10), we see that the output sinking current, I
k
, is given approximately by
k ref
I k I . ~ (5-31)
This result is promoted by four observations. First, current I
ref
flows through the drain of
transistor M3. Second, transistors M3 and M4 share the same gate-source voltages. Third, the
gate aspect ratio of M4 exceeds that of M3 by a factor of k. Fourth, we have tacitly ignored
CLM. Dare we now quip Q.E.D as regards the approximate validity of (5-31)?

Figure (5.10). Circuit schematic diagram of an NMOS cascode current mirror.
The bulk terminals of all four transistors are grounded.
As per our source degenerated mirror, let us assume that I
ref
derives from an ideal
source of constant current, which is to say that it boasts infinitely large terminal resistance.
Under this circumstance, the coupling of voltage V
dd
into the gates of either transistor M2 or M4
is precluded. Resultantly, current I
k
is rendered independent of V
dd
. More importantly, the

4
In a twin well process, it may be possible to connect each transistor bulk terminal to its respective source terminal,
thereby negating any bulk-induced modulation of threshold voltages.
M4
M2
+V
dd
I
ref
+V
kk
I
k
R
out
M3
M1
x 1 x k
x 1 x k

- 427 -
inability of V
dd
to couple into the gate of M4 means that no gate-source signal voltage can be
established for M4. In turn, this situation gives rise to a drain to source signal current, g
m4
V
a
, as
we depict in the equivalent circuit of Figure (5.11a), that is forced to zero. The same null stature
applies to the bulk transconductance source,
b4
g
m4
V
b
, since the grounding of both the bulk and
the source terminals remands the bulk-source signal voltage, V
b
, to zero. Resistance R
t3
in this
equivalent circuit represents the Thvenin resistance presented to the gate of transistor M4 by the
diode-connected transistor, M3. This resistance is inconsequential since it conducts no current
and therefore, we can refrain from defining it analytically. Because V
a
= V
b
= 0 in Figure
(5.11a), the only element left standing in the small signal model of transistor M4 is the M4
channel resistance, r
o4
. In effect, transistor M4 in the cascode mirror behaves as a two terminal
resistance and indeed, a rather large drain-source channel resistance.

Figure (5.11). (a). Low frequency, small signal model of transistor M4 in the cascode mirror of Figure
(5.10). (b). Low frequency, small signal model of the M2-M4 subcircuit in the cascode
current mirror of Figure (5.10).
The resultant low frequency model of the M2-M4 subcircuit is the topological structure
appearing in Figure (5.11b). In this model, we have replaced transistor M4 by its channel
resistance, r
o4
, which we now comprehend as an effective source degeneration resistance for
transistor M4. Analogous to the previously defined Thvenin resistance, R
t3
, R
t1
is the presently
inconsequential Thvenin resistance presented to the M2 gate by the subcircuit formed of transis-
tors M1 and M3 in Figure (5.10). But the most important undertone of this modeling exercise is
that the model in Figure (5.11b) is topologically identical to the equivalent circuit we forged in
Figure (5.9) for the conventional form of a source degenerated current mirror. The only
observable electrical difference between the two models is that the source degeneration
resistance, R
ss
/k
21
, in Figure (5.9) appears now as the resistance, r
o4
. This topological similarity
synergizes with our earlier pronouncement to the effect that the cascode mirror is little more than
a special case (indeed, an active form of a special case) of the source degenerated mirror. Its
immediate and practical implication is that we can determine output resistance R
out
in Figure
r
o4
g V
m4 a

b4 m4 b
g V
V
a
V
b
R
t3
= 0 = 0
r
o4
r
o4
(a).
r
o2
g V
m2 1

b2 m2 2
g V
V
1
V
2
R
t1
(b).
I
x
V
x
R
out

- 428 -
(5.11b) merely by modifying the expression for R
out
that we have already filed in our design
notebook for the source degeneration case. Specifically, if we replace R
ss
/k
21
by r
o4
in (5-28), we
see, without need for annoying additional analysis, that
( ) ( )
x
out b2 m2 o4 o2 o4 m2 o4 o2
x
V
R 1 1 g r r r 1 g r r .
I

(
= = + + + ~ +

(5-32)
Because resistance r
o4
is doubtlessly significantly larger than the former degeneration resistance,
R
ss
/k
21
, the output resistance, R
out
of the cascode current mirror is laudably much larger than its
companion output resistance for the conventional mirror.
It is important to appreciate that the channel resistance, r
o4
, which functions as source
degeneration for transistor M2 in Figure (5.10), is large and assuredly much larger than the
passive degeneration resistance, R
ss
/k
21
, which we deployed in the previous current mirror.
Unlike the passive resistance, R
ss
/k
21
, which necessarily supports a static drop of I
k
R
ss
/k
21
, the
active degeneration resistance, r
o4
, does not need to support a static voltage of I
k
r
o4
across its
terminals. Instead, the static voltage required across the drain-source terminals of transistor M4,
where r
o4
is realized, is a drain saturation voltage, which can be as small as only a few tenths of a
volt. This voltage drop is far smaller than the static drop necessarily established across a passive
resistance of value r
o4
. For example, if r
o4
= 20 K, a meager I
k
= 1 mA develops 20 volts across
a passive form of resistance r
o4
. Good luck selling a cell telephone, a global positioning satellite
(GPS) unit for automotive use, or other portable electronic system that requires at least a 20-volt
battery for activation. In a word, voltage V
kk
in the cascode mirror of Figure (5.10) need only be
large enough to ensure that transistors M2 and M4 operate in their saturation domains.
Let us examine more carefully the constraints to which voltage V
kk
is necessarily
subjected. We begin by remembering that the gate-source voltages of transistors M3 and M4 are
the same; that is, V
gs3
= V
gs4
A V
gs
. In view of the facts that transistor M2 has the same gate
aspect ratio and conducts the same drain current that flows through transistor M4, V
gs2
V
gs4
=
V
gs
. This gate-source voltage equality presumes that channel length and bulk-induced threshold
modulations in M4 are negligible. A similar statement applies to transistors M1 and M3; that is,
V
gs1
V
gs3
A V
gs
. We therefore deduce
gs1 gs3 gs4 gs2 gs
V V V V V . ~ = ~ (5-33)
Figure (5.10) additionally confirms that V
kk
must supply drain-source bias to both M2 and M4:
kk ds2 ds4
V V V . = + (5-34)
In order for transistor M2 to remain in saturation, we require V
ds2
(V
gs2
V
hn2
), where V
hn2
, is,
of course, the threshold voltage of transistor M2. Remember that the threshold voltages of
transistors M1 and M2 can be expected to differ from the threshold potential, V
hn4
, of M4 owing
to body effects incurred by the grounding of the bulk terminals of transistors M1 and M2. Since
gs2 gs1 gs3 ds4 gs ds4
V V V V 2V V , = + = (5-35)
M2 is saturated if
ds2 gs2 hn2 gs ds4 hn2
V V V 2V V V . > ~ (5-36)
Inserting this result into (5-34) establishes
kk ds2 ds4 gs hn2
V V V 2V V . = + > (5-37)
Since

- 429 -
dsat1 gs1 hn2 gs hn2
dsat3 gs3 hn4 gs hn4
V V V V V
,
V V V V V
= ~
= ~
(5-38)
we conclude that
kk gs hn2 dsat1 dsat3 hn4
V 2V V V V V ; > = + + (5-39)
that is, voltage V
kk
must be at least as large as nominally one threshold potential above twice the
drain saturation voltage of a transistor. Depending on the channel length of the utilized
transistors, the drain saturation voltage can be in the range of 200 mV to 500 mV, while a gate-
source threshold voltage can be of the order of 400 mV to 800 mV. Accordingly, we can expect
that voltage V
kk
must lie in the range, 800 mV < V
kk
< 1.8 V.
5.3.4. WILSON CURRENT MIRROR
[1]-[2]

Figure (5.12) depicts the basic schematic diagram of the Wilson current sink. As in the
cascode network, we have not shown the bulk terminal connections of transistors, but we
nonetheless assume that these terminals are incident with circuit ground. Thus, bulk-induced
threshold modulation takes place in transistors M1 and M2. However, our analyses and
discussions of the Wilson mirror adopt the simplifying stance of gate oxide layers that are thin
enough to allow for the tacit neglect of threshold voltage modulation in all active devices.

Figure (5.12). Circuit schematic diagram of an NMOS Wilson current
mirror. The bulk terminals of all four transistors are
presumed returned to circuit ground.
If we compare the network before us with that of the cascode configuration in Figure
(5.10), we see that the Wilson circuit interchanges the roles of transistors M3 and M4. In other
words, transistor M3 functions as a diode in the cascode circuit, while in the Wilson network, it
serves effectively as a grounded source amplifier. More than simply a grounded source am-
plifier, M3 implements active feedback from the source of transistor M2 to the source terminal of
M1. This feedback serves to protect current I
k
from spurious vulnerabilities. For example, sup-
pose current I
k
increases by an amount that is not so large as to threaten the removal of transis-
tors M2 and M3 from their saturation domains. Since the diode-connected device, M4, acts as a
two terminal resistance, the increase in current I
k
manifests a commensurate increase in the
drain-source voltage of M4 and hence, in the gate-source voltage of transistor M3. The rise in
M3 gate-source voltage produces a decrease in the drain-source voltage of M3 for, as we learned
M4
M2
+V
dd
I
ref
+V
kk
I
k
R
out
M3
M1
x 1 x k
x 1 x k

- 430 -
in the preceding chapter, I/O (gate to drain) phase inversion is implicit to common source
amplifiers. The decrease in M3 drain-source voltage pulls down the voltage observed at the gate
of M2. With the gate voltage of M2 falling and the source voltage of the same device rising, as
we have already noted, the gate-source voltage of M2 diminishes. This decrease in the M2 gate-
source voltage is met with a decrease in the indicated drain current, I
k
. Accordingly, the original
spurious increase in I
k
is met with a mitigating current decrease to incur an effective stabilization
of the sinking output current. In other words, the original current increase is ostensibly cancelled
by the feedback that is implicit to the Wilson circuit.
Transistors M1 and M3 have identical gate aspect ratios, as do transistors M2 and M4.
But we note that the gate aspect ratios of M2 and M4 are a factor of k larger than the respective
gate aspect ratios of M1 and M3. We shall demonstrate that the indicated output resistance, R
out
,
is potentially very large, despite being somewhat compromised by the designable factor, k. This
laudable attribute does not stem principally from the source degeneration presented to M2 by the
diode-connected transistor M4. Instead, it arises largely from the series-shunt feedback we have
addressed in the preceding paragraph. We shall more definitively investigate the feedback impli-
cit to the Wilson cell when we study the common source-Wilson cascode broadband amplifier
later in this text.
We see that the applied input current, I
ref
, flows through the drain of transistor M3.
Since the gate-source voltages, V
gs3
and V
gs4
, of M3 and M4, respectively, are identical, M3 and
M4 comprise a traditional two-transistor current mirror. The drain current resultantly conducted
by transistor M4 is necessarily kI
ref
, where we have made use of the fact that the gate aspect ratio
of M4 is larger than that of transistor M3 by factor k. In asserting this mirrored current value, we
have ignored the effects of CLM in M3 and M4. The mirrored current flows through M2,
whence we conclude that output current I
k
approximates kI
ref
.
Let us now support the foregoing intuitive disclosures with a more focused analysis.
We begin by monitoring the drain-source voltage, V
ds3
, of transistor M3 as V
ds3
= (V
gs2
V
gs1
+
V
gs4
). Then, by the square law model, modified to account for CLM,
( )
( )
2
gs2 gs1 gs4 gs3 hn
ref n gs3 hn
V V V V V
I V V 1 .
V
|
(
+
(
= +
(
(

(5-40)
Since V
gs3
V
gs4
,
( )
2
gs2 gs1 hn
ref n gs3 hn
V V V
I V V 1 .
V
|
+ | |
|
= +
|
\ .
(5-41)
For transistor M4,
( )
2
hn
k n gs3 hn
V
I k V V 1 ,
V
|
| |
| = +
|
\ .
(5-42)
where we have exploited identical threshold voltages of M3 and M4 resulting from the absence
of body effect in these two devices. Moreover, the CLM voltage, V
, should be nominally the

same in M3 and M4, as long as no wide disparity prevails between the drain-source voltages of
these two devices. We can combine (5-41) and (5-42) to obtain

- 431 -
hn
k ref
gs2 gs1 hn
V
1
V
I kI .
V V V
1
V
| |
|
+
|
=
|
+
|
+
|
|
\ .
(5-43)
In addition to confirming our mirroring intuition, the last expression renders clear the fundamen-
tal purpose of diode-connected transistor M1. To wit, if M1 were supplanted by a short circuit,
so that the input current, I
ref
, is applied directly to the drain of M3, V
gs1
in (5-43) is effectively
zero. This means that the parenthesized correction factor on the right hand side of (5-43) be-
comes
hn
gs2 hn
V
1
V
,
V V
1
V
+
+
+

thereby making it likely that I
k
is noticeably smaller than the mirrored value, kI
ref
, of this current.
But with M1 included in the circuit, it is plausible that V
gs2
equals, or at least closely approx-
imates, V
gs1
, wherein we conclude that I
k
kI
ref
. Thus, the mirroring factor we have noted is ren-
dered virtually insensitive to channel length effects
5
. We should point out that achieving V
gs1

V
gs2
is not a challenge. In particular, since M1 and M2 are physically identical transistors whose
gate aspect ratios are scaled in accord with the quiescent currents they respectively conduct, their
gate-source voltages should be nominally equal, assuming reasonably robust CLM voltages.
Moreover, while it is necessary for the relative gate aspect ratio of transistor M4 to be k, there is
nothing sacred about setting the gate aspect ratio of transistor M2 to k. In a word, it may be both
prudent and desirable in the course of simulating the network to adjust the relative gate aspect
ratio of M2 to effect voltage V
gs2
closely matched to voltage V
gs1
.
In order to determine the output resistance, R
out
, of the Wilson mirror, we turn to the
low frequency, small signal equivalent circuit we display in Figure (5.13). This model reflects
two simplifying and reasonable assumptions. The first of these assumptions is that BITM, which
is nonexistent in transistors M3 and M4, is negligible in transistors M1 and M2. This stipulation
is entirely reasonable for the thin gate oxide MOSFETs that are routinely available from state of
the art integrated process foundries. Our second assumption is the tacit neglect of CLM, which
is equivalent to asserting infinitely large drain-source channel resistances, in transistors M1 and
M4. The latter assumption is justifiable in that M1 and M4 are diode-connected transistors that
exhibit terminal resistances that are no larger than the small resistance values implied by their
respective inverse forward transconductances. We recall from our previous experiences that the
resistances of these diode-connected devices equate to the parallel combination of channel resis-
tance (r
o
) and inverse forward transconductance (g
m
). In turn, this shunt interconnection pro-
duces a resistance that closely approximates 1/g
m
since g
m
r
o
is invariably much larger than one.
Finally, we have delineated various branch currents to facilitate writing the Kirchhoff equili-
brium relationships for the Wilson small signal model.
A conventional circuit analysis of the model reveals

5
It is worthwhile noting that transistor M1 was not included in Wilsons initial seminal disclosure
[2]
.

- 432 -

Figure (5.13). Approximate, low frequency, small signal model used to determine the driving
point output resistance, R
out
, of the Wilson current mirror in Figure (5.12).
( )
x
x o2 x m2 a
m4
I
V r I g V ,
g
= + (5-44)
where
( )
x
b
m4
x
a m3 o3 b b m3 o3
m4
I
V
g
.
I
V g r V V 1 g r
g
=
| |
| = = +
|
\ .
(5-45)
It follows that
( )
x m2
out m3 o3 o2
x m4 m4
V g
1
R 1 1 g r r .
I g g
( | |
( | = = + + +
|
(
\ .
(5-46)
We can argue that the transconductances, g
m2
and g
m4
, are identical because transistors M2 and
M4 have identical gate aspect ratios and conduct the same quiescent current. Because the drain-
source channel resistances of transistors M2 and M3 are large, as is the product, g
m3
r
o3
, (5-46)
collapses to
( )
out m3 o3 o2
R 2 g r r . ~ + (5-47)
Since the current conducted by M2 is k-times larger than the current flowing in transistor M3, r
o2

r
o3
/2, whence
( )
o3
out m3 o3
r
R 2 g r .
k
| |
~ + |
|
\ .
(5-48)
We conclude that the output resistance of the Wilson mirror is large and comparable to that of
the cascode current mirror. We should note, however, that the Wilson output resistance is
compromised by a large ratio, k, of transistor gate aspect ratios
EXAMPLE #5.3:
Design the Wilson current mirror of Figure (5.12) for an output current, I
k
,
of 1 mA when the reference current, I
ref
, is 100 A. For the purposes of
r
o2
g V
m2 a
I
x
I
x
V
x
R
out
1/g
m4
1/g
m1
V
a r
o3
g V
m3 b
g V
m3 b
g V
m2 a
V
b
I g V
x m2 a

- 433 -
this exercise, assume that I
ref
derives from an ideal source of constant cur-
rent. Although the value of voltage V
dd
is inconsequential because of the
presumed ideality of current source I
ref
, use a power line voltage, V
dd
, of
3.8 volts. Assume that V
kk
is set to a steady state value of 2.7 volts. For
the NMOS transistor, whose parameters appear in Table (4.1) and whose
drawn channel length is 1.5 m, use HSPICE or its equivalent to simulate,
and provide engineering commentary of, the following performance
characteristics:
(a). the static transfer characteristic, I
k
versus V
kk
, for 0 V
kk
4 volts;
(b). the real part of the driving point output impedance, Z
out
, as a function
of signal frequency;
(c). the shunt output port capacitance as a function of signal frequency;
(d). the transient response to voltage V
kk
, where V
kk
is taken as a 2.7 volt
pulse train having 2 SEC pulse widths and a 4 SEC period.
SOLUTION #5.3:
(1). Very little work is required to design the Wilson configuration. We begin by selecting the
gate width of transistors M1 and M3 in Figure (5.12). There is no with problem setting W
1
=
W
3
= L = 1.5 m. But in this case, we shall make W
1
= W
3
= 5L = 7.5 m in order to incur
larger transistor capacitances, which serve to subdue voltage response overshoots to suddenly
applied line voltages. Since we need I
k
= 1 mA, W
2
= W
4
= 10W
1
= 75 m. Making W
1
and
W
3
too large begets very large W
2
and W
4
, which may incur layout challenges that we shall
address in due time. As already noted, larger capacitances in bias networks are generally
desirable in that they tend to mitigate, albeit perhaps incompletely, the overshoots associated
with an abrupt application of voltage V
kk
. We shall observe somewhat dramatic response
overshoots when we address the issue of the transient response to voltage V
kk
.
(2). The area and peripheral dimensions associated with device capacitances compute in accord
with (4-155). We have
11 2
s1 s3 d1 d3 1
s1 s3 d1 d3 1
A A A A 2W L 2.2 x 10 m
.
P P P P W 4L 13.5 m
= = ~ =
= = ~ + =
(E3-1)
In addition,
10 2
s2 s4 d2 d4 2
s2 s4 d2 d4 2
A A A A 2W L 2.25 x 10 m
.
P P P P W 4L 81 m
= = ~ =
= = ~ + =
(E3-2)
In most simulators, these geometrical parameters are inputted in conventional MKS units
(meters, meters
2
, etc.)
(3). Figure (5.14) displays the simulated static transfer characteristic, I
k
versus V
kk
. We can con-
firm that the current, I
k
, ultimately reaches its constant value of 1.008 mA at V
kk
1.6 volts.
The current goes on to increase minutely to 1.0081 mA at V
kk
= 4 volts. The 1.008 mA output
current is within 0.8% of the 1 mA design target. This minute increase in current suggests
excellent power supply rejection, which we understand requires a high output resistance, R
out
.
Undoubtedly, we can lower this error to nearly zero by slightly reducing the gate aspect ratios
of transistors M2 and M4. No attempt is made herewith to reduce this error since it lies well
within routine processing and manufacturing tolerances typically embodied by integrated cir-
cuit design.
As already noted, the 1.008 mA current level is attained at about V
kk
= 1.6 volts. An inspec-
tion of the network in Figure (5.12) affirms that V
kk
must be large enough to supply at least a

- 434 -
drain saturation voltage, V
dsat2
, across the drain-source terminals of transistor M2, plus a gate-
source bias, V
gs4
, for transistor M4. Table (5.1) shows the operating point data for all Wilson
transistors in Figure (5.12), where at this operating point, V
dd
= 3.8 volts, V
kk
= 2.7 volts, and
I
ref
= 100 A. We see from the static operating point data that V
dsat2
= 0.5060 volts, while V
gs4

= 1.1027 volts. Thus, V
kk
V
dsat2
+ V
gs4
= 1.609 volts, which is only 0.54% larger than the
extracted minimum required voltage value ( 1.6 volts) of V
kk
.

Figure (5.14). Simulated static transfer characteristic, I
k
-versus- V
kk
, of the Wilson current
mirror shown in Figure (5.12) and studied in Example #5.3.
M2 M4 M3 M1
MODEL USCN USCN USCN USCN
ID 1.0073E-03 1.0081E-03 1.0001E-04 9.9961E-05
IBD -2.7080E-12 -1.1107E-12 -1.1071E-12 -2.3499E-12
IBS -1.1152E-12 -2.7662E-15 -2.7707E-16 -1.1079E-12
VGS 1.2371 1.1027 1.1027 1.2425
VDS 1.5973 1.1027 1.0973 1.2425
VBS -1.1027 0.0000 0.0000 -1.0973
VTH 0.7160 0.5739 0.5770 0.7244
VDSAT 0.5060 0.4985 0.4954 0.5029
GM 3.2979E-03 3.2431E-03 3.2253E-04 3.2798E-04
GDS=1/ro 1.6219E-05 1.5948E-05 1.5781E-06 1.6053E-06
GMB 3.5151E-04 5.4415E-04 5.5825E-05 3.6683E-05
CBD 9.9478E-14 1.1987E-13 1.3350E-14 1.1450E-14
CBS 1.1978E-13 1.5182E-13 1.6919E-14 1.3348E-14
CGSOVL 2.4000E-14 2.4000E-14 2.4000E-15 2.4000E-15
CGDOVL 2.3250E-14 2.3250E-14 2.3250E-15 2.3250E-15
CGBOVL 7.7000E-16 7.7000E-16 7.7000E-16 7.7000E-16
CGS 2.5444E-13 2.5444E-13 2.5444E-14 2.5444E-14
CGD 0.0000E+00 0.0000E+00 0.0000E+00 0.0000E+00
CGB 0.0000E+00 0.0000E+00 0.0000E+00 0.0000E+00
Table (5.1). Simulated operating point data for the Wilson mirror in Figure (5.12). The operating point is
fixed by V
dd
= 3.8 volts, V
kk
= 2.7 volts, and I
ref
= 100 A.
(4). Figure (5.15) is the simulated frequency response for the shunt output resistance, R
out
, of the
Wilson mirror operated at V
dd
= 3.8 volts, V
kk
= 2.7 volts, and I
ref
= 100 A. Because of the
0
0.2
0.4
0.6
0.8
1.0
1.2
0 1 2 3 4
Input Voltage, (volts) V
kk
O
u
t
p
u
t

C
u
r
r
e
n
t

(
m
A
)
I
k

- 435 -
transistor capacitances itemized in Table (5.1), this resistance monotonically degrades with
increasing frequency. At low frequencies, HSPICE yields R
out
= 14.3 MEG, which is
assuredly indicative of a high quality current sink. Let us see how this simulated value com-
pares with the output resistance predicted by (5-48). To this end, we know that k = 10, while
Table (5.1) gives g
m3
= 322.53 mho and r
o3
= 633.67 K. Accordingly, (5-48) predicts a
shunt output resistance of R
out
= 13.08 MEG, which is 8.55% lower than the simulated
value. This error lies within the expected accuracy limits of our manual analysis.

Figure (5.15). Simulated frequency response of the shunt output resistance for the Wilson cur-
rent mirror shown in Figure (5.12) and studied in Example #5.3.
We have already noted that transistor capacitances incur a frequency rolloff in the output
capacitance response. It is therefore germane for us to study Figure (5.16), which shows the
frequency response of the shunt output capacitance, C
out
, of the Wilson circuit operated at the
stipulated quiescent level. The simulated response shows essentially constant shunt output
capacitance of an amount slightly larger than 373 fF over a passband spanning a KHz to 10
MHz. When we study high frequency electronic amplifiers, we shall learn how to estimate
analytically the capacitances effectively manifested at network input and output ports.
(5). Figure (5.17) displays the simulated transient response to the specified pulse train of voltage
V
kk
. We witness dramatic current peaking whenever V
kk
rises suddenly to 2.7 volts; indeed,
overshoots corresponding to currents larger than 10.6 mA are recorded. A negative current
peak of about 1.8 mA is also transparent whenever V
kk
turns off to its zero value. In addi-
tion to this excessive positive and significant negative current peaking, we can see that the
circuit requires about 209 nSEC of settling time. In other words, it takes about 209 nSEC af-
ter voltage V
kk
rises suddenly to its standby level of 2.7 volts for the Wilson mirror to achieve
its steady state output current of 1.008 mA.
We have a lot to talk about, although some parts of our discussion must remain parochial un-
til we address more complex electronic circuits and systems. Let us begin by returning to Ta-
ble (5.1). In that table, we note, as expected, that the gate-source voltages, V
gs
, of transistors
M3 and M4 are identical. Moreover, and as we predicted earlier in view of including transis-
tor M1 into the Wilson network, the gate-source voltages of M1 and M2 are nearly the same.
In fact, the gate-source voltages of M1 and M2 are so close that adjustment of the M2 gate as-
pect ratio, which would be aimed toward equalizing gate-source biases, is arguably unneces-
sary.
0
3
6
9
12
15
0.001 0.01 0.1 1 10
Signal Frequency (MHz)
S
h
u
n
t

O
u
t
p
u
t

R
e
s
i
s
t
a
n
c
e

(
M
e
g
)

- 436 -

Figure (5.16). Simulated frequency response of the shunt output capacitance for the Wilson
current mirror shown in Figure (5.12) and studied in Example #5.3.

Figure (5.17). Simulated transient output current response to a pulse train excitation of the
Wilson current mirror shown in Figure (5.12) and studied in Example #5.3.
We observe in Table (5.1) that the active gate-drain capacitances, C
gd
, of all transistors are
zero. This observation synergizes with our understanding of the manner in which the drain
depletion zones affect gate-drain capacitances of saturated transistors. In contrast, however,
overlap components to gate-drain (as well as to gate-source) capacitances prevail.
The bulk transconductance, g
mb
(=
b
g
m
) bears no significance for transistors M3 and M4,
since both the source and bulk terminals of these two transistors are grounded. Our inspec-
tion of Table (5.1) indicates that the bulk transconductances for the remaining two transistors
remain respectively only moderately significant since both are smaller than 11.2% of the for-
ward transconductance, g
m
of these devices. This is to say that
b1
= 0.112, while
b2
= 0.107.
Apparently, our decision to ignore body effect in M1 and M2 warrants applause.
The low frequency output resistance of more than 14 MEG is laudable and is indeed indica-
tive of the nearly constant current observed in Figure (5.14) for V
kk
1.6 volts. But we note
in Figure (5.15) that this driving point output resistance attenuates dramatically with increas-
370.0
370.5
371.0
371.5
372.0
372.5
373.0
373.5
374.0
0.001 0.01 0.1 1 10
Signal Frequency (MHz)
S
h
u
n
t

O
u
t
p
u
t

C
a
p
a
c
i
t
a
n
c
e

(
f
F
)
0
0.5
1.0
1.5
2.0
2.5
3.0
-3
0
3
6
9
12
0 2 4 6 8 10 12
Time ( SEC)
C
u
r
r
e
n
t
,

(
m
A
)
I
k
V
o
l
t
a
g
e
,

(
v
o
l
t
s
)
V
k
k

- 437 -
ing signal frequency. The non-constant nature to the output resistance is a perennial problem
with active current sources. It is caused, of course, by unavoidable transistor capacitances
and, at least in this case, the feedback nature of the Wilson topology. The problem is often
sufficiently severe in broadband networks to motivate circuit designers away from active cur-
rent sinks and sources and towards conventional linear resistances. An acceptable, two-ter-
minal, monolithic resistor doubtlessly does not have the resistance value indigenous to an
active circuit operated at low frequencies, but at very high signal frequencies, its resistance
value may, in fact, exceed that of a current source or sink.
The output capacitance of better than 370 fF is typical of active current sinks and sources and
contributes to the rather sharp decrease of output resistance over signal frequency. In the
present case, capacitances implicit to all transistors manifest the aforementioned settling time
of roughly 209 nSEC. This settling time corresponds to a frequency of only 4.8 MHz, which
explains why circuit designers are concerned with current sinks and sources that appear in the
forward signal flow paths of networks destined to operate at gigahertz frequencies.
Most importantly, the transient response displayed in Figure (5.17) causes great concern.
The overshoots, which derive from transistor capacitances whose voltages are incapable of
responding quickly to sudden changes in excitation, can damage transistors. It is therefore
understandable that in an attempt to reduce the kind of current spiking shown in Figure
(5.17), the power supplies applied to many high performance and particularly sensitive cir-
cuits are designed so that bus line voltages are brought to their steady state values gradually,
not abruptly. These regulated power supplies, which proactively address undesirable network
startup transients, are one of several reasons that explain why we have to wait for our laptop
computers, cellular telephones, GPS receivers, and such to wake up.
5.4.0. VOLTAGE REFERENCES
A voltage reference is active subcircuit whose output port sustains a voltage that is
suitable for biasing one or more other active subcircuits in a considered network. In the simplest
of routinely encountered designs, the reference voltage is used to energize the gate-source port of
a transistor whose drain current functions as a constant current source or sink. In these cases, the
Thvenin resistance we see looking into the reference output port need not be especially small
since the gate of the gate-source port the reference is intended to drive conducts no static current.
In high performance applications, stringent operating requirements are invariably imposed on the
open circuit output voltages and Thvenin output impedances of the voltage reference module.
For example, we may require a reference output port to drive biasing control ports of broadband
amplifiers, broadband operational transconductors, high bit-rate data converters, precision
instrumentation networks, high frequency voltage controlled oscillators, and other sophisticated
electronics. These control voltages may be used to establish predictable and reliable,
temperature invariant, and stable transconductances, I/O impedances or other performance
metrics that must be rendered substantively insensitive to spurious perturbations in the applied
power supply voltage. Moreover, the reference voltages must be relatively oblivious to a variety
of parasitic phenomena incurred by the layout or the general environment into which our
network is embedded.
5.4.1. ACTIVE VOLTAGE DIVIDER
We commence our present discussion by studying the active voltage divider offered in
Figure (5.18a). As usual, bulk connections are not delineated, but both transistor bulk terminals
are indeed returned to circuit ground. In the subject circuit, transistors M1 and M2 are identical

- 438 -
except for the fact that the gate aspect ratio, W
1
/L
1
, of transistor M1 differs from the gate aspect
ratio, W
2
/L
2
, of M2 in accordance with the design stipulation,

Figure (5.18). (a). Active voltage divider for a series interconnection of two NMOS diode-
connected transistors. (b). Passive model of the circuit in (a). Resistance R
x

is given by (5-57).
2
1 1
12
2 2
W L
k .
W L
= (5-49)
Both transistors function MOSFET diodes since their respective gate and drain terminals are
connected together. These connections ensure that the transistors operate in saturation. In the
absence of significant CLM, (5-4) and (5-5) are therefore applicable. Since fast responses are
not an issue in a static divider and indeed, in most biasing networks, the device channel lengths,
L
1
and L
2
, can be large to placate the effects of CLM. Large channel lengths and commensu-
rately large gate widths incur the additional advantage of increased device capacitances that
effectively ground any high frequency signals coupled parasitically to the output port of the di-
vider. Additionally, the approximation of nominally equal threshold voltages, V
hn
, between the
two transistors is valid if the gate oxide thicknesses of the transistors are matched and small.
The upshot of the foregoing discourse allows us to write
( ) ( )
2 2
p n2 dd ref hn n1 ref hn
I V V V V V . = = (5-50)
Parameter |
n1
is directly proportional to W
1
/L
1
, and |
n2
is analogously proportional to W
2
/L
2
.
Thus, (5-50) combines with (5-49) to deliver
dd 12
ref hn
12 12
V k 1
V V .
k 1 k 1
| |
= +
|
+ +
\ .
(5-51)
We observe that for k
12
= 1, V
ref
is simply one-half of the supply line voltage. This result is
comforting in that k
12
= 1 is tantamount to a series connection of two identical transistors (inclu-
sive of identical gate aspect ratios) that are configured to operate as two-terminal elements. In
other words, the static characteristics of the circuit for k
12
= 1 emulate those of a simple voltage
divider comprised of two identical resistances. Strictly speaking, however, we need to be mind-
M2
V
ref
+V
dd
+V
dd
I
p
I
p
(a). (b).

V
hn

k R
12 x
R
x
M1
V
ref

V
hn

x 1
x k
12
2

- 439 -
ful of the fact that (5-51) and the voltage result corresponding to the special case of unity k
12
are
approximations because the body effect in M2 renders its threshold potential larger than that of
M1, which experiences no BITM.
The foregoing resistive divider interpretation can be expanded by modeling the circuit
in Figure (5.18a) by the behavioral representation in Figure (5.18b). In the latter diagram, the
current, I
p
, is given by
( )
dd hn
p
12 x
V 2V
I ,
k 1 R
=
+
(5-52)
whereupon voltage V
ref
follows as
( )
dd hn
ref x p hn hn
12
V 2V
V R I V V ,
k 1
= + = +
+
(5-53)
which is identical to (5-51). The model electrically reflects the static performance of the two-
transistor biasing cell if we choose the value of resistance R
x
, such that the static power, P
diss
,
dissipated by the active divider equates to the power dissipated in the behavioral network.
Specifically,
( )
( )
( )
2
dd dd hn
diss dd p dd n1 ref hn
12 x
V V 2V
P V I V V V ,
k 1 R
= = =
+
(5-56)
where we have invoked (5-50) and (5-52). The last expression produces the requisite resistance,
( )( )
dd h
x
2
n1 12 ref h
V 2V
R .
k 1 V V
=
+
(5-57)
EXAMPLE #5.4:
The circuit in Figure (5.18a) is to be designed to deliver a reference output
voltage, V
ref
, of 1.25 V when the supply line, which supports a static vol-
tage, V
dd
, of 3 V, delivers 5 mW of power to the active divider. The n-
channel transistor utilized in the network is parameterized in Table (4.1).
Determine suitable gate aspect ratios for the two devices and confirm the
propriety of the design through simulations executed with HSPICE or
similar computer-aided design software.
SOLUTION #5.4:
(1). With a supply voltage of V
dd
= 3 V and a desired circuit power dissipation of P
diss
= 5 mW,
the drain current conducted by both transistors, which is also the power supply current, I
p
, in
the circuit of Figure (5.18a) is I
p
= P
diss
/V
dd
= 1.667 mA. We are free to make this current
smaller than the indicated computed value since no one is going to ostracize a circuit designer
who delivers targeted circuit performance at reduced power dissipation levels.
(2). Since the threshold voltage and transconductance parameter of the transistor are not known
explicitly, we initiate the design exercise by investigating the volt-ampere characteristics of
the transistor operated as a diode for the case of unity gate aspect ratio. The pertinent base-
line circuit for this simulation is given in Figure (5.19), where the null voltage source in se-
ries with the drain terminal facilitates the extraction of the simulated drain current. The
transistor whose parameters appear in Table (4.1) features a channel length, L of 0.5 m. But
the static nature of the circuit of interest, together with a desire to mitigate the dominant im-

- 440 -
pact of channel length modulation, encourage adopting a channel length that is longer than
0.5 m. To this end, choose L =2 m and, of course, W = 2 m for the initial simulation.

Figure (5.19). Circuit used to simulate the diode volt-ampere
characteristics of the transistors used in the voltage
divider design considered in Example #5.4.
(3). An HSPICE simulation of the circuit in Figure (5.19) reveals I
d
= 23.537 A if V
ds
is set to
the desired reference output voltage of 1.25 V and W
1
/L
1
= 2 m/2m = 1. This result im-
plies the need to increase the gate aspect ratio of the device by a factor of 1.667 mA/23.537
A = 70.81, which means that W
1
= (70.81)(2 m) = 141.6 m. At V
ds
= 1.25 V, the simula-
tion for this increased gate aspect ratio delivers I
d
= 1.706 mA, which is higher than the maxi-
mum allowable current of 1.667 mA by about a factor of 1.023 (2.3%). If we decrease W
1
by
this factor, we get W
1
~ 138 m. A simulation for this gate width update results in I
d
= 1.663
mA, which is close enough to the target current of 1.667 mA. For V
ds
= 1.25 volt and I
d
=
1.663 mA, HSPICE predicts a threshold voltage of V
hn
= 699 mV. In the interest of complete-
ness, V
ds
= V
ref
= 1.25 volt, V
hn
= 699 mV, and I
d
= 1.663 mA predicts an effective value of
the transconductance parameter, |
n1
, in (5-50) of |
n1
= 5.478 mmho/volt.
(4). From (5-52), parameter k
12
necessarily abides by
dd ref h
12
ref h
V V V
k .
V V

=
(E4-1)
With V
dd
= 3V, V
ref
= 1.25 V, and V
hn
= 699 mV, k
12
= 1.907. The square of this number,
which is 3.638, is, by (5-49), the factor by which the gate aspect ratio of transistor M2 in the
circuit of Figure (5.18a) must be smaller than the gate aspect ratio of the companion device,
transistor M1. Hence, for W
1
/L
1
= 138 M/2 M, W
2
/L
2
~ 38 m/2 M. We find in accor-
dance with the foregoing calculations, that HSPICE predicts an output voltage of V
ref
= 1.124
V, which is about 10% smaller than the design target of 1.25 V. By (5-51), we reason that a
decrease in parameter k
12
is in order. To this end, we determine through iterative simulations
that k
12
= 1.423 is appropriate, with the proviso that it increases the circuit power dissipation
to about 3.5 mW. In this particular case, we shall not be concerned by this power dissipation
increase. But in other designs, this increased dissipation may be a significant factor warrant-
ing further engineering attention. The revised k
12
metric corresponds to W
1
/L
1
= 77 m/2 m,
which delivers V
ref
= 1.253 V. Figure (5.20) depicts the final schematic diagram.
The biasing cell addressed herewith is an elementary example of a potentially viable biasing
cell. The design procedure and strategy offer a valuable engineering lesson in that they con-
firm that MOSFET circuit design adjustments are likely, if not inevitable, when the first order
design result is premised on simplified device models. In the present case, the significant
limitation to our first order analysis is our tacit neglect of bulk-induced modulation of the
+
V
ds

0
I
d
M1
W /L
1 1

- 441 -
threshold voltage for transistor M2. In particular, it turns out that in the final design solution,
the threshold potential of M2 is about 28% larger than the simulated 579 mV threshold vol-
tage of transistor M1.

Figure (5.20). Final schematic diagram of the active voltage
divider circuit designed in Example #5.4. The
HSPICE parameters of the transistors appear
in Table (4.1). The reference output voltage,
V
ref
, is 1.253 volts at 27 C.
While the output voltage result satisfies output voltage design requirements postured in the
problem statement, the circuit is nonetheless flawed in at least two respects. In particular, (5-
51) confirms that the output response, V
ref
, is linearly dependent on the supply voltage, V
dd
,
which is to say that V
ref
is vulnerable to any signal spurs that couple to the power line to cause
a change in the value of the supply line voltage. A second shortfall (unless k
12
= 1) is the
dependence of V
ref
on the threshold potential, V
h
, which renders V
ref
sensitive both to chip
temperature variations and vulnerable to body effect, which unfortunately is functionally
dependent on vagarious device model parameters. However, two positive notes do
reverberate. First, V
ref
is nominally independent of the transconductance parameter
n
, and
hence, it is ostensibly insensitive to the mobility variable to which parameter
n
is propor-
tional. A second positive note is sounded by the functional reliance of voltage V
ref
on the
geometrical parameter, k
12
. In particular, since k
12
is related to a ratio of transistor gate aspect
ratios, we can set this metric accurately.
5.4.1.1. Current Sink Application of the Active Divider
A common application of the active divider cell we have just investigated is the current
sink offered in Figure (5.21). In this diagram, the M1-M2 subcircuit is identical to the network in
Figure (5.18a). The output of the divider energizes the gate of M3 so that voltage V
ref
serves as
the gate-source biasing voltage, V
gs3
, applied to M3. We also include a capacitor, C
p
, in shunt
with the gate-source port of M3. This capacitor serves two fundamental purposes. First, if we
choose C
p
large enough (more about this design requirement shortly), it serves as a high fre-
quency short circuit that harmlessly routes to ground spurious signals that might invade the gate-
source port of M3. For example, such invasion can materialize as a divided voltage response to
interference that couples to the power supply line. In turn, this interference can derive from
proximate radio frequency (RF) signals or, perhaps, from relatively poor regulation of the supply
line. Second, since a capacitor cannot change its voltage instantaneously (or even very quickly,
for that matter), C
p
reduces any excessive transient overshoot evidenced at the divider output
port in response to the sudden application of power line voltage V
dd
. From a circuit modeling
perspective, C
p
superimposes with the gate-source capacitance, C
gs3
, of M3. To be sure, this
M2
M1
V
ref
+3 V
I
d
77 m/2 m
38 m/2 m

- 442 -
effective increase in gate-source capacitance degrades the unity gain frequency of M3, and
potentially the overall bandwidth of the network. But the unity gain frequency of a transistor and
the bandwidth of the circuit into which the transistor is connected, are rarely crucial design issues
in networks earmarked for biasing purposes.

Figure (5.21). Active divider used to bias a grounded source current
sink network to realize a nominally constant current, I
k
.
If (5-49) remains applicable and negligible body effect prevails, voltage V
ref
in Figure
(5.21) remains given by (5-51). This contention follows from the fact that the gate of transistor
M3 and the compensation capacitance, C
p
, conduct no static current. Additionally, we choose
the gate aspect ratio, W
3
/L
3
, of transistor M3 as
3 3 n3
31
1 1 n1
W L
k ,
W L
= (5-58)

Figure (5.22). An illustration of the use of the current sink in Figure (5.21) to bias a ba-
lanced differential amplifier. The differential amplifier consists of iden-
tical transistors M4 and M5 and the identical resistive loads, R
l
, imposed
on the drains of the matched transistor pair.
M3
+V
kk
I
k
W /L
3 3
R
out
R
p
M1
V
ref
W /L
1 1
C
p
M2
+V
dd
I
p
W /L
2 2
M2
M1
+V
dd
I
k
I
d4
I
d5
M3
M4
+V
kk
I = I +I
k d4 d5
W /L
1 1
W /L
2 2
W /L
3 3
R
out
R
l
R
l
Input #1
Output #1
Input #2
M5
Output #2
R
p
V
ref
C
p

- 443 -
where k
31
is viewed as a greater than one scaling factor. We observe that the gate of M3 is con-
nected directly to the gate of transistor M1, while the drain of M3 is incident with a node that
supports a voltage of V
kk
. In most embodiments of the subject mirror, voltage V
kk
is smaller than
the power line voltage V
dd
. For example, V
kk
might represent the source terminal voltage of a
source-coupled differential pair whose resistively loaded drain terminals are biased by V
dd
, as we
suggest in Figure (5.22). In the differential configuration, transistor M
3
is called upon to estab-
lish a current path to ground that sinks the sum of the net drain currents, I
d4
and I
d5
, flowing in
the matched transistors, M4 and M5, respectively. This is to say that current I
k
necessarily flows
through the drain of M3, which we have previously referred to as the tail of the balanced
differential pair. Regardless of the specific nature of voltage V
kk
, the fundamental design objec-
tive of the mirror is the establishment of a predictable M3 static drain current, I
k
, which is vir-
tually constant and assuredly predictable. Moreover, current I
k
must be relatively impervious to
signal-induced perturbations in voltage V
kk
, which is to say that the indicated output resistance,
R
out
, must be sufficiently large.
Before plunging into the mathematical analysis of the network in Figure (5.21), let us
extol our engineering comprehension of the circuit, for it is insightful understanding that sows
the seeds of design propriety, creativity, and innovation. The first point to be made is that the
drawn channel lengths of all transistors in the subject biasing network can be relatively long (at
least as long as 1.5 M), for fast response speeds in biasing circuits are rarely important. Indeed
slow response speeds in biasing circuits are usually preferred so that the potentially destructive
effects of significant transient overshoots are mitigated. Moreover, long channel lengths mediate
the effects of CLM and DIBL, which is to say that drain currents are rendered minimally depen-
dent on drain-source voltages. This relative insensitivity to drain-source voltages is further fos-
tered if design care is exercised to preclude a significant difference between the three observable
drain-source voltages; namely, (V
dd
V
ref
), V
ref
, and V
kk
. To be sure, we certainly need not make
these three voltages identical, but in concert with relatively long channel lengths, the closer the
voltages are to one another, the less critical they are to the predictable determination of the static
drain currents. Yet another biasing advantage of long channels is the reduced carrier mobility
degradation incurred by lateral, drain-source electric fields. Negating significant mobility
degradation, not to mention the tacit neglect of DIBL, simplifies transistor modeling and post-
ures transistor performance that is essentially independent of drain-source voltage and many
nebulously defined and difficult to control physical parameters. Finally, body effect is
manifested in transistor M2 since its bulk terminal is grounded while its source terminal is inci-
dent with the output port of the voltage divider. Significant body effect fosters observable differ-
ences in threshold voltages (of the order of 25% or so, as we have witnessed by way of simula-
tion example). In turn, threshold differences promote a dependence of voltage V
ref
on the
threshold potentials of both transistors M1 and M2, even if the relative gate aspect ratio of the
transistors is one. Body effect phenomena are minimized if the transistors boast very thin oxides
(less than 80 ). Of course, one downside to thin gate oxides is that they exacerbate the charge
trapping that may accompany large vertical electric fields in the channel. These effects are held
to a minimum if the applied gate-source voltages are not excessive in comparison to their rele-
vant threshold potentials. We recall from our long standing association with Schichman and
Hodges that for a desired or given drain current, gate-source voltages can be held small through
increases in gate aspect ratios.
In view of the foregoing discussion and since transistor M1, like transistor M2, is ob-
viously saturated, current, I
p
, which flows through the drains of transistors M1 and M2, is

- 444 -
( ) ( )
2 2
ref dsat1
hn
p n1 ref hn n1 ref hn

V V
V
I V V 1 V V 1 ,
V V
| | | |
= + = +
| |
\ . \ .
(5-59)
where V
ref
is the gate-source voltage, V
gs1
, applied to M1, as well as the gate-source voltage, V
gs3
,
which activates transistor M3. Moreover, (5-59) exploits the fact that the drain saturation vol-
tage, V
dsat1
, for M1 is
dsat1 gs1 h ref h
V V V V V . = = (5-60)
The drain current, I
k
, conducted by M3 is, assuming the satisfaction of the M3 saturation require-
ment, V
k
> (V
ref
V
hn
), follows as
( )
( ) 2 kk ref hn
k n3 ref hn
V V V
I V V 1 ,
V
(

(
= +
(

(5-61)
where the channel length, L
3
, of transistor M3 is presumed identical to L
1
, which is the drawn
channel length of M1. This channel length identity ensures that both transistors have nominally
the same CLM voltage, V
, despite likely differences between their gate aspect ratios, W

3
/L
3
and
W
1
/L
1
. Recalling (5-58), (5-59) and (5-61) combine to produce
( )
kk ref hn
k 31 p
hn
V V V
1
V
I k I .
V
1
V
(

(
+
(
=
(
+ (
(

(5-62)
In (5-62), we note with more than casual interest that if voltage V
kk
is of the order of the
gate-source voltage, V
ref
, developed across the gate-source terminals of both transistors M1 and
M3 and/or if
( )
kk ref hn
V V V V , >> + (5-63)
the foregoing drain current is nicely approximated by
k 31 p
I k I , ~ (5-64)
As we have already surmised qualitatively, (5-64) posits an M3 drain current that matches the
current, I
p
, conducted by transistor M1 to within a constant scale factor of k
31
. The result at hand
is similar to the fruits of analogous work we documented in Section (5.3.1).
An arguably more reliable realization of the current sink in Figure (5.21) is the struc-
ture in Figure (5.23), wherein transistor M2 in the former diagram is supplanted by an off chip,
constant current source, I
p
. An analysis of this particular structure appears in Section (4.7.3) of
the preceding chapter. Current I
p
flows through transistor M1 to produce a gate-source voltage,
V
ref
. Once this gate-source voltage is established, regardless of its precise value, current I
k
tracks
with current I
p
in accordance with (5-62) or its approximation in (5-64).
As we have already learned, the output resistance, R
out
, seen looking into the drain ter-
minal of transistor M3 in Figure (5.23) must be large if the sensitivity of current I
k
with respect to
perturbations in voltage V
kk
is to be minimized. We can deduce this output resistance through
mere engineering inspection. First, no signal appears across the gate-source port of M3 since
voltage V
dd
in this network is a constant. Even if signal spurs superimpose with the static
component of V
dd
, the presumably large capacitance, C
p
, grounds the time domain response to
these spurs. With the signal component, V
gs3s
, of gate-source voltage V
gs3
equal to zero, the

- 445 -
resultant drain-source signal current, g
m3
V
gs3s
, in the low frequency, small signal model of M3 is
forced to zero. Then, we note the absence of body effect in M3. This means that the drain-
source signal current,
b3
g
m3
V
bs3s
, is null because the bulk-source voltage, V
bs3
, and therefore its
signal component, V
bs3s
, applied to transistor M3 is clamped to zero. Accordingly, the only ele-
ment in the low frequency equivalent circuit of M3 is the drain-source channel resistance, r
o3
. It
therefore follows that R
out
= r
o3
, which is reasonably large for long drawn channel length and/or
a relatively small quiescent drain current (I
k
) conducted by M3.

Figure (5.23). An alternative realization of the current sink in Figure (5.21).
Assuming transistor M3 is held in saturation and channel
length modulation is insignificant, current I
k
is directly propor-
tional to constant current I
p
, which is typically realized accu-
rately and controllably off chip.
We suggested in the preceding paragraph that large C
p
in Figure (5.21) serves to short
circuit any parasitic signal voltage that may surface across the gate-source terminals of transistor
M3. Since the gate of M3 behaves as an open circuit to low and even to moderately high
frequencies, the net resistance seen by capacitance C
p
is solely the resistance, R
p
, which is mani-
fested by the series interconnection of the two diode-connected transistors. We can evaluate this
resistance by replacing both M1 and M2 by their respective low frequency, small signal models.
For this resistance computation, we must replace V
dd
and any spurious voltage component the-
reof by short circuits. Such replacement does not derive from habit. Instead, it follows from
Thvenins theorem, wherein all independent sources of energy must be set to zero while
evaluating a resistance between any pair of circuit nodes. We can then argue that R
p
is a parallel
interconnection of two resistances that are indigenous to the models used to represent transistors
M1 and M2. One of these shunt resistances, say R
p1
, is established by diode-connected transistor
M1; the other, say R
p2
, by diode-connected transistor M2. Because the present M1 subcircuit is
identical to the M1 network studied in Figure (5.4a) we defer to Figure (5.4d) to write by inspec-
tion,
o1
p1 o1
m1 m1 o1
r
1
R r .
g 1 g r
= =
+
(5-65)
The analytical form of resistance R
p2
differs slightly from that of R
p1
because while M1
experiences no body effect, M2 is subjected to BITM. Accordingly, we turn to Figure (5.24a),
which displays the low frequency, small signal model pertinent to computing the resistance, R
p2
,
as the voltage to current ratio, V
x
/I
x
. Of course, resistance R
p2
is a portion of the net resistance
presented to the output port of the active voltage divider by diode-connected transistor M2. The
model at hand renders very clear that the controlling voltages, V
a
and V
b
, satisfy the constraint,
+V
dd
I
p
M3
+V
kk
I
k
W /L
3 3
R
out
V
ref
C
p
M1
W /L
1 1
R
p

- 446 -
V
a
= V
b
= V
x
. This fact is incorporated into our small signal modeling exercise to produce the
equivalent structure in Figure (5.24b). Observe that the immediate impact of the foregoing vol-
tage equivalence is to reverse the direction of the voltage controlled current sources in the model
of Figure (5.24a). We note, interestingly enough, that the controlling voltages for the reversed
current sources are the ohmmeter voltage, V
x
. But this voltage appears directly across, and in
associated polarity convention with, each of the two controlled current sources, g
m2
V
x
and
b2
g
m2
V
x
. It follows that the g
m2
V
x
source is equivalent to a branch resistance of 1/g
m2
, while
b2
g
m2
V
x
produces the same branch current as does the branch resistance, 1/
b2
g
m2
. We adopt
these observations in Figure (5.24c), which transparently delivers

Figure (5.24). (a). Low frequency, small signal model for determining R
p2
= V
x
/I
x
, the resistance presented by the
M2 subcircuit to the reference voltage output port in Figure (5.22). (b). The model in (a), modified
to account for the fact that control voltages V
a
and V
b
in the small signal model are identical to the
mathematical ohmmeter voltage, V
x
. (c). Reduced version of the equivalent circuit in (b).
( ) ( )
o2
p2 o2
b2 m2 b2 m2 o2
r
1
R r .
1 g 1 1 g r
= =
+ + +
(5-66)
As we might have expected, the form of this expression is identical to that of R
p1
in (5-65) if we
ignore BITM, which forces the bulk transconductance to forward transconductance ratio,
b2
, to
zero. Our intermediate conclusion is that the resistance, R
p
, seen by capacitance C
p
, is, by (5-65)
and (5-66)
( )
o1 o2
p p1 p2
m1 o1 m1 m2
b2 m2 o2
r r
1
R R R .
1 g r g g
1 1 g r
(
(
(
(
= = ~
(
( + +
+ +
(

(5-66)
R
p2
M2
+V
dd
W /L
2 2
r
o2
g V
m2 a

b2 m2 b
g V
V
a
V
b
I
x
I
x
V
x
V
x

(a).
r
o2
g V
m2 x

b2 m2 x
g V
V
a
V
b
I
x
V
x
(b).
V
x
I
x
V
x
(c).
r
o2
V
x
1/(1 )g
b2 m2
R
p2
R
p2
R
p2

- 447 -
where we have invoked the reasonable presumptions,
b2
<< 1, g
m1
r
o1
>> 1, and g
m2
r
o2
>> 1.
Recall that MOSFET transconductances are proportional to the square root of the product of gate
aspect ratio and static drain current. Noting in Figure (5.21) that the series interconnection of
transistors M1 and M2 forces these two devices to conduct the same static current, (5-49) impli-
citly gives rise to
m1
12
m2
g
k .
g
= (5-67)
Thus, we can express resistance R
p
as
( )
12
p p1 p2
m1 m2
12 m1
k
1
R R R .
g g
k 1 g
= ~ =
+
+
(5-68)
In view of the foregoing resistance disclosures, we now surmise that the net impedance,
say Z
p
(j), established between the gate terminal of transistor M3 and ground is the parallel
combination of resistance R
p
and capacitance C
p
; that is,
( )
p
p p
p p p
R
1
Z j R .
j C 1 j R C
= =
+ e e
(5-69)
The magnitude of this resistance-capacitance (RC) impedance is
( )
( )
p
p
2
p p
R
Z j .
1 R C e
=
+
(5-70)
Since we wish C
p
to emulate a short circuit for all signal frequencies above a prescribed mini-
mum frequency, f
min
6
, we choose C
p
to satisfy the design requirement,
( ) ( )
2 2
min p p min p p
R C 2 f R C 1 , = >> e t (5-71)
for which
( )
p
12
min p min p
12 m1
R
k
1 1
.
C 2 f C 10
10 k 1 g
t
= s ~
+
(5-72)
generally suffices. In plain engineering language, (5-72) directs us to select capacitance C
p
, such
that the magnitude of its impedance at a frequency of
min
= 2f
min
is at least a factor of root ten
smaller than the resistance (in this case R
p
) faced by capacitance C
p
in the circuit. Since resis-
tance R
p
is usually small, C
p
is likely to be large, especially if frequency f
min
is small. Unfortu-
nately, large capacitors cannot be synthesized monolithically. This limitation forces us to imple-
ment capacitance C
p
as a discrete, off chip component. And while progressively larger
capacitances approximate progressively better short circuits, engineering reason must prevail, for
large capacitances can be bulky and are generally less reliable than are smaller valued capacit-
ances.

6
Frequency f
min
must be identified from the performance requirements of the system into which the current sink and
active voltage divider are embedded.

- 448 -
5.4.1.2. Multistage Current Mirror
We shall commonly encounter the need for several current sinks or sources in a variety
of analog circuit applications. For example, the signal flow path in an analog circuit may em-
body a cascade of balanced differential amplifiers, each of which requires a tail current to sink
the drain currents of each respective pair. In this case, each current sink need not be biased by a
distinct reference circuit. Instead, one reference circuit can be exploited to bias the gates of all
sinks, as we depict in Figure (5.25) for a general N-stage current mirror. In this diagram, the
reference circuit, which is comprised of transistor MO, current source I
ref
, and supply line vol-
tage, V
dd
, establishes the reference voltage, V
ref
, which is applied to the gates of all the remaining
N transistors. Unlike a multistage mirror realized in bipolar technology, which is plagued by
modest, but nonetheless nonzero, base currents, the input gate ports of the N transistors in the
MOSFET mirror do not load the reference circuit since the gates of MOSFETs do not conduct
static current. Then, with the understanding that

Figure (5.25). Schematic diagram of a multistage current mirror. In the diagram, k
i
represents the gate aspect
ratio, W
i
/L
i
of the i
th
transistor, normalized to the gate aspect ratio, W
o
/L
o
, of reference transistor
MO, where i = 1, 2, 3,N.
i i
i
o o
W L
k ,
W L
(5-73)
we see that the current, I
ki
, conducted by the drain of the i
th
transistor in the N-stage cascade is
ki i ref
I k I . = (5-74)
Of course, (5-74) requires that the i
th
transistor be biased in its saturation regime, where V
kki
>
(V
ref
V
hn
), with V
hn
naturally representing the threshold potential of all transistors (all devices
are presumed matched). Equation (5-74) also requires negligible CLM, which in turn requires
long channels and/or voltage V
kki
reasonably close to the value of the reference potential, V
ref
.
A mere inspection of the schematic diagram in Figure (5.25) suggests immediately that
the output resistance, R
outi
, of the i
th
stage is simply the drain-source channel resistance, r
oi
, of the
i
th
MOSFET in the cascade. This observation points out a potential shortfall of the cascade. In
particular, we recall that the channel resistance is inversely proportional to static drain current.
Thus, for progressively larger k
i
in (5-74), R
outi
= r
oi
becomes progressively smaller.
5.4.2. LOW VOLTAGE REFERENCE
The low-voltage, low power integrated circuit culture that comports with present day
portable electronic systems demands current sinks, current sources, and other types of biasing
MO
V
ref
+V
dd
I
ref
M1
+V
kk1
I
k1
W /L
o o
x k
1
R
out1
M2
+V
kk2
I
k2
x k
2
R
out2
M3
+V
kk3
I
k3
x k
3
R
out3
MN
+V
kkN
I
kN
x k
N
R
outN
C
p

- 449 -
networks that operate gainfully with low static input voltages. To this end, the network shown in
Figure (5.26) is commonly used for several reasons. First, its open circuit output voltage, V
ref
,
need be only modestly larger than the threshold voltages of transistors M1 and M2. We should
interject here that the presence of BITM in M1 increases the M1 threshold voltage above that of
M2. Despite this inescapable fact, we shall adopt the simplifying stance of identical threshold
potentials in both transistors. Second, and to the extent that current source I
ref
approximates an
ideal current generator, output voltage V
ref
is independent of the supply line voltage, V
dd
. Third,
the driving point output resistance, R
out
, is relatively small and as we shall demonstrate, it is of
the order of the terminal resistance associated with our previously examined diode-connected
transistor. In contrast to a current output port, a small output resistance is a desired design target
for a voltage output port that establishes a predictable voltage capable of driving a variety of
other network ports within the considered integrated circuit.

Figure (5.26). Schematic diagram of a voltage reference cir-
cuit capable of supplying a low voltage output,
V
ref
, and a reasonably low output resistance,
R
out
. Observe that the gate aspect ratio of
transistor M2 is normalized to the gate aspect
ratio of transistor M1.
In the circuit of Figure (5.26), voltage V
bias
, which can be either generated on chip or
supplied from a source that is extrinsic to the considered integrated circuit, is adjusted so that
transistor M2 operates on the ideal cusp between ohmic and saturated operating regimes. In
other words, V
bias
is used to set the drain-source voltage, V
ds2
, of M2 to a value of (V
ref
V
hn
),
where V
hn
identifies the threshold potentials of both NMOS devices. Aside from constraining
M2 to operate in its saturation domain, biasing the drain-source terminals of M2 at its drain
saturation level negates CLM in this transistor. Interestingly, setting V
ds2
= (V
ref
V
hn
) imposes
a drain-source voltage, V
ds1
, on transistor M1 that is only one threshold drop (if we indeed ignore
body effect). This contention follows from the fact that V
ds1
= V
ref
V
ds2
= V
ref
(V
ref
V
hn
)
V
hn
. In view of this small drain-source bias, it is not immediately plausible that transistor M1 can
operate in saturation. But it indeed can. All we need to ensure saturation of M1 is V
hn
(V
gs1

V
hn
) = V
bias
V
ds2
V
hn
= V
bias
V
ref
+ V
hn
V
hn
= V
bias
V
ref
. In brief, we require
bias ref hn
V V V . s + (5-75)
This saturation constraint makes retrospective sense, for it implies an M1 gate to drain voltage,
V
gd1
= (V
bias
V
ref
), that is smaller than one threshold potential. But because of body effect and
carrier mobility degradation caused be lateral electric fields in the channel, the resultant drain-
+V
dd
I
ref
V
ref
M1
M2
R
out
V
bias
x 1
x k
21
2

- 450 -
source saturation voltage of transistor M1 is likely to lie slightly below the idealized drain satura-
tion level.
The flow of current, I
ref
, through the drains of both M1 and M2 in Figure (5.26) estab-
lishes a distinct relationship between the gate-source voltages of these two devices. We see that
the gate-source voltage, V
gs2
, of M2 is reference voltage V
ref
and that the gate aspect ratio of M2
is a factor of k
21
2
larger than that of transistor M1. With V
bias
tuned to force V
ds2
= (V
ref
V
hn
),
which ideally forces V
ds1
= V
hn
, we also witness no CLM in M1 and invariably negligible CLM
in M2. Thus, we assert,
( ) ( ) ( )
2 2 2
2
ref n1 gs1 hn n1 bias ref 21 n1 ref hn
I V V V V k V V , | | | = = = (5-76)
which straightforwardly delivers
bias 21 hn
ref
21
V k V
V .
k 1
+
=
+
(5-77)
By virtue of the constraint imposed by (5-75) on voltage V
bias
,
bias 21 hn 21
ref hn
21 21
V k V k 1
V V .
k 1 k
| | + +
| = s
|
+
\ .
(5-78)
The only electrical variable on which V
ref
is dependent is the transistor threshold voltage. Thus,
the output voltage, V
ref
, is comparatively small and independent of reference current I
ref
and
power line voltage V
dd
. Of course, V
ref
can be no smaller 2V
hn
, which is as expected since V
ref

must supply the V
hn
bias across the drain-source terminals of transistor M1 and the (V
ref
V
hn
)
bias imposed across the drain-source terminals of M2.
A downside of the foregoing result is that the reference voltage increases with tempera-
ture. We deduce this reality from (5-7), which, when combined with (5-78), gives us
o 21
ref h o F
21 o
T T k 1
V V (T ) 2V .
k T
( | | | | +
( | | s +
| |
(
\ . \ .
(5-79)
Equation (5-79) portrays V
ref
as nominally PTAT
7
with a voltage versus temperature slope that is
designable through the gate aspect ratio parameter, k
21
. As we learned when we studied BJT
biasing networks and as we shall continue to witness, the utility of PTAT voltage generators is a
appreciated in a multitude of analog networks.
The Thvenin output resistance, R
out
, of the low voltage cell can be evaluated from an
investigation of its small signal equivalent circuit. To this end, the pertinent low frequency small
signal model is submitted in Figure (5.27), where g
m1
and r
o1
respectively denote the
transconductance and drain-source channel resistance of transistor M1, g
m2
and r
o2
correspon-
dingly represent the transconductance and channel resistance of M2, and the current and voltage
sources, I
ref
and V
bias
, are presumed ideal, constant sources of energy. Moreover, bulk-induced
modulation of the threshold voltage of transistor M1 is tacitly ignored. A straightforward analy-
sis of the subject model reveals
( )
( )
o1 m1 o1 o2
x
out
x
m2 m1 o1 o2
r 1 g r r
V
R ,
I
1 g 1 g r r
+ +
= =
+ +
(5-80)

7
Recall that PTAT is the astonishingly clever acronym for proportional to absolute temperature.

- 451 -

Figure (5.27). Low frequency, small signal model of the low voltage reference of Figure (5.26). The output
resistance, R
out
, is determined as the ratio, V
x
/I
x
, of mathematical ohmmeter variables V
x
and I
x
.
which reduces to
( )
( )
o1 m1 o1 o2
out
m2
m2 m1 o1 o2
r 1 g r r
1
R
g
1 g 1 g r r
+ +
= ~
+ +
(5-81)
for large g
m1
r
o1
and large g
m2
r
o2
. The obvious implication of (5-81) is that insofar as the output
resistance is concerned, the configuration in Figure (5.26) behaves as a single diode-connected
transistor. We accentuate this disclosure with the macromodel in Figure (5.28), where we have
inserted (5-77) into (5-76) to stipulate quantify the reference current, I
ref
.
Since current I
ref
in Figure (5.27) is
( )
2 2
2
bias hn 21
ref n2 n1 bias hn
21 21
V V k
I V V ,
k 1 k 1
| |
| | | |
| | = =
| |
+ +
\ . \ .
(5-82)
we are gifted a clue as to how the voltage, V
bias
, which is applied to the low voltage reference
network, might be implemented electronically. This clue is exploited in Figure (5.29) where the
gate aspect ratios of transistors M1, M2, and M3, satisfy

Figure (5.28). Approximately electrically equivalent macromodel of the low voltage reference provided in
Figure (5.26).
+V
dd
I
ref
M1
M2
V
ref
R
out
R
out
V
bias
x 1
x k
21
2
r
o1
r
o2
g V
m1 1
g V
m2 x
V
1
I
x
I
x
V
x
I g V
x m1 1
I g V
x m2 X
+V
dd
+V
dd
M2
V
ref
V
ref
R
out
V
bias
x k
21
2
Low Voltage
Reference
[Figure (5.26)]
out
R ~
n2
( )
V V
bias hn
k 1
21
2
I =
ref

- 452 -

Figure (5.29). Alternative version of the low voltage reference in Figure
(5.26), wherein voltage V
bias
is implemented electronically
by diode-connected transistor M3 and an adjustable, off
chip current source, I
in
. Equation (5-83) defines the requi-
site relative gate aspect ratios for all three transistors.
2
2 1
21
2 1
2 2
3 21 1 2
3 21 1 21 2
W W
k
L L
.
W k W W
1
L k 1 L k 1 L
=
| | | |
| | = =
| |
+ +
\ . \ .
(5-83)
Ideally, the current identified in Figure (5.29) as I
in
is identical to the originally stipulated refer-
ence current, I
ref
. But in recognition of the vagarious nature of a monolithic fabrication process,
we implement this current in the form of an adjustable, likely off chip, current source, I
in
. In this
way, we can adjust current I
in
to fine tune voltage V
bias
so that the drain-source voltage estab-
lished on transistor M2 is its drain saturation voltage, as stipulated earlier. If current I
in
is imple-
mented as an off chip branch element, reference current I
ref
need not be an off chip current
source. It should also be clear that since the gate terminals of transistors M1 and M2 conduct no
low frequency currents and are therefore electrically isolated from the appended M3 subcircuit,
the output resistance indicated in Figure (5.29) is unchanged from the value predicted by (5-81).
A popular application of the low voltage reference in Figure (5.29) is the high output
resistance, cascode current mirror depicted in Figure (5.30). In this diagram, current I
in
, which is
usually an off chip current source, is adjusted to set the drain-source voltage of transistor M2 to
(V
ref
V
hn
), which is, of course, the idealized drain saturation voltage of M2. Voltage V
kk
must
be sufficiently large to guarantee that transistors M4 and M5 in the cascode current sink operate
in saturation. We note that transistor M4 mirrors the current, I
ref
, which is conducted by transis-
tor M2, with a scale factor of k
o
k
21
2
/k
21
2
= k
o
. In order to equalize the current densities of transis-
tors M4 and M5, as well as minimize the drain saturation voltage of M5, it is a good idea to set
the gate aspect ratio of M5 equal to that of M4. Thus, with body effect in M5 ignored and CLM
effects minimized, the output current, I
k
, of the cascode sink reflects the approximation,
k o ref
I k I . ~ (5-84)
This result confirms of our intuitive suspicion that a stable and accurately predictable output cur-
rent mandates an equivalently stable and predictable reference current, I
ref
. Additionally, a suita-
bly large, and likely off chip, capacitance, while not shown in the subject schematic diagram,
+V
dd
I
ref
I
in
V
ref
M1
M2 M3
R
out
V
bias

- 453 -
might be required from the gate of transistor M2 to ground if the shunt resistance associated with
reference current source I
ref
is not big enough to ensure adequate rejection of the supply line vol-
tage spurs. Recalling (5-81), this capacitance must establish an impedance magnitude at the low-
est system frequency of interest that is much smaller than the approximate output resistance,
1/g
m2
, of the reference voltage circuit.

Figure (5.30). The low voltage reference used to bias a high output resistance,
cascode current source. Observe that all gate aspect ratios are
referred to the gate aspect ratio of transistor M1.
The output resistance, R
ok
, of the cascode current sink is laudably very large owing to
the deployment of transistor M4 as a source degeneration element for transistor M5. In order to
quantify this assertion, we turn to the low frequency, small signal equivalent circuit in Figure
(5.31). The model reflects the absence of bulk-induced threshold modulation in transistor M4
and the presumption of negligible body effect in transistor M5. The current sources, I
in
and I
ref
in
Figure (5.30) are set to zero because we interpret these applied energy elements as ideal, constant
current sources. Moreover, we have replaced diode-connected transistor M3 by a resistance,
1/g
m3
, which is an action that presumes the M3 drain-source channel resistance, r
o3
, is such that
g
m3
r
o3
>> 1. In accordance with (5-81), we have also represented the Thvenin output resistance
of the voltage reference circuit driving the gate of M4 as the approximation, 1/g
m2
.
An inspection of the subject circuit model shows that since no current can enter the gate
of transistor M4, the voltage drop across the resistance, 1/g
m2
, is zero, which forces control vol-
tage V
b
to zero. This means that transistor M4 behaves as a simple two terminal resistance that
equals the M4 channel resistance, r
o4
. In other words, r
o4
functions as a large source degenera-
tion resistance for transistor M5. With V
b
= 0, g
m4
V
b
= 0, which suggests that the current con-
ducted by r
o4
is simply the mathematical ohmmeter current, I
x
. Since the gate of transistor M5,
like the gate of M4, conducts no low frequency current, the control voltage, V
a
, follows as V
a
=
r
o4
I
x
. In turn, the current flowing through resistance r
o5
is (I
x
g
m5
V
a
) = I
x
(1 + g
m5
r
o4
). These
discoveries and the venerable KVL readily produce the output resistance result,
( )
x
ok o4 m5 o4 o5
x
V
R r 1 g r r ,
I
= ~ + + (5-85)
which is substantively larger than either of the relatively large channel resistances, r
o4
and r
o5
.
I
in
V
ref
M4 M3
M1
M2
R
ok
V
bias
+V
dd
I
ref
M5
V
kk
I
k
x 1
x k k
o 21
2
x k
21
2
2
21
21
k
x
k 1
| |
|
|
+
\ .
x k k
o 21
2

- 454 -

Figure (5.31). The approximate, low frequency, small signal equivalent circuit
of the cascode current sink appearing in Figure (5.30). The
model is used to find the output resistance, R
ok
, which is deter-
mined analytically as the ratio, V
x
/I
x
, of the mathematical
ohmmeter variables, V
x
and I
x
.
EXAMPLE #5.5:
In the low voltage, cascode current sink of Figure (5.30), set the nominal
values of current I
in
, current I
ref
and voltage V
kk
to I
in
= 100 A, I
ref
= 100
A, and V
kk
= 3.5 volts. Since the circuit is fundamentally a static net-
work, all transistors, whose SPICE parameters appear in Table (4.1) can
have relatively large drawn channel lengths of, say L = 1.5 m. Let
transistor M1 have a gate aspect ratio of 4.5 m/1.5 m. Use HSPICE or
equivalent computer-aided design software to design the circuit for a tar-
get output current, I
k
, of 500 A. Investigate the specific value of current
I
in
that sets the drain-source voltage of transistor M2 to its drain saturation
value. Adjust the relevant gate aspect ratios so that at the nominal settings
of I
in
, I
ref
, and V
kk
, all transistors operate in accordance with the results of
the analyses in this subsection of material. Determine the individual
ranges of I
in
and V
kk
over which current I
k
is held reasonably constant near
its 500 A target. Finally, simulate the real part, g
ok
= 1/R
ok
, of the small
signal admittance seen looking into the drain of transistor M5. Examine
carefully this frequency response plot of the network output conductance.
SOLUTION #5.5:
(1). Since transistors M1 and M3 are driven by ideal sources of constant current, we shall simulate
the network in Figure (5.30) with voltage V
dd
set to zero. Realistically, however, current
sources I
in
and/or I
ref
are implemented either on chip or off chip with active devices.
Pragmatically, therefore, voltage V
dd
must be sufficiently large to bias the active current
source devices, as well as transistors M1, M2, and M3 in the circuit schematic.
(2). Parameter k
21
must be large enough to minimize the indicated reference voltage and the
corresponding drain saturation voltage of transistor M2. Since we have not been given a tar-
r
o5
g V
m5 a
V
a
1/g
m3
r
o4
g V
m4 b
V
b
1/g
m2
I
x
I
x
V
x
I
x
I g V
x m5 a
I g V
x m4 b
R
ok

- 455 -
get voltage for V
ref
, we somewhat arbitrarily choose k
21
= 4. Accordingly, our first iterated
gate width for transistor M2 is W
2
= k
21
2
W
1
= 16(4.5 M) = 72 M, whence a gate aspect ra-
tio for transistor M2 of 72 M/1.5M = 48. It follows that for M3,
( )
2
2
21
3 1
21
k 4
W W 4.5 M 2.88 M ,
k 1 5
| |
| |
= = =
| |
+
\ .
\ .
(E5-1)
which gives an M3 gate aspect ratio of 2.88 M/1.5 M = 1.92. Since we wish to have I
k
=
500 A with I
ref
= 100 A, and transistors M2 and M4 obviously form a current mirror, we use
k
o
= I
k
/I
ref
= 500 A/100 A = 5, which means that the gate width of transistor M4 is W4 =
k
o
k
21
2
W
1
= (5)(16)(4.5 M) = 360 M. In order to equalize the current densities between M4
and M5, we set the gate aspect ratio of both of these transistors to 360 M/1.5 M = 240.
There is no need to calculate the periphery and area parameters for all devices until finalized
gate aspect ratios are determined.
(3). Our first simulation chore is to examine the quiescent operating points of all transistors to en-
sure that they operate in saturation. Moreover, we recall that we require V
ds2
= V
dsat2
. For the
quoted input currents and the calculated gate aspect ratios, HSPICE predicts I
k
= 501.84 A,
V
ds2
= 176.3 mV, and V
dsat2
= 154.0 mV. Changing the gate aspect ratio of M1 to secure
proper circuit operation is messy in that it requires changes to the gate aspect ratios of transis-
tors M2 and M3. Thus, we elect to perturb current I
in
appropriately.
After a few playful iterations, we find that I
in
= 94.4 A delivers V
ds2
= 154.3 mV, V
dsat2
=
154.0 mV, and I
k
= 501.79 A. Voltages V
ds2
and V
dsat2
are close enough for government
work, while current I
k
can be tweaked by changing the gate aspect ratio of transistor M4.
Such a change does not require changes in the gate aspect ratios of transistors M1, M2, and
M3, since the current mirroring scale factor between M2 and M4 is determined by parameter
k
o
, and not by k
21
. But to equalize current densities in transistors M4 and M5, we should
match the gate aspect ratio of M5 to the new gate aspect ratio of M4. We find that with I
in
=
94.4 A, an M4 (and M5) gate aspect ratio of W
4
/L
4
= 358.7 M/1.5 M = 239.1 results in I
k

= 500.0 A, which is the design target. Under these conditions, HSPICE delivers V
bias
= 1.48
volts and V
ref
= 706.9 mV. The latter voltage is less than 133 mV above the threshold voltage
of transistor M4.
We should mention that with W
1
/L
1
= 4.5 M/1.5 M, W
2
/L
2
= 72 M/1.5 M, W
3
/L
3
= 2.88
M/1.5 M, W
4
/L
4
= W
5
/L
5
= 358.7 M/1.5 M, I
in
= 94.4 A, I
ref
= 100 A, V
kk
= 3.5 V, and
V
dd
= 0 V, transistor M1 is close to operating in its saturation domain. Strictly speaking,
however, it functions in its ohmic regime since our HSPICE simulations confirm V
ds1
= 552.7
mV, while V
dsat1
= 661.2 mV. In other words, the M1 drain-source voltage is 108.5 mV below
its drain saturation value. A fundamental reason for this disparity is that M1 is subjected to
body effect, which renders its threshold voltage larger than the threshold potential of transis-
tor M2. Indeed, the threshold potential for M1 is V
hn1
= 606.8 mV, while for M2, V
hn2
= 575.3
mV. Of course, the threshold voltage influences both the M1 gate-source voltage commensu-
rate with the observed 100 A drain current in this device, as well as the corresponding drain
saturation voltage.
The ostensibly meager M1 intrusion into its ohmic regime engenders a non-zero active
component to the net gate-drain capacitance. That is, the net gate-drain capacitance of M1 is
not simply precipitated from an oxide overlap with the drain volume. The enhanced gate-
drain capacitance can prove problematic in high-speed networks, which our current sink
surely is not. As long as the static performance of our network remains true to our design tar-
gets, we shall therefore ignore this ohmic regime issue. For the record, we do find that all
other transistors operate solidly within their saturation domains.
(4). We can now compute the periphery and area dimensions for all transistor capacitances.
Borrowing from (E3-1) and (E3-2),

- 456 -
( )
11 2
s1 d1
s1 d1
A A 1.35 10 m
,
P P 10.5 M
= =
= =
(E5-2)
( )
10 2
s2 d2
s2 d2
A A 2.16 10 m
,
P P 78.0 M
= =
= =
(E5-3)
( )
12 2
s3 d3
s3 d3
A A 8.64 10 m
,
P P 8.88 M
= =
= =
(E5-5)
and finally,
( )
9 2
s4 d4 s5 d5
s4 d4 s5 d5
A A A A 1.08 10 m
.
P P P P 365 M
= = = =
= = = =
(E5-6)

Figure (5.32). The simulated dependence on input current I
in
of the current sink output current,
I
k
, for the network studied in Example #5.5.
(5). Figure (5.32) displays the static transfer characteristic between input current I
in
and output
current I
k
, The input current region below roughly 80 A is impertinent owing to our adopt-
ing ideal, as opposed to realistic, current sources for currents I
in
and I
ref
. Fundamentally, an
output current of nominally 500 A is achieved for 90 A I
in
200 A. More precisely, the
simulations show that I
k
varies from 507.82 A at I
in
= 90 A to 502.19 A at I
in
= 200 A. In
other words, we observe a delightfully small 1.1% change in output current I
k
over the 110
A change in applied input current, I
in
.
(6). In Figure (5.33), we show the simulated dependence of output current I
k
on applied voltage
V
kk
. The curve confirms that current I
k
remains essentially constant at near its 500 A target
value over an impressively wide range of voltage V
kk
values. Specifically, I
k
varies from
496.85 A at V
kk
= 390 mV to 500 A at V
kk
= 4 volts.
(7). Figure (5.34) projects the simulated frequency response of the shunt output conductance, g
ok
,
where we understand that g
ok
is merely the inverse of the resistance, R
ok
, in the schematic dia-
gram of Figure (5.30). Both good news and bad news surface from the fruits of this simula-
tion. The good news is that at very low signal frequencies, HSPICE predicts g
ok
= 21.66
nmho, which corresponds to R
ok
= 46.17 MEG. Obviously, this shunt output resistance is
0
1
2
3
4
5
6
7
0 40 80 120 160 200
Input Current, ( A) I
in

O
u
t
p
u
t

C
u
r
r
e
n
t
,

(
m
A
)
I
k

- 457 -
very large, and it therefore conflates with our engineering expectations of a high quality cur-
rent sink. The result also agrees reasonably well with our theoretic result in (5-85). Specifi-
cally, at the operating point defined earlier, HSPICE yields r
o4
= 84.40 K, r
o5
= 83.33 K,
and g
m5
= 5.758 mmhos, whence, by (5-85), R
ok
= 40.66 K. This approximately 13.5% er-
ror is reasonable in light of the simplified nature of our small signal model.

Figure (5.33). The simulated dependence on input voltage V
kk
of the current sink output
current, I
k
, for the network studied in Example #5.5.

Figure (5.34). The simulated frequency response of the shunt output conductance of the
current sink shown in Figure (5.30) and addressed in Example #5.5.
The bad news is that the plot in Figure (5.34) infers that our high performance current sink is
a potentially unstable network. In particular, we should be alarmed by the fact that above a
signal frequency in the neighborhood of 1 MHz, g
ok
is negative. From a simplistic point of
view, we surmise that since positive conductance dissipates power, negative conductance
must generate power. But we expect our network to dissipate the power it receives from an
applied signal source, as opposed to surprising the signal source with signal power reflected
from its own output port and back to the applied source of signal. In other words, and despite
0
100
200
300
400
500
0 1 2 3 4
Input Vol tage, (V) V
kk
O
u
t
p
u
t

C
u
r
r
e
n
t
,

(
A
)
I
k
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
0.001 0.01 0.1 1 10
Si gnal Frequency (MHz)
S
h
u
n
t

O
u
t
p
u
t

C
o
n
d
u
c
t
a
n
c
e
,

(
m
h
o
)
g
o
k

- 458 -
the fact that our current sink is designed expressly to establish a quiescent operating point,
any high frequency component in voltage V
kk
produces signal power reflected back to V
kk
.
Because of this signal reflection, we must view our network as potentially unstable electron-
ics. We say potentially unstable because the net effective resistance seen at the output port
depends on the electrical nature of the external load imposed on this port. For example, if the
conductance of a passive load appended to the output port of the current sink exceeds the
magnitude of the negative conductance manifested by the sink at its output port at all signal
frequencies of interest, the net conductance established at the output port is positive, and the
loaded network remains operationally stable. Otherwise, our network is indeed unstable.

Figure (5.35). The current sink of Figure (5.30), compensated to ensure unconditional stability at all sig-
nal frequencies. The dimensions of the numerators and denominators of all gate aspect
ratio are in microns. Voltage V
dd
is set to zero because of the use of the ideal current
sources for currents I
in
and I
ref
.
We shall have much more to offer later as regards stability issues and the mitigation of poten-
tial instabilities. For now, potential instability can be neutralized by incorporating a 10 pF
capacitor from the gate of transistor M5 to ground and a 1.5 pF capacitor between the gate
and drain terminals of M5. Our compensated structure is submitted as Figure (5.35). The
first of these two compensation capacitors effectively ground the gate of transistor M5 at high
frequencies, while the second (1.5 pF) capacitor slows down the response speed, thereby
increasing the signal delay time, of M5. As we have noted, these compensation measures re-
ceive definitive attention later. For now, we relish the fact that the two capacitors render our
compensated current sink unconditionally stable, as is projected by the frequency response of
the current sink output conductance in Figure (5.36). We note therein that the subject
conductance remains positive for all frequencies. The introduced capacitances do not alter
the low frequency output conductance since capacitances act as open circuits at low signal
frequencies. But we note, with more than mere passing concern, that the output conductance
rises dramatically, and therefore the output shunt resistance falls precipitously, at progres-
sively higher frequencies. In other words, our active current sink, while assuredly stable, be-
comes progressively less indicative of an ideal current sink as the frequency of the signal
component implicit to V
kk
increases.
Numerous circuit design and analysis lessons derive from this example. The first, and per-
haps most important, of these lessons is that the satisfaction of quiescent operating specifica-
tions does not tell the complete story in which we, as presumably skilled and competent cir-
cuit designers, must be well-versed. To wit, after we jiggled a couple of gate aspect ratios
and systematically adjusted the value of the applied input current, I
in
, we satisfied all of the
quiescent operating specifications articulated in the problem statement. Had we not ex-
amined the frequency response of the driving point output admittance (or impedance) of our
V
ref
M4
M3
M1
M2
R
ok
V
bias
M5
V
kk
I
k
I
in
(94.4 A)
I
ref
(100 A)
(3.5 V)
358.7
1.5
2.88
1.5
72
1.5
4.5
1.5
358.7
1.5
10 pF
1.5 pF

V
dd
(0 V)

- 459 -
current sink, we would have courted possible processing disaster by prematurely (and
inappropriately) claiming design success. In particular, the simulated real part of the driving
point output admittance infers potential high frequency instability, which indeed is not
uncommon in current sinks and sources that utilize feedback and boast huge Thvenin output
resistances. A simulated transient analysis to a step form of voltage V
kk
would have corrobo-
rated our potential instability revelations by displaying significant and/or prolonged time
periods of response overshoots and undershoots, if not actual self-sustaining sinusoidal
oscillations.

Figure (5.36). The simulated frequency response of the shunt output conductance of the compensated
current sink shown in Figure (5.35) and addressed in Example #5.5.
The second lesson to be learned is that the manual analyses we executed to ascertain the static
and low frequency performance of our current sink are gratifyingly accurate. For example,
we needed to reduce current I
in
by only 5.6% from its nominal 100 A value to achieve proper
biasing of transistor M2. Moreover, our computed low frequency output resistance was low
by 13.5%. While the latter error does not pass the taste and smell tests for blatant insignific-
ance, it, along with the aforementioned 5.6% current adjustment, lies well within the toler-
ances that are typical to a monolithic circuit realization. Yet another laudable example of
analytical propriety is embraced by the gate aspect ratios of transistors M4 and M5, which
needed to be reduced from their respective nominal values of 360 by only 0.36% to 358.7.
The third lesson learned is that simulations nicely and insightfully complement necessarily
simplified manual work. In this case, HSPICE clearly reveals that body effect in transistor
M1 makes it difficult to operate M1 in saturation when transistor M2 operates on the cusp be-
tween ohmic and saturation domains.
We should also have derived two other items of interest from the HSPICE simulations. The
first of these deals with Figure (5.32). In particular, setting I
in
to 94.4 A places the input
operating point of our current sink fairly close to the lower limit of I
in
that is commensurate
with the targeted 500 A output current goal. Depending on the accuracy, reliability and
reproducibility of I
in
, this proximity of the quiescent value of I
in
to the lowest allowable value
of I
in
may require additional design modifications, which we did not pursue here. The second
issue offers news that is more positive. In the static transfer curve of Figure (5.33), the fact
that the output current is virtually independent of applied voltage V
kk
purports very high out-
put impedance for, as we have come to understand, infinitely large output impedance begets
zero sensitivity to applied voltage. Of course, this prognosis is germane only to static, zero
0
0.2
0.4
0.6
0.8
1.0
0.001 0.01 0.1 1 10
Si gnal Frequency (MHz)
S
h
u
n
t

O
u
t
p
u
t

C
o
n
d
u
c
t
a
n
c
e
,

(
m
h
o
)
g
o
k

- 460 -
frequency conditions and does not illuminate the potential instability problem we uncovered
at high signal frequencies.
5.5.0. SUPPLY-INDEPENDENT BIASING
We have applauded biasing networks delivering static responses that are independent of
power supply voltages. Supply voltage independence circumvents the effects of poor supply line
regulation, noise and spurious other signal coupling to the supply line, battery degradation, and
other miscellaneous phenomena. At this point of our electronic system travels, such indepen-
dence has been accomplished by inserting a current source, which is ideally characterized by
infinitely large terminal impedance, between the supply voltage and the electronic system that
the supply line is intended to activate. The downside to this design tack is that ideal current
sources and sinks live and prosper only within the hallowed halls of academe. Fortunately, how-
ever, reasonable approximations of ideal current sources can be designed and implemented as a
means of securing adequate power supply rejection in high performance electronic systems.
5.5.1. SUPPLY-INDEPENDENT CURRENT SOURCE
An example of a practical alternative to the current source approach for mitigating
power line uncertainties is the five-transistor network shown in Figure (5.37). The circuit uses
three PMOS transistors and two NMOS devices to establish an output current, I
o
, which can be
supplied to any conductive, two terminal load. In this case, the load is taken to be a simple linear
resistance, R
l
. As long as the power supply voltage, V
dd
, is large enough to sustain saturation of
transistors M2, M4, and M5, and CLM in these three transistors is insignificant, current I
o
is
demonstrably independent of voltage V
dd
. We note in passing that the diode-connected transis-
tors, M1 and M3, are guaranteed to operate in saturation by virtue of their diode-type
interconnections.

Figure (5.37). Schematic diagram of a biasing network that delivers an
output current, I
o
, which is nominally independent of the
power supply voltage, V
dd
. Although substrate terminals are
not shown, the bulk substrate terminals of the three PMOS
transistors are returned to the positive bus line, while the
bulk terminals of the two NMOS devices are grounded.
Because transistors M3 and M5 comprise a classic current mirror and since the gate as-
M3 M5 M4
M2 M1
V
dd
I
Q
I
Q
I
o
x 1 x k
21
2
x 1 x 1
x k
p
R
R
l

- 461 -
pect ratio of transistor M5 exceeds that of M3 by a factor of k
p
, the output current is given simply
by I
o
= k
p
I
Q
. Of course, this claim ignores CLM, body effect, and all other second order transis-
tor modeling phenomena. Consequently, we conclude immediately that if I
Q
can be made
independent of V
dd
, output current I
o
must similarly be invariant with V
dd
.
We see that current I
Q
flows through both transistors M1 and M4. Because of the iden-
tical gate aspect ratios in the M3-M4 mirror, current I
Q
is also conducted by transistors M3 and
M1. But the gate aspect ratio of transistor M2 is larger than the gate aspect ratio of M1 by a fac-
tor of k
21
2
. Accordingly, the gate source-voltage, V
gs2
, of M2 is necessarily smaller than V
gs1
, the
gate-source voltage developed on M1. The resultant difference, (V
gs1
V
gs2
), of these two gate-
source potentials necessarily appears across the resistance, R, which degenerates the source of
M2. Our stalwart buddy, George Ohm, insists that I
Q
derive as this difference voltage divided by
R. But remember that I
Q
flows through M1 and therefore V
gs1
is almost entirely determined by
I
Q
. Moreover, I
Q
flows through M2, which means that V
gs2
is similarly a function of quiescent
current I
Q
. These current-voltage dependencies allow hint as to how supply independence of I
Q
,
whence output current I
o
, can be achieved. In particular, since current I
Q
satisfies
gs1 gs2
Q
V V
I ,
R
= (5-86)
and both V
gs1
and V
gs2
are functionally dependent on current I
Q
, it follows, that I
Q
is independent
of V
dd
and other circuit variables. Let us now examine the details that analytically underpin this
intuitive glimpse.
From the circuit diagram in Figure (5.37), we see that to the extent that CLM is negligi-
ble,
( ) ( )
2 2
2
Q n gs1 hn 21 n gs2 hn
I V V k V V , | | = = (5-87)
which gives rise to the voltage interrelationship,
gs1 hn
gs2 hn
21
V V
V V .
k
= (5-88)
We should note that (5-87), in addition to being oblivious to CLM effects, tacitly ignores body
effect in transistor M2. This body effect is negligible for thin oxide transistors and is minimized
by ensuring that degeneration resistance R is small. We see that (5-87) postures an unambiguous
functional dependence of both voltages V
gs1
and V
gs2
on static current, I
Q
. Using (5-86),
( ) ( )
gs1 hn gs2 hn gs1 gs2
Q
V V V V V V
I .
R R

= (5-89)
Upon inserting (5-88) into (5-89), we determine that
( )
gs1 hn
Q
21 21
Q
21 n
1
V V 1
I
k k 1
I ,
R k R |
| |
|
|
| |
\ .
| = =
|
\ .
(5-90)
where we have once again profited from (5-87). If we square both sides of this expression, we
determine that

- 462 -
2
21
Q
n 21
k 1
1
I ,
k R |
| |
| =
|
\ .
(5-91)
which is indeed independent of the power line voltage, V
dd
. Of course, this voltage independence
is observed if and only if voltage V
dd
is larger than the minimum line voltage commensurate with
ensuring the saturation of all transistors embedded in the considered biasing network. Although
current I
Q
and thus, the output current,
2
p
21
o p Q
n 21
k
k 1
I k I ,
k R |
| |
| = =
|
\ .
(5-92)
are independent of the applied static voltage, V
dd
, currents I
Q
and I
o
are temperature variant. In
particular, transconductance coefficient
n
decreases with increasing temperature because of its
direct dependence on the mobility of channel charge carriers. If we assume that resistance R is
independent of temperature, which is less than an entirely rational declarative, we see from (5-6)
that current I
o
in (5-91) rises as a three-half power law of temperature.
An interesting aspect of (5-91) is that it produces a constant device transconductance.
A confirmation of this contention compels a return to (5-87) to obtain the forward transconduc-
tance, g
m1
, of transistor M1. We have, recalling our small signal modeling ventures in the
preceding chapter,
( )
Q
m1 n gs1 hn n Q
gs1
I
g 2 V V 2 I .
V
| |
c
= = =
c
(5-93)
If we insert (5-90) into (5-92), we get
21
m1 n Q
21
k 1
g 2 I 2 ,
k R
|
| |
| = =
|
\ .
(5-94)
which clearly infers a predictable transconductance that is determined exclusively by the norma-
lized gate aspect ratio parameter, k
21
, and circuit resistance R. We note in passing that for k
21
=
2, g
m1
= 1/R; that is, the inverse of the source degeneration resistance, R, defines the forward
transconductance. Analogous current independent results can be obtained for the transconduc-
tances of transistors M2 and M5.
We should highlight the significance of a transconductance that is invariant with bias
currents and voltages. This importance stems from the fundamental fact that the forward
transconductance of any transistor is a measure of the I/O gain that can be supplied by that
transistor when operated with its source terminal grounded. To the extent that the I/O gain is
directly proportional to forward transconductance, constant transconductance means that the
observable gain is rendered constant, independent of bias settings and signal levels. In other
words, perturbations in quiescent operating points caused by signal swings do not incur changes
(or at least incur only minimal changes) in forward transconductance. In a word, I/O nonlineari-
ties are at least partially mitigated. Recall that BITM in transistor M2 is held to a minimum if
resistance R is kept small. We now have a second reason that compels small R. In particular, the
fact that g
m1
(and other transistor transconductances) is inversely proportional to resistance R af-
firms the need to keep R small if large forward gain is to be realized.
Before addressing an engineering shortfall that is endemic to virtually all supply-
independent biasing networks, it is important that we understand the three design requirements

- 463 -
that underlie the nominal invariance of currents I
Q
and I
o
with respect to perturbations in power
line voltage V
dd
. The first of these conditions is that PMOS transistor M4 must function to emu-
late an ideal current source. The output current, I
Q
, of this current source establishes the gate-
source potential for diode-connected transistor M1. To the extent that this current source boasts
very large terminal resistance, the M1 gate-source potential is essentially independent of the line
voltage, V
dd
. Figure (5.38) depicts the pertinent M4-M1 subcircuit we have extracted from the
schematic in Figure (5.37). The subject subcircuit is seen to generate current I
Q
as a foundation
for establishing the gate-source voltage, V
gs1
, observed for transistor M1 and given by (5-87).
Note that the resultant circuit model in Figure (5.38) is similar to the biasing cell we studied in
Section (4.7.3). It also mirrors a subcircuit deployed in the schematic diagram of Figure (5.23).
Because the current source formed of transistor M4 must approximate an ideal branch element if
supply voltage independence is to be nurtured, the channel resistance, r
o4
, needs to be as large as
possible. Recall that a large channel resistance is associated with a relatively long drawn channel
length and/or small I
Q
. In turn, small I
Q
requires small gate aspect ratios for transistors M1 and
M4. Alternatively, the resistance associated with the M4 current source cell can be enhanced
through either passive or active source degeneration in M4. Of course, a topological modifica-
tion to the M4 subcircuit mandates that appropriate changes be made in the M3 and M5 subcir-
cuits implicit to Figure (5.37).

Figure (5.38). The M1-M4 subcircuit extracted from the self-biasing net-
work in Figure (5.37). Transistor M4 functions as a sim-
ple current source.
The second requirement in the design of the self-biasing network is that the current, I
Q
,
be mirrored as accurately as possible by PMOS transistor M3. High current mirroring accuracy
implies the relative unimportance of CLM, which in turn commands suitably long channel
lengths in both M4 and M3. We show this mirroring as the extracted subcircuit in Figure (5.39).
This figure purports that current I
Q
is forced to flow through both the M1-M4 and M2-M3
branches of the bias circuit. At this point of our discussion, it is important to remember that by
virtue of (5-87), current I
Q
and gate-source voltage V
gs1
are inextricably intertwined; that is, the
value of current I
Q
uniquely fixes the M1 gate-source voltage, V
gs1
.
The third design requirement is that the current, I
Q
, which flows through transistor M3
because of M4-M3 mirroring, be made to flow through the drain of transistor M2. Transistor M2
must have a gate aspect ratio that differs from the gate aspect ratio of transistor M1. The differ-
ence between these gate aspect geometries is critical because if M1 and M2 conduct the same
current, I
Q
, as we underscore in Figure (5.39), the larger transistor, which is M2 in this case,
generates a gate-source voltage, V
gs2
, which is smaller than V
gs1
. The differential voltage, (V
gs2

M4
M1
V
dd
I
Q
x 1
x 1
Bias
From M3
To Gate
of M2
V
gs1
+
M1
V
dd
I
Q
I
Q
x 1
To Gate
of M2
V
gs1
+

- 464 -
V
gs1
), consequently appears across the terminals of source degeneration resistance R, which ulti-
mately engenders (5-89). If M1 and M2 were assigned the same gate aspect ratios (meaning k
21

= 1), V
gs1
and V
gs2
are necessarily identical to first order, and I
Q
is remanded to zero. But for k
21

> 1, V
gs2
< V
gs2
, and current I
Q
, which is proportional to (V
gs1
V
gs2
), ensures nonzero I
Q
. In the
first component on the right hand side of (5-89), it is notable that, by the Schichman-Hodges
model, current I
Q
fixes both of the gate-source voltages, V
gs1
and V
gs2
. This circumstance enables
us to conclude that I
Q
is effectively a function of itself and is therefore independent of line vol-
tage V
dd
.

Figure (5.39). TheM4-M3 current mirror subcircuit extracted from the
self-biasing network in Figure (5.37).
The fact that current I
Q
in Figure (5.37) can be ominously couched as a function of it-
self proffers a clue that a problem surrounds the constant current disclosure of (5-91) and hence,
the accompanying response in (5-92). In particular, (5-91) is not the only solution to (5-90),
which can indeed be satisfied trivially for I
Q
= 0. In other words, it is possible for the network in
Figure (5.37) to register the quiescent current given by (5-91) when supply voltage V
dd
is applied
suddenly. But it is also and unfortunately possible that upon boot up, the subject network latches
to its useless null solution nest of I
Q
= 0. To be sure, such a null solution is programmatically
unlikely because of processing uncertainties that incur at least small parametric differences, and
thus current imbalances, in transistors M3, M4, and M5. But because of the insidious nature of
Murphys Law, we must take care to preclude the null startup state.
Viable startup modules, which are topologically similar to those deployed in the BJT
form of this supply-independent biasing network, are available to preclude the foregoing null
current state. Fundamentally, these startup modules force an imbalance among transistors M3,
M4, and M5. Ideally, these startup cells, which generally require at least two additional transis-
tors, consume no power in the steady state.
We should interject that the null current state is not unique to the circuit presently be-
fore us. To be sure, most biasing networks that boast supply voltage independence suffer from a
small, but nonzero, probability of a null current latching upon startup.
Figure (5.40) depicts a simple startup module that has been appended to the supply-
independent circuit of Figure (5.37)
[3]
. The startup cell in question is comprised of capacitor C
and the grounded source transistors, M6 and M7. Note that the gate terminal of M6 is incident
M2
x k
21
2
R
M3
I
Q
x 1
M4
M1
V
dd
I
Q
x 1
x 1
V
gs1
+
V
gs1
+
C
u
r
r
e
n
t
M
i
r
r
o
r

- 465 -
with the junction of the drain terminals of M1 and M4, while the drain of M7 is connected to the
junction of the drain and gate terminals of M3. In the steady state, where capacitance C behaves
as an open circuit, no static voltage is delivered to the gate of M7, thereby forcing M7 into cutoff.
In addition, the open circuited nature of C in the steady state precludes any drain current in M6.
Thus, we can appreciate that the highlighted startup cell is effectively disconnected from the
supply-independent configuration when steady state biasing levels are achieved. Although the
startup cell is transparent to strict DC, it does load the M4 and M3 drain nodes with parasitic
device capacitances. Fortunately, this loading is rarely an issue because the nodes in question
exhibit low driving point impedances under small signal conditions owing to the diode-con-
nected nature of M1 and M3. Accordingly, these parasitic capacitances forge small time con-
stants that rarely impact circuit response speeds.

Figure (5.40). The supply-independent biasing network of Figure (5.32) with a startup
module incorporated to preclude a null current state when the voltage,
V
dd
, is applied suddenly to activate the network.
As we did in the BJT version of the circuit before us, we choose to investigate the
functionality of the startup module in a largely qualitative manner. To this end, we assume that
the power supply voltage, V
dd
, is applied as a voltage step at time t = 0. If capacitance C is in-
itially uncharged and is much larger than the net device capacitance witnessed at the gate of
transistor M7, almost all of V
dd
appears instantly between said gate and circuit ground, thereby
turning on M7. We see then that the drain current of M7 establishes the aforementioned current
imbalance that ostensibly precludes the null current setup.
Let us look at the startup scenario of the circuit at hand. The current flowing in M7 is
necessarily sourced by the drain of transistor M3. This device turns on prior to M4, which awaits
the time required for voltage V
dd
to charge the M4 source-gate capacitance to the transistor thre-
shold potential. It follows that because of capacitance C and its inherent inability to change its
terminal voltage instantaneously, transistor M7 forces M3 to begin conducting some of its current
into the drain of M2. Immediately after time t = 0, M4 and M1 remain nominally cutoff. When
current flows through M2, the sum of the gate-source voltage of M2 and the voltage drop across
M3 M5 M4
M2
M6
M7
M1
V
dd
I
Q
I
Q
I
o
x 1 x k
21
2
x 1 x 1
x k
p
R
R
l
C
S
t
a
r
t
u
p
M
o
d
u
l
e

- 466 -
resistance R begins to rise to the threshold potential of M1, thereby supporting the initiation of
current in the drains of M1 and M4. As the gate-source voltage of diode-connected transistor M1
continues to increase, so does the gate-source voltage of M6, which throughout this interlude re-
mains cutoff. But as the gate-source voltage of M6 rises beyond threshold level, M6 conducts
current, which charges capacitance C toward V
dd
, thereby lowering the voltage at the gate of M7.
When C charges to a level larger than (V
dd
V
h7
), where V
h7
is the M7 threshold voltage, M7
switches off, which is tantamount to the initiation of steady state circuit operation. Since zero
current response has been precluded by the current imbalance induced by the startup cell at the
instant of voltage application, this steady state condition supports the establishment of (5-91) as
the only observable solution for current I
Q
.
5.5.2. BANDGAP REFERENCE NETWORK
In addition to affording low voltage, low power, and supply-independent operation,
voltage references for high performance analog integrated circuits, and especially circuits ear-
marked for high-speed data acquisition and information processing, must project superior
temperature insensitivity. The temperature sensitivity problem can be especially pronounced in
deep submicron technologies for which even modest current levels correspond to high current
densities that routinely produce intrinsic temperatures rising to as much as 75 C or higher.
The arguably finest engineering solution to the temperature dilemma problem is the
bandgap reference circuit. This circuit, which also boasts static performance that is nominally
insensitive to power line voltage variations produces an almost temperature invariant reference
voltage. This temperature insensitivity is achieved by exploiting the inherently negative
temperature coefficient we witnessed in Chapter #2 for the junction potential developed across a
forward biased PN junction diode. Specifically, the bandgap reference produces an output re-
sponse that is proportional to the sum of the aforementioned junction forward bias and the output
voltage of a PTAT generator, whose voltage output is directly proportional to absolute tempera-
ture. Accordingly, a theoretic cancellation of temperature effects is made possible
The bandgap reference cell is explored thoroughly in Section (3.5.2) and therefore, its
analysis is not repeated here.
5.6.0. HIGH PERFORMANCE BIASING
Before concluding our expository on MOSFET biasing networks, we should address a
few special purpose, but nonetheless commonly exploited, biasing cells that offer exceptionally
high performance. High performance is a generic descriptive whose meaningful definition is
often tied to the application of interest. In the present case of biasing, we associate performance
quality with two fundamental engineering requirements. First, we demand that the output cur-
rents or voltages of a biasing network be predictable and reproducible. Foremost among the
engineering implications of predictable and reproducible static responses is biasing invulnerabil-
ity to supply voltage variations incurred by temperature changes, poor line regulation, spurious
signals, or other environmental phenomena. Yet another implication is a biasing response that is
not overtly sensitive to vagarious transistor model parameters and poorly controlled values of
circuit branch elements. Second, we wish to have a biasing network emulate the performance of
an idealized circuit structure. In the case of voltage sources, this means that Thvenin output
resistances must be very small. In contrast, current sources naturally exude very high Thvenin
output resistances.

- 467 -
5.6.1. REGULATED CASCODE CURRENT SINK
The network depicted in Figure (5.41) is referred to as a regulated cascode current sink.
It exploits active feedback to achieve a very large output impedance, R
out
. The active feedback
to which we refer derives from the indicated connection of a voltage amplifier
8
whose gain, A
v
, is
taken as the ratio of the amplifier output voltage, V
a
, to the applied differential input voltage, V
d
.
In particular,

Figure (5.41). Schematic diagram of a regulated cascode current sink. The am-
plifier, voltage gain is V
o
/V
d
= A
v
. It also delivers infinitely large
input impedance at both its non-inverting and inverting input ports.
a
v
d
V
A ,
V
= (5-95)
for which
d bias 2
V V V . = (5-96)
In (5-96), V
2
symbolizes the drain-source voltage imposed on transistor M2. On the assumption
that the feedback amplifier offers very high impedances seen looking into both its non-inverting
and inverting input ports, the output current, I
k
, is determined largely by the applied input cur-
rent, I
in
. Specifically, the current mirror nature of transistors M3 and M2 deliver
k 23 in
I k I , = (5-97)
where k
23
is the ratio of the gate aspect ratio of transistor M2 to the gate aspect ratio of transistor
M3. Equation (5-97) assumes that the effects of CLM in M2 and M3 are mitigated by maintain-
ing comparably equal drain-source voltages between these two transistors and/or by using
transistors that feature reasonably long channel lengths. Thus, the utilized amplifier has little
impact on the particular value of output current I
k
. But, as we are about to demonstrate, it does
boost the output resistance, and unselfishly offers other performance advantages. The most nota-
ble of these additional advantages is that it effectively regulates drain-source voltage V
2
by
keeping it nearly constant, independent of perturbations in the applied voltage V
kk
.
Figure (5.42) displays the small signal equivalent circuit pertinent to determining the
output resistance, R
out
, of the regulated cascode. In this structure, we have tacitly ignored bulk-

8
As we shall see in the subsequent chapter, an especially simple form of this feedback amplifier requires but a
single MOSFET and a single resistance.
M1
M2
A
v
V
bias
M3
I
in
+V
dd
V
kk
R
out
I
k
x 1 x k
23
x k
23
V
d
V
a
V
2

- 468 -
induced threshold modulation in transistor M1. Moreover, we assume that V
bias
is a constant vol-
tage that is divorced of any signal component. Accordingly, the signal voltage, say V
as
, devel-
oped with respect to ground at the gate of transistor M1 is A
v
V
2s
, where we have invoked (5-95)
and (5-96). Moreover, we have represented the signal component of the M2 drain-source voltage
as V
2s
. The small signal equivalent circuit of M2 embodies only the drain-source channel resis-
tance, r
o2
, across which signal voltage V
2s
is developed. This situation reflects the presumption
that input current I
in
is constant and derives from an ideal current source possessed of infinitely
large terminal resistance. It follows that no signal voltage can be developed across the gate-
source terminals of either M3 or M2, whence no signal current proportional to the M3 gate-
source voltage can evolve in the model for transistor M2. The model at hand makes clear the
fact that the gate-source signal voltage applied to transistor M1 is

Figure (5.42). Low frequency, small signal equivalent circuit of the regulated
cascode current sink shown in Figure (5.44). The circuit is
used to evaluate the output resistance, R
out
, as the ratio, V
x
/I
x
, of
mathematical ohmmeter variables.
( )
1 as 2s v 2s 2s v o2 x
V V V A V V 1 A r I , = = = + (5-98)
while
( )
x o1 x m1 1 o2 x
V r I g V r I . = + (5-99)
After we substitute (5-98) into (5-99), we arrive at the output resistance result,
( ) ( ) ( )
x
out v m1 o1 o2 o1 o2
x
V
R 1 1 A g r r r r .
I
(
= = + + +
(

(5-100)
The last result encourages two observations. First, the output resistance of the regulated cascode
is a markedly enhanced version of the series combination of the channel resistances offered by
transistors M1 and M2. We note that this resistance enhancement is embellished by the feedback
amplifier, whose positive voltage gain is A
v
. Second, in the likely case that g
m1
(1+A
v
)(r
o1
||r
o2
)
>> 1,
( )( ) ( ) ( )
out m1 o1 o2 v o1 o2 v m1 o1 o2
R 1 g r r 1 A r r 1 A g r r ,
(
= + + + ~ +
(

(5-101)
which projects the fact that R
out
is large because the reasonably large gain metric, g
m1
r
o1
, multip-
lies a large channel resistance (r
o2
), which is itself multiplied by (1 + A
v
).
An illuminating sidebar of the regulated cascode network is the nature of the signal vol-
r
o1
r
o2
g V
m1 1
V
1
+
A V
v 2s
+
V
2s
I
x
V
x
I g V
x m1 1
I
x
R
out
V
as

- 469 -
tage, V
2s
, developed across the drain-source terminals of transistor M2 in Figure (5.41). From
Figure (5.45), (5-100), and (5-101), we have
( )
x x
2s o2 x o2
out
m1 o1 v
V V
V r I r ,
R
g r 1 A
= = ~
+
(5-102)
which portends a very small signal voltage because of a presumably large M1 channel resistance,
a realistic forward transconductance (g
m1
) for transistor M1, and the amplifier gain (A
v
). Three
interesting aspects to this miniscule small signal voltage unfold. First, if V
2s
is indeed very
small, the signal component, I
x
, of the M2 drain current that arises from our mathematical
ohmmeter is necessarily very small, thereby portending a high output resistance, as we have con-
firmed with (5-101). We are therefore moved to say that the feedback amplifier, whose voltage
gain serves to reduce signal voltage V
2s
, encourages the high output resistance, R
out
, we deduced
for the regulated cascode. The second noteworthy point is that our mathematical ohmmeter vol-
tage, V
x
, can be interpreted as a perturbation, AV
kk
, in applied voltage V
kk
. Moreover, our
mathematical ohmmeter current can be viewed as a signal-induced change, say AI
k
, in the drain
current, I
k
, which transistors M1 and M2 conduct. We can therefore conclude, with the aid of (5-
15), that the high output resistance supported by the feedback amplifier ensures a low sensitivity
of output (drain) current to voltage V
kk
in that
( )
x kk kk
k x
out out
m1 v o1
V V V
I I .
R R
g 1 A r
A A
A = = = ~
+
(5-103)
The third point to be made surrounds the nature of the net voltage, V
2
, which is devel-
oped from the drain to the source on transistor M2, in light of the conclusion that the signal
component, V
2s
, of this voltage is very small. Figure (5.44) renders clear the fact that
2 bias d
V V V . = (5-104)
Since V
bias
eschews any signal component and V
2
boasts almost zero signal component, differen-
tial voltage V
d
necessarily follows as a voltage displaying virtually no signal component. From
(5-96),
a
2 bias d bias
v
V
V V V V ,
A
= = (5-105)
which suggests that if voltage gain A
v
is large (an often challenging design requirement, to be
sure), the drain-source voltage, V
2
, of transistor M2 is held nominally constant at the bias level,
V
bias
. Stated in another way, a high gain amplifier forces the differential input voltage of the am-
plifier in question toward zero. Since holding a circuit voltage constant is akin to classic voltage
regulation, we now understand why the amplifier in the regulated cascode is said to regulate
voltage V
2
. Even if A
v
is not very large, the amplifier output voltage, V
a
, which excites the gate
of transistor M1 is virtually divorced of signal voltage because of small V
2s
. In this case, we say
that voltage V
2
is regulated to a value that is less than V
bias
by an amount that equals the quies-
cent value of voltage V
a
divided by gain A
v
.
5.6.2. ENHANCED OUTPUT IMPEDANCE CURRENT SINK
A modified version of the regulated cascode current one that is particularly suited for
circuits using deep submicron MOS technology devices sink appears in Figure (5.43)
[4]
.
Submicron transistors invariably require low voltage biasing to preclude excessive electric fields
in the device channels and impedance enhancement methods that compensate for relatively small

- 470 -
drain-source channel resistances. The network boasts low voltage operating capabilities because
of the low voltage reference cell comprised of transistors M3 and M4 and the applied bias vol-
tage, V
bias
. As we describe in Section (5.4.2), V
bias
places transistor M3 on the cusp of operating
in its saturation domain, while M4 operates in (or very near) saturation with a drain-source vol-
tage that is nominally its threshold potential. Current I
bias
and designable parameter p
2
are se-
lected to satisfy power dissipation limits. Along with applied voltage V
kk
, I
bias
and p
2
ensure that
all other transistors operate in saturation. Ordinarily, p is a number that is greater than one.

Figure (5.43). Schematic diagram of the enhanced output resistance current sink. The network
is the regulated cascode sink in Figure (5.41), modified for deployment in net-
works that exploit deep submicron technology MOSFETs.
5.6.2.1. Static Investigation
Under static, or quiescent (zero input signal), circumstances, the circuit in Figure (5.43)
yields
k bias d2 d5
I I I I , + = + (5-106)
where I
d2
and I
d5
are the quiescent drain currents conducted by transistors M2 and M5, respec-
tively. Since the gate-source voltages of M2 and M5 are identical and M2 has a gate aspect ratio
that is a factor of k larger than the gate aspect ratio of transistor M5, I
d2
= kI
d5
. Moreover, I
d5
=
I
d3
/k owing to the current mirroring nature of the M3-M5 connection. We also note that the static
drain current, I
d3
, of transistor M3 is the input current, I
in
. Thus, the output current, I
k
, of the sub-
ject current sink is, using the preceding equation
k d2 d5 bias in bias
1
I I I I 1 I I .
k
| |
= + = +
|
\ .
(5-107)
If I
bias
is selected so that I
bias
= I
in
/k, output current I
k
mirrors I
in
with unity scale factor; that is, I
k

= I
in
. But if I
bias
= I
in
/k = I
d5
, (5-107) shows that current I
k
does not divide between transistors
M2 and M5. Instead, current I
k
flows solely into the drain of transistor M2. If I
bias
flows into M5
and I
k
flows into M2, no current is conducted by the metallization that connects the drain of
transistor M2 to the drain terminal of M5. If we indeed wish current I
k
to be identical to input
current I
in
, we are well advised to adopt the computer-aided design tack of carefully adjusting
current I
bias
until null current flow is observed at the aforementioned branch interconnect be-
tween the drain terminals of transistors M2 and M5. In this manner, we pragmatically adjust the
M4
M3 M5
x k
x k x 1
V
bias
I
in
I
bias
p I
2
bias
M6
x 1
M7
M1
x 1
x k
V
dd
M2
x k
V
kk
I
k
R
out

- 471 -
nominal setting of I
bias
= I
in
/k to account for subtle device performance differences incurred by
CLM, BITM, and other high order modeling phenomena that we ignore, or at least de-emphasize
peremptorily.
The network in Figure (5.43) also projects
( )
2
2
bias n7 gs7 hn
p I V V , | = (5-108)
where we are using, in general,
ni
and V
gsi
to represent the transconductance coefficient and
static gate-source voltage, respectively, of the i
th
MOSFET. Moreover and as has become our
normal analytical strategy, we adopt the simple long channel approximation that ignores CLM,
body effect (which invokes identical threshold voltages for all transistors in the schematic dia-
gram at hand), DIBL, and all other second order phenomena. Since transistors M6 and M7 are
identical, inclusive of gate aspect ratios,
n6
=
n7
. We also see that
( )
2
bias n7 gs6 hn
I V V . | = (5-109)
The foregoing two equations deliver
( )
gs7 gs6 hn
V pV p 1 V . = (5-110)
In view of the facts that
n5
=
n7
the gate aspect ratio of M3 is k-times that of M5, and
current I
in
flows in the drain of transistor M3,
( )
2
in
n7 gs5 hn
I
V V ,
k
| = (5-111)
which is to say that the drain saturation voltage, V
dsat5
, of transistor M5 is
in
dsat5 gs5 hn
n7
I
V V V .
k|
= = (5-112)
If we choose to set the drain-source voltage of M5, and thus of M2, to V
dsat5
, Figure (5.43), (5-
109), (5-110), and (5-112) combine to deliver
( )
( )
( )
in bias
dsat5 gs6 gs7 gs6 hn
n7 n7
I I
V V V p 1 V V p 1 .
k| |
= = + = = (5-113)
In short, transistor M5 is biased at its saturation domain cusp if
( )
2
in
bias
I
p 1 I .
k
= = (5-114)
We can advance two important points in conjunction with the last result. The first of
these is that by holding the drain saturation voltage of M5, and thus M2, to V
dsat5
, the voltage
drop from the source of transistor M1 to ground is held to a minimum. Of course, minimal vol-
tage developed from the source of M1 to ground complements the intent to set the drain-source
voltage of transistor M5 at its drain saturation value. This means that the applied voltage, V
kk
,
need only supply the net voltage, (V
dsat5
+ V
dsat1
), where V
dsat1
represents the drain saturation vol-
tage of M1. In other words, V
kk
need only be a relatively small voltage (of the order of twice
drain saturation value) for the current sink to operate properly. And, of course, small V
kk
con-
flates admirably with the design constraints implicit to deep submicron technology. The second
point to be made recalls (5-107), which confirms that I
bias
= I
in
/k makes current I
bias
flow through
the drain of M5, while output current I
k
flows in the drain of M2. In other words, no current

- 472 -
flows through the M2-M5 drain interconnect. From (5-114), I
bias
= I
in
/k, implies that parameter
p must ideally be two; that is p = 2. We are therefore afforded the luxury of a nominal setting
for parameter p, which we can adjust carefully to set the drain-source voltage of M5 to its drain
saturation level, despite uncertainties in key transistor model parameters. It is interesting that
while I
bias
effectively controls the current conducted by the M2-M5 drain metallization, p sets the
drain-source voltage of M5 and therefore, the drain-source voltage of M2. In a word, the circuit
designer is gifted the luxury of tweaking two nominally independent circuit variables to achieve
proper operation of the current sink in Figure (5.43).
5.6.2.2. Small Signal Investigation
The small signal model for quantifying the low frequency output resistance, R
out
, of the
enhanced output impedance current sink appears in Figure (5.44). In arriving at this model, we
have neglected BITM in all transistors, and in transistor M6, we have ignored the drain-source
channel resistance, r
o6
. The latter approximation is appropriate in that r
o6
shunts resistance 1/g
m6

in the small signal model of M6. This shunt resistance combination collapses to 1/g
m6
in that we
expect g
m6
r
o6
>> 1. All three current sources, I
in
, I
bias
, and p
2
I
bias
, are presumed ideal sources of
constant current. In addition to projecting infinitely large resistances across their respective
terminals, these current sources offer no signal components. Analogously, voltage V
bias
is taken
as a source of constant voltage, which is to say that it too produces no signal component. Since
I
in
and V
bias
contain no signal, no gate-source signal voltages can be developed on transistors M2
and M5. In light of the drain connection of these two transistors, this means that M2 and M5
combine to forge a net resistance, (r
o2
||r
o5
), from the source terminal of transistor M1 to ground.
While zero static current is conducted by the M2-M5 drain interconnect, we note with interest
that this same metallization establishes signal feedback from the source terminal of M1 to the
gate-source terminals of M6 and thus, to the gate of transistor M7. The basic function of this
feedback is similar to the feedback offered by the amplifier in the regulated cascode sink of Fig-
ure (5.41). Of course, the output resistance follows as the ratio, V
x
/I
x
, of our mathematical
ohmmeter variables, V
x
and I
x
.

Figure (5.44). Low frequency, small signal equivalent circuit for calculating the output resis-
tance, R
out
, of the current sink in Figure (5.43).
In Figure (5.47), a conventional circuit analysis produces
( )
b o2 o5 x
V r r I , = (5-115)
r
o1
r ||r
o2 o5
r
o7
g V
m1 a
g V
m7 b
V
a
R
out
1/g
m6
V
b
V
x
I
x
I
x
g V
m7 b
I g V
x m1 a
0

- 473 -
( )
a m7 o7 b o2 o5 x
V g r V r r I , = (5-116)
and
( ) ( )
x o1 x m1 a o2 o5 x
V r I g V r r I . = + (5-117)
Upon inserting (5-115) into (5-116) and then putting the resultant form of (5-116) into (5-117),
we obtain
( )( ) ( )
x
out o1 m1 o1 m7 o7 o2 o5
x
V
R r 1 g r 1 g r r r ,
I
(
= = + + +

(5-118)
which clearly implies a very large output resistance. For large values of (g
m1
r
o1
) and (g
m7
r
o7
), the
output resistance in (5-118) reduces to
( )( ) ( )
( )( )( )
out o1 m1 o1 m7 o7 o2 o5
m1 o1 m7 o7 o2 o5
R r 1 g r 1 g r r r
g r g r r r .
(
= + + +

~
(5-119)
In principle, this resistance can be enormous (of the order of several hundreds of MEG.
5.6.3. LOW VOLTAGE, HIGH RESISTANCE CURRENT SINK
A popular variation of the regulated cascode circuit is the configuration submitted in
Figure (5.45)
[5]
. The two notable features of this current sink are the low voltage biasing module
formed of transistors M4 and M6 and the regulated cascode output stage contrived of transistors
M1 through M3. The regulated cascode cell enables the realization of a very large output resis-
tance, R
out
. Along with its active degeneration via transistor M3, it also facilitates a controllable
and predictable output current, I
k
. The combination of these performance traits encourages the
deployment of the subject current sink in such high performance applications as data and
information processors, communication systems, and data converters. Moreover, the low voltage
cell, which we studied in Section (5.4.2), allows the realization of high R
out
and both predictable
and reliable I
k
at low voltage and low power levels. These formidable attributes explain the
popularity of the biasing network in a myriad of portable electronic systems.

Figure (5.45). Low voltage, regulated cascode, current sink featuring the
low voltage biasing cell examined in Section (5.4.2) and
active source degeneration via transistor M3.
M1
M3
M2
M6
I
Q2
I
Q1
I
in
V
kk
I
k
M5
M4
+V
dd
R
out
x 1
x 1
x k
x k
x 1
x 1
V
ref
V
Q1
V
Q2

- 474 -
We shall execute both a static analysis and a small signal analysis of the low voltage,
high impedance current sink. These analyses, and especially their static constituent, are some-
what intricate, and their proper engineering interpretation is a challenge. But it is precisely these
intricacies and challenges that motivate us to undertake the analytical effort, for its proper execu-
tion serves to test our comprehension of fundamental MOSFET biasing concepts.
5.6.3.1. Static Analysis
For our first order manual analyses, we shall continue to subscribe to our traditional
assumptions of negligible CLM, BITM, carrier mobility degradation, and other high order physi-
cal modeling phenomena. The fruits of the resultant simplified analysis lay a sturdy foundation
upon which we can ultimately rest our definitive computer-aided optimization of the network.
Noting that transistors M4 and M6 share the same gate aspect ratio, (5-78) gives for the
output voltage, V
ref
, of the low voltage biasing subcircuit,
Q1 hn
ref
V V
V ,
2
+
= (5-120)
where, of course, V
hn
is the threshold voltage of all NMOS transistors. Voltage V
ref
is applied
across the gate-source terminals of transistor M6. It is also the voltage established at the drain
node of transistor M4 with respect to circuit ground. Since the static input current, I
in
, which
may derive from an off chip current source, flows through the drain of transistor M4, V
ref
also
appears across the gate-source terminals of M4. In addition, V
ref
couples directly to the gate-
source terminals of transistor M3, whose gate aspect ratio is k-times larger than that of transistor
M6. In view of the facts that transistor M1 conducts the current flowing through M3 and has a
gate aspect ratio that is identical to that of M3, voltage V
ref
appears across the gate-source termin-
als of transistor M1. At this juncture, we therefore see that V
ref
is the voltage that appears across
the gate-source terminals of M6, M4, M3, and M1. Additionally, V
ref
is the voltage developed
with respect to ground at the drain node of transistor M4.
Using our simple MOSFET model, we have
( )
2
in n6 ref hn
I V V , = | (5-121)
and because M6 and M3 comprise a current mirror,
( ) ( )
2 2
k n3 ref hn n6 ref hn in
I V V k V V k I . = = = | | (5-122)
In the last equation, we have made use of the design stipulation that the gate aspect ratio of
transistor M3 (and of M1) is k-times that of transistor M6. We therefore see that to the extent that
care is exercised to assure the validity of our simplifying modeling approximations, the
predictability of current I
k
rests on our ability to realize input current I
in
predictably.
As we have already documented, V
gs4
= V
ref
. The drain-source voltage, V
ds6
, of transis-
tor M6, which is identical to the gate-source voltage, V
gs5
, of transistor M5, is
ds6 gs5 Q1 gs4 Q1 ref
V V V V V V . = = (5-123)
But if we use (5-120) to eliminate voltage variable V
Q1
in (5-123), we find that
ds6 gs5 Q1 ref ref hn
V V V V V V . = = (5-124)

- 475 -
No less than four interesting points surface from the last expression. The first of these is that the
drain-source bias on M6, and hence, the gate-source bias applied to M5, is controlled exclusively
by input current I
in
. Specifically and appealing to (5-121),
in
ds6 gs5 Q1 ref ref hn
n6
I
V V V V V V . = = =
|
(5-125)
The second point is that because the gate-source bias of transistor M6 is V
ref
, the drain-source
voltage of M6 is exactly its idealized drain saturation voltage, (V
ref
V
hn
), which is indeed the
drain saturation voltage for low, drain to source electric fields. Thus, we are assured that transis-
tor M6 is saturated. Third, if transistor M4 is to operate in its saturation regime, it requires a
drain-source voltage, V
ds4
, of
( )
ds4 ref ds6 ref ref hn hn ref hn
V V V V V V V V V , = = = > (5-126)
or equivalently,
ref hn
V 2V . s (5-127)
In addition to constraining V
ref
to a relatively small voltage, the subject inequality reassuringly
mirrors our generalized reference voltage constraint in (5-78). Fourth and finally, we can easily
confirm the saturation regime operation of transistor M5. In particular, its drain source voltage,
V
ds5
, is V
Q1
and by (5-120),
ds5 Q1 ref hn
V V 2V V . = (5-128)
On the other hand, recall from (5-125) that the gate-source voltage of M5 is
gs5 ref hn
V V V . = (5-129)
It follows that M5 is saturated if (2V
ref
V
hn
) (V
ref
V
hn
) V
hn
, which is equivalent to the ob-
viously satisfied constraint, V
ref
V
hn
.
Current I
Q1
flows through the drain of transistor M5, while current I
Q2
is conducted by
transistor M6. Recalling (5-129),
( ) ( )
2
2 2
ref hn
Q1 n5 ref hn n6 ref hn in
ref hn
2
hn
in
ref hn
V 2V
I V 2V V 2V I
V V
V
I 1 ,
V V
| |
|
= = =
|
\ .
| |
|
=
|
\ .
| |
(5-130)
which asserts that I
Q1
is necessarily slightly smaller than input current I
in
. If set I
Q2
= I
Q1
, we
resultantly expect the gate-source voltage, V
gs2
, of transistor M2 to be the same as the voltage,
V
gs5
, which is stipulated by (5-129). More pragmatically, we expect that the current, I
Q2
, which
gives rise to V
gs2
= V
gs5
= (V
ref
V
hn
), to differ slightly from current I
Q1
, owing to the presump-
tions to which we have adhered in the course of this static analysis. Regardless of the value of
current I
Q2
that renders V
gs2
= V
gs5
, we can assert V
Q2
= V
Q1
= (2V
ref
V
hn
), in accord with (5-
120). For this operating environment, the voltage developed with respect to ground at the gate
terminal of transistor M2 is forced to mirror the voltage we observe at the gate of transistor M5.
Accordingly, M2 and M3 are saturated for the same reasons that ensure the saturation domain
operation of transistors M5 and M6, respectively.
We complete the delineation of the static design conditions for the circuit before us by

- 476 -
ascertaining the minimum value to which node voltage V
kk
must subscribe if transistor M1 is to
be confined to its saturation regime. To this end, we note that the drain-source voltage, V
ds1
, to
which transistor M1 is subjected is
( )
ds1 kk gs2 kk gs5 kk ref hn
V V V V V V V V . = = = (5-131)
Since the gate-source voltage, V
gs1
, of M1 is V
gs1
= V
Q2
(V
ref
V
hn
), the saturation of M1 com-
mands
( ) ( ) ( ) ( )
kk ref hn Q2 ref hn ref hn ref hn
V V V V V V 2V V V V , > = (5-132)
where we have invoked our earlier conclusion that V
Q2
= V
Q1
= (2V
ref
V
hn
). The inequality in
(5-132) collapses to the design condition,
kk ref hn
V 2V V . > (5-133)
In a word, voltage V
kk
can be no smaller than one threshold potential below twice the reference
potential developed at the gate of transistor M6.

Figure (5.46). Low voltage, regulated cascode current sink with requisite node voltages de-
fined as functions of reference voltage V
ref
and NMOS threshold potential V
hn
.
The myriad of voltages we need to quantify so that we can ensure the desired saturation
regime operation of all NMOS transistors in the current sink of Figure (5.45) can understandably
foster confusion and even engineering uncertainty. In an attempt to dispel these problems, we
provide in Figure (5.46) the schematic diagram with all node voltages defined in terms of refer-
ence and threshold potentials. This type of a diagram, but with actual numerical voltages in-
serted, as opposed to the indicated generalities, is a recommended prerequisite to running simula-
tions in that it serves as a convenient reference for ascertaining whether the circuit is functioning
properly under static operating conditions. In the diagram, we show I
in
as an adjustable source of
current that can be varied to mitigate parametric uncertainties while attempting to achieve the
target reference potential, V
ref
. Similarly, we allow for a tunable current I
Q2
so that we can set, as
accurately as possible, the static node voltage at the gate of transistor M2. Ideally, I
Q2
= I
Q1
but
in the real world of device mismatches and parametric uncertainties, we can proffer as much as a
10% to 15% difference between these currents.
Before proceeding, it is worth interjecting that on the assumption that voltage V
ref
is
M1
M3
M2
M6
I
Q2
I
Q1
I
in
V
kk
I
k
M5
M4
+V
dd
R
out
x 1
x 1
x k
x k
x 1
x 1
V
ref
V
ref
V
Q1
V
Q2
V V
ref hn
V V
ref hn

2
V

V
r
e
f
h
n
> 2V V
ref hn
2
V

V
r
e
f
h
n

- 477 -
desirably temperature invariant, the parametric ratio, I
in
/
n
, should project an appropriately nega-
tive temperature coefficient. We arrive at this contention because (5-125) shows that voltage V
ref

is a linear superposition of threshold potential V
hn
and the square root of the ratio, I
in
/
n
. We
know, by virtue of the studies we undertook in Section (4.5.5), that threshold voltage V
hn
dis-
plays a positive temperature coefficient. Accordingly, the square root of I
in
/
n
must offset this
positive temperature coefficient if there is any hope of maintaining V
ref
nominally independent of
temperature. Observe that this requirement is helped along by transconductance metric
n
, which
is proportional to carrier mobility and therefore exudes a negative temperature coefficient.
5.6.3.2. Small Signal Analysis
As we argued earlier, a measure of quality for a current sink or source is the Thvenin
resistance it presents at the network port to which the current sink or source connects. In the
present case, our current sink connects to a network node that supports a sufficiently large vol-
tage, V
kk
. Recall that at this node, a large Thvenin output resistance, R
out
, is desired to minimize
the sensitivity of current I
k
to perturbations in voltage V
kk
.
We shall determine resistance R
out
in the circuit schematic diagram of Figure (5.45) by
applying our mathematical ohmmeter strategy to an appropriate small signal model of the current
sink. Before displaying this model, it is wise to discuss its topological composition. The model
in question need only embrace transistors M1 through M3 since grounding the source terminal of
transistor M5 precludes the subcircuit comprised of transistors M4 through M6 from interacting
dynamically with the M1 through M3 subcircuit. To be sure, the gate of transistor M6 is incident
with the gate of M3. But (5-81) reminds us that the resistance seen looking back from the gate of
M3 is small and approximately equal to 1/g
m6
. Moreover, if I
in
emulates an ideal source of con-
stant current, no signal impinges on the M3 gate since current source I
in
isolates said gate from
any perturbations witnessed in the power line voltage, V
dd
. With no signal applied to the M3
gate, and given that both the bulk and source terminals of M3 are grounded, the small signal
model for transistor M3 is simply a channel resistance, r
o3
, connected between its drain terminal
and circuit ground. We shall also presume that current sources I
Q1
and I
Q2
are ideal.
Continuing with the model development, transistor M2, like transistor M3, has no bulk-
source voltage and therefore, there is no bulk transconductance generator in its drain-source cir-
cuit. Of the three transistors of present interest, only M1 displays both small signal CLM and
BITM effects. The resultant small signal model is the topology appearing in Figure (5.47). In
this model, we have used (4-173) to represent the small signal effects of BITM in transistor M1.

Figure (5.47). Small signal equivalent circuit for determining the Thvenin output resistance,
R
out
, of the current sink shown in Figures (5.45) and (5.46).
In Figure (5.47), we see that that the controlling voltages, V
c
, V
b
, and V
a
are given by
r
o1
r
o2
r
o3
g V
m1 a
g V
m2 c
b1 m1 b
g V
V
a
V
b
V
c
V
x
I
x
I
x
R
out
I
g V
g V
x
m1 a
b1 m1 b


- 478 -
c b o3 x
V V r I , = = (5-134)
and
( )
a m2 o2 c c m2 o2 o3 x
V g r V V 1 g r r I . = = + (5-135)
In addition,
( )
x o1 x m1 a b1 m1 b o3 x
V r I g V g V r I . = + (5-136)
Upon substituting (5-134) and (5-135) into (5-136), we arrive at the conclusion,
( )
x
out o1 b1 m2 o2 m1 o1 o3
x
V
R r 1 1 g r g r r .
I
(
= = + + + +

(5-137)
In view of the fact that products of transistor transconductances and channel resistances tend to
be large, we can approximate this result as
( )
x
out m1 o1 m2 o2 o3
x
V
R g r g r r .
I
= ~ (5-138)
Since the general product, g
m
r
o
, is usually of the order of at least ten, (5-138) enables our
expectation of an output resistance, R
out
, which is in the neighborhood of two orders of a magni-
tude larger than the drain-source channel resistance of a single transistor. The latter resistance
(channel resistance) is generally at least several thousand ohms in prudently biased, deep submi-
cron MOSFETs.
5.7.0. REFERENCES
[1]. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
1997, pp. 135-146.
[2]. G. R. Wilson, A Monolithic Junction FET n-p-n Operational Amplifier, IEEE J. of Solid-State
Circuits, vol. SC-3, pp. 341-348, 1968.
[3]. Q. A. Khan, S. J. Wadhwa, and K. Misri, Low Power Startup Circuits for Voltage and Current
Reference With Zero Steady State Current, Proc. 2003 ISLPED Conf., pp. 184-188, Aug. 25-
27, 2003.
[4]. U. Gatti, F. Maloberti, and G. Torelli, A Novel CMOS Linear Transconductance Cell for
Continuous Time Filters, Proc. of the IEEE Int. Symp. on Circuits and Systems, pp. 1173-
1176, May 1990.
[5]. E. Sckinger and W. Guggenbhl, A High-Swing, High-Impedance MOS Cascode Circuit,
IEEE J. of Solid-State Circuits, vol. 25, pp. 289-298, Feb. 1990.

EXERCI SES
PROBLEM #5.1
The divider circuit in Figure (5.1a) is modified to the configuration depicted in Figure (P5.1) in
which the bulk terminal of transistor M2 is grounded, as opposed to being returned to the source ter-
minal of the device. Consequently, the observed threshold voltage, V
h2
of M2 differs from the thre-
shold voltage, V
h1
, which is indigenous to transistor M1.
(a). If W
1
/L
1
= k
12
2
(W
2
/L
2
), derive an expression for output voltage V
ref
as a function of the supply
voltage, V
dd
, and the threshold voltages, V
h1
and V
h2
.

- 479 -
(b). Use the relevant parameters in Table (4.1) to deduce the threshold voltage difference, (V
h1

V
h2
), at room temperature, where the intrinsic carrier concentration can be taken as n
i
= 10
10

atoms/cm
3
. Assume a reference output voltage, V
ref
, of 1.25 volts.

Figure (P5.1)
PROBLEM #5.2
Design the circuit in Figure (P5.1) to deliver V
ref
= 1.50 volts when V
dd
= 3 volts. The static power
dissipated by the circuit is to be no more than 2 mW. Use the HSPICE parameters in Table (4.1) to
submit a simulation that displays how voltage V
ref
varies with supply voltage V
dd
to confirm the pro-
priety of the design.
PROBLEM #5.3
Use the HSPICE parameters in Table (4.1) to submit a simulation of the circuit designed in the
preceding exercise. The simulation must display how voltage V
ref
varies with operating temperature
when V
dd
= 3 V. Consider temperatures of 0 C, 27 C, 50 C, 75 C, 100 C, and 125 C.
PROBLEM #5.4
In the network of Figure (P5.4), which is a slightly modified form of the NMOS current mirror
shown in Figure (5.3a), the steady state values of V
dd
and V
kk
are V
dd
= 3.5 volts and V
kk
= 1.75 volts.
Corresponding to these voltages, the steady state values of I
ref
and I
k
are I
ref
= 100 A and I
k
= 1.0
mA. For the HSPICE or alternative SPICE simulations requested below, use the NMOS parameters
itemized in Table (4.1) to model the transistors. In these simulations, set the drawn channel lengths
of transistors M1 and M2 to L = 1.5 M, and pick the gate widths of the two transistors to assure
proper operation of the mirror in the steady state. The resistance, R
r
, associated with current source
I
ref
is R
r
= 55 K, while capacitance C
r
is 30 fF. Once you have chosen the gate widths of both
transistors, make sure that you appropriately set the area and periphery parameters, A
s
, A
d
, P
s
, and P
d

so that a proper account is made of high frequency effects in the transistors.

Figure (P5.4)
(a). Simulate a static sweep of the current, I
k
, versus voltage V
dd
, for 0 V
dd
5 volts.
i. Over what range of V
dd
is current I
k
held fast to within 10%?
ii. How does this output current sensitivity to V
dd
compare with the pertinent disclosures in
Example #5.2?
(b). Simulate the small signal frequency response of the magnitude of the driving point output
M2
M1
V
ref
+V
dd
I
d
M2
x k
21
+V
kk
I
k
M1
+V
dd
I
ref
V
ref
I
d1
Z
out
R
r
C
r

- 480 -
impedance, Z
out
, making sure to maintain the quiescent operating point in the course of execut-
ing this simulation.
i. What is the significance of the low frequency value of Z
out
?
ii. Does capacitance C
r
dominantly affect the magnitude response of Z
out
, especially at signal
frequencies for which the magnitude of the output impedance degrades from its low fre-
quency value by a factor of the square root of two?
(c). Repeat both parts of Part (a), but now, execute a static output current sweep with respect to vol-
tage V
kk
for 0 V
kk
3 volts. How does the static output current sensitivity to V
kk
relate to the
low frequency output impedance?
(d). Simulate the frequency responses of the real and imaginary components of the driving point
output admittance, Y
out
= 1/Z
out
.
i. What engineering significance can be attached to the low frequency value of the inverse of
the real part of impedance Z
out
?
ii. Plot the simulated output capacitance as a function of signal frequency.
iii. What engineering significance can be attached to the low frequency value of the output
capacitance?
PROBLEM #5.5
In an attempt to highlight MOSFET temperature issues, consider a p-channel MOSFET having a do-
nor impurity concentration in the substrate of N
sub
= 10
14
atoms/cm
3
. At a reference temperature of
T
o
= 27 C, the PMOS transistor, which is biased for a drain current of I
d
= 500 A, delivers
p
=
850 mhos/volt, and a threshold voltage of V
hp
= 650 mV. Assume a reference temperature intrinsic
carrier concentration of 10
10
atoms/cm
3
. Determine the requisite source-gate voltage, V
sg
, such that
the room temperature, 500 A of drain current, is sustained at an elevated operating temperature of
100 C.
PROBLEM #5.6
Derive expressions for the Thvenin resistances, R
t1
, and R
t3
, introduced in the small signal, cascode
mirror models shown in Figure (5.11). The cascode mirror itself appears in Figure (5.10). In the
course of deriving these relationships, neglect neither CLM nor BITM. However, finalize your
resistance conclusions by invoking justifiable approximations with respect to the transistor model
parameters.
PROBLEM #5.7
In the network of Figure (P5.7), which is a slightly modified form of the cascode current mirror
shown in Figure (5.10), the steady state value of V
dd
is V
dd
= 3.5 volts. In concert with this power
line voltage and a value of voltage V
kk
that is 10% larger than its minimum required value, the steady
state values of I
ref
and I
k
are I
ref
= 100 A and I
k
= 1.0 mA. For the HSPICE or alternative SPICE
simulations requested below, use the NMOS parameters itemized in Table (4.1) to model the transis-
tors. In these simulations, set the drawn channel lengths of transistors M1 and M2 to L = 1.5 m,
and pick the gate widths of the transistors to assure proper operation of the mirror in the steady state.
The resistance, R
r
, associated with current source I
ref
is R
r
= 80 K, while capacitance C
r
, which is
also associated with this reference source, is C
r
= 25 fF. Once you have chosen the gate widths of
both transistors, make sure that you appropriately set the area and periphery parameters, A
s
, A
d
, P
s
,
and P
d
so that a realistic account is made of high frequency effects in the transistors. As mentioned
at the beginning of this chapter, bulk connections, while not explicitly depicted in the schematic dia-
gram of Figure (P5.7), are presumed connected to ground potential.
(a). Simulate a static sweep of the current, I
k
, versus voltage V
dd
, for 0 V
dd
5 volts. Over what
range of V
dd
is current I
k
held fast to within 10%?
(b). Simulate the small signal frequency response of the magnitude of the driving point output
impedance, Z
out
, making sure to maintain the quiescent operating point in the course of execut-
ing this simulation.
i. What is the significance of the low frequency value of Z
out
?

- 481 -
ii. Does capacitance C
r
dominantly affect the magnitude response of Z
out
, especially at signal
frequencies for which the magnitude of the output impedance degrades from its low fre-
quency value by a factor of the square root of two?

Figure (P5.7)
(c). Repeat Part (a), but now, execute a static output current sweep with respect to voltage V
kk
for 0
V
kk
3 volts. How does the static output current sensitivity to V
kk
relate to the low frequency
output impedance?
(d). Simulate the frequency responses of the real and imaginary components of the driving point
output admittance, Y
out
= 1/Z
out
.
i. What engineering significance can be attached to the low frequency value of the inverse of
the real part of impedance Z
out
?
ii. Plot the simulated output capacitance as a function of signal frequency.
iii. What engineering significance can be attached to the low frequency value of the output
capacitance?
PROBLEM #5.8
For the modified Wilson current sink shown in Figure (P5.8), use the low frequency, small signal
equivalent circuit of a MOSFET to derive an expression for the indicated resistance, R
in
, established
between circuit ground and the drain/gate node of transistor M1. In this equivalent circuit, ignore
body effect but account for channel resistance, as required. Comment as to the effect exerted on this
nodal resistance by the ratio, k, of gate aspect ratios. Bulk connections are presumably made to net-
work ground.

Figure (P5.8)
PROBLEM #5.9
In some current mirrors, such as the modified Wilson sink given in Figure (P5.8), the reference cur-
M4
M2
+V
dd
I
ref
+V
kk
I
k
R
out
M3
M1
x 1 x k
x 1 x k
R
r
C
r
M4
M2
+V
dd
+V
kk
I
k
R
out
R
in
M3
M1
x 1 x k
x 1 x k
R
r

- 482 -
rent, I
ref
, is realized on chip with an active circuit. In this case, I
ref
derives as the drain current of
PMOS transistor M5. In the simulations requested below, use the HSPICE transistor model parame-
ters itemized in Tables (4.1) and (4.2). In these simulations, let the channel lengths of all transistors
be 1.5 M. The gate widths of transistors M1, M3, and M5 are 5 M. For steady state operation, V
dd

kk
= 2.7 volts.

Figure (P5.9)
(a). Using HSPICE or equivalent simulation software, adjust voltage V
bias
to obtain I
ref
= 100 A.
With I
ref
= 100 A, output current I
k
should nominally equal 1 mA.
(b). Simulate the static transfer characteristic of I
k
-versus- voltage V
kk
for 0 V
kk
4 volts. Discuss
the results in light of the work executed in Example #5.3.
(c). Simulate the static transfer characteristic of I
k
-versus- voltage V
dd
for 0 V
dd
5 volts. How
might the M5 subcircuit be modified to improve this static transfer characteristic?
PROBLEM #5.10
In the simplified Wilson current sink of Figure (P5.10), reference current I
ref
derives as the drain cur-
rent of PMOS transistor M5. In the simulations requested below, use the HSPICE transistor model
parameters itemized in Tables (4.1) and (4.2). In these simulations, let the channel lengths of all
transistors be 1.5 M. The gate widths of transistors M3 and M5 are 5 M. For steady state
operation, V
dd
kk
= 2.7 volts.

Figure (P5.10)
(a). Using HSPICE or equivalent simulation software, adjust voltage V
bias
to obtain I
ref
= 100 A.
With I
ref
= 100 A, output current I
k
should nominally equal 1 mA.
(b). Simulate the static transfer characteristic of I
k
-versus- voltage V
kk
for 0 V
kk
4 volts. Discuss
the results in light of the work executed in Example #5.3.
(c). Use the low frequency, small signal model to deduce an expression for the indicated output
resistance, R
out
. Ignore body effect in all transistors and ignore channel length modulation
M4
M2
+V
dd
+V
kk
I
k
I
ref
R
out
M3
M1
M5
x 1 x k
x 1 x k
V
bias
M4
M2
+V
dd
+V
kk
I
k
I
ref
R
out
M3
M5
x 1 x k
x k
V
bias
R
in

- 483 -
whenever it is appropriate to do so. What effect does the M5 channel resistance, r
o5
, have on
R
out
?
(d). Use the low frequency, small signal model to deduce an expression for the indicated input
resistance, R
in
. Ignore body effect in all transistors and ignore channel length modulation
whenever it is appropriate to do so. What effect does the M5 channel resistance, r
o5
, have on
R
in
?
PROBLEM #5.11
In the circuit of Figure (5.22), let Input #1 and Input #2 be driven by the same small signal voltage,
say V
cs
. Assume that in response to this applied input voltage, current I
d3
remains unchanged.
(a). Explain clearly why the voltage responses at Output #1 and Output #2 are zero when current I
d3

remains unaffected by the applied input signals.
(b). If current I
d3
is indeed unchanged when voltage V
cs
are applied to both input ports of the am-
plifier, what is the resultant change in voltage V
kk
. Do not execute a definitive small signal
analysis to answer this query. Rather, submit your answer in the form of valid, qualitative
engineering arguments.
PROBLEM #5.12
In the degenerated current sink of Figure (P5.12), the gate aspect ratios of transistors M1, M2, M3,
and M4 are such that
3 4 1 2
31 31 31
3 1 2 4
W W W W
k k k .
L L L L
= = =
All transistors show negligible bulk-induced threshold modulation, while CLM can be ignored in all
devices, except transistor M3.

Figure (P5.12)
(a). If current I
k
is to be determined as I
k
= k
31
I
p
, how must the gate aspect ratio of transistor M5 be
selected?
(b). Why is it appropriate to neglect channel length modulation in transistors M1, M2, M4, and M5,
but not in transistor M3?
(c). Which transistors experience bulk-induced threshold voltage modulation? For each of these
transistors, what is the static bulk-source voltage?
(d). Determine analytical expressions for resistance R
p
and capacitance C
p
. The capacitance is to
behave nominally as a short circuit for frequencies exceeding the value, f
l
.
(e). Derive an analytical expression for the indicated output resistance, R
out
. Discuss the effect that
transistor M5 has on this output resistance.

M3
+V
kk
I
k
W /L
3 3
R
out
R
p
M1
M4 M5
V
ref
W /L
1 1
W /L
4 4
W /L
5 5
C
p
M2
+V
dd
I
p
W /L
2 2

- 484 -
PROBLEM #5.13
In the balanced, folded cascode, differential amplifier of Figure (P5.13), all transistors operate in
their saturation domains and project negligible mobility degradation, negligible CLM, and negligible
threshold voltage body effect. All NMOS transistors are matched, inclusive of their gate aspect ra-
tios, while the PMOS devices, M3, M4, M5, and M6 are likewise matched, inclusive of their respec-
tive gate aspect ratios. Moreover, while transistor M11 is a chip device that is similar to matched
transistors M3 and M4, the gate aspect ratios of M3 and M4 (and, of course, M5 and M6) are k
p
-times
larger than that of M11. Finally, the indicated tail current, I
k
, is sufficiently large to render
inconsequential any I/O nonlinearities that may be incurred by reasonable amplitudes of the applied
differential input signal, V
di
. What is the quiescent drain current conducted by transistors M5 and
M6? Express your answer in terms of currents I
k
, I
bias
, and k
p
.

Figure (P5.13)
PROBLEM #5.14

Figure (P5.14))
The amplifier in the high impedance current sink of Figure (P5.14) is ideal in the senses of having
infinitely large input resistances at both of its input ports, zero output resistance at its output port,
M1 M10
M7
M8
M2 M9
I
k
I
bias
M3
M4 M11
+V
dd
+
V
gg

V
di
2
V
di
2
M5 M6
V
bias1
V
bias2
C
L
V
o
x 1 x k
p
x k
p
x k
p
x k
p
+
M3
M2 M1
x K
x K x 1
A

V
B

I
i
I
o
V
x
R
out

- 485 -
and constant, finite, positive voltage gain, A. All NMOS devices are identical except for the fact
that the gate aspect ratios of transistors M2 and M3 are each larger than the gate aspect ratio of M1
by a factor of K. The traditional square law relationship, I
d
= |
n
(V
gs
V
h
)
2
, applies to all transistors,
with the understanding that parameter
n
is directly proportional to gate aspect ratio. Observe that
the drain of transistor M3 is connected to a node that supports a quiescent voltage of V
x
. Finally,
current I
i
is a constant and derives from an ideal, constant current source. The applied voltage, V
B
,
likewise derives from a constant source of voltage.
(a). In terms of current I
i
, device threshold voltage, V
h
, and device parameter
n
, determine the M3
gate-source voltage, V
gs3
, which supports the indicated output current, I
o
.
(b). In terms of I
i
, V
h
,
n
, and amplifier gain A, what minimum value of voltage V
B
is required to en-
sure that transistor M2 operates in saturation?
(c). Assuming voltage V
B
satisfies the constraint imposed in Part (b), what minimum value of vol-
tage V
x
is required to assure saturation of transistor M3? Express this minimum voltage in
terms of I
i
, and
n
.
(d). Use small signal analysis to find the indicated low frequency output resistance, R
out
, in terms of
amplifier gain A and the forward transconductances and channel resistances of pertinent transis-
tors
PROBLEM #5.15
In the majority of portable electronic networks, it is desirable to render the static current, I
load
, sup-
plied to an arbitrary load as independent as possible of the power supply voltage, say V
dd
. It is also
advantageous to have this static current nominally independent of the effective load resistance, R
load
,
through which it flows. To these ends, the biasing circuit shown in Figure (P5.15) can achieve
supply-independent biasing and load-independent biasing if voltage V
dd
is large enough to ensure the
saturation regime operation of all transistors in the diagram. In the indicated schematic diagram, the
bulk terminals of the two NMOS transistors are incident with circuit ground, while the bulk termin-
als of the three PMOS transistors are returned to the +V
dd
supply line. All NMOS transistors are
identical, as are all PMOS devices, subject to the following gate aspect ratio provisos.
(1). The gate aspect ratio of transistor M4 is W
4
/L
4
= 20.
(2). The gate aspect ratio of M5 is W
5
/L
5
=
2
(W
4
/L
4
) = 20
2
.
(3). The gate aspect ratios of both M1 and M2 are 5; that is, W
1
/L
1
= W
2
/L
2
= 5.
(4). The gate aspect ratio of M3 is W
3
/L
3
= 10(W
1
/L
1
) = 10(W
2
/L
2
) = 50.

Figure (P5.15)
(a). Derive an expression for the indicated biasing current, I
load
, by using the simple Schichman-
Hodges, square law model of a MOSFET. Reduce this expression for the case of a large resis-
M2
M3 M1
M5
R R
k
R
m
I
Q5
M4
I
Q4
I
load
+V
dd

- 486 -
tance, R
m
. In particular, ignore the effects of CLM, BITM, mobility degradation incurred by
both vertical and lateral channel electric fields, and all other higher order phenomena. The re-
sult requested should be expressed exclusively in terms of n-channel transistor parameter K
n
,
geometry factor , and circuit resistance R.
(b). What purpose is served by resistance R
m
?
(c). Aside from producing a small load current, I
load
, an excessively large resistance value, R, breeds
at least one other detriment to acceptable circuit operation. What is this shortfall?
(d). What undesirable operating condition arises from too large a value of the effective load resis-
tance, R
k
?
PROBLEM #5.16
The biasing circuit in Problem #P5.15 is to be designed to deliver I
load
= 125 A when V
dd
= 2.5
volts. All transistors boast 0.5 M channel lengths, and their SPICE Level 3 model parameters ap-
pear in Tables (4.1) and (4.2). Remember that for all simulations, the capacitance area and peri-
phery parameters, A
s
, A
d
, P
s
, and P
d
, must be specified to reflect the adopted gate aspect ratio of each
transistor.
(a). Design the circuit by specifying all transistor gate aspect ratios and all resistance values. Be
aware that there is no unique answer. There are only reasonable design answers, based on the
simulations you must execute.
(b). Simulate the static transfer characteristic, I
load
versus V
dd
, for 0 V
dd
5 volts. What is the
minimum required value of supply voltage V
dd
, which is commensurate with a load current that
is at least 90% of its design target? How might this minimum voltage be reduced? Comment
as to the sensitivity of I
load
with respect to V
dd
and offer suggestions as to how this sensitivity
can be improved.
(c). Simulate the transient drain current responses of all transistors for the case when V
dd
is a 2.5
volt step activated at time t = 0. What, if any, transistors are candidates for potentially cata-
strophic current overstress?
PROBLEM #5.17
Using the simple square law volt-ampere model of a MOSFET (no CLM, no mobility degradation,
no BITM, no second order effects in general), derive an expression for the indicated current, I
load
, in
the biasing network of Figure (P5.17). The two PMOS devices have identical gate aspect ratios but
otherwise, do not presume that all transistors, which are fabricated on the same chip, have identical
gate aspect ratios. All transistors operate in their saturation regimes.

Figure (P5.17)
PROBLEM #5.18
The subcircuit formed of transistors M1, M2, M3, and M4 in Figure (P5.18) is the self-biasing
configuration addressed Section (5.5.1). Recall that this network suffers from a potential startup
problem, wherein it is possible that the subcircuit gives the useless steady state response I
Q1
= I
Q2
=
M2 M1
M4 M3
R
+V
dd
I
load

- 487 -
0. In an attempt to mitigate this possible shortfall, the second subcircuit comprised of transistors M5
and M6, resistances R
1
and R
2
, and capacitance C is appended as depicted in the schematic diagram.
The gate aspect ratios of M1 and M2 are identical, while the gate aspect ratio of M4 is k
2
-times larger
than that of M3.

Figure (P5.18)
(a). Explain the operation of startup subcircuit immediately subsequent to closing switch SW at time
t = 0, which is tantamount to turning on the biasing circuit.
(b). Derive the design-oriented constraint that ensures the M5-M6-R
1
-R
2
compensation subcircuit is
nominally non-conductive in the steady state. Why is it desirable to have this network non-
conductive in the steady state? Use the simple Schichman-Hodges model for the transistors.
PROBLEM #5.19
The current, I
ref
, in the self-biased cascode of Figure (P5.19) is the current of an ideal, constant cur-
rent sink. In what range of values must the voltage, RI
ref
, dropped across resistance R lie to ensure
that transistors M1 and M2 are biased in their saturation domains? Use the simple square law model
of the volt-ampere characteristic of a MOSFET. The gate aspect ratios of the two active devices are
not necessarily the same.

Figure (P5.19)

M4 M3 M5
M6
R
R
1
R
2
M2 M1
I
Q1
I
Q2
C
S
W
+V
dd
M2
M1
R
I
ref
+V
dd

- 488 -
PROBLEM #5.20
In the supply independent biasing network of Figure (5.37), derive an expression for the smallest
allowable value, say V
min
, of voltage V
dd
that guarantees the operation of all MOSFETs in the consi-
dered network in their respective saturation domains. Express this minimum voltage in terms of cir-
cuit and device parameters and current I
Q
.
PROBLEM #5.21
Figure (5.40) depicts a plausible startup module for the supply-independent network offered in Fig-
ure (5.37). An alternative and simpler startup scenario utilizes a single resistance, say R
p
, between
ground, and the gate of transistor M7, as shown in Figure (P5.21). Unlike the startup subcircuit pro-
posed in Figure (5.33), the resistance approach proposed herewith dissipates steady state power.
However, the power increment incurred by deploying R
p
can be kept to a minimum by selecting
resistance R
p
suitably large. Demonstrate analytically that a null current state is impossible in the
configuration of Figure (P5.21).

Figure (P5.21)
PROBLEM #5.22
The transistor in the subcircuit shown in Figure (P5.22) is to operate in its saturation domain. Body
effect can be ignored tacitly, but due account should be made of channel length modulation pheno-
mena.

Figure (P5.22)
(a). Deduce the quiescent design criterion that ensures transistor M6 operates in its saturation do-
main.
(b). Derive an expression for the indicated small signal resistance, R
dd.

M3 M5 M4
M2 M1
V
dd
I
Q
I
Q
I
o
x 1 x k
21
2
x 1 x 1
x k
p
R
R
p
R
l
M
R
1
R
2
+V
dd
R
dd
I
Q

- 489 -
PROBLEM #5.23
Return to Example #5.5 and use HSPICE or equivalent computer-aided analysis software to examine
the transient response of current I
k
to step excitation of voltage V
kk
in both the uncompensated and
compensated versions of the current sink. In particular, let V
kk
be a zero to 3.5 volt pulse waveform
having 1 nSEC rise and fall times, a 2 SEC pulse width, and a period of 5 SEC. Execute the
simulation for at least three time periods. Examine and assess both responses from the standpoints
of steady state performance, the time required to settle to steady state operation, overshoots and
undershoots, and general stability considerations.
PROBLEM #5.24
In the current sink of Figure (P5.24), all transistors are biased in saturation, have negligible CLM
and BITM, and all project negligible mobility degradation; in short, the static volt-ampere
characteristics of all transistors subscribe to the classic, long channel, Schichman-Hodges relation-
ship. All transistors are fabricated on the same chip. But while transistors M1 and M2 have iden-
tical gate aspect ratios, transistors M3 and M4, respectively, have gate aspect ratios that are k-times
larger than the gate aspect ratios of the other two devices. In the design process, resistance R is cho-
sen, and independent current source I
ref
is adjusted, to ensure that the drain-source voltage, V
ds1
, of
transistor M1 is its idealized drain saturation value, V
dsat
= (V
gs1
V
hn
), where V
hn
represents the
threshold potential of the NMOS transistors. Finally, capacitance C is large enough to emulate a
short circuit for all relevant nonzero frequencies.

Figure (P5.24)
(a). Determine the following static voltages:
i. the voltage, expressed in terms of current I
ref
, device transconductance metric
n1
, and thre-
shold potential V
hn
, to which capacitor C charges in the steady state;
ii. the voltage, expressed in terms of current I
ref
and device transconductance metric
n1
, devel-
oped across resistance R;
iii. in terms of current I
ref
and device transconductance metric
n1
, the minimum required value
of voltage V
o
that ensures operation of transistors M3 and M4 in saturation;
(b). Determine the requisite value of resistance R in terms of reference current I
ref
and transconduc-
tance parameter,
n
.
(c). Derive an expression for the indicated small signal output resistance, R
out
. In the course of
addressing this problem, do not ignore channel resistances in transistors M3 and M4.
(d). Determine the approximate time constant associated with capacitance C. In this calculation,
channel resistances in all active devices can be ignored tacitly.
PROBLEM #5.25
In the biasing network shown in Figure (P5.25a), all MOSFETs operate in their saturation regimes
where they boast negligible body effect, negligible mobility degradation, and negligible CLM.
M4
M3
M1
M4 M2
R
I
ref
V
dd
I
o
V
o
R
out
C
x k
x k
x 1
x 1

- 490 -
Transistors M1 and M2 are identical pairs, inclusive of gate aspect ratios, as are transistors M3 and
M4, as indicated in the diagram. Transistor M5 is matched to M4, but has a gate aspect ratio that is
bigger than that of either M3 or M4 by a factor of P. The bipolar junction transistors, Q1, Q2, and
Q3, are matched devices, with the proviso that while Q1 and Q3 have identical emitter-base junction
injection areas, the emitter-base junction area of Q2 is a factor of M larger than the junction area of
either Q1 or Q3. With reference to Figure (P5.25b), the static volt-ampere characteristics of each
PNP bipolar junction transistor is given by
eb T
V V
e c j s
I I A J , e ~ ~
where for large static beta, the emitter current, I
e
, approximates the collector current, I
c
. Moreover,
A
j
represents the emitter-base junction injection area, J
s
is the density of bipolar saturation current,
V
eb
is the static voltage applied from the emitter to the base, and V
T
is the familiar Boltzmann vol-
tage.

Figure (P5.25)
(a). In terms of appropriate circuit resistances, Boltzmann voltage V
T
, and parameters P and M, de-
velop an expression for the reference current, I
ref
.
(b). Assume that the temperature coefficient, dV
eb
/dT, of the emitter-base voltages of the bipolar
junction transistors is the constant, (S
e
). How must the resistance ratio, R
2
/R
1
, be chosen if the
reference output voltage, V
ref
, is to boast zero temperature coefficient? Assume that resistance
ratio R
2
/R
1
is independent of operating temperature.
(c). Respond clearly and briefly to the following queries.
i. What makes voltage V
ref
substantially independent of power line voltage V
dd
?
ii. What makes an idealized zero temperature coefficient to V
ref
possible in this problem?
iii. What fundamental purpose is served by capacitance C?
iv. Is the low frequency output resistance, R
out
, large or small? Explain briefly!
PROBLEM #5.26
Convert the regulated cascode current sink of Figure (5.41) into a regulated cascode current source.
Submit a circuit diagram of the current source.
PROBLEM #5.27
In the network shown in Figure (P5.27), all transistors operate in saturation and show negligible
body effect. The NMOS transistors, M1 and M2, are identical and have identical gate aspect ratios,
while for the physically similar PMOS devices, the gate aspect ratio of transistor M3 is k-times that
of transistor M4. The currents, I
kk
and I
ss
derive from ideal, constant current sinks.
M2 M1
M4
M3
+V
dd
Q1 Q2 Q3
M5
R
1
R
2
V
ref
R
out
C
A
j
MA
j
A
j
W /L
1 1
W /L
1 1
W /L
3 1
W /L
3 1
PW /L
3 1
(a).
Q
A
j
I
e
I
ref
I
c
+
V
eb
(b).

- 491 -
(a). In terms of relevant circuit and/or transistor parameters, determine the quiescent values of the
currents, I
1
, I
2
, I
3
, and I
o
.
(b). Derive an expression for the indicated output resistance, R
out
. Ignore channel length modulation
only if you can justify its tacit neglect.

Figure (P5.27)
PROBLEM #5.28
The NMOS transistor in the common source amplifier of Figure (P5.28) has a gate aspect ratio, W/L,
of 10, a threshold voltage, V
hn
, of 1 volt, and a channel length modulation voltage, V
, of 45 volts.
Approximate the bulk-induced threshold modulation voltage, V
, as 0 volts. Also, measurements

taken in the laboratory show that for a gate-source voltage, V
gs
, of 1.5 V and a drain-source voltage,
V
ds
, of 400 mV, the static drain current conducted by the transistor is I
d
= 60 A. The indicated load
resistance, R
l
, is 10 K, while the source resistance, R
s
, is 300 .

Figure (P5.28)
(a). Compute the values of resistance R
d
and bias voltage V
bias
so that the transistor conducts a static
drain current, I
d
, of 500 A when the static value of the output voltage, V
o
, is 0 V. Be advised
that when computing the requisite bias voltage, V
bias
, an acceptable first order approximation is
the tacit neglect of CLM phenomena.
(b). What is the error incurred in static drain current as a result of the neglect of channel length
M1 M2
M4
I
kk
I
ss
M3
x 1 x k

V
gg

R
l
I
o
I
2
I
3
I
1
+V
dd
R
out
+
V
bias

R
d
R
l
R
s
2.5 V
2.5 V
I
d
V
o
V
s
R
out

- 492 -
modulation?
[Assume that the approximate operating point corresponding to the computed input bias vol-
tage prevails for the remaining parts of this question.]
(c). Give a general expression for, and compute the value of, the small signal Thvenin output port
resistance, R
out
.
(d). Give a general expression for, and compute the value of, the small signal low frequency
transconductance, G
m
, which is recalled to be the ratio of the Norton load current to the signal
source voltage.
PROBLEM #5.29
In the PMOS common source amplifier of Figure (P5.29), the transistor has a gate aspect ratio, W/L,
of 20 M/3 M, a threshold voltage, V
hn
, of 700 mV, and a channel length modulation voltage, V
,
which can be taken to be infinitely large. Assume that the bulk-induced threshold modulation vol-
tage, V
, is 0 volts. Also, measurements taken in the laboratory confirm that K

p
=
p
C
ox
= 30 A/V
2
.
The indicated load resistance, R
l
, is 10 K, while the source resistance, R
s
, is 300 .

Figure (P5.29)
(a). Compute the values of resistance R
d
and bias voltage V
bias
so that the transistor conducts a static
drain current, I
d
, of 500 A when the static value of the output voltage, V
o
, is 0 V.
[Assume that the approximate operating point corresponding to the computed input bias voltage
prevails for the following remaining parts of this question.]
(b). Give a general expression for, and compute the value of, the small signal Thvenin output port
resistance, R
out
.
(c). Give a general expression for, and compute the value of, the small signal low frequency Norton
transconductance, G
m
.
PROBLEM #5.30
In the CMOS common source amplifier of Figure (P5.30), the p-channel device, transistor M2, has
a gate aspect ratio, W/L, of 20 M/3 M, a threshold voltage, V
hn
, of 700 mV, and a CLM voltage,
V
, that can be presumed infinitely large. Assume further that its BITM voltage, V
, is 0 volts.
Measurements taken in the laboratory confirm that K
p
=
p
C
ox
= 30 mho/volt. On the other hand,
M1 is an NMOS device having a gate aspect ratio, W/L, of 10, a threshold voltage, V
hn
, of 1 volt,
and a CLM voltage, V
, of 45 volts. Assume that its BITM voltage, V
, is 0 volts. For this transis-

tor, a gate-source voltage, V
gs
, of 1.5 V and a drain-source voltage, V
ds
, of 400 mV, delivers a static
drain current of I
d
= 60 A. The indicated load resistance, R
l
, is 5 K, while the source resistance,
R
s
, is 300 .
(a). Compute the values of the biasing voltages, V
bias2
and V
bias1
, so that the transistors conduct static
drain currents of I
d2
= I
d1
= 100 A when the static value of output voltage V
o
is 0 V.
[Assume that the approximate operating point corresponding to the computed input bias voltage
+
V
bias

R
d
R
l
R
s
2.5 V
2.5 V
I
d
V
o
V
s
R
out

- 493 -
prevails for the following remaining parts of this question.]
(b). Give a general expression for, and compute the value of, the small signal Thvenin output port
resistance, R
out
.

Figure (P5.30)
(c). Give a general expression for, and compute the value of, the small signal low frequency Norton
transconductance, G
m
.
PROBLEM #5.31
The biasing task underlying the design of even relatively simple CMOS amplifiers can rarely be
accomplished by inspection. Moreover, the biasing requirements can rarely be cast in convenient
closed mathematical forms. A case in point is the amplifier depicted in Figure (P5.31). The PMOS
transistor in this configuration has K
p
= 90 mho/volt, W
p
/L
p
= 100, V
hp
= 800 mV, V
= 0, and V

. On the other hand, the NMOS device is characterized by K
n
= 150 mho/volt, W
n
/L
n
= 10, V
hp
=
700 mV, V
= 0, and V
. The supply line voltage, V

dd
, is 3.3 volts, the source resistance, R
s
, is
50 , and the load resistance, R
l
, is 1 K. The design objective is to select the biasing voltages, V
bias

and V
gg
, such that both transistors operate in their respective saturation regions when the output vol-
tage, V
o
, swings from its minimum allowable value to its maximum possible value.

Figure (P5.31)
(a). Convince yourself that the maximum possible value of the output voltage, V
o
, is realized when
+
V
bias2

V
bias1

R
l
R
s
2.5 V
2.5 V
I
d1
V
o
V
s
R
out
M1
M2
I
d2
+
V
gg

V
bias

R
l
R
s
V
dd
I
d1
V
o
V
s
M1
M2
I
d2

- 494 -
transistor M1 is cutoff. Under this cutoff condition, evaluate
i. the current, I
d2
, conducted by transistor M2;
ii. the numerical value of the maximum output voltage, say V
omax
;
iii. the numerical value of the biasing voltage, V
bias
, required to sustain the current, I
d2
;
iv. the anticipated change in current I
d2
if V
o
is allowed to fall below its maximum value.
(b). What is the required value of the biasing voltage, V
gg
, commensurate with minimum output vol-
tage and saturation operation of both transistors? What current is conducted by the load and
transistor M1 under this minimum output voltage condition?
(c). Subject to the foregoing saturation constraints, determine the maximum possible, peak to peak
swings in
i. the current, I
d2
ii. the current, I
d1
iii. the output voltage, V
o
;
iv. the net effective input voltage, (V
gg
+ V
s
).
(d). What value of V
gg
would you pick to ensure saturation region operation of transistor M1, de-
spite the possibility of maximum output voltage swing?
PROBLEM #5.32
In the reference biasing circuit of Figure (P5.32), both transistors exhibit negligible CLM, negligible
carrier mobility degradation, and negligible body effect. Observe that the gate aspect ratio of
transistor M2 is larger than the gate aspect ratio of M1 by a factor of k
2
. The constant current, I
k
, can
be presumed to derive from an ideal current source.

Figure (P5.32)
(a). In terms of current I
k
, what condition must circuit resistance R satisfy to ensure that transistor
M2 operates in its saturation domain.
(b). Assuming that M2 indeed operates in saturation, determine, in terms of parameter k, the indi-
cated output resistance, R
out
.
(c). Assuming that parameter k is held as a fixed constant, give two design recommendations that
support low output resistance.
PROBLEM #5.33
The network in Figure (P5.33) is proposed as a biasing circuit that establishes a current sink current,
I
Q
, which is reasonably independent of the supply line voltage, V
dd
. In all transistors, CLM, mobility
degradation, BITM, and other high order modeling phenomena are ignored. This means that the
NMOS drain currents, I
d
, relate to their applied gate-source voltages V
gs
and threshold voltages, V
hn
,
trough the classic, square law, Schichman-Hodges expression. Observe in the schematic diagram
that while all NMOS and PMOS devices are respectively identical integrated circuit transistors, the
gate aspect ratio of transistor M5 is k-times larger than that of either transistors M1 or M2.
M2
M1
x k
2
x 1
R
+V
dd
I
k
V
ref
R
out

- 495 -
(a). In terms of resistance R, threshold voltage V
hn
, transconductance factor
n1
, and gate aspect
variable k, derive an expression for the indicated current, I
Q
.
(b). In terms of the same variables noted in the preceding part of this problem, what is the minimum
allowable value of static voltage V
x
?

Figure (P5.33)
(c). If channel length modulation is not ignored, what, in terms of relevant transistor parameters, is
the indicated output resistance, R
out
?
(d). The circuit at hand provides a sinking bias current, I
Q
; that is I
Q
is sunk through a transistor and
thence to ground from a circuit node that supports a suitable voltage, V
x
. Can transistor M5 and
its circuit connections be modified so the circuit sources the current I
Q
? By current sourcing
is meant a current injected to ground from an appropriately connected transistor.
(e). Is circuit boot up or start up a problem with the network at hand?
PROBLEM #5.34
In the self-biasing network of Figure (P5.34), the PMOS and NMOS transistors are respectively
identical, transistors M1, M2, and M3 have identical gate aspect ratios, and the gate aspect ratio of
transistor M4 is K
2
-times larger than the gate aspect ratio of M3. For static analysis purposes, CLM
can be ignored. All transistors operate in their saturation regimes.

Figure (P5.34)
(a). Derive an expression for the indicated quiescent output current, I
out
; express your result in terms
of resistance R
ss
, gate aspect ratio parameter K, and relevant transistor parameters.
(b). To the extent that all transistors operate in saturation, respond to the following queries as
clearly, but as briefly, as possible.
i. Is the static output current, I
out
, independent of supply voltage, V
dd
?
ii. Is the static output current, I
out
, independent of temperature?
M1
R
M5
M2
M4 M3
+V
dd
I
d1
I
d2
I
Q
+V
x
R
out
x1
x 1
xk
x1 x1
M4
R
ss
M3
W/L K W/L
2
+V
dd
M2 M1
W/L W/L
I
out
C

- 496 -
iii. Is the static output current, I
out
, independent of such processing parameters as gate width,
channel length, and gate oxide thickness?
(c). If CLM is not ignored, would static current I
out
remain independent of V
dd
? Briefly explain your
conclusion without re-solving the problem for current I
out
.
PROBLEM #5.35
One way of examining the first order effect of channel length modulation in the biasing structure of
Figure (P5.34) commences with allowing V
dd
to take on a small voltage change, say V
dd
. Then, a
solution is found for the small signal transconductance, G
dd
I
out
/V
dd
, where I
out
is understood to
be the change in output current that results from the presumed small change, V
dd
, in supply voltage
V
dd
.
(a). For the biasing network in Figure (P5.34), draw the small signal equivalent circuit pertinent to
an evaluation of the aforementioned transconductance, G
dd
. Neglect channel resistances in
transistors M1 and M4, but not in transistors M2 and M3. Assume that the change in power
supply voltage is caused by noise incurred at frequencies that are large enough to enable
capacitance C in the biasing structure to be represented by a signal short circuit.
i. Do not necessarily presume that corresponding small signal transistor parameters are iden-
tical. To this end, what is the relationship between the small signal transconductances, g
m1

and g
m2
, of transistors M1 and M2, respectively?
ii. What is the transconductance parameter interrelationship of transistors M3 and M4?
(b). Evaluate the transconductance, G
dd
, implied by the model deduced in Part (a).
(c). What channel resistance must be very large if V
dd
is to have negligible impact on current I
out
?
(d). Why is it reasonable to ignore the channel resistances of transistors M1 and M4?
(e). Recalling that we are interested in gauging the effect that voltage V
dd
has on output current I
out
,
why is it inappropriate to ignore the channel resistances in all transistors? Explain your conclu-
sion!
(f). Do we need to have small or large G
dd
if current I
out
is to be invulnerable to any electrical noise
incurred along the power supply bus?
PROBLEM #5.36
In the current mirror shown in Figure (P5.35a), all transistors are matched, inclusive of their gate as-
pect ratios, and all devices operate in their saturation domains. The bulk terminals of all transistors
are returned to ground and although these connections do not achieve zero bulk-source bias in all
transistors, BITM is ignored tacitly in all devices.

Figure (P5.36)
(a). Give an expression that relates the static output current, I
o
, to the applied static reference cur-
rent, I
ref
.
M4
M2
M3
M1
I
ref
+V
dd
R
out
I
o
(a).
M4
M2 M1
I
ref
+V
dd
I
o
(b).

- 497 -
(b). A colleague of yours argues that transistor M3 is superfluous and that the circuit shown in Fig-
ure (P5.36b) works just as well. You argue that because of your unimpeachable education, you
can see that while the alternative configuration is fundamentally functional, your original circuit
in Figure (P5.36a) provides superior current mirroring. What rationale in support of the excel-
lent current mirroring provided by your circuit did you provide to your depraved technical col-
league?
(c). Derive an expression for the output resistance, R
out
, in the current mirror in Figure (P5.36a).
Why is it reasonable to ignore channel resistance in transistors M2 and M3 but unreasonable to
invoke this approximation for transistors M1 and M4?
PROBLEM #5.37
In the low voltage, high resistance current sink diagrammed in Figure (P5.37) and studied in Section
(5.6.3), derive expressions for the indicated driving point resistances, R
g4
and R
d5
. Assume that all
current sources are ideal, constant currents, and ignore BITM throughout. Furthermore, assume all
MOSFETs operate in their respective saturation regimes. Ignore transistor channel resistances if and
only if you can clearly justify such neglect.

Figure (P5.37)
PROBLEM #5.38

Figure (P5.38)
The network shown in Figure (P5.38) is used to establish three static voltages, V
QA
, V
QB
, and V
QC
,
which can be used to bias other monolithic subcircuits that are not shown in the subject figure. Bias
M1
M3
M2
M6
I
Q2
I
Q1
I
in
V
kk
I
k
M5
M4
+V
dd
R
out
R
g4
x 1
x 1
x k
x k
x 1
x 1
V
ref
V
Q1
V
Q2
R
d5
M1
M3
M2
M4
x1
x k
p
x1
M6
M6
M5
M5
x k
n
x 9
x1
x1
x k
p
R
V
QB
V
QC
+V
dd
V
QA
V
B1
V
B2

- 498 -
sources V
B1
and V
B2
are constant voltages implemented by circuitry that is not shown in the diagram.
Assuming negligible CLM, BITM, and all other high order modeling phenomena, use the square
law, Schichman-Hodges model to analyze the circuit. Your analysis should minimally offer the
following results.
(a). A general expression for output voltage V
QA
.
(b). A general expression for output voltage V
QB
.
(c). A general expression for output voltage V
QC
.
(d). General expressions for the static voltages established at all circuit nodes. An implicit design
requirement is that all transistors operate in their respective saturation regimes.

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LECTURE SUPPLEMENT #5 . . .

, and thus, it is functionally related to the drawn channel

, which is achieved for long drawn channel lengths, current I

, which requires a suitably long drawn channel, likewise off-

, should be nominally the

Chapter 5 MOSFET Biasing

Chapter 5 MOSFET Biasing

, despite likely differences between their gate aspect ratios, W

Chapter 5 MOSFET Biasing

Chapter 5 MOSFET Biasing

Chapter 5 MOSFET Biasing

Chapter 5 MOSFET Biasing

Chapter 5 MOSFET Biasing

, as 0 volts. Also, measurements

, is 0 volts. Also, measurements taken in the laboratory confirm that K

, of 45 volts. Assume that its BITM voltage, V

, is 0 volts. For this transis-

. The supply line voltage, V

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