Computer Organization 10CS46

DEPT OF CSE,SJBIT Page 1

UNIT-I: BASIC STRUCTURE OF COMPUTERS
1. With a neat diagram explain different processor registers June 2010
2. Explain the important technological features and devices that characterized each
generation of computers Dec 2010
3. Discuss two ways in which byte addresses are assigned June 2011
4. Explain the different functional units of a computer with a neat block diagram
Dec 2011
5. Write the basic performance equation. explain the role of each of the parameters in
the equation on the performance of the computer. July 2012
6. With a neat diagram ,discuss the basic operational concepts of a computer
July 2013
7. List the different systems used to represent a signed number July 2013
8. Explain with necessary block diagram the basic functional unit of a computer.
Jan 2014
9. Explain in detail the generation of computers. Jan 2014
UNIT-II- MACHINE INSTRUCTIONS AND PROGRAMS CONTD.:
1. What is an addressing mode .Explain different generic addressing modes with an
example for each June 2010 /July 2013
2. Define subroutine. Explain subroutine linkage using a link register Dec 2010
3. Explain the shift and rotate operation with examples June 2011
4. What is the need for an addressing mode? Explain the following addressing modes
with examples: immediate, direct, indirect, index, relative Dec 2011 /July 2013
5. a)What is subroutine linkage?how are parameters passed to subroutines June 2012
b.What is stack frame? Explain
6. Discuss briefly encoding of machine instructions. July 2013
7. Big-Endian and Little-Endian assignment,explain with necessary figure. Jan 2014
8. List the name, assembler syntax and addressing functions for the dufferent addressing
modes. Jan 2014
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9. Explain logical and arithmetic shift instructions with an example. Jan 2014
UNIT-III- INPUT/OUTPUT ORGANIZATION
1. A. Explain the following (i) Interrupt concepts (ii) Interrupt hardware
B. Define exceptions. Explain two kinds of exceptions
C. What is the necessity of bus arbitration .Explain the different methods of bus
arbitration. July 2013
D. Define the following(i) cycle stealing (ii) burst mode June 2010
2. A. discuss the different schemes available to disable and enable the interrupts
B. how are simultaneous interrupt from more than one devices handled? July 2013
C. What does the term cycle stealing mean?
D. Write a short note on any 1 bus arbitration scheme.(10M)Dec 2010
3. A .define and explain briefly the following
i) Interrupt
ii) Vectored interrupt
iii) Interrupt nesting
B. Explain in with the help of a diagram the working of daisy chain with multiple
priority levels and multiple devices in each level June 2011
4. A. In modern computers, why interrupts are required ? Support your claim with suitable
example
B. In the interrupt mechanism, how the simultaneous arrivals of interrupts from various
(multiple) devices (I/O) are handled? July 2013
C. With neat sketches, Explain the various approaches to bus arbitration. Dec 2011
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5. A. Explain with a diagram, how interrupt request from several I/O devices can be
communicated to a processor through a single INTR line
B. How can the processor obtain the starting address of different interrupt service
routines usingvectored interrupts?
C. Why is bus arbitration required? Explain with block diagram bus arbitration using
daisy chain. June 2012
6.a) Draw the arrangement of a single bus structure and brief about memory mapped
I/O. Jan 2014
b) Explain i)interrupt enabling
ii)edge triggering with respect interrupts.
c) Draw the arrangements for bus arbitration using a daisy chain and explain in
brief.
UNIT-IV- INPUT/OUTPUT ORGANIZATION CONTD.
1. A. Explain the important functions input/output interface July 2013
B. With a neat block diagram explain a general 8-bit parallel interface circuit
C. Explain the following w.r.t. USB(i) USB architecture (ii) USB addressing (iii) USB
protocols June2010 / Jul y 2013
2. A.Draw and explain the block diagram of a typical serial interface. How does it
compare with a parallel interface?
B. explain the main phases involved in SCSI bus operation Dec2010
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3. A. in a computer system, PCI bus is used to connect devices to the processor (system
bus) bus. Consider a bus transactional which the processor reads four 32-bit words
from the memory. Explain the read operation on the PCI bus between memory and
processor .give signal and timing diagram
B. Draw the block diagram of universal bus(USB)structure connected to the host
computer Briefly explain all fields of packets that are used for communication between a
host and a device connected to an USB port.June2011 / Jul y 2013
4. A .With a neat sketch, explain the individual input and output interface circuits. Also
elicit their salient feature.
B. In a computer system why a PCI bus is used? With a neat sketch, explain how the read
operation is performed along with the role of IRDY#/TRDY# on the PCI bus (10)
Dec2011
5. A. Explain with a block diagram a general 8 bit parallel interface.
B. With the help of a data transfer signals explain how a real operation is performed
using PCI bus.
C. Explain briefly bus arbitration phase in SCSI bus. June 2012
6. a. Draw the hardware components needed for connecting a keyboard to a process and
explain in brief. Jan 2014
b. Explain the use of PCI bus in a computer system with necessary figure.
c. List the SCSI bus signals with their functionalities.
UNIT-V- MEMORY SYSTEM
1. A. with the block diagram, explain the operations of 16 megabit DRAM configured as
2Mx8 June 2010
B. Explain different mapping functions used in cache memory
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C. What do you mean by memory interleaving? Explain. June 2010
2. A. differentiate between SRAM and DRAM Dec 2010
B. Sketch and explain the internal organization of a 2Mx8 dynamic memory chip
C. Explain any 1 cache mapping function. Dec 2010
3. A. Define and explain the following
i) Memory access time ii) memory cycle time
iii) Random access memory(RAM) iv)static memory
B. Differentiate the static RAM (SRAM) and dynamic RAM (DRAM) giving four key
differences. State the primary usage of SRAM and DRAM in contemporary computer
systems June 2011
C. Define memory latency and bandwidth in case of burst operation that is used for
transferring a block of data to or from synchronous DRAM memory unit June 2011
4. A draw a diagram and explain the working of a 16-M bit DRAM chip configured as
2M x8 Also explain as to how it can be made to work in fast page mode Dec 2011
5. A. Draw the organization of a 1Kx1 memory cell and explain its working.
B. Explain the working of a single-transistor dynamic memory cell
C. Calculate the average access time experienced by a processor if a cache bit rate is
0.88,miss penalty is 0.015 milliseconds and cache access time is 10 microseconds.
June 2012
6. Explain any two cache mapping functions. July 2013
7. Explain the translation of virtual address to physical addresss July 2013
8. a. Draw for 1K*1 memory chip with neat figure. Jan 2014
b. Show with diagram the memory hierarchy with respect to speed,size and cost.
c. With figure explain about direct mapping cache memory.
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UNIT-VI: ARITHMETIC
1. A. what do you mean by address translation. Explain how TLB is used to implement
virtual memory
B. Mention four major functions of disk controller on disk drive side.
C. Explain how a 16-bit carry look ahead adder can be built from 4-bit adder
Dec 2009
2. A. Draw a block diagram and explain how a virtual address from the processor is
translated into a physical address in the main memory
B. write short notes on (i) optical technology used in CD systems (ii) RAID disk
arrays(8M)
C. Draw a figure to illustrate and explain a 16-bit carry look ahead adder using 4-bit
adder blocks. Show that the sum and carry are generated in 5 and 8 gate delays
respectively(6M) June 2010
3 .A. Explain a simple method of translating virtual address of a program into physical
address, with the help of a diagram July 2013
B. Explain structural organization of moving head magnetic hard disk, with multiple
surfaces for storage of data. Explain hw moving head assembly works for reading data
Dec 2010
C. Answer the following w.r.t. to magnetic disk, the secondary storage device(6M)
i) Seek time
ii) Latency
iii) Access timeJune 2011
4. Explain in detail the working principle of a magnetic hard diskDec 2011
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5. A. Show the organization of virtual memory address translation based in fixed-length
pages and explains its working.
B. How can performance and reality be improved using RAID technology?
C. Explain the design of a 4-bit carry-look a head adder.June 2012 /july 2013
6.a) Explain with figure the design of a 4-bit carry look adder. Jan 2014
b) With figure explain circuit arrangements for binary division.
c) IEEE standard for floating point numbers,explain.
UNIT-VII: BASIC PROCESSING UNIT
1 .A. Show the multiplication of (+13) and (-6) using multiplier bit pair recording
technique.
B. Differentiate between restoring and non restoring division July 2013
C. Explain the IEEE standard for floating point number representationJune2010
2. A. Draw the hardware implementation of Booths multiplication algorithm.June 2012
B. Trace the steps in the above implementation to multiply -5x-4
C. Illustrate the steps for non restoring division algorithm on the following data:
dividend=1011 divisor=0101 ?Dec 2010
3. A In carry look a head addition explain generating G
i
and propagating P
i
functions for
stage I with the help of Boolean expression for G
i
and P
B.Performance signed multiplication of numbers -12and -11 using both multiplication
algorithm represent the numbers in 5-bit including sign bit .Give booth multiplier
recording table that is used in the above multiplication
C. Perform division of numbers 8 by 3 using non-restoring division algorithms June
2011
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4. A Explain booths algorithm Multiply 01110(+14) and 11011(-5) using Booths
multiplication July 2013
B.Write the algorithm for binary division using restoring division method
C. List the rules for addition, subtraction, multiplication and division of floating point
Numbers June 2012
5. a. Draw and explain the single-bus organization of tha data path inside a
processor. Jan 2014
b. Write the control sequence for an un-conditional branch instruction.
c. Draw the block diagram of the control unit organization.
UNIT-VIII: MULTICORES, MULTIPROCESSORS, AND CLUSTERS
1. A. Write and explain the control sequences for execution of following instruction
Add(R3),R1
B. With neat diagram, explain 3 bus organization and write control sequence for the
instruction
Add R1,R2,R3.
C. Differentiate between hardwired and micro programmed control June 2010
2. A. Draw a figure of single bus organization of the processor unit
B. list the actions needed to execute the instruction Add R1,(R3). Write the sequence of
control steps to perform actions for a single bus structure. Explain the steps.
C. Compare hardwired control unit with micro programmed control unit. Dec 2010
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3.A. Draw the block diagram of the three-bus organization of data path, which provides
multiple internal paths to enable several transfer to take place in parallel. Lable the
registers and fuctional components of the processor and their connection to respective bus
of data path July 2013
5. A .Write and explain the control sequences for the execution of an unconditional
branch instruction
B. Explain with block diagram the basic organization of a microprogrammed control
unit
C. What are modifications required in the basic organization of a microprogrammed
control unit to support conditional branching in the microprogram June 2012
6. List out differences between shared memory multiprocessor and cluster July 2013
7. a.Explain in brief about multiprocessor systems. Jan 2014
b. Explain about memory organization in multiprocessors.
c. What are the classifications of parallel processing.