CS2071-Computer Architecture QB

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DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING
SUBJECT CODE : CS2071
SUBJECT NAME : COMPUTER ARCHITECTURE
PREPARED BY : Ms. SANDHYA.V.P A.P/EIE
Mr.R.ISSAN RAJ A.P/EIE
SEMESTER/BRANCH :VII/EIE
UNIT I INSTRUCTION SET ARCHITECTURE
PART A
1. Define Computer Architecture.
2. List out the reasons to study computer architecture.
3. What is computer organization?
4. Define abstraction:
5. Define word
6. Define word length
7. Define addressing modes.
8. What are the addressing modes in MiniMIPS?
9. Give an example each of zero-address, one-address, two-address, and three address
instructions.
10. What is operand?
11. What is an opcode? How many bits are needed to specify 32 distinct operations?
12. What is a Procedure?
13. What are the functions of program counter (PC)?
14. What is the difference between Pseudoinstructions & Macroinstructions?
15. Write down the instructions to push a value onto stack.
16. Write down the instructions to pop a value from the stack.
17. What is the function of linker?
18. What is the function of loader?
19. What are the instruction set attributes?
20. What are the features of RISC architecture?
21. What are the advantages of CISC architecture?
22.List out the methods used to improve system performance.
23. What is Byte Addressability?
24. What is meant by Bid-Endian and Little Endian?
26. What are the available instruction formats in miniMIPS?
27. Write notes on register instruction format.
29. Write notes on Jump instruction format.
30. Short notes on Pseudoinstructions.
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PART B
1. Discuss about instructions formats, instruction and addressing modes (16). (EIE Dec 2011)
2. What are the types of basic instruction formats? Explain each type with an example. (CS
Nov10)
3. Explain the Data transfer, Logic and Program Control Instructions with examples? (16) (EIE
Dec 2009)
4. Define addressing mode and describe in detail the different addressing mode with an
example(8).(May08)
5. Describe the addressing modes and instructions designed for control flow (10)
6. Explain the following: (EIE Dec 2011, EEE Dec 2010)
(i) Procedures and data. (8)
(ii) Instruction set. (8)
7. What is the difference between register addressing and direct addressing? Is it possible to
combine register addressing and directing addressing? Explain.
8. What are the steps in transforming an assembly language program to an executable program
residing in memory? Explain in detail.
9. List the various addressing modes with example. Give the importance of each in detail. (EIE
Dec 2012)
10. How do you classify the instruction set of a processor? Explain usage of each classification
with a suitable example. (EIE Dec 2012)
UNIT II ARITHMETIC LOGIC UNIT
PART A
1. Draw a half adder circuit. (EIE Dec 2012)

2. Write the logic equations of a binary half adder. (CS May11)
4. State the purpose of binary adder. (EIE Nov11)
5. Write down the equation for carry generate and propagate.
6. Define a multiplier. (EIE Nov11)
7. What is a carry look-ahead adder? (ECE Nov11)
8. What is meant by underflow and overflow? (ECE Nov11)
9. Define priority encoder. (EC Nov11)
10. Draw the full adder circuit using two half adders.
11. List out rules for Booth recoded multiplier?
12. List out the rules for mul /div of floating point number?
13. What is the principle of booth multiplication?
14. List the two techniques used for speeding up the multiplication process:
15. Define n-bit ripple-carry adder.
16. List out the rules for add/sub of floating point number?
17. Short notes on counter.
18. Short notes on incrementer.
19. Write down the equation for design of fast adders
20. What are the logic and shift operation instruction in ALU.
PART B
1. Explain floating point adder unit and explain the process addition with a flow chart. (16) (EIE
dec 2012)
2. A) starting from truth table explain how to construct a full adder (8) (EIE dec 2012)
B) What is ripple carry added? Mention the disadvantage and explain how it is resolved.(8)
3. Design a 4 bit Carry look ahead adder and explain its operation with an example. (EIE dec
2012, EIE dec 2011)
4. Explain 2s complement multiplier with a neat block diagram. (16) (EC Nov11)
5. Explain floating point adder pipeline with neat block diagram. (16) (EIE dec 2011, EC
Nov11)
6. Write notes on the following: (CS Nov10)
a) Fixed and Floating point representation,
b) 2's compliment addition and subtraction, and
c) Decimal fixed-point representation.
7. Draw the block diagram of a 4 bit register level magnitude comparator and explain. (EC
Nov11)
8. Design a binary multiplier using sequential adder. Explain its operation.(CS Nov10)
9. Draw the circuit for integer division and explain.(CS Nov10)
10. What is a priority encoder? Design a 16-bit priority encoder using two copies of an 8-bit
priority encoder. (6)
11. What are floating point instructions. Explain in detail.
.
UNIT III- DATA PATH AND CONTROL
PART A
1. What are the advantages of pipelining? (EIE Dec 2012)

2. State the function of control unit. (EIE Nov11)
3. What is pipelining. (EIE Nov11)
4. What is microinstruction and what factors determines the length of the microinstructions?
(ECE Nov11)
5. Differentiate between hardwired and micro-programmed control unit. (ECE Nov11)
6. Define Pipeline Hazards?
7. What are the major hazards occur in pipelining? or What are the major hurdle occur in
pipelining?
8. What is Structural Hazards:
9. What is Control Hazard:
10. What is Data Hazards:.
11. What is pipelining?
12. Explain latency and throughput.
13. What are the major characteristics of a pipeline?
14. what is instruction pipeline?
16. What is superscalar processor?
17. What do you mean by out-of order execution? Is it Desirable?

18. What are Hazards?
19. List out Various branching technique used in micro program control unit?
20. Compare hardwired control unit and microprogrammed control unit
21. What is micro programming and micro programmed control unit?
22. What is meant by hardwired control?
PART B
1. Draw schematic diagram of micro programmed control unit and explain its functioning.
Compare it with hardwired control unit (EIE dec 2012) (EC Nov11)
2. List out all pipeline hazards. Explain any one hazard with suitable example (EIE dec 2012)
3. Explain the following: (EIE dec 2011)
i. Control unit synthesis. (8)
ii. Microprogramming. (8)
4. Discuss the instruction execution steps with suitable illustrations. (16) (EIE dec 2011)
5. Describe various factors that reduce the performance of pipelined CPU and the mechanisms
used to overcome it.
6. Design a micro programmed control unit of non-pipelined general purpose computers.
7. Discuss the data and control path methods in pipelining.
8. Explain micro programmed control unit. What are the advantages and disadvantages of it.
9. Design a 4-stage instruction pipeline and show how its performance is improved over
sequential execution.
10. (i) Describe the role of cache memory in pipelined system. (8)
11. (ii) Discuss the influence of pipelining on instruction set design. (8)
12. Write short notes on: Data Forwarding and Branch Prediction (16)
UNIT IV MEMORY SYSTEM
PART A
1. List any three characteristics of memory device. (EIE dec 2012)

2. Compare main memory and secondary memory. (EIE dec 2012)
3. What is cache memory? (EIE Nov11)
4. What is byte addressable memory? (EIE Nov11)
6. Give the features of ROM cell. (May08)
7. What is memory system?
8. Give the classification of memory
9. Define Static Memories and Dynamic Memories.
10. What is read access time?
11. Define RAM
12. What is ROM?
13. What are PROMs?
14. What is SRAM AND DRAM?

15. What is volatile memory?
17. What is flash memory?
18. Mention two system organizations for caches.
Two system organizations for caches are a. look aside and b. look through
19. What is RAMBUS memory?
20. Give the difference between EEPROM and Flash memory?
21. Differences between cache memory and virtual memery
22. Uses of Virtual Memory.
.
PART B
1. Explain about Static & Dynamic memory systems and ROM technologies. (NOV/DEC 2007)
2. What is mapping? Explain various mechanisms of mapping main memory address into cache
memory addresses. (MAY 2008) (MAY/JUNE 2006)
3. Explain the performance factors in memory. (MAY/JUNE 2006)
4. Explain the concept of memory hierarchy (NOV/DEC 2007)&( NOV/DEC 2006)
5. Discuss different page replacement policies in virtual memory system. (MAY 2006)
6. Describe the working principle of a typical magnetic disk.(APRIL 2008)
7. How a virtual address gets translated into a physical address? Explain in detail. Explain the
use of TLB.
(APRIL/MAY 2008)&( NOV/DEC 2006) & (MAY/JUNE 2007)
8. What is virtual memory? How is it implemented? (NOV/DEC 2007)
9. Discuss the various memory types and mention their advantages (NOV/DEC 2009)
10. Explain the operation of Associative cache memories. (NOV/DEC 2009)
11. List cache memory organization and explain in detail with suitable diagrams and compare it
with other organization (EIE dec 2012)
12. With neat sketch explain virtual memory management techniques. (EIE dec 2012)
13. Describe cache memory in detail. (16) (EC Nov11) (NOV/DEC 2006)
14. (i) Describe the organization of typical RAM chip.(6)
(ii).What is virtual memory? Explain how the logical address is translated into physical address
in the virtual memory with a neat diagram (10). (MAY/JUNE 2007) (MAY 2008)
15. Explain paging in detail. (EIE dec 2009, may 2010)
16. Define Cache Mapping Functions. Explain different types of mapping functions in cache
memory. (MAY 2009)
17. What are the different secondary storage devices? Elaborate on any one of these devices.(8)
18. Discuss the following
i. Interleaving (5)
ii. Hit rate and Miss penalty (6)
iii. Pre-fetching (5)
UNIT V I/O AND INTERFACES

PART A
1. What is need for interfacing? (EIE dec 2012)
2.Define polling. (EIE Nov11)
3. What is an interrupt ? (EIE dec 12)(EIE Nov11)
4. What are the types of interrupts? (EIE dec 2012)
5.What are the uses of interrupts?

6. Define vectored interrupts.
7. What is the need for reduced instruction chip?
8. Mention the group of lines in the system bus?
9. What is bus master and slave master?
10. What is the use of IO controller?
11. Differentiate synchronous and asynchronous communication?
12.What is strobe signal?
13.What is bus arbitration?
14.Mention the types of bus arbitration?
15.What is IO control method?
16 .What is DMA?
17.What are the advantage and disadvantages of bus?
18.What are the types of buses?
19.what are the i/o data transfer method using memory busses
20. How the interrupt is handled during exception?
23. What is interrupt latency?
24. Define Centralized Arbitration.
25. Define Distributed Arbitration.
26. Define Bus Master.
PART B
1. Give the need for DMA transfer. What are different modes of DMA transfer? Explain the
sequence of operation required for a DMA transfer? (EIE dec 2012), (EIE dec 2012)
2. Write short notes on: multithreading (8) and context switching (8) (EIE dec 2012), (EIE dec
2011)
3. Explain the use of DMA controllers in a computer system with a neat diagram(8) (EC Nov11)
4. Describe vectored interrupt scheme with a neat block diagram.(8) (EC Nov11)
5. Explain how I/O devices can be interfaced with a block diagram.(8) (CS Nov10)
6. How do you connect multiple I/O devices to a processor using interrupts? Explain with
suitable diagrams
7. Explain Handshake protocol. Depict clearly how it controls data transfer during an input
operation.
8. Describe the hardware mechanism for handling multiple interrupt requests.(8)
9. What are handshaking signals? Explain the handshake control of data transfer during input and
output operation.(8)
10. Explain different types of bus arbitration scheme. (8)
11. What is mean by bus arbitration? Describe bus arbitration daisy chaining and polling
schemes for bus arbitration in detail. (10)

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www.vidyarthiplus.

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

SUBJECT CODE : CS2071

SUBJECT NAME : COMPUTER ARCHITECTURE

PREPARED BY : Ms. SANDHYA.V.P A.P/EIE

Mr.R.ISSAN RAJ A.P/EIE

UNIT I INSTRUCTION SET ARCHITECTURE

UNIT II ARITHMETIC LOGIC UNIT

1. Draw a half adder circuit. (EIE Dec 2012)

1. What are the advantages of pipelining? (EIE Dec 2012)

17. What do you mean by out-of order execution? Is it Desirable?

UNIT IV MEMORY SYSTEM

1. List any three characteristics of memory device. (EIE dec 2012)

14. What is SRAM AND DRAM?

UNIT V I/O AND INTERFACES

5.What are the uses of interrupts?

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