Chapter 5 Transistors BJT Part II

Biasing for the BJT
For amplifier applications, the Q-

point is located in the region in which
high voltage, current, and/or power
can be achieved.
For example, in this circuit, to
establish this Q-point, a dc bias
voltage VBE is applied to the base
and small ac signal vbe is added to
vary the base voltage around this
value.
Two practical biasing circuits used for
a BJT are:
Four-Resistor Bias Network
Two-Resistor Bias Network
BJT Biasing | Four-Resistor Bias Network
It is desirable that the Q-point is not affected by the properties of
the transistors.
One of the best circuit to stabilize the Q-point is the Four-resistor
bias.
2 1
2 1
2 1
1
|
Network Bias Base of Equivalent Thevenin
R R
R R
R
R R
R
V V
TH CC EQ
+
=
+
=
Forward active region is correct
Q-point is (202 A, 4.29 V)
Thevenin Equivalent of
Base Bias Network
V
EQ
=V
CC
R
1
R
1
+ R
2
= 4 V
R
TH
=
R
1
R
2
R
1
+ R
2
=12 kW
V
EQ
= I
B
R
EQ
+V
BE
+ I
E
R
E
I
B
=
V
EQ
-V
BE
R
EQ
+ b
F
+1
( )
R
E
I
B
=
4V -0.7V
12kW+ 76
( )
16kW
= 2.69 mA
I
C
= b
F
I
B
= 202 mA
I
E
= b
F
+1
( )
I
B
= 204 mA
V
CE
=V
CC
- I
C
R
C
- I
E
R
E
= 4.29 V
All calculated currents > 0, V
BC
= V
BE
- V
CE
= 0.7 - 4.32 = - 3.62 V
Hence, base-collector junction is reverse-biased, and assumption of
forward-active region operation is correct.
Load-line for the circuit is:
The two points needed to
plot the load line are (0, 12
V) and (314 A, 0). The
resulting load line is plotted
on the common-emitter
output characteristics.
I
B
= 2.7 A - the intersection
of the corresponding
characteristic with load line
gives the Q-point: (200 A,
4.3 V)
C C
F
E
C CC CE
I I
R
R V V 38200 12 =
|
|
.
|
\
|
+ =
o
BJT Biasing | Four-Resistor Bias Design
Objectives
We know that
We desire I
B
<< I
R2
that I
R1
= I
R2
. In this case, base current doesnt disturb
the voltage divider action of R
1
and R
2
. Thus, the Q-point is independent of
base current as well as current gain!
Also, V
EQ
is designed to be large enough that small variations in the
assumed value of V
BE
wont affect I
E
and I
C
.
Current in the base voltage divider network is set by choosing I
2
I
C
/5.
This ensures that power dissipation in bias resistors is < 17 % of the total
quiescent power consumed by circuit, and I
2
>> I
B
for b > 50.
I
C
@ I
E
=
V
EQ
-V
BE
- I
B
R
EQ
R
E
@
V
EQ
-V
BE
R
E
for I
B
R
EQ
<< V
EQ
-V
BE
( )
BJT Biasing | Four-Resistor Bias Design
Guidelines
Choose Thvenin equivalent base voltage
Select R
1
to set I
1
= 9I
B
.
Select R
2
to set I
2
= 10I
B
.
R
E
is determined by V
EQ
and the desired I
C
.
R
C
is determined by desired V
CE
.
V
CC
4
V
EQ

V
CC
2
R
1
=
V
EQ
9I
B
R
2
=
V
CC
-V
EQ
10I
B
R
E
@
V
EQ
-V
BE
I
C
R
C
@
V
EQ
-V
BE
I
C
- R
E
Four-Resistor Bias for BJT | Design
Example
Problem: Design 4-resistor bias circuit with given parameters.
Given data: I
C
= 750 A, |
F
= 100, V
CC
= 15 V, V
CE
= 5 V
Assumptions: Forward-active operation region, V
BE
= 0.7 V
Analysis: Divide (V
CC
- V
CE
) equally between R
E
and R
C
. Thus, V
E
= 5 V
and V
C
= 10 V; Choose nearest 5% resistor values.
R
C
=
V
CC
-V
C
I
C
= 6.67 kW6.8 kW
R
E
=
V
E
I
E
= 6.60 kW6.8 kW
V
B
=V
E
+V
BE
= 5.7 V
I
B
=
I
C
b
F
= 7.5 mA
I
2
=10I
B
= 75.0 mA
I
2
= 9I
B
= 67.5 mA
R
1
=
V
B
9I
B
= 84.4 kW82 kW
R
2
=
V
CC
-V
B
10I
B
=124 kW120 kW
BJT Biasing | Two-Resistor Bias Example
Problem: Find the Q-point a for pnp transistor in a 2-resistor bias circuit
with given parameters.
Given data: |
F
= 50, V
CC
= 9 V
Assumptions: Forward-active operation region, V
EB
= 0.7 V
Analysis:
Forward-active region operation is
correct Q-point is : (6.01 mA, 2.88 V)
9 =V
EB
+18000I
B
+1000 I
C
+ I
B
( )
9 =V
EB
+18000I
B
+1000 51I
B
( )
I
B
=
9 -0.7
69000
V
W
=120 mA I
C
= 50I
B
= 6.01 mA
V
EC
= 9 -1000 I
C
+ I
B
( )
= 2.88 V V
EC
>V
BE
Tolerances & Worst-Case Analysis
Example
Problem: Find worst-case values of I
C
and V
CE
in the circuit below.
Given data: |
FO
= 75 with 50% tolerance, V
A
= 50 V, 5 % tolerance on V
CC
, 10%
tolerance for each resistor. R
1
= 18 kO, R
2
= 36 kO.
Simplified Analysis:
To maximize I
C
, V
EQ
should be maximized, R
E
should be minimized and the opposite for
minimizing I
C
. Extremes of R
E
are: 14.4 kO and
17.6 kO.
To maximize V
EQ
, V
CC
and R
1
should be
maximized, R
2
should be minimized and
opposite for minimizing V
EQ
.
I
C
@ I
E
@
V
EQ
-V
BE
R
E
V
EQ
=V
CC
R
1
R
1
+ R
2
=
V
CC
1+ R
2
R
1
( )
Example (cont.)
V
EQ
max
=
12V(1.05)
1+ 36kW(0.9) 18kW 1.1)
( )
= 4.78 V V
EQ
min
=
12V(0.95)
1+ 36kW(1.1) 18kW 0.9)
( )
= 3.31 V
I
C
max
@
4.78V -0.7V
16kW 0.90
( )
= 283 mA I
C
min
@
3.31V -0.7V
16kW 1.1
( )
=148 mA
V
CC
=12V 5%
R
1
=18kW10%
R
2
= 36kW10%
V
EQ
=V
CC
R
1
R
1
+ R
2
=
V
CC
1+ R
2
R
1
( )
R
EQ
=
R
1
R
2
R
1
+ R
2
= R
1
R
2
Example (cont.)
Extremes of V
EQ
are: 4.78 V and 3.31 V.
Extremes for I
C
are: 283 A and 148 A.
To maximize V
CE
, I
C
and R
C
should be minimized, and opposite for minimizing V
EQ
.
Extremes of V
CE
are: 7.06 V (forward-active region) and
0.471 V (saturated, hence calculated values for
V
CE
and I
C
actually not correct).
V
CE
=V
CC
- I
C
R
C
- I
E
R
E
@V
CC
- I
C
R
C
-
V
EQ
-V
BE
R
E
R
E
V
CE
@V
CC
- I
C
R
C
-V
EQ
+V
BE
V
CE
max
=12V 1.05
( )
-0.148mA 22kW
( )
.9
( )
-3.31+0.7 = 6.73 V
V
CE
min
=12V 0.95
( )
-0.283mA 22kW
( )
1.1
( )
- 4.78+0.7 = 0.471 V

Chapter 5 Transistors BJT Part II

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Biasing for the BJT

For amplifier applications, the Q-

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