Potential Induced Degradation of Photovoltaic Modules: Influence of Temperature and Surface Conductivity
Potential Induced Degradation of Photovoltaic Modules: Influence of Temperature and Surface Conductivity
Potential Induced Degradation of Photovoltaic Modules: Influence of Temperature and Surface Conductivity
By
Faraz Ebneali
April 2012
Overview
Goals Introduction to Photovoltaic Reliability Why PID?
PID Definition IEC standard
Goals
Study High voltage, Temperature and humidity (surface conductivity) effects on crystalline silicon modules (Poly -Si and Mono-Si) To compare the effect of temperature on reaction rate and degradation level To find out the correlation between leakage current and power reduction To compare and evaluate the rate of degradation among Fresh, Thermal Cycling (TC) and Damp Heat (DH) samples To understand what type of samples are suitable for PID test Level of Electrochemical Corrosion and shunting within the interface To analyze the power reversibility of the samples after degradation To estimate the internal series resistance (Rs) of the samples before and after PID stress test To verify and confirm previous PRL PID studies
Reliability in PV Industry
The first period : Eliminate by Qualification test The Second Period : Low failure rate The last Period : End of the useful life PID test : decreases early field failure rate and increases the normal life cycle
Why PID?
Oh no! Our modules are down 40%, we think it is potential induced degradation anonymous module manufacturer, 2010. [1] Australias silent module killer (due to high temperatures and humidity, specially in the north of the country)
But what conditions actually cause the effect to occur? Ideal conditions for PID; 1. 2. 3. High voltage (600 -1500 V) Temperature Surface Conductivity (Humidity)
Q-Cells PID Test Conditions: 25C, damp module surface (what %RH?) 600 Volt (what polarity?) 300 hours test Tainergy PID Test Conditions: 25C, (what %RH?) -1000 Volt 140 hours test
IEC61215 standard
Current Standard ! Qualification tests like Thermal Cycling, Damp Heat and Require testing for safety issues at high voltage conditions.
Inclusion of PID in IEC standard Need to standardize the PID test that completely evaluate the durability of the modules under stressed conditions. Early detection of damage with applying both negative and positive potential and other conditions. Reasonable PID test in case of cost, time and stress level.
PID Definition
The potential difference between the frame and the cells results in a leakage current (charge transferred or polarization)
Polarization : Charge accumulate in the encapsulation! Shunting, FF, Short and open circuit
Flow of leakage current from active cell layer through the encapsulation and the glass along the surface to the frame [2]
Module Level
1. Encapsulant material 2. Module design (frame, mounting, isolation)
System Level
1. Voltage (1000V) 2. Humidity (85%RH) 3. Temperature (85 C) 4. Grounding connected with frame [3]
[4] 1.Transformerless Inverter (no transformer): Lighter, cheaper and higher efficiency 2.Transformer-based Inverter: PID effect can be prevented by grounding the negative string, however high potential may cause new failure mechanisms
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Transformless Inverters
PV Offset box (SMA in cooperation with Evergreen) Operates at nigh (2 mA Max and 600 V) Still can not reverse the electrochemical degradations
[5]
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Leading to degradation of the material such as silicon nitride (ARC), EVA and the active cell. encapsulation material via cell, causing polarization, not only lowering the parallel resistance but the FF and the output. This is associated with significant shunting of individual cells.
[6] 12
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Grounding Point
DAS
Resistors
Power Supply
14
System Setup
PRL complete PID stress test package Precise Upgradable (2kV) Safe (Ground Fault Protection) Automated (2 round per day) Durability (18AWG)
7.5 kV Insulator
15
Process Flow
Goal Project 1 and 2: Share similar characteristics. To discover the effect of polarity on PV samples and study the temperature variation effect on the amount of Leakage current (LC) Project 3 and 4 : Monitor and analyze the effect of temperature
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Procedure Description
I. Phase-I Positive Bias (Negatively grounded): +600V
Apply +600V to cell active layer 5h intervals at 85C or 60C and 85%RH (excluding 1 hour ramp rate) 35hours ( 7-PID cycles-Characterization after 2nd ,4th and 7th cycle )
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Arrhenius behavior
Arrhenius plots are used to analyze the effect of temperature on the rates of chemical reactions
75C
3.5
45C
y = -8.2745x + 26.819
25C
3.0 2.5
DH
2.0
TC
1.5 y = -5.7052x + 18.735
1.0 0.5 y = -7.4607x + 23.991
Fresh
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Arrhenius behavior
Project 1-Arrhenius plot, Cycle 7(-Bias, 35h) at 85 C/85%RH
4.0
75C
3.5
45C
25C
2.5
DH
y = -7.2263x + 23.911 2.0
TC
1.5
Fresh
1.0
2.8
2.9
2.9
3.0
3.0
3.1
3.1
3.2
3.2
3.3
3.3
1000/T(K)
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Arrhenius Plot
Project 3, Arrhenius plot- Cycle 2(+Bias, 10h) at 85 C/85%RH
4.0
75C
3.5
45C
25C
3.0
2.5
DH
2.0
TC Fresh
1.5
1.0
0.5
1000/T(K)
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Ea Summary
These (~.6 ev to.8 eV) correspond closely to the activation energy for current conduction through soda-lime silicate glasses. In the presence of high RH, the top surface becomes coated with a macroscopic layer of water, is fairly conductive, and behaves as an equipotential that approximates earth ground potential [2].
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0.6
0.5
0.2
0
Before
Round 2
Round 7
Coulombs
DH-Coulombs
TC-Coulombs
Fresh-Coulombs
TC
DH
Fresh
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1.1
1.4
0.6 0.5
0.2 0
Before
Round 1
Round 7
Coulombs
DH-Coulombs
TC-Coulombs
Fresh-Coulombs
TC
DH
Fresh
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0.7 0.4 0.6 0.5 Before Round 1 Round 4 Test Hours Round 7 Coulombs 0.2 0
DH-Coulombs
TC-Coulombs
Fresh-Coulombs
TC
DH
Fresh
24
DH-Coulombs
TC-Coulombs
Fresh-Coulombs
TC
DH
Fresh
25
0.9
0.8 0.7 0.6 0.5 0.4
Before
Round 1
Round 7
Coulombs
DH-Coulombs
TC-Coulombs
Fresh-Coulombs
TC
DH
Fresh
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Current
I-V curves at Standard Test Condition (STC) Power Performance Negative bias caused drop in power output Increase in PID stress test increase the power loss due to shunting and polarization effect Small changes in Voc but significant FF drop
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 10 20
Voltage 30
40
50
Current
35h
Voltage
30
40
50
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3.0
2.5 +Bias, 85C -Bias, 85C +Bias, 60C -Bias, 60C
2.0
1.5
1.0
0.5
0.0
Coulombs transferred
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1.00
1.20
0.80
1.00
0.80
0.60
0.20
0.00 DH Fresh TC
0.00
Coulombs Transferred
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1.00
0.70 0.60
0.80 0.50
0.60 0.40
0.40
0.30
0.20
0.20
0.10
0.00 Fresh DH TC 0.00
Coulombs Transferred
30
1.00
0.90
TC
0.80
0.70
Fresh
0.60 0.50
Neg35h
Round 4
DH Broke
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DH 0.80
TC 0.70
Fresh
0.60 0.50 0.40 0.30 Before Neg-35 Round 2 Test Hours Rround 4 Round 7
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160 140
Pre-Test-P(W)
Neg 35h-P(W)
Current
120
Reg+5h-P(W) Reg+10h-P(W)
Reg+20h-P(W)
100 80
60
Reg+35h-P(W)
40 20
0
10
20
30
40
50
Voltage
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Resistance ()
Pre and Post PID test Rs calculated using IEC 60891 standard
DH
TC Fresh
Post-Rs (P1)
Pre-Rs (P2)
Post-Rs (P2)
1.80 1.60
Resistance ()
1.40
1.20 1.00 DH TC
Fresh
Post-Rs (P1)
Pre-Rs (P2)
Post-Rs (P2)
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Post-Test Rs
Pre-Test Rs
3.00 2.50
1.00
0.90 0.80
0.70 0.60
2.00 1.50
1.00 0.50
0.50
0.00
Before
Round 2
Rround 4
Round 7
Series Resistance ()
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Electroluminescence Image
Project 2, DH Module (Regeneration, +Bias)-Power Regeneration
1.10
1.00 0.90
0.80
Cell shunting
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Electroluminescence Image
1- Moisture penetration 2- Less resistive path to ground
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TC DH Fresh
Infrared Scan
TC DH
Fresh
Infrared Scan
TC DH Fresh
Infrared Scan
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Summary
Carbon paste
42
Summary
Carbon paste
43
Summary
Carbon paste
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Summary of Findings
Positive Bias Positive potential bias does not seem to affect the performance, irrespective of pre-history (fresh, TC or DH) and surface conductivity (conductive carbon or humidity) of the modules. Negative Bias In the negative bias modules that were subjected to TC tests did not show power output deterioration when humidity (water film) was used for the surface conductivity; however, in the same projects DH and fresh modules lost up to 50% of their original power. Therefore degradation in negative bias depends on pre-history (fresh, TC or DH) and surface conductivity
Phase Transition of components and materials, cure EVA and back sheet That is in contrast to the previous study
Regeneration Bias Reverse polarity can recover modules power to approximately their original power EL Image Dead cells and shunting effects were observed in negative PID test samples IR Scan Majority of samples in both polarities have an elevated average operating module temperature after 35 hours of PID testing Damp Heat samples DH samples experienced more noticeable amounts of charge transfer than other samples (DH = 4.59, fresh =3.43 coulombs transferred) Correlation of Power loss and charge transferred in Negative Bias Larger amount of charge transferred, larger degradation and vice versa
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Further investigation
Why thermal cycling samples of this study show resistance to the PID? (but not in previous study) Increase 35 hours stress test (7 cycles) to more cycles; it allows better auditing methods for any type of phase transition or new mechanisms in the cell and polymeric materials. Large sample size but from the same model System level study
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Acknowledgements
Thankful to my advisor Dr. Govindasamy Tamizhmani for introducing me to the world of Photovoltaic industry and specifically reliability of photovoltaic. His encouragements and supports in various ways. And thanks to Joseph Kuitche for discussing valuable information with me in relevance to the study. I gratefully thank Dr. Narcio F. Macia and Dr. Bradely Rogers for their time and constructive comments on this paper. Thanks to Dr.Peter Hacke, NERL, for sharing his experiences regarding this study.
Regards and blessings to my parents, who without them it was impossible to make it to this point. Their kind and unconditional support in all aspects during the completion of my masters studies.
Sandyha Goranti Sai Tatapudi Kolapo Olakonu Meena Vemula Annie Jose Cano Saurabh Surya Narayana
End
References
[1] Peter Hacke Considerations for a Standardized Test for Potential Induced Degradation of Crystalline SiliconPV Modules February 29, 2012 NREL/PR-520054581 [2] J.A. del Cueto and S.R. Rummel Degradation of Photovoltaic Modules Under High Voltage Stress in the Field 2010 [3] Simon Koch Potential Induced Degradation (PID) effects on crystalline solar modules 2011 [4] Ivo Kastle Dealing with high voltage stress PV Magazin , 2011 [5] www.SMA.de PV OFFSET BOX Night -time discharging of PV panels SMA Solar Technology [6] P. B. Ghate Electromigration-induced failures in VLSI interconnects texas instruments incorporated, Thin Film Electromigration" Workshop, International Reliability Physics Symposium, March 30, 1982.