PIC16F8X: 8-Bit CMOS Flash/EEPROM Microcontrollers

PIC16F8X
8-Bit CMOS Flash/EEPROM Microcontrollers

Devices Included in this Data Sheet:
PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 Extended voltage range devices available (PIC16LF8X, PIC16LCR8X)
Pin Diagram
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16F8X PIC16CR8X
High Performance RISC CPU Features:

Only 35 single word instructions to learn All instructions single cycle (400 ns @ 10 MHz) except for program branches which are two-cycle Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle
Memory Device Flash PIC16F83 512 words PIC16CR83 512 words PIC16F84 1 K-words PIC16CR84 1 K-words F = Flash; CR = ROM RAM 36 36 68 68 Data EEPROM 64 64 64 64 10 MHz 10 MHz 10 MHz 10 MHz Freq Max.
Special Microcontroller Features:

Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Code-protection Power saving SLEEP mode Selectable oscillator options Serial In-System Programming - via two pins (ROM devices support only Data EEPROM programming)
14-bit wide instructions 8-bit wide data path 15 special function hardware registers Eight-level deep hardware stack Direct, indirect and relative addressing modes Four interrupt sources: - External RB0/INT pin - TMR0 timer overow - PORTB<7:4> interrupt on change - Data EEPROM write complete 1,000,000 data memory EEPROM ERASE/WRITE cycles EEPROM Data Retention > 40 years
CMOS Technology:
Low-power, high-speed CMOS Flash/EEPROM technology Fully static design Wide operating voltage range: - Commercial: 2.0V to 6.0V - Industrial: 2.0V to 6.0V Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 2V, 32 kHz - < 1 A typical standby current @ 2V
Peripheral Features:
13 I/O pins with individual direction control High current sink/source for direct LED drive - 25 mA sink max. per pin - 20 mA source max. per pin TMR0: 8-bit timer/counter with 8-bit programmable prescaler
1996 Microchip Technology Inc.
DS30430B-page 1
This document was created with FrameMaker 4 0 4
PIC16F8X
Table of Contents
1.0 General Description ............................................................................................................................................ 3 2.0 PIC16F8X Device Varieties ................................................................................................................................ 5 3.0 Architectural Overview........................................................................................................................................ 7 4.0 Memory Organization ....................................................................................................................................... 11 5.0 I/O Ports............................................................................................................................................................ 21 6.0 Timer0 Module and TMR0 Register.................................................................................................................. 27 7.0 Data EEPROM Memory.................................................................................................................................... 33 8.0 Special Features of the CPU ............................................................................................................................ 37 9.0 Instruction Set Summary ...................................................................................................................................55 10.0 Development Support ........................................................................................................................................67 11.0 Electrical Characteristics for PIC16F83 and PIC16F84.................................................................................... 71 12.0 DC & AC Characteristics Graphs/Tables for PIC16F83 and PIC16F84 ........................................................... 83 13.0 Electrical Characteristics for PIC16CR83 and PIC16CR84...............................................................................85 14.0 DC & AC Characteristics Graphs/Tables for PIC16CR83 and PIC16CR84 ......................................................97 15.0 Packaging Information .......................................................................................................................................99 Appendix A: Feature Improvements .........................................................................................................................103 Appendix B: Compatibility.........................................................................................................................................103 Appendix C: Whats New ..........................................................................................................................................104 Appendix D: Whats Changed...................................................................................................................................104 Appendix E: PIC16C84 to PIC16F83/CR83 and PIC16F84/CR84 Conversion Considerations...............................104 Appendix F: PIC16/17 Microcontrollers ....................................................................................................................105 Index............................................................................................................................................................................ 115 PIC16F8X Product Identication System ....................................................................................................................121
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DS30430B-page 2
PIC16F8X
1.0 GENERAL DESCRIPTION
The PIC16F8X is a group in the PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. This group contains the following devices: PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 The devices with Flash program memory allow the same device package to be used for prototyping and production. In-circuit reprogrammability allows the code to be updated without the device being removed from the end application. This is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. This is also useful for remote applications where the code may need to be updated (such as rate information). Table 1-1 lists the features of the PIC16F8X, and Appendix D: list the features of all of the Microchip microcontrollers. A simplied block diagram of the PIC16F8X is shown in Figure 3-1. The PIC16F8X ts perfectly in applications ranging from high speed automotive and appliance motor control to low-power remote sensors, electronic locks, security devices and smart cards. The Flash/EEPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, security codes, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O exibility make the PIC16F8X very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, PWM functions and co-processor applications). The serial in-system programming feature (via two pins) offers exibility of customizing the product after complete assembly and testing. This feature can be used to serialize a product, store calibration data, or program the device with the current rmware before shipping.
All PIC16/17 microcontrollers employ an advanced RISC architecture. PIC16CXX devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set is used to achieve a very high performance level. PIC16F8X microcontrollers typically achieve a 2:1 code compression and up to a 2:1 speed improvement (at 10 MHz) over other 8-bit microcontrollers in their class. The PIC16F8X has up to 68 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/counter is also available. The PIC16CXX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake the chip from sleep through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock-up.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A: for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to the PIC16F8X (Appendix B:).
1.2
Development Support
The PIC16CXX family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A C compiler and fuzzy logic support tools are also available.
DS30430B-page 3
PIC16F8X
TABLE 1-1: PIC16F8X FAMILY OF DEVICES
Clock
n (M Hz )
Memory
em o ry
s)
Peripherals
Features
Fl as h
In
PIC16C84 PIC16F84(1) PIC16CR84(1) PIC16F83(1) PIC16CR83(1)
10 10 10 10 10
1K 512
1K
1K 512
36 68 68 36 36
64 64 64 64 64
TMR0 TMR0 TMR0 TMR0 TMR0
4 4 4 4 4
13 13 13 13 13
I/O
xim
EE
RO
Da
Da
Ti
Pi
um
O PR
ta
ta
er
ru er
ns
q re
ue
cy
of
er
io at
P
M
g ro
ra
em
or
(b
e yt
EE
RO
t by
es
)
l du e( s)
pt u So rc es
Vo
g lta
g an
l Vo
ts
Pa
a ck
ge
2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales ofce for availability of these devices.
DS30430B-page 4
PIC16F8X
2.0 PIC16F8X DEVICE VARIETIES
2.2
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in this section. When placing orders, please use the PIC16F8X Product Identication System at the back of this data sheet to specify the correct part number. There are four device types as indicated in the device number. 1. F, as in PIC16F84. These devices have Flash program memory and operate over the standard voltage range. LF, as in PIC16LF84. These devices have Flash program memory and operate over an extended voltage range. CR, as in PIC16CR83. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR84. These devices have ROM program memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices have all Flash locations and conguration options already programmed by the factory. Certain code and prototype verication procedures do apply before production shipments are available. For information on submitting a QTP code, please contact your Microchip Regional Sales Ofce.
2.
2.3
3.
Serialized Quick-Turnaround-Production (SQTP SM ) Devices
4.
Microchip offers the unique programming service where a few user-dened locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. For information on submitting a SQTP code, please contact your Microchip Regional Sales Ofce.
When discussing memory maps and other architectural features, the use of F and CR also implies the LF and LCR versions.
2.1
Electrically Erasable Devices
These devices are offered in the lower cost plastic package, even though the device can be erased and reprogrammed. This allows the same device to be used for prototype development and pilot programs as well as production. A further advantage of the electrically erasable version is that they can be erased and reprogrammed in-circuit, or by device programmers, such as Microchip's PICSTART Plus or PRO MATE II programmers.
2.4
ROM Devices
Some of Microchips devices have a corresponding device where the program memory is a ROM. These devices give a cost savings over Microchips traditional user programmed devices (EPROM, EEPROM). ROM devices (PIC16CR8X) do not allow serialization information in the program memory space. The user may program this information into the Data EEPROM. For information on submitting a ROM code, please contact your Microchip Regional Sales Ofce.
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PIC16F8X
NOTES:
DS30430B-page 6
PIC16F8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. PIC16CXX opcodes are 14-bits wide, enabling single word instructions. The full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (400 ns @ 10 MHz) except for program branches. The PIC16F83 and PIC16CR83 address 512 x 14 of program memory, and the PIC16F84 and PIC16CR84 address 1K x 14 program memory. All program memory is internal. The PIC16CXX can directly or indirectly address its register les or data memory. All special function registers including the program counter are mapped in the data memory. An orthogonal (symmetrical) instruction set makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make programming with the PIC16CXX simple yet efcient. In addition, the learning curve is reduced signicantly. PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register le. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register), and the other operand is a le register or an immediate constant. In single operand instructions, the operand is either the W register or a le register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplied block diagram for the PIC16F8X is shown in Figure 3-1, its corresponding pin description is shown in Table 3-1.
DS30430B-page 7
PIC16F8X
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
13 Flash/ROM Program Memory PIC16F83/CR83 512 x 14 PIC16F84/CR84 1K x 14 Program Bus 14 Instruction reg 5 Direct Addr Program Counter Data Bus 8 EEPROM Data Memory RAM File Registers PIC16F83/R83/84 36 x 8 PIC16F84/CR84 68 x 8 7 RAM Addr
8 Level Stack (13-bit)
EEDATA
EEPROM Data Memory 64 x 8
EEADR
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
DS30430B-page 8
PIC16F8X
TABLE 3-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F8X PINOUT DESCRIPTION

DIP No. 16 15 SOIC No. 16 15 I/O/P Type I O Buffer Type Description
ST/CMOS (3) Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST (1) TTL TTL TTL TTL TTL TTL/ST (2) TTL/ST (2)
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = Input/Output P = power = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when congured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when congured in RC oscillator mode and a CMOS input otherwise.
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PIC16F8X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ow is shown in Figure 3-2. An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)

PC PC+1 PC+2
Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1 4. BSF
INSTRUCTION PIPELINE FLOW

Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is ushed from the pipeline while the new instruction is being fetched and then executed.
DS30430B-page 10
PIC16F8X
4.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F8X. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the core are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is, an indirect address pointer species the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 7.0.
FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PIC16F83/CR83

PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1

13
Stack Level 8 Reset Vector User Memory Space Peripheral Interrupt Vector
0000h 0004h
1FFh
4.1
Program Memory Organization
The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F83 and PIC16CR83, the rst 512 x 14 (0000h-01FFh) are physically implemented (Figure 4-1). For the PIC16F84 and PIC16CR84, the rst 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). Accessing a location above the physically implemented address will cause a wraparound. For example, for the PIC16F84 locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at 0004h.
1FFFh
FIGURE 4-2: PROGRAM MEMORY MAP AND STACK PIC16F84/CR84

PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1

13
Stack Level 8 Reset Vector Peripheral Interrupt Vector

0000h 0004h
User Memory Space
3FFh
1FFFh
DS30430B-page 11
PIC16F8X
4.2 Data Memory Organization
4.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. The rst is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-3 and Figure 4-4 show the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file (F), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register le or indirectly through the File Select Register (FSR) (Section 4.5). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The rst twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM. All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Ch or 08h will access the same GPR. 4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-3, Figure 4-4 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classied into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specic feature.
DS30430B-page 12
PIC16F8X
FIGURE 4-3:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 36 General Purpose registers (SRAM) 2Fh 30h Mapped (accesses) in Bank 0 AFh B0h EEDATA EEADR PCLATH INTCON EECON1 EECON2(1) PCLATH INTCON Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB
REGISTER FILE MAP PIC16F83/CR83

File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
REGISTER FILE MAP PIC16F84/CR84

File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB EECON1 EECON2(1) PCLATH INTCON 80h 81h 82h 83h 84h 85h 86h 87h EEDATA EEADR PCLATH INTCON 88h 89h 8Ah 8Bh 8Ch
Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB
68 General Purpose registers (SRAM)
Mapped (accesses) in Bank 0
4Fh 50h
CFh D0h
7Fh Bank 0 Bank 1
FFh
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location; read as '0'. Note 1: Not a physical register.
Unimplemented data memory location; read as '0'. Note 1: Not a physical register.
DS30430B-page 13
PIC16F8X
TABLE 4-1: REGISTER FILE SUMMARY
Value on Power-on Reset Value on all other resets (Note3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh EECON1 EECON2 PCLATH INTCON INDF OPTION PCL STATUS (2) FSR TRISA TRISB Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 ---- ---1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---- ---EEIF WRERR WREN WR RD ---0 x000 ---- ------0 0000 INTF RBIF 0000 000x ---- ---1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 ---- ------0 q000 ---- ------0 0000 0000 000u EEDATA EEADR PCLATH INTCON INDF TMR0 PCL STATUS FSR PORTA PORTB
(2)
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of the Program Counter (PC) IRP RP1 RP0 TO PD Z DC C
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
---- ---uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu ---- ---uuuu uuuu uuuu uuuu ---0 0000 0000 000u
Indirect data memory address pointer 0 RB7 RB6 RB5 RA4/T0CKI RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0/INT
---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx
Unimplemented location, read as '0' EEPROM data register EEPROM address register GIE EEIE T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x
Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO
Indirect data memory address pointer 0 PORTA data direction register
PORTB data direction register Unimplemented location, read as '0'
EEPROM control register 2 (not a physical register) GIE EEIE T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430B-page 14
PIC16F8X
4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16F8X and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specied bit(s) will be updated according to device logic
FIGURE 4-5:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 (00h - FFh) 1 = Bank 2, 3 (100h - 1FFh) The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most signicant bit of the result occurred 0 = No carry-out from the most signicant bit of the result occurred Note:For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
DS30430B-page 15
PIC16F8X
4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to congure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
FIGURE 4-6:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81h)

R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30430B-page 16
PIC16F8X
4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-7:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 EEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure, please refer to Section 8.5. EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt T0IE: TMR0 Overow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 overow interrupt ag bit 1 = TMR0 has overowed (must be cleared in software) 0 = TMR0 did not overow INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS30430B-page 17
PIC16F8X
4.3 Program Counter: PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low byte is the PCL register, which is a readable and writable register. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. The PCLATH (PC latch high) register is a holding register for PC<12:8>. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value. This occurs during a CALL, GOTO or a write to PCL. The high bits of PC are loaded from PCLATH as shown in Figure 4-8. manipulation of the PCLATH<4:3> is not required for the return instructions (which pops the PC from the stack). Note: The PIC16F8X ignores the PCLATH<4:3> bits, which are used for program memory pages 1, 2 and 3 (0800h - 1FFFh). The use of PCLATH<4:3> as general purpose R/W bits is not recommended since this may affect upward compatibility with future products.
4.4
Stack
FIGURE 4-8:
PCH 12 PC 5
LOADING OF PC IN DIFFERENT SITUATIONS

PCL 8 7 0 INST with PCL as dest PCLATH<4:0> 8 ALU result
The PIC16FXX has an 8 deep x 13-bit wide hardware stack (Figure 4-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The entire 13-bit PC is pushed onto the stack when a CALL instruction is executed or an interrupt is acknowledged. The stack is popped in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a push or a pop operation. Note: There are no instruction mnemonics called push or pop. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
PCLATH PCH 12 11 10 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCL 8 7 0 GOTO, CALL
PCLATH
4.3.1
COMPUTED GOTO
The stack operates as a circular buffer. That is, after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the rst push. The tenth push overwrites the second push (and so on). If the stack is effectively popped nine times, the PC value is the same as the value from the rst pop. Note: There are no status bits to indicate stack overow or stack underow conditions.
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 word block). Refer to the application note Implementing a Table Read (AN556). 4.3.2 PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of program memory. The PIC16F84 and PIC16CR84 have 1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. For future PIC16F8X program memory expansion, there must be another two bits to specify the program memory page. These paging bits come from the PCLATH<4:3> bits (Figure 4-8). When doing a CALL or a GOTO instruction, the user must ensure that these page bits (PCLATH<4:3>) are programmed to the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack (see next section). Therefore,
DS30430B-page 18
PIC16F8X
4.5 Indirect Addressing; INDF and FSR Registers EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 4-1:

INDIRECT ADDRESSING
CONTINUE
movlw movwf clrf incf btfss goto :
Register le 05 contains the value 10h Register le 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h Increment the value of the FSR register by one (FSR = 06) A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-9. However, IRP is not used in the PIC16F8X.
FIGURE 4-9:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 (FSR) 0
RP1 RP0
from opcode
bank select
location select
bank select
location select
00 00h
01
10 not used
11 00h not used
0Bh 0Ch Data Memory (3) 2Fh (1) 30h (1) 4Fh (2) 50h (2) 7Fh Bank 0 Note 1: PIC16F83 and PIC16CR83 devices. 2: PIC16F84 and PIC16CR84 devices 3: For memory map detail see Figure 4-1. Bank 1 Bank 2 Bank 3 7Fh Addresses map back to Bank 0
DS30430B-page 19
PIC16F8X
NOTES:
DS30430B-page 20
PIC16F8X
5.0 I/O PORTS
EXAMPLE 5-1:
CLRF PORTA
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by setting output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA4 as outputs TRISA<7:5> are always read as '0'.
The PIC16F8X has two ports, PORTA and PORTB. Some port pins are multiplexed with an alternate function for other features on the device.
5.1
PORTA and TRISA Registers
BSF MOVLW
STATUS, RP0 0x0F
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can congure these pins as output or input. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedence mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are rst read, then this value is modied and written to the port data latch. The RA4 pin is multiplexed with the TMR0 clock input.
MOVWF
TRISA
FIGURE 5-2:
Data bus WR PORT
BLOCK DIAGRAM OF PIN RA4
Q Q
CK
N Data Latch VSS

D Q Q
RA4 pin
WR TRIS
CK
TRIS Latch
FIGURE 5-1:
Data bus WR Port
BLOCK DIAGRAM OF PINS RA3:RA0

RD TRIS Q VDD
Q
Schmitt Trigger input buffer
D EN EN
CK
P RD PORT
Data Latch N D WR TRIS Q VSS CK Q TTL input buffer I/O pin TMR0 clock input Note: I/O pin has protection diodes to VSS only.
TRIS Latch
RD TRIS Q D
EN RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
DS30430B-page 21
PIC16F8X
TABLE 5-1:
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type TTL TTL TTL TTL ST Function
Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type. Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2:
Address 05h 85h Name PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Bit 7 Bit 6 Bit 5 Bit 4 RA4/T0CKI TRISA4 Bit 3 RA3 TRISA3 Bit 2 RA2 TRISA2 Bit 1 RA1 TRISA1 Bit 0 RA0 TRISA0 Value on Power-on Reset ---x xxxx ---1 1111 Value on all other resets ---u uuuu ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30430B-page 22
PIC16F8X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is congured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTBs pins, RB7:RB4, have an interrupt on change feature. Only pins congured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin congured as an output is excluded from the interrupt on change comparison). The pins value in input mode are compared with the old value latched on the last read of PORTB. The mismatch outputs of the pins are ORed together to generate the RB port change interrupt. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Read (or write) PORTB. This will end the mismatch condition. Clear ag bit RBIF.
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition, and allow the RBIF bit to be cleared. This interrupt on mismatch feature, together with software congurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression (see AN552 in the Embedded Control Handbook). Note 1: For a change on the I/O pin to be recognized, the pulse width must be at least TCY wide. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF PINS RB7:RB4

VDD
FIGURE 5-4:
RBPU(1)
BLOCK DIAGRAM OF PINS RB3:RB0

VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(2)
RBPU(1) Data Latch D CK TRIS Latch D WR TRIS CK Q Q
weak P pull-up
Data bus WR Port
Data bus WR Port
I/O pin(2)
WR TRIS TTL Input Buffer
CK
TTL Input Buffer
RD TRIS RD TRIS Latch Q RD Port Set RBIF From other RB7:RB4 pins D EN RB0/INT Schmitt Trigger Buffer Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS. RD Port Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS. RD Port RD Port Q D EN
D EN
DS30430B-page 23
PIC16F8X
EXAMPLE 5-2:
CLRF PORTB
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit bit0 Buffer Type TTL/ST
(1)
I/O Consistency Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger. Note 1: This buffer is a Schmitt Trigger input when congured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address 06h 86h 81h Name PORTB TRISB OPTION
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 TRISB5 T0CS Bit 4 RB4 TRISB4 T0SE Bit 3 RB3 TRISB3 PSA Bit 2 RB2 TRISB2 PS2 Bit 1 RB1 TRISB1 PS1 Bit 0 RB0/INT TRISB0 PS0 Value on Power-on Reset xxxx xxxx 1111 1111 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30430B-page 24
PIC16F8X
5.3
5.3.1
I/O Programming Considerations

BI-DIRECTIONAL I/O PORTS
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs dened. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (i.e., bit0) and it is dened as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch is unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (i.e., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired-and). The resulting high output current may damage the chip.
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such that the pin voltage stabilizes (load dependent) before the next instruction which causes that le to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. Example 5-3 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.
EXAMPLE 5-3:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp ppp 11pp ppp BCF PORTB, 6 ; 10pp ppp 11pp ppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp ppp 11pp ppp BCF TRISB, 6 ; 10pp ppp 10pp ppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
FIGURE 5-5:
SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 MOVF PORTB,W NOP NOP PC + 2 PC + 3
Note: This example shows as write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where:TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
Instruction fetched RB7:RB0
MOVWF PORTB write to PORTB
Port pin sampled here Instruction executed MOVWF PORTB write to PORTB MOVF PORTB,W NOP NOP
DS30430B-page 25
PIC16F8X
NOTES:
DS30430B-page 26
PIC16F8X
6.0 TIMER0 MODULE AND TMR0 REGISTER
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module. The prescaler is not readable or writable. When the prescaler (Section 6.3) is assigned to the Timer0 Module, the prescale value (1:2, 1:4, ..., 1:256) is software selectable.
The Timer0 module timer/counter has the following features: 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overow from FFh to 00h Edge select for external clock
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode TMR0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the T0 source
6.1
TMR0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overows from FFh to 00h. This overow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt (Figure 6-4) cannot wake the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 6-1:
TMR0 BLOCK DIAGRAM

Data bus FOSC/4 0 1 1 PSout Sync with Internal clocks (2 cycle delay) Set bit T0IF on Overow 8 TMR0 register PSout
RA4/T0CKI pin T0SE
Programmable Prescaler 3 PS2, PS1, PS0 T0CS
PSA
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction Fetch T0
PC-1
PC MOVWF TMR0
PC+1
PC+2
PC+3
PC+4 MOVF TMR0,W
PC+5 MOVF TMR0,W
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Instruction Executed
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
DS30430B-page 27
PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction Fetch TMR0 T0 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
FIGURE 6-4:
TMR0 INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit 4 (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle Interrupt Latency(2) PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: T0IF interrupt ag is sampled here (every Q1). 2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. 4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit. The TMR0 register will roll over 3 Tosc cycles later.
DS30430B-page 28
PIC16F8X
6.2 Using TMR0 with External Clock
6.2.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 Module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
6.3
Prescaler
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of pin RA4/T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (plus a small RC delay) and low for at least 2Tosc (plus a small RC delay). Refer to the electrical specication of the desired device. When a prescaler is used, the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (plus a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the AC Electrical Specications of the desired device.
An 8-bit counter is available as a prescaler for the Timer0 Module, or as a postscaler for the Watchdog Timer (Figure 6-6). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 Module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 Module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 Module, all instructions writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1, BSF 1,x ....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Ext. Clock Input or Prescaler Out (Note 2) Ext. Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0 T0 T0 + 1 T0 + 2 (Note 3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
DS30430B-page 29
PIC16F8X
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus CLKOUT (= Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
1 0 M U X SYNC 2 Cycles
8 TMR0 register
T0CS
PSA
Set bit T0IF on overow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
PSA 0 MUX 1 PSA
WDT Enable bit
WDT time-out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30430B-page 30
PIC16F8X
6.3.1 SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
The prescaler assignment is fully under software control (i.e., it can be changed on the y during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be taken even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
CHANGING PRESCALER (TIMER0WDT)

;Bank 0 ;Clear TMR0 ; and Prescaler ;Bank 1 ;Clears WDT ;Select new ; prescale value ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION STATUS, RP0
EXAMPLE 6-2:
CLRWDT BSF MOVLW
CHANGING PRESCALER (WDTTIMER0)

;Clear WDT and ; prescaler ;Bank 1 ;Select TMR0, new ; prescale value and clock source ; ;Bank 0
STATUS, RP0 b'xxxx0xxx'
MOVWF BCF
OPTION STATUS, RP0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0

Value on Power-on Reset xxxx xxxx INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 ---1 1111 Value on all other resets uuuu uuuu 0000 0000 1111 1111 ---1 1111
Address 01h 0Bh 81h 85h
Name TMR0 INTCON OPTION TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 modules register GIE RBPU EEIE INTEDG T0IE T0CS
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
DS30430B-page 31
PIC16F8X
NOTES:
DS30430B-page 32
PIC16F8X
7.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register le space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: EECON1 EECON2 EEDATA EEADR When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory.
7.1
EEADR
The EEADR register can address up to a maximum of 256 bytes of data EEPROM. Only the rst 64 bytes of data EEPROM are implemented. The upper two bits are address decoded. This means that these two bits must always be '0' to ensure that the address is in the 64 byte memory space.
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F8X devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write-time will vary with voltage and temperature as well as from chip to chip. Please refer to AC specications for exact limits.
FIGURE 7-1:
U bit7 U
EECON1 REGISTER (ADDRESS 88h)

U R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-x RD bit0 R W S U = Readable bit = Writable bit = Settable bit = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7:5 bit 4
Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software). 0 = Does not initiate an EEPROM read
bit 3
bit 2
bit 1
bit 0
DS30430B-page 33
PIC16F8X
7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with ve low order bits physically implemented. The upper-three bits are non-existent and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset during normal operation. In these situations, following reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt ag bit EEIF is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence. To write an EEPROM data location, the user must rst write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specic sequence to initiate the write for each byte.
EXAMPLE 7-2:
BSF BCF BSF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE

; ; ; ; ; ; ; ; ; ; Bank 1 Disable INTs. Enable Write Write 55h Write AAh Set WR bit begin write Enable INTs.
Required Sequence
STATUS, RP0 INTCON, GIE EECON1, WREN 55h EECON2 AAh EECON2 EECON1,WR INTCON, GIE
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 7-1:
BCF MOVLW MOVWF BSF BSF BCF MOVF
DATA EEPROM READ

; ; ; ; ; ; ; Bank 0 Address to read Bank 1 EE Read Bank 0 W = EEDATA
STATUS, RP0 CONFIG_ADDR EEADR STATUS, RP0 EECON1, RD STATUS, RP0 EEDATA, W
DS30430B-page 34
PIC16F8X
7.5 Write Verify 7.6 Protection Against Spurious Writes
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be veried (Example 7-3) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specication limit. The Total Endurance disk will help determine your comfort level. Generally the EEPROM write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the bit). There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.
7.7
EXAMPLE 7-3:
BCF : : MOVF BSF READ BSF
WRITE VERIFY
Bank 0 Any code can go here Must be in Bank 0 Bank 1
Data EEPROM Operation during Code Protect
STATUS, RP0 ; ; ; EEDATA, W ; STATUS, RP0 ; EECON1, RD
When the device is code protected, the CPU is able to read and write unscrambled data to the Data EEPROM. For ROM devices, there are two code protection bits (Section 8.1). One for the ROM program memory and one for the Data EEPROM memory.
BCF ; ; Is the value written (in W reg) and ; read (in EEDATA) the same? ; SUBWF EEDATA, W ; BTFSS STATUS, Z ; Is difference 0? GOTO WRITE_ERR ; NO, Write error : ; YES, Good write : ; Continue program
; YES, Read the ; value written STATUS, RP0 ; Bank 0
TABLE 7-1:
Address 08h 09h 88h 89h Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx xxxx xxxx EEIF WRERR WREN WR RD ---0 x000 ---- --- Value on all other resets uuuu uuuu uuuu uuuu ---0 q000 ---- ----
EEDATA EEADR EECON1 EECON2
EEPROM data register EEPROM address register EEPROM control register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by Data EEPROM.
DS30430B-page 35
PIC16F8X
NOTES:
DS30430B-page 36
PIC16F8X
8.0 SPECIAL FEATURES OF THE CPU
8.1 Conguration Bits
The conguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device congurations. These bits are mapped in program memory location 2007h. Address 2007h is beyond the user program memory space and it belongs to the special test/conguration memory space (2000h - 3FFFh). This space can only be accessed during programming.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16F8X has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: OSC Selection Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID locations In-circuit serial programming The PIC16F8X has a Watchdog Timer which can be shut off only through conguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a xed delay of 72 ms (nominal) on power-up only. This design keeps the device in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode offers a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer time-out or through an interrupt. Several oscillator options are provided to allow the part to t the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conguration bits are used to select the various options.
DS30430B-page 37
PIC16F8X
FIGURE 8-1:
R-u CP bit13 R-u CP
CONFIGURATION WORD - PIC16CR83 AND PIC16CR84

R-u CP R-u CP R-u CP R-u CP R/P-u DP R-u CP R-u CP R-u CP R-u R-u R-u R-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged
bit 13:8 CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 7 DP: Data Memory Code Protection bit 1 = Code protection off 0 = Data memory is code protected CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 6:4
bit 3
bit 2
bit 1:0
FIGURE 8-2:
CONFIGURATION WORD - PIC16F83 AND PIC16F84

R/P-u R/P-u R/P-u R/P-u R/P-u CP PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP CP CP CP CP bit13
bit 13:4 CP: Code Protection bit 1 = Code protection off 0 = All memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 2
bit 1:0
DS30430B-page 38
PIC16F8X
8.2
8.2.1
Oscillator Congurations
OSCILLATOR TYPES
TABLE 8-1:
PIC16F83/CR83/F84/CR84 CAPACITOR SELECTION FOR CERAMIC RESONATORS
The PIC16F8X can be operated in four different oscillator modes. The user can program two conguration bits (FOSC1 and FOSC0) to select one of these four modes: LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz OSC1/C1 OSC2/C2
HS
Note :
47 - 100 pF 47 - 100 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
8.2.2
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-3).
FIGURE 8-3:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

OSC1 To internal logic SLEEP PIC16FXX
Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.
Resonators Tested: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA10.00MTZ 0.3% 0.5% 0.5% 0.5% 0.5%
C1(1)
XTAL OSC2 C2(1) Note1: 2: 3: RS(2)
RF(3)
None of the resonators had built-in capacitors.
See Table 8-1 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen.
The PIC16F8X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 8-4).
FIGURE 8-4:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)

OSC1 PIC16FXX Open OSC2
Clock from ext. system
DS30430B-page 39
PIC16F8X
TABLE 8-2: PIC16F83/CR83/F84/CR84 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz OSC1/C1 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF OSC2/C2 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
10k 20 pF 20 pF
FIGURE 8-5:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other Devices
Mode LP XT
+5V 10k 4.7k 74AS04 74AS04 CLKIN PIC16FXX
HS
Note :
10k XTAL
Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specication. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested: 32.768 kHz 100 kHz 200 kHz 1.0 MHz 2.0 MHz 4.0 MHz 10.0 MHz 8.2.3 Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 KHz ECS ECS-10-13-2 ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
Figure 8-6 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-6:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other Devices 74AS04 CLKIN
330 k 74AS04
330 k 74AS04 0.1 F XTAL
PIC16FXX
EXTERNAL CRYSTAL OSCILLATOR CIRCUIT
Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits are available; one with series resonance, and one with parallel resonance. Figure 8-5 shows a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.
DS30430B-page 40
PIC16F8X
8.2.4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low Cext values. The user needs to take into account variation due to tolerance of the external R and C components. Figure 8-7 shows how an R/C combination is connected to the PIC16F8X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 5 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With little or no external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See the electrical specication section for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance has a greater affect on RC frequency). See the electrical specication section for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for waveform).
FIGURE 8-7:
VDD Rext
RC OSCILLATOR MODE
OSC1 Cext VSS Fosc/4 OSC2/CLKOUT
Internal clock PIC16FXX
Note:
When the device oscillator is in RC mode, do not drive the OSC1 pin with an external clock or you may damage the device.
DS30430B-page 41
PIC16F8X
8.3 Reset
The PIC16F8X differentiates between various kinds of reset: Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) reset state on POR, MCLR or WDT reset during normal operation and on MCLR reset during SLEEP. They are not affected by a WDT reset during SLEEP, since this reset is viewed as the resumption of normal operation. Table 8-3 gives a description of reset conditions for the program counter (PC) and the STATUS register. Table 8-4 gives a full description of reset states for all registers. The TO and PD bits are set or cleared differently in different reset situations (Section 8.7). These bits are used in software to determine the nature of the reset.
Figure 8-8 shows a simplied block diagram of the on-chip reset circuit. The MCLR reset path has a noise lter to ignore small pulses. The electrical specications state the pulse width requirements for the MCLR pin. Some registers are not affected in any reset condition; their status is unknown on a POR reset and unchanged in any other reset. Most other registers are reset to a
FIGURE 8-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset
MCLR WDT Module VDD rise detect VDD OST/PWRT OST 10-bit Ripple counter OSC1/ CLKIN PWRT On-chip RC OSC(1) 10-bit Ripple counter R Q Chip_Reset SLEEP WDT Time_Out Reset Power_on_Reset S
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
See Table 8-5

Enable OST
DS30430B-page 42
PIC16F8X
TABLE 8-3: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up Interrupt wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
Legend: u = unchanged, x = unknown. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 8-4:
RESET CONDITIONS FOR ALL REGISTERS

MCLR Reset during: normal operation SLEEP WDT Reset during normal operation uuuu uuuu ---- ---uuuu uuuu 0000h 000q quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u ---- ---1111 1111 0000h 000q quuu(3) uuuu uuuu ---1 1111 1111 1111 ---0 q000 ---- ------0 0000 0000 000u Wake-up from SLEEP: through interrupt through WDT Time-out
Register
Address
Power-on Reset
W INDF TMR0 PCL STATUS FSR PORTA PORTB EEDATA EEADR PCLATH INTCON INDF OPTION PCL STATUS FSR TRISA TRISB EECON1 EECON2 PCLATH INTCON
00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 80h 81h 82h 83h 84h 85h 86h 88h 89h 8Ah 8Bh
xxxx xxxx ---- ---xxxx xxxx 0000h 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x ---- ---1111 1111 0000h 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---0 x000 ---- ------0 0000 0000 000x
uuuu uuuu ---- ---uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) ---- ---uuuu uuuu PC + 1 uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---0 uuuu ---- ------u uuuu uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: Table 8-3 lists the reset value for each specic condition.
DS30430B-page 43
PIC16F8X
8.4 Power-on Reset (POR) FIGURE 8-9:
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." The POR circuit does not produce an internal reset when VDD declines.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)

VDD
VDD D
R R1 MCLR C PIC16FXX
8.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a xed 72 ms nominal time-out (TPWRT) from POR (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13). The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level (Possible exception shown in Figure 8-13). A conguration bit, PWRTE, can enable/disable the PWRT. See either Figure 8-1 or Figure 8-2 for the operation of the PWRTE bit for a particular device. The power-up time delay TPWRT will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR pin is 5 A). A larger voltage drop will degrade VIH level on the MCLR pin. 3: R1 = 100 to 1 k will limit any current owing into MCLR from external capacitor C in the event of an MCLR pin breakdown due to ESD or EOS.
8.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13). This ensures the crystal oscillator or resonator has started and stabilized. The OST time-out (TOST) is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its nal value. In this case (Figure 8-13), an external power-on reset circuit may be necessary (Figure 8-9).
DS30430B-page 44
PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TOST
OST TIME-OUT
INTERNAL RESET
DS30430B-page 45
PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
TOST
OST TIME-OUT
INTERNAL RESET When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its nal value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS30430B-page 46
PIC16F8X
8.7 Time-out Sequence and Power-down Status Bits (TO/PD) 8.8 Reset on Brown-Out
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset a PIC16F8X device when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 8-14 and Figure 8-15.
On power-up (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator conguration and PWRTE conguration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
TABLE 8-5:
Oscillator Conguration XT, HS, LP RC
TIME-OUT IN VARIOUS SITUATIONS

Power-up PWRT PWRT Enabled Disabled 72 ms + 1024TOSC 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC
FIGURE 8-14: BROWN-OUT PROTECTION CIRCUIT 1

VDD VDD 33k 10k 40k MCLR PIC16F8X
Since the time-outs occur from the POR reset pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high, execution will begin immediately (Figure 8-10). This is useful for testing purposes or to synchronize more than one PIC16F8X device when operating in parallel. Table 8-6 shows the signicance of the TO and PD bits. Table 8-3 lists the reset conditions for some special registers, while Table 8-4 lists the reset conditions for all the registers.
This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage.
FIGURE 8-15: BROWN-OUT PROTECTION CIRCUIT 2

VDD VDD R1 Q1 MCLR R2 40k PIC16F8X
TABLE 8-6:
TO 1 0 x 0 0 1 1 PD 1 x 0 1 0 1 0
STATUS BITS AND THEIR SIGNIFICANCE

Condition Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset (during normal operation) WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
VDD
R1 R1 + R2
= 0.7V
DS30430B-page 47
PIC16F8X
8.9 Interrupts
The PIC16F8X has 4 sources of interrupt: External interrupt RB0/INT pin TMR0 overow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt When an interrupt is responded to; the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. For external interrupt events, such as the RB0/INT pin or PORTB change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-17). The latency is the same for both one and two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ag bits. The interrupt ag bit(s) must be cleared in software before re-enabling interrupts to avoid innite interrupt requests.
The interrupt control register (INTCON) records individual interrupt requests in ag bits. It also contains the individual and global interrupt enable bits. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. Bit GIE is cleared on reset. The return from interrupt instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overow interrupt ags are contained in the INTCON register.
Note 1: Individual interrupt ag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
FIGURE 8-16: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE EEIF EEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
DS30430B-page 48
PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF ag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 1 Interrupt Latency 2
Note 1: INTF ag is sampled here (every Q1). 2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
8.9.1
INT INTERRUPT
8.9.3
PORT RB INTERRUPT
External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing control bit INTE (INTCON<4>). Flag bit INTF must be cleared in software via the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake the processor from SLEEP (Section 8.12) only if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether the processor branches to the interrupt vector following wake-up. 8.9.2 TMR0 INTERRUPT
An input change on PORTB<7:4> sets ag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<3>) (Section 5.2). Note 1: For a change on the I/O pin to be recognized, the pulse width must be at least TCY wide.
An overow (FFh 00h) in TMR0 will set ag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 6.0).
DS30430B-page 49
PIC16F8X
8.10 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. Example 8-1 stores and restores the STATUS and W registers values. The User dened registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values. Example 8-1 does the following: a) b) c) d) e) Stores the W register. Stores the STATUS register in STATUS_TEMP. Executes the Interrupt Service Routine code. Restores the STATUS (and bank select bit) register. Restores the W register.
EXAMPLE 8-1:
PUSH MOVWF SWAPF MOVWF : : : : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM

W_TEMP STATUS, W STATUS_TEMP ; ; ; : ; ; ; ; ; ; ; ; ; Copy W to TEMP register, Swap status to be saved into W Save status to STATUS_TEMP register Interrupt Service Routine should configure Bank as required Swap nibbles in STATUS_TEMP register and place result into W Move W into STATUS register (sets bank to original state) Swap nibbles in W_TEMP and place result in W_TEMP Swap nibbles in W_TEMP and place result into W
ISR
POP
STATUS_TEMP, W STATUS W_TEMP, F W_TEMP, W
DS30430B-page 50
PIC16F8X
8.11 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT Wake-up causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming conguration bit WDTE as a '0' (Section 8.1). 8.11.1 WDT PERIOD part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a WDT time-out. 8.11.2 WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source (Figure 6-6)
0 WDT Timer
M U X
Postscaler 8 8 - to -1 MUX PS2:PS0
WDT Enable Bit
PSA
0 MUX 1
To TMR0 (Figure 6-6)
PSA
WDT Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 8-7:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWRTE(1) PSA Bit 2 Bit 1 Bit 0 Value on Power-on Reset (2) 1111 1111 1111 1111 Value on all other resets
2007h 81h
Cong. bits OPTION
(2) RBPU
(2) INTEDG
(2) T0CS
(2) T0SE
WDTE PS2
FOSC1 PS1
FOSC0 PS0
Legend: x = unknown. Shaded cells are not used by the WDT. Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit. 2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.
DS30430B-page 51
PIC16F8X
8.12 Power-down Mode (SLEEP)
8.12.2 WAKE-UP FROM SLEEP A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 8.12.1 SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. WDT Wake-up (if WDT was enabled). Interrupt from RB0/INT pin, RB port change, or data EEPROM write complete.
The Power-down mode is entered by executing the SLEEP instruction. If enabled, the Watchdog Timer is cleared (but keeps running), the PD bit (STATUS<3>) is cleared, the TO bit (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For the lowest current consumption in SLEEP mode, place all I/O pins at either at VDD or VSS, with no external circuitry drawing current from the I/O pins, and disable external clocks. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by oating inputs. The T0CKI input should also be at VDD or VSS. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low.
Peripherals cannot generate interrupts during SLEEP, since no on-chip Q clocks are present. The rst event (MCLR reset) will cause a device reset. The two latter events are considered a continuation of program execution. The TO and PD bits can be used to determine the cause of a device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). While the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF ag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note
1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30430B-page 52
PIC16F8X
8.12.3 WAKE-UP USING INTERRUPTS
8.15
In-Circuit Serial Programming
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt ag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the ag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
PIC16F8X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. Customers can manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product, allowing the most recent rmware or custom rmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low, while raising the MCLR pin from VIL to VIHH (see programming specication). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) points to location 00h. A 6-bit command is then supplied to the device, 14-bits of program data is then supplied to or from the device, using load or read-type instructions. For complete details of serial programming, please refer to the PIC16CXX Programming Specications (Literature #DS30189).
8.13
Program Verication/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verication purposes. Note: Microchip does not recommend code protecting widowed devices.
FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL PROGRAMMING CONNECTION

To Normal Connections PIC16FXX VDD VSS MCLR/VPP RB6 RB7
External Connector Signals +5V 0V VPP CLK Data I/O
8.14
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations to store checksum or other code identication numbers. These locations are not accessible during normal execution but are readable and writable only during program/verify. Only the 4 least signicant bits of ID location are usable. For ROM devices, these values are submitted along with the ROM code.
VDD To Normal Connections
For ROM devices, both the program memory and Data EEPROM memory may be read, but only the Data EEPROM memory may be programmed.
DS30430B-page 53
PIC16F8X
NOTES:
DS30430B-page 54
PIC16F8X
9.0 INSTRUCTION SET SUMMARY
Each PIC16FXX instruction is a 14-bit word divided into an OPCODE which species the instruction type and one or more operands which further specify the operation of the instruction. The PIC16FXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode eld descriptions. Byte-oriented instructions: 'f' represents a le register designator and 'd' represents a destination designator. The le register designator species which le register is to be used by the instruction. The destination designator species where the result of the operation is to be placed. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed in the le register specied by the instruction. Bit-oriented instructions: 'b' represents a bit eld designator which selects the number of the bit affected by the operation, while 'f' represents the address of the le in which the bit is located. Literal and control operations: 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: Byte-oriented Bit-oriented Literal and control All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. The execution takes two instruction cycles with the second cycle executed as a NOP. Each cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. The instruction execution time is 2 s for program branches. Table 9-2 lists the instructions Microchips assembler (MPASM). recognized by
Figure 9-1 shows the three general formats of instructions. Note: To maintain upward compatibility with future PIC16FXX products, do not use the OPTION and TRIS instructions.
TABLE 9-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS

Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signies a hexadecimal digit.
Register le address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit le register Literal eld, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in le register f. Default is d = 1 Top of Stack Program Counter Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit
FIGURE 9-1:
GENERAL FORMAT FOR INSTRUCTIONS

0
Byte-oriented le register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit le register address Bit-oriented le register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit le register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
label Label name TOS PC GIE WDT TO PD
PCLATH Program Counter High Latch
dest Destination (Either the W register or the specied register le location) [ ] Options Contents Assigned to Register bit eld In the set of
( ) <>
k = 11-bit immediate value
italics User dened term (font is courier)
DS30430B-page 55
PIC16F8X
TABLE 9-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
INSTRUCTION SET SUMMARY

Description Cycles MSb Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through carry Rotate right f through carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff 14-Bit Opcode LSb ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff Status Affected C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z Notes
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS

BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff None None None None 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD None Z None None None None TO,PD C,DC,Z Z
Note 1: When an I/O register is modied as a function of itself (i.e., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin congured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the TMR0. 3: If Program Counter (PC) is modied or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS30430B-page 56
PIC16F8X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed back in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register is ANDed with the eight bit literal 'k'. The result is placed back in the W register.
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register to register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
1 1
ADDWF FSR, 0 W = FSR = 0x17 0xC2 0xD9 0xC2
1 1
ANDWF FSR, 1 W = FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W = FSR =
After Instruction
W = FSR =
DS30430B-page 57
PIC16F8X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG,7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f<b>) None

01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction.

FLAG_REG = 0x47
1 1(2)
HERE FALSE TRUE BTFSC GOTO PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1>=0, PC=address if FLAG<1>=1, PC=address TRUE FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f<b>) None

01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG= 0x0A
After Instruction
FLAG_REG= 0x8A
DS30430B-page 58
PIC16F8X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is 1 then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2 cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z

00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
1 1(2)
HERE FALSE TRUE BTFSC GOTO PC = FLAG,1 PROCESS_CODE

FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1>=0, PC=address if FLAG<1>=1, PC=address FALSE TRUE
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k (PC<10:0>), (PCLATH<4:3>) (PC<12:11>) None
10 0kkk kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W Register [ label ] CLRW None 00h (W) 1Z Z

00 0001 0000 0011 W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
1 2
HERE CALL PC = THERE Address HERE Address THERE Address HERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction

PC = TOS =
DS30430B-page 59
PIC16F8X
CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 The CLRWDT instruction resets the watchdog timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) 1 (dest) Z

00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
1 1
DECF CNT, CNT Z 1 = = = = 0x01 0 0x00 1
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescale = TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] ( f ) (dest) Z

00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) 1 (dest); skip if result = 0 None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
1 1
COMF REG1 REG1,0 = = = 0x13 0x13 0xEC
1 1(2)
HERE DECFSZ GOTO CONTINUE CNT, 1 LOOP

REG1 W
Before Instruction
PC CNT if CNT PC if CNT PC = = = = = addressHERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
DS30430B-page 60
PIC16F8X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Go to address [ label ] GOTO k 0 k 2047 k (PC<10:0>) (PCLATH<4:3>) (PC<12:11>) None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
HERE 1 INCFSZ CNT, LOOP
After Instruction
PC =
Example
GOTO CONTINUE
Before Instruction
PC = addressHERE CNT + 1 0, addressCONTINUE 0, addressHERE +1
After Instruction
CNT = if CNT = PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z

00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z
11 1000 kkkk kkkk The contents of the W register are ORed to the eight bit literal 'k'. The result is placed in the W register.
1 1
IORLW W 0x35 = = 0x9A 0xBF
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1

W
Before Instruction
After Instruction
CNT Z
DS30430B-page 61
PIC16F8X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (W) Z
00 0100 dfff ffff Inclusive OR the W register to register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z

00 1000 dfff ffff The contents of register f is moved to destination d. If d = 0, destination is W register. If d = 1, the destination is le register f itself. d = 1 is useful to test a le register since status ag Z is affected.
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93
1 1
MOVF FSR, 0 W =value in FSR register
Before Instruction
After Instruction
RESULT = W =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move literal to W [ label ] k (W) None

11 00XX kkkk kkkk The eight bit literal 'k' is loaded into W register. The dont cares will assemble as 0s.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None

00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
DS30430B-page 62
PIC16F8X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None

00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS (PC), 1 GIE None

00 0000 0000 1001 The Stack is popped and Top of Stack (TOS) is loaded into the PC. Interrupts are enabled by setting the Global Interrupt Enable bit. This is a two cycle instruction.
NOP
RETFIE
No operation.
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION

00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return Literal to W [ label ] RETLW k 0 k 255 k (W), TOS (PC) None

11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
OPTION
Status Affected: None

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example Note:
1 1 To maintain upward compatibility with future PIC16FXX products, do not use this instruction.
1 2
CALL TABLE ;W contains table ;offset value ;W now has table value TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ;End of table
Before Instruction
W W = = 0x07 value of k7
After Instruction
DS30430B-page 63
PIC16F8X
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS (PC) None
00 0000 0000 1000 Return from subroutine. The stack is popped and the Top of Stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff
RETURN
1 2
RETURN
The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
C Register f
After Interrupt
PC = TOS
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 1
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
SLEEP Syntax: Operands: Operation:
Go into Standby Mode [ label ] None 00h WDT, 0 WDT prescaler 1 TO, 0 PD TO, PD
00 0000 0110 0011
RLF
f,d
SLEEP
The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'.
C Register f
1 1
RLF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 1100 1100 1
The power down status bit (PD) is cleared. Time-out status bit (TO) is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 SLEEP
Words: Cycles: Example:
Before Instruction
After Instruction
REG1 W C
DS30430B-page 64
PIC16F8X
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k (W) (W) C, DC, Z 11 110x kkkk kkkk The W register is subtracted (2s complement method) from the eight bit literal 'k'. The result is placed in the W register. 1 1 SUBLW
W C
SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) (W) (dest) C, DC, Z 00 0010 dfff ffff Subtract (2s complement methodize W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 SUBWF REG1,1 Before Instruction
REG1 = 3 W = 2 C = ?
Words: Cycles: Example 1:
0x02
= 1 = ?
Words: Cycles: Example 1:
Before Instruction
After Instruction
W C = 1 = 1; result is positive
Example 2:
Before Instruction
W C = 2 = ?
After Instruction
REG1 = 1 W = 2 C = 1; result is positive
After Instruction
W C = 0 = 1; result is zero
Example 2:
Before Instruction
REG1 = 2 W = 2 C = ?
Example 3:
Before Instruction
W C = 3 = ?
After Instruction
REG1 = 0 W = 2 C = 1; result is zero
After Instruction
W C = FF = 0; result is negative
Example 3:
Before Instruction
REG1 = 1 W = 2 C = ?
After Instruction
REG1 = FF W = 2 C = 0; result is negative
DS30430B-page 65
PIC16F8X
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap f [ label ] SWAPF f,d XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: 1110 dfff ffff Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register. 1 1 XORLW 0xAF
W SWAP F REG, 0 = 0xB5
0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None 00 The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. 1 1 Before Instruction
REG1 = 0xA5
Words: Cycles: Example:

W = 0x1A
After Instruction
REG1 W = = 0xA5 0x5A
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register (f) f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff
f,d
Status Affected: None 00 0000 0110 0fff

The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Words: Cycles: Example Note:
1 1 To maintain upward compatibility with future PIC16FXX products, do not use this instruction. Words: Cycles: Example
Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
DS30430B-page 66
PIC16F8X
10.0
10.1
DEVELOPMENT SUPPORT
Development Tools
10.3
ICEPIC: Low-cost PIC16CXXX InCircuit Emulator
The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools: PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator PRO MATE II Universal Programmer PICSTART Plus Entry-Level Prototype Programmer PICDEM-1 Low-Cost Demonstration Board PICDEM-2 Low-Cost Demonstration Board PICDEM-3 Low-Cost Demonstration Board MPASM Assembler MPLAB-SIM Software Simulator MPLAB-C (C Compiler) Fuzzy logic development system (fuzzyTECHMP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
10.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXXX, PIC17CXX and PIC14000 devices. It can also set conguration and code-protect bits in this mode.
10.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, make and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily recongured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
10.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efcient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.
DS30430B-page 67
PIC16F8X
10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board
include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. PICDEM-3 will be available in the 3rd quarter of 1996.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchips microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-16B programmer, and easily test rmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the rmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
10.9
MPLAB Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: A full featured editor Three operating modes - editor - emulator - simulator A project manager Customizable tool bar and key mapping A status bar with project information Extensive on-line help MPLAB allows you to: Edit your source les (either assembly or C) One touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) Debug using: - source les - absolute listing le Transfer data dynamically via DDE (soon to be replaced by OLE) Run up to four emulators on the same PC The ability to use MPLAB with Microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
10.7
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test rmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test rmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test rmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test rmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features
10.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.
DS30430B-page 68
PIC16F8X
MPASM allow full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). MPASM has the following features to assist in developing software for specic use applications. Provides translation of Assembler source code to object code for all Microchip microcontrollers. Macro assembly capability. Produces all the les (Object, Listing, Symbol, and special) required for symbolic debug with Microchips emulator systems. Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable. Both versions include Microchips fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation.
10.14
MP-DriveWay Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually congure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchips MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
10.15
SEEVAL Evaluation and Programming System
10.11
Software Simulator (MPLAB-SIM)

The SEEVAL SEEPROM Designers Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signicantly reduce time-to-market and result in an optimized system.
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost exibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
10.16
TrueGauge Intelligent Battery Management
10.12
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a complete C compiler and integrated development environment for Microchips PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display (PICMASTER emulator software versions 1.13 and later).
The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verication can be accomplished before hardware prototypes are built. User interface is graphically-oriented and measured data can be saved in a le for exporting to Microsoft Excel.
10.17
KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
10.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
DS30430B-page 69
Product
MPLAB C Compiler
TABLE 10-1:
PIC12C508, 509 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006
** MPLAB Integrated Development Environment SW007002 SW006005 MP-DriveWay Applications Code Generator
fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. Tool
DS30430B-page 70
DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 ****PRO MATE PICSTART Lite PICSTART Plus *** PICMASTER/ ICEPIC Low-Cost PICMASTER-CE Ultra Low-Cost Low-Cost II Universal In-Circuit In-Circuit Dev. Kit Universal Microchip Emulator Emulator Dev. Kit Programmer EM167015/ DV007003 DV003001 EM167101 EM147001/ DV007003 DV003001 EM147101 EM167015/ EM167201 DV007003 DV162003 DV003001 EM167101 EM167033/ DV007003 DV003001 EM167113 EM167021/ EM167205 DV007003 DV162003 DV003001 N/A EM167025/ EM167203 DV007003 DV162002 DV003001 EM167103 EM167023/ EM167202 DV007003 DV162003 DV003001 EM167109 EM167025/ EM167204 DV007003 DV162002 DV003001 EM167103 EM167035/ DV007003 DV162002 DV003001 EM167105 EM167027/ EM167205 DV007003 DV162003 DV003001 EM167105 EM167027/ DV007003 DV162003 DV003001 EM167105 EM167025/ DV007003 DV162002 DV003001 EM167103 EM167029/ DV007003 DV162003 DV003001 EM167107 EM167029/ EM167206 DV007003 DV162003 DV003001 EM167107 EM167029/ DV007003 DV162003 DV003001 EM167107 EM167031/ DV007003 DV003001 EM167111 EM177007/ DV007003 DV003001 EM177107 ***All PICMASTER and PICMASTER-CE ordering part numbers above include PRO MATE II programmer ****PRO MATE socket modules are ordered separately. See development systems ordering guide for specic ordering part numbers Hopping Code Security Programmer Kit N/A N/A N/A N/A PG306001 Hopping Code Security Eval/Demo Kit N/A N/A DM303001 SEEVAL Designers Kit DV243001 DV114001 N/A
PIC14000
SW007002
PIC16F8X
PIC16C52, 54, 54A, 55, 56, 57, 58A PIC16C554, 556, 558
SW007002
SW007002
PIC16C61
SW007002
PIC16C62, 62A, 64, 64A PIC16C620, 621, 622
SW007002
SW007002
PIC16C63, 65, 65A, 73, 73A, 74, 74A PIC16C642, 662*
SW007002
SW007002
PIC16C71
SW007002
PIC16C710, 711
SW007002
DEVELOPMENT TOOLS FROM MICROCHIP
PIC16C72
SW007002
PIC16F83
SW007002
PIC16C84
SW007002
PIC16F84
SW007002
PIC16C923, 924*
SW007002
PIC17C42, SW007002 SW006005 SW006006 42A, 43, 44 *Contact Microchip Technology for availability date **MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and MPASM Assembler
Product All 2 wire and 3 wire Serial EEPROM's MTA11200B HCS200, 300, 301 *
TRUEGAUGE Development Kit N/A
PIC16F8X
Applicable Devices F83 CR83 F84 CR84
11.0
ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS(2) ...................................................................................................... -0.3 to +14V Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA.....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB ..................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specication is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DS30430B-page 71
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16F84-04 PIC16F83-04
VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.5V to 5.5V 4.5 mA typ. at 5.5V 1.0 A typ. at 4.5V WDT dis 4.0 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
OSC RC
PIC16F84-10 PIC16F83-10
4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4..0 MHz max. 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4.0 MHz max. 4.5V to 5.5V 10 mA max. at 5.5V typ. 1.0 A typ. at 4.5V WDT dis 10 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
PIC16LF84-04 PIC16LF83-04
2.0V to 6.0V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.0 MHz max. 2.0V to 6.0V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.0 MHz max.
XT
HS
Do not use in HS mode
LP
4.0V to 6.0V 35 A typ. at 32 kHz, 3.0V Do not use in LP mode 0.6 A typ. at 3.0V WDT dis 200 kHz max.
VDD: IDD: IPD: Freq:
2.0V to 6.0V 32 A max. at 32 kHz, 3.0V 7 A max. at 2.0V WDT dis 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specications. It is recommended that the user select the device type that ensures the specications required.
DS30430B-page 72
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 11.1 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 4.0 4.5 1.5 *

DC Characteristics Power Supply Pins

Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2)
D001 D001A D002 D003
6.0 5.5

V V V V
XT, RC and LP osc conguration HS osc conguration Device in SLEEP mode See section on Power-on Reset for details
VSS
D004
SVDD
0.05*
V/ms See section on Power-on Reset for details
IDD D010 D010A
1.8 7.3
4.5 10
mA mA
D013 5 10 mA (3) D020 IPD Power-down Current 7.0 28 A D021 1.0 14 A D021A 1.0 16 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specied. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc conguration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc conguration(4) FOSC = 4.0 MHz, VDD = 5.5V FOSC = 4.0 MHz, VDD = 5.5V (During Flash programming) HS OSC CONFIGURATION (PIC16F84-10) FOSC = 10 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, industrial VDD = 4.0V, WDT disabled, commercial VDD = 4.0V, WDT disabled, industrial
DS30430B-page 73
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 11.2 DC CHARACTERISTICS: PIC16LF84, PIC16LF83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 2.0 1.5 * VSS 6.0 V V V XT, RC, and LP osc conguration Device in SLEEP mode See section on Power-on Reset for details

Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2)
D001 D002 D003
D004
SVDD
0.05*
IDD D010 D010A
1 7.3
4 10
mA mA A
D014
15
32
IPD D020 Power-down Current(3) 3.0 16 A D021 0.4 7.0 A D021A 0.4 9.0 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specied. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc conguration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc conguration(4) FOSC = 2.0 MHz, VDD = 5.5V FOSC = 2.0 MHz, VDD = 5.5V (During Flash programming) LP osc conguration FOSC = 32 kHz, VDD = 2.0V, WDT disabled VDD = 2.0V, WDT enabled, industrial VDD = 2.0V, WDT disabled, commercial VDD = 2.0V, WDT disabled, industrial
DS30430B-page 74
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 11.3 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16LF83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, HS and LP modes)(1) OSC1 (RC mode) Input High Voltage I/O ports with TTL buffer Min Typ Max Units Conditions
DC Characteristics All Pins Except Power Supply Pins

Parameter No.
Sym VIL
D030 D030A D031 D032 D033 D034 VIH D040 D040A D041 D042 D043 D050 D070 D060 D061 D063
VSS VSS VSS Vss Vss Vss
0.8 0.16VDD 0.2VDD 0.2VDD 0.3VDD 0.1VDD
V V V V V V
4.5 V VDD 5.5 V entire range(4) entire range
VHYS IPURB IIL
with Schmitt Trigger buffer MCLR, RA4/T0CKI, OSC1 (RC mode) OSC1 (XT, HS and LP modes)(1) 0.7 VDD Hysteresis of TBD Schmitt Trigger inputs PORTB weak pull-up current 50* Input Leakage Current(2,3) I/O ports MCLR, RA4/T0CKI OSC1

2.4 0.48VDD 0.45VDD 0.85 VDD
VDD VDD VDD VDD VDD
V V V V V
4.5 V VDD 5.5V entire range(4) entire range
250*

400* 1 5 5
A VDD = 5.0V, VPIN = VSS A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc conguration
Output Low Voltage I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V OSC2/CLKOUT 0.6 V IOL = 1.6 mA, VDD = 4.5V Output High Voltage D090 VOH I/O ports(3) VDD-0.7 V IOH = -3.0 mA, VDD = 4.5V D092 OSC2/CLKOUT VDD-0.7 V IOH = -1.3 mA, VDD = 4.5V * These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator conguration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F8X with an external clock while the device is in RC mode, otherwise chip damage may result. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specied levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is dened as coming out of the pin. 4: The user may use better of the two specs. D080 D083 VOL
DS30430B-page 75
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 11.4 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16F83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Min Typ Max Units Conditions

Parameter No.
Sym
Characteristic Capacitive Loading Specs on Output Pins OSC2 pin
D100
COSC2
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
CIO
All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program Flash Memory Endurance VDD for read
50
pF
D120 D121 D122 D130 D131
ED VDRW TDEW EP VPR
1M VMIN
10M
6.0 10
E/W 25C at 5V V VMIN = Minimum operating voltage ms
E/W V VMIN = Minimum operating voltage D132 VPEW VDD for erase/write 4.5 5.5 V D133 TPEW Erase/Write cycle time 10 ms Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
100 VMIN
1000
6.0
DS30430B-page 76
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 TABLE 11-2: TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time io I/O port inp INT pin mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
Time
os,osc ost pwrt rbt t0 wdt
OSC1 oscillator start-up timer power-up timer RBx pins T0CKI watchdog timer
P R V Z
Period Rise Valid High Impedance
FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION

All timings are measure between high and low measurement points as indicated in the gures below.
0.7 VDD XTAL 0.8 VDD RC (High) 0.3 VDD XTAL 0.15 VDD RC (Low) OSC1 Measurement Points I/O Port Measurement Points
0.9 VDD (High) 0.1 VDD (Low)
FIGURE 11-2: LOAD CONDITIONS

Load Condition 1 VDD/2 RL Pin VSS RL = CL = 464 50 pF 15 pF for all pins except OSC2. for OSC2 output. CL Pin VSS CL Load Condition 2
DS30430B-page 77
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 11.5 Timing Diagrams and Specications
FIGURE 11-3: EXTERNAL CLOCK TIMING

Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 11-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS

Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC DC 0.1 0.1 1.0 DC 500 250 100 5.0 500 250 500 250 100 5.0 0.4 60 * 50 * 2.0 * 35 * 25 * 50 * 15 * Typ 4/Fosc Max 2 4 10 200 2 4 2 4 10 200 10,000 10,000 1,000 DC Units Conditions MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz ns ns ns s ns ns ns ns ns s s ns ns s ns ns ns ns XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04
Oscillator Frequency(1)
Tosc
External CLKIN Period(1)
Oscillator Period(1)
2 3
TCY TosL, TosH
Instruction Cycle Time(1) Clock in (OSC1) High or Low Time
TosR, TosF
Clock in (OSC1) Rise or Fall Time
XT osc XT osc LP osc HS osc XT osc LP osc HS osc
PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-10 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-10
* These parameters are characterized but no tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specied values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specied limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30430B-page 78
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 11-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 22 23 12 18 16 Q1 Q2 11 Q3
20, 21 Note: All tests must be done with specied capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT.
TABLE 11-4:
Parameter No. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 19 20 20A 21 21A 22 22A 23 23A
CLKOUT AND I/O TIMING REQUIREMENTS

Sym TosH2ckL Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time PIC16F8X PIC16LF8X TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X CLKOUT to Port out valid Port in valid before CLKOUT OSC1 (Q1 cycle) to Port out valid PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X Min 0.30TCY + 30 * 0.30TCY + 80 * 0* TBD TBD 20 * 55 * TOSC TOSC Typ 15 15 15 15 15 15 15 15 10 10 10 10 Max 30 * 120 * 30 * 120 * 30 * 100 * 30 * 100 * 0.5TCY +20 * 125 * 250 * 25 * 60 * 25 * 60 * Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Port in hold after CLKOUT
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X PIC16F8X PIC16LF8X
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30430B-page 79
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR 30 Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32
31 34
TABLE 11-5:
Parameter No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or reset 28 * Min 1000 * 7* Typ 18 1024TOSC 72 132 * 100 * Max 33 * Units ns ms ms ms ns Conditions 2.0V VDD 6.0V
VDD = 5.0V
TOSC = OSC1 period
VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30430B-page 80
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 11-6:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS

Min No Prescaler With Prescaler 0.5TCY + 20 * 50 * 30 * 0.5TCY + 20 * 50 * 20 * TCY + 40 * N Typ Max Units Conditions ns ns ns ns ns ns ns 2.0V VDD 3.0V 3.0V VDD 6.0V N = prescale value (2, 4, ..., 256) 2.0V VDD 3.0V 3.0V VDD 6.0V
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42 *
Tt0P T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30430B-page 81
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 NOTES:
DS30430B-page 82
PIC16F8X
12.0
DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16F83 AND PIC16F84

NOT AVAILABLE AT THIS TIME.
DS30430B-page 83
PIC16F8X
DS30430B-page 84
PIC16F8X
13.0
ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS(2) ...................................................................................................... -0.3 to +14V Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA.....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB ..................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specication is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DS30430B-page 85
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CR84-04 PIC16CR83-04
VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.5V to 5.5V 4.5 mA typ. at 5.5V 1.0 A typ. at 4.5V WDT dis 4.0 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
OSC RC
PIC16CR84-10 PIC16CR83-10
4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4..0 MHz max. 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4.0 MHz max. 4.5V to 5.5V 10 mA max. at 5.5V typ. 1.0 A typ. at 4.5V WDT dis 10 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
PIC16LCR84-04 PIC16LCR83-04
2.0V to 6.0V 4.5 mA max. at 5.5V 6.0 A max. at 2V WDT dis 2.0 MHz max. 2.0V to 6.0V 4.5 mA max. at 5.5V 6.0 A max. at 2V WDT dis 2.0 MHz max.
XT
HS
Do not use in HS mode
LP
4.0V to 6.0V 35 A typ. at 32 kHz, 3.0V Do not use in LP mode 0.6 A typ. at 3.0V WDT dis 200 kHz max.
VDD: IDD: IPD: Freq:
2.0V to 6.0V 32 A max. at 32 kHz, 3.0V 6.0 A max. at 2V WDT dis 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specications. It is recommended that the user select the device type that ensures the specications required.
DS30430B-page 86
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 13.1 DC CHARACTERISTICS: PIC16CR84, PIC16CR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 4.0 4.5 1.5 *


Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2)
D001 D001A D002 D003
6.0 5.5

V V V V
XT, RC and LP osc conguration HS osc conguration Device in SLEEP mode See section on Power-on Reset for details
VSS
D004
SVDD
0.05*
IDD D010 D010A
1.8 7.3
4.5 10
mA mA
D013 5 10 mA (3) D020 IPD Power-down Current 7.0 28 A D021 1.0 14 A D021A 1.0 16 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specied. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc conguration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc conguration(4) FOSC = 4.0 MHz, VDD = 5.5V FOSC = 4.0 MHz, VDD = 5.5V (During EEPROM programming) HS OSC CONFIGURATION (PIC16CR84-10) FOSC = 10 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, industrial VDD = 4.0V, WDT disabled, commercial VDD = 4.0V, WDT disabled, industrial
DS30430B-page 87
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 13.2 DC CHARACTERISTICS: PIC16LCR84, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 2.0 1.5 * VSS 6.0 V V V XT, RC, and LP osc conguration Device in SLEEP mode See section on Power-on Reset for details

Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2)
D001 D002 D003
D004
SVDD
0.05*
IDD D010 D010A
1 7.3
4 10
mA mA A
D014
15
32
IPD D020 Power-down Current(3) 3.0 16 A D021 0.4 5.0 A D021A 0.4 6.0 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specied. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc conguration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc conguration(4) FOSC = 2.0 MHz, VDD = 5.5V FOSC = 2.0 MHz, VDD = 5.5V (During EEPROM programming) LP osc conguration FOSC = 32 kHz, VDD = 2.0V, WDT disabled VDD = 2.0V, WDT enabled, industrial VDD = 2.0V, WDT disabled, commercial VDD = 2.0V, WDT disabled, industrial
DS30430B-page 88
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 13.3 DC CHARACTERISTICS: PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, HS and LP modes)(1) OSC1 (RC mode) Input High Voltage I/O ports with TTL buffer Min Typ Max Units Conditions

Parameter No.
Sym VIL
D030 D030A D031 D032 D033 D034 VIH D040 D040A D041 D042 D043 D050 D070 D060 D061 D063
VSS VSS VSS Vss Vss Vss
0.8 0.16VDD 0.2VDD 0.2VDD 0.3VDD 0.1VDD
V V V V V V
4.5 V Vdd 5.5 V entire range(4) entire range
VHYS IPURB IIL
with Schmitt Trigger buffer MCLR, RA4/T0CKI, OSC1 (RC mode) OSC1 (XT, HS and LP modes)(1) 0.7 VDD Hysteresis of TBD Schmitt Trigger inputs PORTB weak pull-up current 50* Input Leakage Current(2,3) I/O ports MCLR, RA4/T0CKI OSC1

2.4 0.48VDD 0.45VDD 0.85 VDD
VDD VDD VDD VDD VDD
V V V V V
4.5 V VDD 5.5V entire range(4) entire range
250*

400* 1 5 5
A VDD = 5.0V, VPIN = VSS A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc conguration
Output Low Voltage I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V OSC2/CLKOUT 0.6 V IOL = 1.6 mA, VDD = 4.5V Output High Voltage D090 VOH I/O ports(3) VDD-0.7 V IOH = -3.0 mA, VDD = 4.5V D092 OSC2/CLKOUT VDD-0.7 V IOH = -1.3 mA, VDD = 4.5V * These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator conguration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16CR8X with an external clock while the device is in RC mode, otherwise chip damage may result. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specied levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is dened as coming out of the pin. 4: The user may use better of the two specs. D080 D083 VOL
DS30430B-page 89
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 13.4 DC CHARACTERISTICS: PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LCR84A, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Min Typ Max Units Conditions

Parameter No.
Sym
Characteristic Capacitive Loading Specs on Output Pins OSC2 pin
D100
COSC2
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
CIO
All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write
50
pF
D120 D121
E/W 25C at 5V V VMIN = Minimum operating voltage D122 TDEW Erase/Write cycle time 10 ms Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. ED VDRW 1M VMIN
10M
6.0
DS30430B-page 90
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 TABLE 13-2: TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time io I/O port inp INT pin mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
Time
os,osc ost pwrt rbt t0 wdt
OSC1 oscillator start-up timer power-up timer RBx pins T0CKI watchdog timer
P R V Z
Period Rise Valid High Impedance
FIGURE 13-1: PARAMETER MEASUREMENT INFORMATION

All timings are measure between high and low measurement points as indicated in the gures below.
0.7 VDD XTAL 0.8 VDD RC (High) 0.3 VDD XTAL 0.15 VDD RC (Low) OSC1 Measurement Points I/O Port Measurement Points
0.9 VDD (High) 0.1 VDD (Low)
FIGURE 13-2: LOAD CONDITIONS

Load Condition 1 VDD/2 RL Pin VSS RL = CL = 464 50 pF 15 pF for all pins except OSC2. for OSC2 output. CL Pin VSS CL Load Condition 2
DS30430B-page 91
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 13.5 Timing Diagrams and Specications
FIGURE 13-3: EXTERNAL CLOCK TIMING

Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 13-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS

Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC DC 0.1 0.1 1.0 DC 500 250 100 5.0 500 250 500 250 100 5.0 0.4 60 * 50 * 2.0 * 35 * 25 * 50 * 15 * Typ 4/Fosc Max 2 4 10 200 2 4 2 4 10 200 10,000 10,000 1,000 DC Units Conditions MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz ns ns ns s ns ns ns ns ns s s ns ns s ns ns ns ns XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc PIC16LCR8X-04 PIC16CR8X-04 PIC16CR8X-10 PIC16LCR8X-04 PIC16LCR8X-04 PIC16CR8X-04 PIC16LCR8X-04 PIC16CR8X-04 PIC16CR8X-10 PIC16LCR8X-04 PIC16LCR8X-04 PIC16CR8X-04 PIC16CR8X-10 PIC16LCR8X-04 PIC16LCR8X-04 PIC16CR8X-04 PIC16LCR8X-04 PIC16CR8X-04 PIC16CR8X-10 PIC16LCR8X-04
Oscillator Frequency(1)
Tosc
External CLKIN Period(1)
Oscillator Period(1)
2 3
TCY TosL, TosH
Instruction Cycle Time(1) Clock in (OSC1) High or Low Time
TosR, TosF
Clock in (OSC1) Rise or Fall Time
XT osc XT osc LP osc HS osc XT osc LP osc HS osc
PIC16LCR8X-04 PIC16CR8X-04 PIC16LCR8X-04 PIC16CR8X-10 PIC16CR8X-04 PIC16LCR8X-04 PIC16CR8X-10
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specied values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specied limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30430B-page 92
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 13-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 22 23 12 18 16 Q1 Q2 11 Q3
20, 21 Note: All tests must be done with specied capacitive loads (Figure 13-2) 50 pF on I/O pins and CLKOUT.
TABLE 13-4:
Parameter No. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 19 20 20A 21 21A 22 22A 23 23A
CLKOUT AND I/O TIMING REQUIREMENTS

Sym TosH2ckL Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time PIC16CR8X PIC16LCR8X TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X CLKOUT to Port out valid Port in valid before CLKOUT OSC1 (Q1 cycle) to Port out valid PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X Min 0.30TCY + 30 * 0.30TCY + 80 * 0* TBD TBD 20 * 55 * TOSC TOSC Typ 15 15 15 15 15 15 15 15 10 10 10 10 Max 30 * 120 * 30 * 120 * 30 * 100 * 30 * 100 * 0.5TCY +20 * 125 * 250 * 25 * 60 * 25 * 60 * Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Port in hold after CLKOUT
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X PIC16CR8X PIC16LCR8X
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30430B-page 93
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR 30 Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32
31 34
TABLE 13-5:
Parameter No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or reset 28 * Min 1000 * 7* Typ 18 1024TOSC 72 132 * 100 * Max 33 * Units ns ms ms ms ns Conditions 2.0V VDD 6.0V
VDD = 5.0V
TOSC = OSC1 period
VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30430B-page 94
PIC16F8X
Applicable Devices F83 CR83 F84 CR84 FIGURE 13-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 13-6:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS

Min No Prescaler With Prescaler 0.5TCY + 20 * 50 * 30 * 0.5TCY + 20 * 50 * 20 * TCY + 40 * N Typ Max Units Conditions ns ns ns ns ns ns ns 2.0V VDD 3.0V 3.0V VDD 6.0V N = prescale value (2, 4, ..., 256) 2.0V VDD 3.0V 3.0V VDD 6.0V
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42 *
Tt0P T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30430B-page 95
PIC16F8X
DS30430B-page 96
PIC16F8X
14.0 DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16CR83 AND PIC16CR84 NOT AVAILABLE AT THIS TIME.
DS30430B-page 97
PIC16F8X
DS30430B-page 98
PIC16F8X
15.0
15.1
PACKAGING INFORMATION
Package Marking Information
18L PDIP
MMMMMMMMMMMMXXX MMMMMMMMXXXXXXXX AABB CDE
Example
PIC16F84 10I/P 9305 CBA
18L SOIC
MMMMMMMM XXXXXXXX
Example
PIC16LF84 04I/S0218
AABB CDE
9310 CBA
Microchip part number information Customer specic information* Year code (last two digits of calendar year) Week code (week of January 1 is week 01) Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specic information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofce. For QTP devices, any special marking adders are included in QTP price.
Legend: MM...M XX...X AA BB C
DS30430B-page 99
PIC16F8X
15.2 18-Lead Plastic Dual In-line (PDIP) - 300 mil
N E1 E Pin No. 1 Indicator Area eA eB C
D S Base Plane Seating Plane B1 B D1 e1 L A1 A2 A S1
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 Min 0 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 Max 10 4.064 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 Notes Min 0 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.310 0.120 18 0.035 0.005 Inches Max 10 0.160 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 Notes
Reference Typical Reference
Reference Typical Reference
Typical Reference
Typical Reference
DS30430B-page 100
PIC16F8X
15.3 18-Lead Plastic Surface Mount (SOIC) - 300 mil
e B N Index Area E Chamfer h x 45 1 2 3 H L C h x 45
Seating Plane
CP
Base Plane
A1
Package Group: Plastic SOIC (SO) Millimeters Symbol A A1 B C D E e H h L N CP Min 0 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 Max 8 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 Notes Min 0 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 Inches Max 8 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 Notes
Reference
Reference
DS30430B-page 101
PIC16F8X
NOTES:
DS30430B-page 102
PIC16F8X
APPENDIX A: FEATURE IMPROVEMENTS
The following is the list of feature improvements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register le (128 bytes now versus 32 bytes before). A PC latch register (PCLATH) is added to handle program memory paging. PA2, PA1 and PA0 bits are removed from the status register and placed in the option register. Data memory paging is redened slightly. The STATUS register is modied. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions, TRIS and OPTION, are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, the Oscillator Start-up Timer (OST) and Power-up Timer (PWRT), are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change features. T0CKI pin is also a port pin (RA4/T0CKI). FSR is a full 8-bit register. "In system programming" is made possible. The user can program PIC16FXX devices using only ve pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out).
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16F8X, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redene data variables for reallocation. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
3. 4. 5.
2.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
DS30430B-page 103
PIC16F8X
APPENDIX C: WHATS NEW
Not applicable - new document.
APPENDIX D: WHATS CHANGES

Not applicable - new document.
APPENDIX E: PIC16C84 TO PIC16F83/CR83 AND PIC16F84/CR84 CONVERSION CONSIDERATIONS

This appendix discusses some of the issues that you may encounter as you convert your design from a PIC16C84 to a PIC16F83 or PIC16F84 device. These new devices are: 1. PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 The polarity of the PWRTE conguration bit has been reversed. Ensure that the programmer has this bit correctly set before programming. The PIC16F84 and PIC16CR84 have larger RAM sizes. Ensure that this does not cause an issue with your program. The MCLR pin now has an on-chip lter. The input signal on the MCLR pin will require a longer low pulse to generate an interrupt. Many electrical specications have been improved. Compare the electrical specications of the two devices to ensure that this will not cause a compatibility issue.
Some of the issues that may be encountered are:
2.
3.
4.
DS30430B-page 104
F.1 PIC14000 Devices
1996 Microchip Technology Inc. Clock

Hz )
Memory
Peripherals
Features
io at
(M
or
y
)
(x
14
wo
) ds
y nc
r pe fO
em
s te by
I SP
/I
,U
R SA
T)
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in
APPENDIX F: PIC16/17 MICROCONTROLLERS
) r ts gr ol rte nels p ro V s e ( ) P m hi e v n s l a ( -c rc ia ue on ha )( e( ge y gr n u l r q r s n o C o u e e C o t( a S lO Pr D ) Fr R od or tS em pt ins na res A/ -res e M M ui u lP o um M g c i r r e O r u t a r h i e im ri R ta lta di at op ig te /O P m -C ax Se In Sl (h EP I Vo Da Ti Ad Fe M In
Pa
a ck
ge

4K 192 TMR0 I2C/ ADTMR SMBus 14 11 22 2.7-6.0 Internal Oscillator, Bandgap Reference, Temperature Sensor, Calibration Factors, Yes Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2)
PIC14000
20
28-pin DIP, SOIC, SSOP (.300 mil)
PIC16F8X
DS30430B-page 105
F.2
s)
yte
cy of O p er at ion P ( r M og Hz (x ram ) 12 M wo em rd or s) y
y( b
lts
en
or
qu
(s
(V o
em
le
ng
In
str u
cti
on
Fr e
od u
at a
Ra
of
um
ns
im
OM
er
Pi
ag
be r
ax
EP R
RO
RA
Ti m
I/O
PIC16C52 20 20 20 20 20 20 20 20 20 2K 73 TMR0 2K 73 TMR0 2K 72 TMR0 20 12 12 2K 72 TMR0 20 1K 25 TMR0 12 512 24 TMR0 20 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 512 25 TMR0 12 2.0-6.25 512 25 TMR0 12 2.0-6.25 33 33 33 33 33 33 33 33 512 25 TMR0 12 2.5-6.25 33
384
25
TMR0
12
2.5-6.25
Vo lt
33
Nu
18-pin DIP, SOIC 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP
PIC16C54
PIC16C54A
PIC16CR54A
PIC16C55
PIC16C56
PIC16C57
PIC16CR57B
PIC16C58A
PIC16CR58A
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
ac k
ag
es
DS30430B-page 106
PIC16F8X
PIC16C5X Family of Devices
Clock
Memory
Peripherals
Features
F.3

n tio (M H z)
Memory
Peripherals
Features
PIC16CXXX Family of Devices
y or em s) M rd ge ra o lta pe am 4 w o r O V s) of og x1 e te y s Pr ( nc nc by s) ce ( e ( e y s) ur le er qu r ( f o r u e o o Fr Re od tS at em M M al ns ar up um M r n r O p r r Pi e im ta R m te te m a ax O i P o n n / I I I D T E M C
et es R R es ut -o ag ge n k a c lt ow Pa Vo Br
g an e
Yes 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP
(V
ol
ts
PIC16C554 20 20 20 20 20 2K 128 TMR0 2 Yes 4 13 1K 80 TMR0 2 Yes 4 13 512 80 TMR0 2 Yes 4 13 2K 128 TMR0 3 13 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 1K 80 TMR0 3 13 2.5-6.0
20
512
80
TMR0
13
2.5-6.0
PIC16C556
PIC16C558
PIC16C620
PIC16C621
Yes Yes
18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP
PIC16C622
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16F8X
DS30430B-page 107
F.4
Clock
(M H z)
Memory
s)
Peripherals
Features
DS30430B-page 108
y ( or le T) m ) g du e s o in i AR t M d a M r m S r o m e U m M p a w , ) a O ) 2C W gr 4 ts gr of ol /I /P t es ro (x1 ro I t r y e V P y s P r o P ) ( et e l nc S P (b (s pa rc ge e ue es y ria )( le u r m q v n s e R u o e o a la rt( So Fr R ut tS od /C es em lS ui pt ins e M M -o Po re e c M l um u l g n ag r u l r O r i t a a k e r P m a a w i M t i R p t l c r r C o m te ax Se Da In In Br Pa Ca EP RO Ti Pa Vo I/O M
on
PIC16F8X
PIC16C62 20 20 20 20 20 20 20 20 20 20 4K 192 TMR0, TMR1, TMR2 4K 192 TMR0, TMR1, TMR2 4K 192 TMR0, TMR1, TMR2 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 8 8 11 11 2 SPI/I2C, Yes USART 11 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 8 33 33 33 33 33 33 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART 10 22 2.5-6.0 3.0-6.0 2.5-6.0 2.5-6.0 3.0-6.0 2.5-6.0 2.5-6.0 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART 10 22 2.5-6.0 Yes Yes Yes Yes Yes Yes Yes Yes 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C 7 22 2.5-6.0 Yes 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C 7 22 2.5-6.0 Yes
20
2K
128 TMR0, TMR1, TMR2
1 SPI/I2C 7 22 3.0-6.0 Yes
28-pin SDIP, SOIC, SSOP
PIC16C62A(1)
Yes 28-pin SDIP, SOIC, SSOP Yes 28-pin SDIP, SOIC, SSOP Yes 28-pin SDIP, SOIC Yes 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP
PIC16CR62(1)
PIC16C63
PIC16CR63(1)
PIC16C64
PIC16C64A(1)
PIC16CR64(1)
PIC16C65
2 SPI/I2C, Yes USART 2 SPI/I2C, Yes USART
PIC16C65A(1)
PIC16CR65(1)
F.5
Clock
(M ) Hz
Memory
rd s)
Peripherals
ul e( s)
Features
ne ls
g in m U m , M 2C C ) a O ts W it) gr s) em of ol /P PI/I rt te -b ro y M V s e y o c 8 ( ) P r ( S P et l ce (b (s en am pa s) ( e ge er y es ur le ria t gr qu r v n r m o u ( e o e R o t a o la ve Pr Fr R od or tS s es ut tS /C em lS M e M ui on rup -o n re al P ag um le M i g c r O l n C r u k r a i i m P e R i c r ra ta lt pt D te ow m -C ax EP Pa Se In A/ Pa I/O Vo Da Ti M In Br Ca

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PIC16C710 20 20 20 20 20 20 20 4K 4K 192 TMR0, 2 SPI/I2C, Yes TMR1, TMR2 USART 192 TMR0, 2 SPI/I2C, Yes TMR1, TMR2 USART 4K 192 TMR0, 2 SPI/I2C, TMR1, TMR2 USART 5 8 8 4K 192 TMR0, 2 SPI/I2C, TMR1, TMR2 USART 5 11 11 12 12 2K 128 TMR0, 1 SPI/I2C TMR1, TMR2 5 8 22 22 22 33 33 1K 68 TMR0 4 4 13 1K 36 TMR0 4 4 13 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
20
512
36
TMR0
13
2.5-6.0
Yes Yes Yes Yes Yes Yes Yes Yes
Yes 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC Yes 18-pin DIP, SOIC; 20-pin SSOP Yes 28-pin SDIP, SOIC, SSOP 28-pin SDIP, SOIC Yes 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP
PIC16C71 PIC16C711
PIC16C72
PIC16C73
PIC16C73A(1)
PIC16C74
PIC16C74A(1)
PIC16F8X
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales ofce for availability of these devices.
DS30430B-page 109
F.6
as
Fl
DS30430B-page 110 Clock

n tio (M ) Hz
PIC16F8X
Memory
em
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Peripherals
Features
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ts
PIC16C84 PIC16F84(1) 10 10 10 10 512 36 64 512 36 64 1K 68 64 1K 68 64 PIC16CR84(1) PIC16F83(1) PIC16CR83(1)
10
1K
36
64
13 13 13 13 13
2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC
F.7

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Memory
or
M u od le
Peripherals
(s )
Features
ne ls
PIC16C9XX Family Of Devices
g in m m p M 2C C ) O ra gr ts t) W s) of ro ol bi og /P PI/I rt te r y P V s e y o c 8 t ( ) P r e ( n S s P l (b se rc pa s) ( ia ue e e( ge er y e u l r t q r v e n r m l o u ( e e R o a t a o u s ve Fr R Sl od or tS s ut tS ns /C od em ge e M ui on M -o el Pi n re al P up a um l M M i g c r l r n C t O r u k r i P e im c D ri ra ta R lta pt D te pu ow m -C ax Pa Se In A/ LC Pa I/O In Da Vo Ti EP M In Br Ca

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PIC16C923 4K 4 Com 32 Seg 176 TMR0, 1 SPI/I2C TMR1, TMR2 5 9 25 27
4K
176 TMR0, 1 SPI/I2C TMR1, TMR2
4 Com 32 Seg
25
27
3.0-6.0 3.0-6.0
Yes Yes
64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE
PIC16C924
Note
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7. 1: Please contact your local Microchip representative for availability of this package.
PIC16F8X
DS30430B-page 111
F.8
(M
Hz
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um
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PIC17C42 25 25 25 25 25 8K 454 Yes 4K 454 Yes Yes Yes 4K 454 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes Yes Yes 2K 232 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes 11 11 11 11 2K 232 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes 11 33 33 33 33 33
25
2K
232
C a p P tur W e M s s
TMR0,TMR1, 2 2 TMR2,TMR3
Yes
Yes
11
33
4.5-5.5 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Vo
55 58 58 58 58 58
40-pin DIP; 44-pin PLCC, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP
PIC17C42A
PIC17CR42
PIC17C43
PIC17CR43
PIC17C44
TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3
40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
ac k
ag
es
DS30430B-page 112
PIC16F8X
PIC17CXX Family of Devices
Clock
Memory
Peripherals
Features
PIC16F8X
PIN COMPATIBILITY
Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modication to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts.
TABLE F-1:
PIN COMPATIBLE DEVICES

Pin Compatible Devices Package 8-pin 18-pin 20-pin
PIC12C508, PIC12C509 PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622, PIC16C710, PIC16C71, PIC16C711, PIC16F83, PIC16CR83, PIC16C84, PIC16F84A, PIC16CR84 PIC16C55, PIC16C57, PIC16CR57B PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, PIC16C72, PIC16C73, PIC16C73A PIC16C64, PIC16CR64, PIC16C64A, PIC16C65, PIC16C65A, PIC16C74, PIC16C74A PIC17C42, PIC17CR42, PIC17C42A, PIC17C43, PIC17CR43, PIC17C44 PIC16C923, PIC16C924
28-pin 28-pin 40-pin
40-pin 64/68-pin
DS30430B-page 113
PIC16F8X
NOTES:
DS30430B-page 114
PIC16F8X
INDEX A
Absolute Maximum Ratings ..........................................71, 85 ALU .......................................................................................7 Architectural Overview ..........................................................7 Assembler ...........................................................................68 Interrupts .............................................................. 37, 48
L
Loading of PC..................................................................... 18
M
MCLR ....................................................................... 9, 42, 43 Memory Organization Data Memory .............................................................. 12 Memory Organization ................................................. 11 Program Memory........................................................ 11 MPASM Assembler ...................................................... 67, 68 MP-C C Compiler ............................................................... 69 MPSIM Software Simulator .......................................... 67, 69
B
Block Diagram Interrupt Logic ............................................................. 48 On-Chip Reset Circuit ................................................. 42 RA3:RA0 and RA5 Port Pins ...................................... 21 RA4 Pin....................................................................... 21 RB7:RB4 Port Pins ..................................................... 23 TMR0/WDT Prescaler................................................. 30 Watchdog Timer.......................................................... 51 Brown-out Protection Circuit ...............................................47
O
OPTION.................................................................. 16, 43, 49 OSC Selection .................................................................... 37 OSC.................................................................................... 19 OSC.................................................................................... 29 Oscillator HS......................................................................... 39, 47 LP ......................................................................... 39, 47 Oscillator Configurations .................................................... 39
C
C Compiler (MP-C) .............................................................69 Carry .....................................................................................7 CLKIN ...................................................................................9 CLKOUT ...............................................................................9 Code Protection ............................................................37, 53 Compatibility, upward............................................................3 Computed GOTO................................................................18 Configuration Bits................................................................37
P
Paging, Program Memory................................................... 18 PCL............................................................................... 18, 43 PCLATH ....................................................................... 18, 43 PD........................................................................... 15, 42, 47 PICDEM-1 Low-Cost PIC16/17 Demo Board ............... 67, 68 PICDEM-2 Low-Cost PIC16CXX Demo Board............. 67, 68 PICDEM-3 Low-Cost PIC16C9XXX Demo Board .............. 68 PICMASTER RT In-Circuit Emulator................................ 67 PICSTART Low-Cost Development System .................... 67 Pin Compatible Devices ................................................... 113 Pinout Descriptions............................................................... 9 POR.................................................................................... 44 Oscillator Start-up Timer (OST)............................ 37, 44 Power-on Reset (POR)................................... 37, 43, 44 Power-up Timer (PWRT) ...................................... 37, 44 Time-out Sequence .................................................... 47 Time-out Sequence on Power-up............................... 45 TO................................................................... 15, 42, 47 Port RB Interrupt................................................................. 49 PORTA ..................................................................... 9, 21, 43 PORTB ..................................................................... 9, 23, 43 Power-down Mode (SLEEP)............................................... 52 Prescaler ............................................................................ 29 PRO MATE Universal Programmer.................................. 67 Product Identification System ........................................... 121
D
DC Characteristics ....................73, 74, 75, 76, 87, 88, 89, 90 Development Support .........................................................67 Development Tools .............................................................67 Digit Carry .............................................................................7
E
Electrical Characteristics...............................................71, 85 External Power-on Reset Circuit ........................................44
F
Family of Devices PIC14000 .................................................................. 105 PIC16C5X ................................................................. 106 PIC16CXXX .............................................................. 107 PIC16C6X ................................................................. 108 PIC16C7X ................................................................. 109 PIC16C8X ............................................................. 3, 110 PIC16C9XX............................................................... 111 PIC17CXX................................................................. 112 FSR...............................................................................19, 43 Fuzzy Logic Dev. System (fuzzyTECH-MP) ...............67, 69
G
GIE......................................................................................48
R
RBIF bit......................................................................... 23, 49 RC Oscillator .......................................................... 39, 41, 47 Read-Modify-Write.............................................................. 25 Register File ....................................................................... 12 Reset ............................................................................ 37, 42 Reset on Brown-Out ........................................................... 47
I
I/O Ports..............................................................................21 I/O Programming Considerations........................................25 In-Circuit Serial Programming .......................................37, 53 INDF....................................................................................43 Instruction Set Summary.....................................................55 INT Interrupt........................................................................49 INTCON ............................................................17, 43, 48, 49 INTEDG ..............................................................................49 Interrupts Flag ............................................................................. 48 Interrupt on Change Feature....................................... 23
S
Saving W Register and STATUS in RAM........................... 50 SLEEP .................................................................... 37, 42, 52 Software Simulator (MPSIM) .............................................. 69 Special Features of the CPU .............................................. 37 Special Function Registers................................................. 12 Stack................................................................................... 18
DS30430B-page 115
PIC16F8X
Overflows .................................................................... 18 Underflows .................................................................. 18 STATUS ....................................................................7, 15, 43
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow .............................. 10 Example 4-1: Indirect Addressing ...................................... 19 Example 4-2: How to Clear RAM Using Indirect Addressing ................................................... 19 Example 5-1: Initializing PORTA ........................................ 21 Example 5-2: Initializing PORTB ........................................ 24 Example 5-3: Read-Modify-Write Instructions on an I/O Port............................................... 25 Example 6-1: Changing Prescaler (Timer0WDT) ........... 31 Example 6-2: Changing Prescaler (WDTTimer0) ........... 31 Example 7-1: Data EEPROM Read ................................... 34 Example 7-2: Data EEPROM Write ................................... 34 Example 7-3: Write Verify .................................................. 35 Example 8-1: Saving STATUS and W Registers in RAM ...................................................... 50
T
Time-out ..............................................................................43 Timer0 Switching Prescaler Assignment................................. 31 T0IF............................................................................. 49 Timer0 Module ............................................................ 27 TMR0 Interrupt............................................................ 49 TMR0 with External Clock........................................... 29 Timing Diagrams Time-out Sequence..................................................... 45 Timing Diagrams and Specifications.............................78, 92 TRISA..................................................................................21 TRISB............................................................................23, 43
W
W.........................................................................................43 Wake-up from SLEEP ...................................................43, 52 Watchdog Timer (WDT) ....................................37, 42, 43, 51 WDT ....................................................................................43 Period.......................................................................... 51 Programming Considerations ..................................... 51 Time-out...................................................................... 43
LIST OF FIGURES
Figure 3-1: Figure 3-2: Figure 4-1: PIC16F8X Block Diagram .............................. 8 Clock/Instruction Cycle ................................ 10 Program Memory Map and Stack PIC16F83/CR83........................................... 11 Figure 4-2: Program Memory Map and Stack PIC16F84/CR84........................................... 11 Figure 4-3: Register File Map - PIC16F83/CR83 ........... 13 Figure 4-4: Register File Map - PIC16F84/CR84 ........... 13 Figure 4-5: STATUS Register (Address 03h, 83h) ......... 15 Figure 4-6: OPTION Register (Address 81h) ................. 16 Figure 4-7: INTCON Register (Address 0Bh, 8Bh) ........ 17 Figure 4-8: Loading of PC in Different Situations ........... 18 Figure 4-9: Direct/Indirect Addressing ............................ 19 Figure 5-1: Block Diagram of Pins RA3:RA0.................. 21 Figure 5-2: Block Diagram of Pin RA4 ........................... 21 Figure 5-3: Block Diagram of Pins RB7:RB4.................. 23 Figure 5-4: Block Diagram of Pins RB3:RB0.................. 23 Figure 5-5: Successive I/O Operation ............................ 25 Figure 6-1: TMR0 Block Diagram ................................... 27 Figure 6-2: TMR0 Timing: Internal Clock/ No Prescaler ................................................ 27 Figure 6-3: TMR0 Timing: Internal Clock/ Prescale 1:2 ................................................. 28 Figure 6-4: TMR0 Interrupt Timing ................................. 28 Figure 6-5: Timer0 Timing With External Clock.............. 29 Figure 6-6: Block Diagram of the TMR0/WDT Prescaler ...................................................... 30 Figure 7-1: EECON1 Register (Address 88h) ................ 33 Figure 8-1: Configuration Word - PIC16CR83 and PIC16CR84 ........................................... 38 Figure 8-2: Configuration Word - PIC16F83 and PIC16F84.............................................. 38 Figure 8-3: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) .............. 39 Figure 8-4: External Clock Input Operation (HS, XT or LP OSC Configuration) .............. 39 Figure 8-5: External Parallel Resonant Crystal Oscillator Circuit ........................................... 40 Figure 8-6: External Series Resonant Crystal Oscillator Circuit ........................................... 40 Figure 8-7: RC Oscillator Mode ...................................... 41 Figure 8-8: Simplified Block Diagram of On-Chip Reset Circuit .................................. 42 Figure 8-9: External Power-on Reset Circuit (For Slow VDD Power-up)............................. 44 Figure 8-10: Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1.................. 45
X
XT..................................................................................39, 47
Z
Zero bit ..................................................................................7
DS30430B-page 116
PIC16F8X
Figure 8-11: Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2 ................ 45 Figure 8-12: Time-out Sequence on Power-up (MCLR Tied to VDD): Fast VDD Rise Time ..................................................... 46 Figure 8-13: Time-Out Sequence on Power-Up (MCLR Tied to VDD): Slow VDD Rise Time ..................................................... 46 Figure 8-14: Brown-out Protection Circuit 1...................... 47 Figure 8-15: Brown-out Protection Circuit 2...................... 47 Figure 8-16: Interrupt Logic .............................................. 48 Figure 8-17: INT Pin Interrupt Timing ............................... 49 Figure 8-18: Watchdog Timer Block Diagram................... 51 Figure 8-19: Wake-up From Sleep Through Interrupt ........................................................ 52 Figure 8-20: Typical In-system Serial Programming Connection ................................................... 53 Figure 9-1: General Format for Instructions.................... 55 Figure 11-1: Parameter Measurement Information........... 77 Figure 11-2: Load Conditions ........................................... 77 Figure 11-3: External Clock Timing .................................. 78 Figure 11-4: CLKOUT and I/O Timing .............................. 79 Figure 11-5: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ................................ 80 Figure 11-6: Timer0 Clock Timings................................... 81 Figure 13-1: Parameter Measurement Information........... 91 Figure 13-2: Load Conditions ........................................... 91 Figure 13-3: External Clock Timing .................................. 92 Figure 13-4: CLKOUT and I/O Timing .............................. 93 Figure 13-5: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ................................ 94 Figure 13-6: Timer0 Clock Timings................................... 95 Table 11-3: Table 11-4: Table 11-5: External Clock Timing Requirements............78 CLKOUT and I/O Timing Requirements ...... 79 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements ....................80 Timer0 Clock Requirements .........................81 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices)..............86 Timing Parameter Symbology.......................91 External Clock Timing Requirements............92 CLKOUT and I/O Timing Requirements .......93 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements .....................94 Timer0 Clock Requirements .........................95
Table 11-6: Table 13-1:
Table 13-2: Table 13-3: Table 13-4: Table 13-5:
Table 13-6:
LIST OF TABLES
Table 1-1: Table 3-1: Table 4-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 6-1: Table 7-1: Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 9-1: Table 9-2: Table 10-1: Table 11-1: PIC16F8X Family of Devices ......................... 4 PIC16F8X Pinout Description......................... 9 Register File Summary................................. 14 PORTA Functions ........................................ 22 Summary of Registers Associated With PORTA................................................. 22 PORTB Functions ........................................ 24 Summary of Registers Associated With PORTB................................................. 24 Registers Associated with Timer0 ................ 31 Registers/Bits Associated with Data EEPROM ............................................ 35 PIC16F83/CR83/F84/CR84 Capacitor Selection for Ceramic Resonators................ 39 PIC16F83/CR83/F84/CR84 Capacitor Selection for Crystal Oscillator ..................... 40 Reset Condition for Program Counter and the STATUS Register............................ 43 Reset Conditions for All Registers................ 43 Time-out in Various Situations ..................... 47 STATUS bits and Their Significance ............ 47 Summary of Registers Associated With the Watchdog Timer............................. 51 OPCODE Field Descriptions ........................ 55 Instruction Set Summary .............................. 56 Development Tools from Microchip.............. 70 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ............ 72 Timing Parameter Symbology ...................... 77
Table 11-2:
DS30430B-page 117
PIC16F8X
NOTES:
DS30430B-page 118
PIC16F8X
ON-LINE SUPPORT
Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make les and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the <Enter> key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the <Enter> key and Host Name: will appear. 5. Type MCHIPBBS, depress the <Enter> key and you will be connected to the Microchip BBS. In the United States, to nd the CompuServe phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with Host Name:, type NETWORK, depress the <Enter> key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves les submitted to the SIG. No executable les are accepted from the user community in general to limit the spread of computer viruses.
Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The le transfer site is available by using an FTP service to connect to: ftp.mchip.com/biz/mchip The web site and le transfer site provide a variety of services. Users may download les for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specic business information is also available, including listings of Microchip sales ofces, distributors and factory representatives. Other data available for consideration is: Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products
Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
960513
Connecting to the Microchip BBS

Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the U.S.A.
CompuServe Communications Network:

When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS.
fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of their respective companies.
DS30430B-page 119
PIC16F8X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F8X Questions: 1. What are the best features of this document? Y N Literature Number: DS30430B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you nd the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30430B-page 120
PIC16F8X
PIC16F8X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofce. PART NO. Device -XX X /XX Package XXX Pattern Examples: a) PIC16F84 -04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LF84 - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16CR84 - 10I/P = ROM program memory, Industrial temp., PDIP package, 10MHz, normal VDD limits.
Frequency Temperature Range Range
Device
PIC16F8X(2), PIC16F8XT(3) PIC16LF8X(2), PIC16LF8XT(3) PIC16CR8X(2), PIC16CR8XT(3) PIC16LCR8X(2), PIC16LCR8XT(3) 04 10 b(1) I P SO = 4 MHz = 10 MHz = 0C to = -40C to +70C +85C (Commercial) (Industrial)
b)
c)
Frequency Range Temperature Range Package Pattern
= PDIP = SOIC (Gull Wing, 300 mil body)
3-digit Pattern Code for QTP, ROM (blank otherwise)
Note 1: b = blank 2: F = Standard VDD range LF = Extended VDD range CR = ROM Version, Standard VDD range LCR = ROM Version, Extended VDD range 3: T = in tape and reel - SOIC, SSOP packages only.
Sales and Support

Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales ofce (see last page) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchips Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Development Tools For the latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. The latest version of Development Tools software can be downloaded from either our Bulletin Board or Worldwide Web Site. (Information on how to connect to our BBS or WWW site can be found in the On-Line Support section of this data sheet.)
DS30430B-page 121
WORLDWIDE SALES & SERVICE

AMERICAS
Corporate Ofce Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. Suite 150 Two Prestige Place Miamisburg, OH 45342 Tel: 513 291-1654 Fax: 513 291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technmgy Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279 Fax: 905 405-6253
ASIA/PACIFIC
Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Shanghai Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg. 2077 Yanan Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 86 21 6275 5060 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan, R.O.C Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139
EUROPE
United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
All rights reserved. 1996, Microchip Technology Incorporated, USA.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30430B - page 122

PIC16F8X: 8-Bit CMOS Flash/EEPROM Microcontrollers

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PIC16F8X: 8-Bit CMOS Flash/EEPROM Microcontrollers

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PIC16F8X

8-Bit CMOS Flash/EEPROM Microcontrollers

RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4

High Performance RISC CPU Features:

Special Microcontroller Features:

1996 Microchip Technology Inc.

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To Our Valued Customers

1996 Microchip Technology Inc.

Family and Upward Compatibility

1996 Microchip Technology Inc.

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PIC16C84 PIC16F84(1) PIC16CR84(1) PIC16F83(1) PIC16CR83(1)

TMR0 TMR0 TMR0 TMR0 TMR0

1996 Microchip Technology Inc.

Quick-Turnaround-Production (QTP) Devices

Serialized Quick-Turnaround-Production (SQTP SM ) Devices

Electrically Erasable Devices

1996 Microchip Technology Inc.

This document was created with FrameMaker 4 0 4

1996 Microchip Technology Inc.

1996 Microchip Technology Inc.

This document was created with FrameMaker 4 0 4

8 Level Stack (13-bit)

EEPROM Data Memory 64 x 8

Addr Mux 7 Indirect Addr TMR0

FSR reg RA4/T0CKI STATUS reg 8

MUX I/O Ports

1996 Microchip Technology Inc.

PIC16F8X PINOUT DESCRIPTION

RA0 RA1 RA2 RA3 RA4/T0CKI

I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O P P

RB0/INT can also be selected as an external interrupt pin.

1996 Microchip Technology Inc.

OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)

Internal phase clock

Fetch INST (PC) Execute INST (PC-1)

Fetch INST (PC+1) Execute INST (PC)

Fetch INST (PC+2) Execute INST (PC+1)

INSTRUCTION PIPELINE FLOW

1996 Microchip Technology Inc.

FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PIC16F83/CR83

Program Memory Organization

FIGURE 4-2: PROGRAM MEMORY MAP AND STACK PIC16F84/CR84

Stack Level 8 Reset Vector Peripheral Interrupt Vector

User Memory Space

1996 Microchip Technology Inc.

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1996 Microchip Technology Inc.

REGISTER FILE MAP PIC16F83/CR83

REGISTER FILE MAP PIC16F84/CR84

Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB

68 General Purpose registers (SRAM)

Mapped (accesses) in Bank 0

7Fh Bank 0 Bank 1

7Fh Bank 0 Bank 1

1996 Microchip Technology Inc.