Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

Code No: R09220402/R09 II B.Tech. II Semester Examinations

S.1

April/May - 2012 ELECTRONIC CIRCUIT ANALYSIS

(Common to ICE, E.COMP.E, ETM, EIE, ECE)

Set-1
Solutions
Max. Marks: 75

Time: 3 Hours Answer any FIVE questions All questions carry equal marks --1. (a)

Prove that the following two networks (a) and (b) shown in figure have the same currents if excited by same voltages. (Unit-I, Topic No. 1.5)
Z 1= Z (1-AI) 1 1 3 2 2 1 1 2 3
Z2 = A I -1 Z AI

I1 N (a)

I2 N N

I1

I2 N (b)

Figure (b) Draw the simplified hybrid model for the CC circuit and derive expressions for input resistance, output resistance voltage gain and current gain. [7+8] (Unit-I, Topic No. 1.4) Write the equation for overall gain of a n-stage cascaded amplifier. (Unit-II, Topic No. 2.1) How does the frequency response an amplifier change with cascading of amplifier stages? (Unit-II, Topic No. 2.1) Explain the choice of configuration in a cascade of amplifiers. [5+5+5] (Unit-II, Topic No. 2.1) Draw the frequency response of tapped single tuned capacitance coupled amplifier and derive the expression for L for maximum power transfer. (Unit-VIII, Topic No. 8.3) Draw the circuit of double tuned amplifier and explain its working. [8+7] (Unit-VIII, Topic No. 8.3) What is class B amplifier? Where is it employed? Give its circuits, design equations, characteristics and limitations. (Unit-VII, Topic No. 7.3) A transformer coupled class A large signal amplifier has maximum and minimum values of collector to emitter voltage of 25 V and 2.5 V. Determine its collector efficiency. [10+5] (Unit-VII, Topic No. 7.2) What are the characteristics of an amplifier that are modified by negative feedback? (Unit-V, Topic No. 5.3) Draw the four types of feedback amplifiers naming them. (Unit-V, Topic No. 5.2) Define sensitivity and desensitivity factors in feedback amplifiers. [5+5+5] (Unit-V, Topic No. 5.3)

2.

(a) (b) (c)

3.

(a) (b)

4.

(a) (b)

5.

(a) (b) (c)

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6. (a) (b)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Derive an expression for voltage gain of a common source FET amplifier with and without source resistance included in the circuit. (Unit-IV, Topic No. 4.5) Calculate the voltage gain of the FET amplifier shown in the figure, assuming blocking capacitor to be large gm and rd are given as, gm = 4mA/V and rd = 5K. [8+7] (Unit-IV, Topic No. 4.3)

VDD 50 K CD

+ VS + VGG
Figure 7. (a) (b) (c) 8. (a) (b) (c)

10 K

V0

Explain why the upper 3-dB frequency for current gain is not the same as fH for voltage gain. (Unit-III, Topic No. 3.4) A silicon PNP transistor has an FT = 400 MHz. What is the base thickness? (Unit-III, Topic No. 3.4) In terms of what parameters is the high frequency response of a CE stage obtained? [5+5+5] (Unit-III, Topic No. 3.6) Draw the electrical model of a piezoelectric crystal. (Unit-VI, Topic No. 6.5) Sketch the reactance Vs frequency function. (Unit-VI, Topic No. 6.5) Over what portion of the reactance curve do we desire oscillations to take place when the crystal is used as part of a sinusoidal oscillator. Explain. [4+4+7] (Unit-VI, Topic No. 6.5)

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

S.3

SOLUTIONS TO APRIL/MAY-2012, SET-1, QP

Q1. (a) Prove that the following two networks (a) and (b) shown in figure have the same currents if excited by same voltages.
Z 1= Z (1-AI) 1 1 3 2 2 1 1 2 3
Z2 = A I -1 Z AI

I1 N (a)

I2 N N

I1

I2 N (b)

Figure Answer : The given two networks are as shown in figure 1(a) and 1(b).
Z 1 = Z (1-AI) 1 1 3 2 2 1 1 2 3
Z2 = A I -1 Z AI

April/May-12, Set-1, Q1(a) M[7]

I1 N (a)

I2 N N

I1

I2 N (b)

Figure The network in figure (a) consists of arbitrary active or passive linear components between nodes 1, 2 and 3. An impedance Z' is present between node 3 and ground N, which combines the two loops. The current gain of the network is given by, AI =

I 2 I1

Figure (b) is the dual network of figure 1(a). Impedance Z1 is connected to mesh 1 at node 1 impedence Z2 is connected to mesh 2 at node 2 and node 3 is grounded. From Millers theorem, Z1 = Z ' (1 AI) And

AI 1 Z2 = A Z I

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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

Since, the impedance of the dual network at node-1 is Z1 = Z ' (1 AI), the voltage (I1 Z1) is equal to the voltage drop, (I1 + I2)Z ' across Z '. Therefore, the voltage V1'N is equal in both the circuits.

AI 1 Similarly, the impedance of the dual network at node-2 is Z2 = A Z , the voltage I2 Z2 is equal to the voltage I drop (I2 + I1) Z'. Therefore, the voltage V2'N are same in both the circuits.
This equal voltages occur when the currents I1 and I2 are same. Hence, for the same voltages V1'N and V2'N excited on both networks, mesh 1 and mesh 2 consists of the same flow of current I1 and I2 respectively. (b) Answer : For answer refer Unit-I, Q29. Output Resistance (Ro) Ro = Draw the simplified hybrid model for the CC circuit and derive expressions for input resistance, output resistance voltage gain and current gain. April/May-12, Set-1, Q1(b) M[8]

1 Yo

( Yo output admittance)

Approximate Analysis, Output admittance (Yo) =

Short circuit current in output terminals Open circuit voltage between output terminals

Short circuit current in output terminals = 1 + (hfe) Ib = Where, VS is the open circuit voltage between output terminals. Yo =
(1 + h fe )VC hie + R1

VS Q Ib = hie + R1

1 + h fe hie + R1 1 Yo

Hence, the output resistance, Ro =

i.e., Ro =

1 1 + h fe hie + R1
hie + R1 1 + h fe

hie + R1 = 1+ h fe

Ro =

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

Q2. (a) Write the equation for overall gain of a n-stage cascaded amplifier. Answer : Figure (i) illustrates the block schematic of an n stage CE amplifier.

S.5
April/May-12, Set-1, Q2(a) M[5]

Ib1 RS V1 + B1 V1 C1

IC1

Ib2 B2 C2

IC2
RCn1

Ibn Bn Vn En En Cn V3

Icn Io Rcn Vo

E1 E1 Rin

RC1 V2

E2 E2

RC2

Ro1

Ro1

Ro2
Figure (i)

(i)

Voltage Gain (Av) The general expression for the voltage gain of an amplifier circuit is,

Output voltage AV= Input voltage

Stage 1 Voltage gain of the first stage is expressed as,

AV1 =

Output voltage of the first stage Input voltage of the first stage

i.e., Stage 2

V2 AV1 = V 1

The expression for voltage gain of a second stage is,

Output voltage of the second stage AV2 = Input voltage of the second stage V3 V2

Thus, the overall voltage gain of a amplifier is the product of all the individual stages.

i.e.,

AV =

V V2 V3 V4 --- n V1 V2 V3 Vn 1

= AV1 AV2 AV3 - - - AVn

AV = AV 1 AV 2 ...

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S.6
It can also be determined by using the relation,

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 (iii) as, Power Gain (Ap) The power gain of a n-stage cascade amplifier is given

AV =
Where,

AI Rcn Ri1

AI Current gain of the n stage amplifier Rcn Effective load impedance at the collector of nth stage. Ri1 Input impedance of first stage. (ii) is, AI = Stage 1 The expression for current gain of a first stage is, Answer : Current Gain (AI) The general expression for current gain of an amplifier

AP =

Output power of last or n th stage Input power of the first stage

Vo I o V1 I b1

AP = AV . AI
The overall gain of n-stages cascade amplifier is

Output current Input current

AP = AV . AI .

(b)

How does the frequency response an amplifier change with cascading of amplifier stages? April/May-12, Set-1, Q2(b) M[5]

Output current of the first stage AI 1 = Input current of the first stage I o I cn = I b1 I b1

The purpose of designing amplifiers is to offer gain over a particular frequency range. In cascaded amplifiers, the frequency response of the curve changes with respect to the addition of stages (to the existing amplifier). In this amplifier, the stage with lowest upper frequency is used to obtain the upper cut-off frequency. Thus, The upper cut-off frequency of n identification interactive stage amplifier is expressed as, fHn = fH Where, fH = Upper cut-off frequency of a single stage.

I cn AI1 = I b1
Where,

I cn I b1 is the base to collector gain of the first stage.

Stage 2 The expression for current gain of a second stage is,

21/ n 1

fL I b1 I c 2 AI 2 = I = I c1 c1
Therefore the overall current gain of a n stage amplifier is expressed as, Lower cut-off frequency FL2 =

21/ n 1

For instance, upper cut-off frequency of a two stage amplifier is given as, fH2 = fH

I I AI = c1 c 2 .. . I b 2 I c1

21/ 2 1

= 0.64 fH

AI = A1I AI 2 - - -

f H 2 = 0.64 f H

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

The frequency response of cascade amplifier with an impact of cut-off frequencies and bandwidth is as illustrated in figure below.
Av 0 3dB 6dB 9dB 12dB
f L1 f L 2 f L3

S.7
+VCC

R1
f (log scale) n= 1 n= 2 n= 3
f H3 f H2 f H1

L1 L2

R1

C1 Q1 VS

C2 Q2

Figure (c) Answer : Explain the choices of configuration in a cascade of amplifiers. April/May-12, Set-1, Q2(c) M[5]

R2

RE

CE Ist stage

R2

R2

CE

IInd stage

Figure (1): Circuit Diagram of Tapped Tuned Circuit The frequency response of a tapped single tuned capacitance coupled amplifier is represented in figure (2).

The choice of configuration in a cascade of amplifiers depends on, (i) (ii) (i) Maximum voltage gain Impedance matching of the source and input circuit of first stage.

Gain1
1 2

Maximum Voltage Gain

For a common-collector configuration, the voltage gain is less than unity. Hence, such type of configuration is not commonly used in cascading applications. Similarly, for common-base configuration, the voltage gain is minimum and is equivalent to that of last stage alone. Due to this reason, CB configuration is occasionally used. For common-emitter configuration, the short circuit current gain (i.e., hfe) is usually greater than one, which inturn produces maximum voltage gain (when CE stages are cascaded). Hence CE configuration is the most suitable configuration in cascading of amplifiers. (ii) Impedance Matching Impedance matching is an another parameter taken into consideration while selecting transistor configuration in cascading of amplifiers. Irrespective of the voltage or current gain, common collector and common base configurations are most commonly employed because of their good impedance matching capabilities. Q3. (a) Draw the frequency response of tapped single tuned capacitance coupled amplifier and derive the expression for L for maximum power transfer. April/May-12, Set-1, Q3(a) M[8]

fL fM fH

frequency

Figure (2) The expression for Inductance (L) for maximum power transfer. Assume a tapping point which divides the impedence into two parts i.e., L1 and L2. Where, L1 = nL L2 = (1n) L On applying Kirchoffs Voltage Law (KVL) at the input and output terminals, we get, V1 = jL . I1 j (L2 + M) I2 0 = j (L1 + M) I1 + (Ri + jL2) I2 Where, M Mutual inductance between L1 and L2 Solving equations (1) and (2), we get, ... (1) ... (2)

Answer :

Circuit for tapped single tuned capacitor coupled amplifier is shown in figure (1).

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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Equation (1) R + jL2 and equation (2) j(L2 + M) I2 V1 (Ri + jL2) = jL (Ri + jL2) I1 j (L2 + M) (Ri + jL2) I2 0 = ( j) ( j) (L2 + m) (L1 + m) I1 + (Ri + jL2) (j) (L2 + M) I2 V1 (Ri + jL2) = jL (Ri + jL2) I1 + 2 (L2 + M) (L1 + M)I1 V1 (Ri + jL2) = [jL (Ri + jL2 + 2 (L2 + M) (L1 + M)] I1 I1 =
V1 ( Ri + jL2 ) jL( Ri + jL2 ) + 2 ( L1 + M )( L2 + M )

... (3)

The impedance Z provided by the coil with input resistance Ri is expressed as, Z1 =

V1 I1

V1 j L( Ri + j L2 ) + 2 ( L2 + M )( L1 + M ) Z1 = I = ( Ri + j L2 ) 1 j L( Ri + j L2 ) 2 ( L2 + M )( L1 + M ) + Ri + j L2 ( Ri + j L2 )

V1 2 ( L2 + M )( L1 + M ) Z1 = I = jL + Ri + jL2 1
Since, L2 << Ri (i.e., the input resistance of stage (ii) in k) Z1 = jL +

... (4)

2 ( L2 + M )( L1 + M ) Ri

... (5)

We know that, M = K L1 L2 Where, K = Coupling coefficient L1 = nL and L2 = (1 n) L M = K nL (1 n) L = K nL2 (1 n ) M = KL ( n n 2 ) On substituting K = 1, we get, M = L n n2 ... (6)

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

Replacing the value of M in equation (5), we get, Z1 = jL +

S.9

2 L2 + L n n 2
Ri

)( L + L n n )
2 1

[Q L2 = (1 n)L]

... (7)

2 2 2 (1 n) L + L n n nL + L n n = jL + Ri

2 L (1 n) + n n 2 .L n + n n 2 = jL + Ri
2 2 2 L2 (1 n) + n n n + n n = jL + Ri 2 2 2 2 2 L2 (1 n)n + (1 n) n n + n n n + n n . n n = jL + Ri 2 2 2 2 2 2 L2 n n + n n n n n + n n n + n n = jL + Ri

)(

= jL +

2 L2 (2n (1 n ) ) + n n 2 Ri

= jL + Ris ... (8) Therefore, the resistance effectively reflected in a series along with the coil with respect to resistance Ri is expressed as,
2 2 L2 2n(1 n) + n n Ris ~ Ri

Now, equating the resistance Ris in series with the coil L to resistance Rip in shunt which is given as, Rip =

( L ) 2 Ris

The equivalent circuit is as illustrated in figure (a).

g mVbe

C Ro

Rp

Rip

Source

Load

Figure (a)

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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

On further simplification, figure (a) is modified as illustrated in figure (b).

2Qe 2 o Qo L = Ro o Qo 2Qe o Ro
L=
Ro o Qo 2Qe o Ro
2 2QeQo o

gmVb e

Rtt

L Vo

Ro (Qo 2Qe ) 2Qe o Qo Ro (Qo 2Qe ) 2Qe o Qo

Figure (b) Where,

1 1 1 1 + + = Ro R p Rip Rtt

( tt - Tuned Tapped Circuit) Quality factor, Qe = Where, o =

Ro Qo 2Qe = 2Q Q 2Q Q o e o e o
=

Rtt o L

Ro o
Ro o

1 1 2Q Q o e

1 LC
(b)

L =

1 1 2Q Q o e

According to maximum power transfer theorem, The total resistance in a shunt with a coil is equal to Rop (where Rop = Ro || Rp) At resonance, Impedence ( Z) is purely resistive and for maximum power transfer, Z =
Rop R 2

Qe =

2 o L

Rop Q Rtt = 2

... (9)

Rop = 2 Qe oL

Ro R p Q Rop = Ro + R p

Ro R p 2 Qe oL = R + R o p Ro o Qo L 2 Qe oL = R + Q L o o o

(Q R

= o Qo L

Draw the circuit of double tuned amplifier and explain its working. Answer : April/May-12, Set-1, Q3(b) M[7] Double Tuned Amplifier For answer refer Unit-VIII, Q15, Topic: Circuit Diagram of Double Tuned Amplifier. Working of a Double Tuned Amplifier The input signal to be amplified is fed to the double tuned amplifier through coupling capacitor (Cc). By adjusting the values of tuned circuit (4 C1), its resonant frequency is made identical to that of input frequency. At this instant the tuned circuit provides a very high impedence to the input signal. As a result a large output is generated across the tuned circuit (L1 C1). The obtained output is then transmitted towards the inductively coupled tuned circuit L2 C2. Double tuned amplifiers find their major applications in radio and television receivers. Q4. What is a class B amplifier? Where is it employed? Give its circuits, design equations, characteristics and limitations. Answer : April/May-12, Set-1, Q4(a) M[10] Class B Amplifier Class B amplifier is also referred as class B power amplifier. In this amplifier, transistor is biased to cut-off such that the output power is obtained for 180 only i.e., half cycle for the full input cycle. (a)

... (10)

On solving equation (10) for L, we get, 2 Qe o (Ro + o QoL = Ro oQo 2 Qe o Ro + 2Qe 2 o Qo L = Ro oQo

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

Class B amplifiers are used to remove cross-over distortions in the linear power amplifier and tuned amplifiers (which are caused due to cut-in voltage at the transistor junctions). The circuits of push-pull and complementary symmetry configured class B amplifiers are as shown in figure (i) and (ii) respectively.
I1 Q1 Vi VCC I2 T1 Q2 RL

S.11

3.

The expression for AC output power generated during the positive half cycle is expressed as,
1 (V I ) 2 rms rms 1 VCC I m 2 2 2 VCC I m 4 V Q Vrms = CC 2 Im I rms = 2

Pac =

= 4.

Figure (i): Class-B Push-pull Amplifier

+VCC R1 P N

T2

The expression for maximum over all efficiency () is expressed as, =

Pac 100 Pdc

(or)

N Q1

R2 C

1 (Vm .I m ) 4 100 = 1 (Vm .I m )

P Q2 RL V 0

R3 Vin

~
R4

N P

100 4

= 78.5%
VCC

Figure (ii): Complementary Symmetry Class-B Amplifier The design equations of a class B amplifier are as follows, 1. The expression for maximum A.C power developed, (Pac)max
1 VCC 2 RL The input power given to the circuit is expressed as, (Pdc)dc = VCC Idc Where, Idc Peak value of average current and is given
2

Characteristics of a Class-B Amplifier 1. 2. The class B amplifier generates output current flow simply for 180 of input signal i.e., one half cycle. The transistor dissipates no power, when zero input signal is applied. However with an increase in input power, the resultant Ptr(dc) also increases. The overall efficiency of a class B amplifier is higher than that of class A amplifier.

(Pac)max =

2.

3.

Limitations/Disadvantages of class B Amplifier 1. 2. The main disadvantage of class B amplifier is the presence of higher harmonic distortion. It requires stabilised supply source as the current changes with respect to signal. In other words, the technique of self biasing cannot be implemented. The supply voltage must provide good regulation at the input.

Im as, Id = VCC I m Pdc =

The peak value of output current and voltage is expressed as, Im and Vm (or) VCC

3.

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(b)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 A transformer coupled class A large signal amplifier has maximum and minimum values of collector to emitter voltage of 25 V and 2.5 V. Determine its collector efficiency. April/May-12, Set-1, Q4(b) M[5]

rd

(+1)Rs

D + Vd +

Vg + + (+1)Vs

Answer : Given that,

id

V01

For a transformer coupled class A large signal amplifier, Collector to emitter voltage, VCE(max) = 25 V and VCE(min) = 2.5 V Collector efficiency () = ? The expression for collector efficiency () of a transformer coupled class-A amplifier is,

N
Figure (1): Equivalent Circuit of Generalized FET Amplifier from Drain to Ground Voltage gain, AV For a CS amplifier, AVS =

VCE (max) VCE (min) = 50 V CE (max) + VCE (min)

25 2.5 = 50 25 + 2.5

V01 Vg

... (1)

= 50 0.81 = 40.91 %

The expression for AVS is obtained from equivalent circuit in figure (1). Since, for a CS amplifier VS = Vd = 0 the equivalent circuit in figure (1) reduces to as shown in figure (2).
rd (+1)Rs D + Vg +

= 40.91%
Q5. (a) What are the characteristics of an amplifier that are modified by negative feedback? April/May-12, Set-1, Q5(a) M[5] Draw the four types of feedback amplifiers naming them. April/May-12, Set-1, Q5(b) M[5] Define sensitivity and desensitivity factors in feedback amplifiers. April/May-12, Set-1, Q5(c) M[5] Derive an expression for voltage gain of a common source FET amplifier with and without source resistance included in the circuit. April/May-12, Set-1, Q6(a) M[8]
id Rd

V01

Answer : (b) Answer : (c) Answer : Q6. (a)

For answer refer Unit-V, Q6.

Figure (2): Equivalent Circuit for CS Amplifier From figure (2), we have V01 = id Rd And id Rd + id ( + 1) RS + id rd = Vg id = ... (2)

For answer refer Unit-V, Q5.

Vg ( Rd + rd + ( + 1) RS )

... (3)

Substituting equation (3) in equation (2), we get, V01 =

For answer refer Unit-V, Q7.

Vg Rd ( Rd + rd + ( + 1) RS )

Answer : With Source Resistance

Rd V01 = ( Rd + rd + ( + 1) RS ) Vg
AVS = Rd Rd + rd + ( + 1) RS
... (4)

The Thevenins equivalent circuit of a generalized FET amplifier from drain to ground is as shown in figure (1).

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

Without Source Resistance A common source amplifier is as shown in figure (3).
VDD RD D G + Vi RG S RS V0 CS

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Figure (3): Common Source Amplifier The small signal equivalent circuit of common source amplifier is shown in figure (4).
G Vi + RG Vgs D id + V0

Vgs + S

RD

Figure (4) Voltage Gain The capacitor Cs is used as a bypass for source current. Because of Cs, Rs is removed. Applying KVL to source-drain loop, we get,
Vgs Vo + =0 RD rd + RD

RD Vgs RD + rd If Vgs = Vi V RD AV = o = Vi RD + rd (b) Calculate the voltage gain of the FET amplifier shown in the figure, assuming blocking capacitor to be large gm and rd are given as gm = 4mA/V and rd = 5K.
Vo =
VDD 50 K CD

+ VS + VGG

10 K

V0

Figure Answer : Given that, For a FET amplifier, Trans-conductance, gm = 4m A/v Drain resistance, rd = 5 k Voltage gain, Av = ? April/May-12, Set-1, Q6(b) M[7]

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1 1 1 1 + + = R rd RD RL

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

For large blocking capacitor CD : large blocking capacitors act as short circuit and the effective load = rd || RD || RL

RD RL + RL rd + rd RD (50 103 10 103 ) + (10 103 5 103 ) + (5 103 50 103 ) 800 106 = = rd RD RL 5 103 50 103 10 103 2.5 1012 1 1 = 3.2 104 R = R 3.2 10 4
=

Effective load resistance (R) = 3.125 k

The expression for voltage gain of the FET amplifier is given by, Voltage gain (AV) = gm Load resistance = (4 103) (3.125 103) = 12.5

AV = 12.5
The voltage gain of a FET amplifier is 12.5 V. Q7. (a) Explain why the upper 3-dB frequency for current gain is not the same as fH for voltage gain. Answer : April/May-12, Set-1, Q7(a) M[5] The upper 3-dB frequency for current gain can be explained with the help of current gain and upper 3-dB frequency product as,

RS fT . ... (1) 1 + 2 fT CC RL RS + rbb Similarly, the upper 3-dB frequency for voltage gain can be explained with the help of voltage gain and upper 3-dB frequency product as,
|AIS fH| = |AVS fH| =

fT RL . 1 + 2 fT CC RL RS + rbb

... (2)

Where, AIS - Current gain of an amplifier with Rs AVS - Voltage gain of an amplifier with Rs fH - Upper 3-dB frequency fT - Frequency at which short circuit current gain attains unit magnitude RL - Load resistance RS - Source resistance CC - Coupling capacitance rbb' - Base spreading resistance. From the equations (1) and (2) it is clear that the upper 3-dB frequencies for current gain and voltage gain are not unique and vary depending on the values of RS and RL. (b) A silicon PNP transistor has an fT = 400 MHz. What is the base thickness? Answer : April/May-12, Set-1, Q7(b) M[5] Given that, For a silicon pnp transistor fT = 400 MHz = 400 106 Hz Base thickness, W = ?

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

The expression for base-thickness of a transistor is given as, (ii) Base Spreading Resistance (rbb')

S.15

1 W = 6f T 6 DB DB W2 = f T DB f T

The base spreading resistance of a CE stage amplifier is given by, rbb' = hie
h fe gm

= hie rb'e

Since, rbb' depends on hfe and gm which are used to determine the frequency response, rbb' is also used to obtain the high frequency response of CE stage. (iii) Emitter Capacitance (Ce)

W=

Assume DB (Diffusion constant) = 13 cm2/sec W=

The emitter capacitance of a CE stage amplifier is given by, Ce

13 400 106

gm 2f T

= 1.034 10 8 = 1.017 104

fT is used to determine the frequency response of an amplifier. Hence, Ce is used to obtain the high frequency response of CE stage amplifier. (iv) Input Resistance (rb'e) The input resistance of CE amplifier is given by,

W = 1.017 10 4 cm
Base thickness is 1.017104 cm. (c) In terms of what parameters is the high frequency response of a CE stage obtained? April/May-12, Set-1, Q7(c) M[5]

Answer :

rb 'e =

h fe gm

The high frequency response of the CE stage amplifier is obtained from four hybrid parameters. They are, (i) (ii) (iii) (i) Transconductance amplifier (gm) Base spreading resistance (rbb') Emitter capacitances (CE)

hfe and gm are used to determine the frequency response of an amplifier. Hence, rb'e is used to obtain the high frequency response of a CE stage amplifier. Q8. (a) Draw the electrical model of a piezoelectric crystal. April/May-12, Set-1, Q8(a) M[4]

(iv) Input resistance (rb'e). Transconductance Amplifier (gm) The transcondutance of a CE transistor is given by,

Answer :

IC gm = V T
(or) gm =
h fe rb 'e

The symbol of a piezoelectric crystal is as illustrated in figure (1),

Crystal

Since, hfe determines the frequency response of the amplifier and gm depends on hfe, gm is used to obtain the high frequency response of CE stage.

Figure (1): Symbol of Piezoelectric Crystal

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B.Tech. II-Year II-Sem.

S.16

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

The electrical model of a piezoelectric crystal is as illustrated in figure (2).

L CS

CP

Figure (2): Electrical Model (b) Answer : Sketch the reactance Vs frequency function. April/May-12, Set-1, Q8(b) M[4]

The reactance Vs frequency plot of a piezoelectric crystal is as illustrated in figure below,

Reactance X

(inductive) fP

fS (capacitive)

f frequency

Figure Practically, the series and parallel resonating frequencies (i.e., fS and fP) are very close to each other. Thus, it can be stated that a crystal circuit, consists of only one resonating frequency. It offers better frequency stability because of its large quality factor (Q). On neglecting the resistance (R) (i.e., R = 0), the impedance of the crystal becomes a reactance (jx) which relies on the frequency such that,
2 j 2 S . 2 cM 2 p

jX = Where,

s - Series resonant frequency p - Parallel resonant frequency.

B.Tech. II-Year II-Sem.

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Electronic Circuit Analysis (April/May-2012, Set-1) JNTU-Hyderabad

(c) Answer :

S.17

Over what portion of the reactance curve do we desire oscillations to take place when the crystal is used as part of a sinusoidal oscillator. Explain. April/May-12, Set-1, Q8(c) M[7]

The crystal oscillator when used as part of a sinusoidal oscillator produces oscillations at a frequency interval between S and P. i.e., S < fosc < P (with S P) Where, S - Series resonance frequency P - Parallel resonance frequency. Figure (i) illustrates a circuit diagram of a basic crystal oscillator.

3 +AV

2 Z3

I=0 Z1 3

Z2

Figure (i) Figure (ii) illustrates a FET crystal oscillator which is used as part of a sinusoidal oscillator.

V L Cdg + Cstray G 1 MHz XTAL Rg D 2 N2608 S RS CS C Vo

Figure (ii)

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B.Tech. II-Year II-Sem.

S.18
Figure (ii) that the FET crystal oscillator employs, (i) (ii) (iii) A crystal inplace of Z1(jX1) Tuned LC combination inplace of Z2(jX2)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

Capacitance between drain and gate (i.e., Cdg) for Z3 (jX3). The general condition for a resonant circuit oscillator to oscillate is, loop Gain, A =

+ AV X1 1. X2

It can be noticed that for loop gain to exceed unity, X1 must be maintained very small (which is not possible practically). Thus the circuit starts oscillating for a frequency interval between S and P. As S P, the oscillator frequency is evaluated using crystal only.

B.Tech. II-Year II-Sem.

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