H

High CMR, High Speed TTL Compatible Optocouplers Technical Data

6N137 HCNW137 HCNW2601 HCNW2611 HCPL-0600 HCPL-0601 HCPL-0611 HCPL-0630

HCPL-0631 HCPL-0661 HCPL-2601 HCPL-2611 HCPL-2630 HCPL-2631 HCPL-4661

5 kV/s Minimum Common Mode Rejection (CMR) at VCM = 50 V for HCPL-X601/ X631, HCNW2601 and 10 kV/s Minimum CMR at VCM = 1000 V for HCPLX611/X661, HCNW2611 High Speed: 10 MBd Typical LSTTL/TTL Compatible Low Input Current Capability: 5 mA Guaranteed ac and dc Performance over Temperature: -40C to +85C Available in 8-Pin DIP, SOIC-8, Widebody Packages Strobable Output (Single Channel Products Only) Safety Approval UL Recognized - 2500 V rms for 1 minute and 5000 V rms* for 1 minute per UL1577 CSA Approved VDE 0884 Approved with VIORM = 630 V peak for HCPL-2611 Option 060 and VIORM = 1414 V peak for HCNW137/26X1 BSI Certified (HCNW137/26X1 Only) MIL-STD-1772 Version Available (HCPL-56XX/ 66XX)

Features

Applications
Isolated Line Receiver Computer-Peripheral Interfaces Microprocessor System Interfaces Digital Isolation for A/D, D/A Conversion Switching Power Supply Instrument Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement

Power Transistor Isolation in Motor Drives Isolation of High Speed Logic Systems

Description
The 6N137, HCPL-26XX/06XX/ 4661, HCNW137/26X1 are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is

Functional Diagram
6N137, HCPL-2601/2611 HCPL-0600/0601/0611 HCNW137/2601/2611 NC ANODE CATHODE NC 1 2 3 4 SHIELD 8 7 6 5 VCC VE VO GND ANODE 1 CATHODE 1 CATHODE 2 ANODE 2 HCPL-2630/2631/4661 HCPL-0630/0631/0661 1 2 3 4 SHIELD 8 7 6 5 VCC VO1 VO2 GND

TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H

TRUTH TABLE (POSITIVE LOGIC) LED ON OFF OUTPUT L H

*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only. A 0.1 F bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
1-146 5965-3594E

an open collector Schottkyclamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/s for the HCPL-X601/X631 and HCNW2601, and 10,000 V/s for the HCPL-X611/X661 and HCNW2611.

This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40C to +85C allowing troublefree system performance.

The 6N137, HCPL-26XX, HCPL06XX, HCPL-4661, HCNW137, and HCNW26X1 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments.

Selection Guide
Minimum CMR Input OnCurrent Output (mA) Enable 5 YES NO 5,000 10,000 1,000 3, 500 1,000 1,000[2] 1,000 50 1,000 50 300 50 1,000 50 12.5 3 YES NO YES NO YES YES YES NO YES NO
[3]

8-Pin DIP (300 Mil) Single Channel Package 6N137 HCPL-2630 HCPL-2601 HCPL-2631 HCPL-2611 HCPL-4661 HCPL-2602[1] HCPL-2612[1] HCPL-261A[1] HCPL-263A[1] HCPL-261N[1] HCPL-263N[1] Dual Channel Package

Small-Outline SO-8 Single Channel Package HCPL-0600 HCPL-0630 HCPL-0601 HCPL-0631 HCPL-0611 HCPL-0661 Dual Channel Package

Widebody (400 Mil) Single Channel Package HCNW137 HCNW2601 HCNW2611

dV/dt (V/s) NA

VCM (V) NA

Hermetic Single and Dual Channel Packages

HCPL-061A[1] HCPL-063A[1] HCPL-061N[1] HCPL-063N[1] HCPL-193X[1] HCPL-56XX[1] HCPL-66XX[1]

Notes: 1. Technical data are on separate HP publications. 2. 15 kV/s with VCM = 1 kV can be achieved using HP application circuit. 3. Enable is available for single channel products only, except for HCPL-193X devices.

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Ordering Information
Specify Part Number followed by Option Number (if desired). Example: HCPL-2611#XXX 020 = 5000 V rms/1 minute UL Rating Option* 060 = VDE 0884 VIORM = 630 Vpeak Option** 300 = Gull Wing Surface Mount Option 500 = Tape and Reel Packaging Option Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor for information.
*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only. **For HCPL-2611 only. Combination of Option 020 and Option 060 is not available. Gull wing surface mount option applies to through hole parts only.

Schematic
6N137, HCPL-2601/2611 HCPL-0600/0601/0611 HCNW137, HCNW2601/2611

HCPL-2630/2631/4661 HCPL-0630/0631/0661 ICC

ICC 8 IO 6

IF 2+

1
VCC VO

IF1

8 IO1 7

VCC VO1

+ VF1 2

VF 3 SHIELD IE 5 7 VE USE OF A 0.1 F BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5). GND

SHIELD 3 VF2 + 4 SHIELD 5 GND IF2 IO2 6

VO2

1-148

Package Outline Drawings

8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)

OPTION CODE* DATE CODE

HP XXXXZ YYWW RU 1 1.19 (0.047) MAX. 2 3 4

UL RECOGNITION

1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)

5 TYP. 4.70 (0.185) MAX.

0.51 (0.020) MIN. 2.92 (0.115) MIN.

1.080 0.320 (0.043 0.013)

0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010)

DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.

**JEDEC Registered Data (for 6N137 only).

8-pin DIP Package with Gull Wing Surface Mount Option 300 (6N137, HCPL-2601/11/30/31, HCPL-4661)
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5

1.016 (0.040) 1.194 (0.047)

4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)

1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)

0.381 (0.015) 0.635 (0.025)

1.19 (0.047) MAX.

4.19 MAX. (0.165)

+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)

1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.635 0.25 (0.025 0.010)

12 NOM.

1-149

Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)

3.937 0.127 (0.155 0.005)

XXX YWW

5.842 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE
4

0.381 0.076 (0.016 0.003)

1.270 BSG (0.050) 7 0.432 (0.017)

5.080 0.127 (0.200 0.005)

45 X

3.175 0.127 (0.125 0.005)

1.524 (0.060) 0.152 0.051 (0.006 0.002)

0.228 0.025 (0.009 0.001)

DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.305 MIN. (0.012)

8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)

11.15 0.15 (0.442 0.006)

8 7 6 5

11.00 MAX. (0.433) 9.00 0.15 (0.354 0.006) TYPE NUMBER DATE CODE

HP HCNWXXXX YYWW

1.55 (0.061) MAX.

10.16 (0.400) TYP. 7 TYP. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 5.10 MAX. (0.201)

3.10 (0.122) 3.90 (0.154) 2.54 (0.100) TYP. 1.78 0.15 (0.070 0.006) 0.40 (0.016) 0.56 (0.022)

0.51 (0.021) MIN.

DIMENSIONS IN MILLIMETERS (INCHES).

1-150

8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW137, HCNW2601/11)
11.15 0.15 (0.442 0.006)
8 7 6 5

PAD LOCATION (FOR REFERENCE ONLY)

6.15 (0.242)TYP. 9.00 0.15 (0.354 0.006) 12.30 0.30 (0.484 0.012)
1 2 3 4

1.3 (0.051) 1.55 (0.061) MAX. 12.30 0.30 (0.484 0.012) 11.00 MAX. (0.433)

0.9 (0.035)

4.00 MAX. (0.158)

1.78 0.15 (0.070 0.006) 2.54 (0.100) BSC 0.75 0.25 (0.030 0.010)

1.00 0.15 (0.039 0.006)

+ 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 7 NOM.

DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount Option 300 Parts)
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 1 T = 145C, 1C/SEC T = 115C, 0.3C/SEC

TEMPERATURE C

T = 100C, 1.5C/SEC

10

11

12

TIME MINUTES

Note: Use of nonchlorine activated fluxes is highly recommended.

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Regulatory Information
The 6N137, HCPL-26XX/06XX/ 46XX, and HCNW137/26XX have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361.

CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92. (HCPL-2611 Option 060 and HCNW137/26X1 only)

BSI Certification according to BS415:1994 (BS EN60065:1994), BS7002:1992 (BS EN60950:1992) and EN41003:1993 for Class II applications. (HCNW137/26X1 only)

Insulation and Safety Related Specifications

8-pin DIP (300 Mil) Value 7.1 SO-8 Value 4.9 Widebody (400 Mil) Value Units 9.6 mm

Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance)

Symbol L(101)

L(102)

7.4

4.8

10.0

mm

0.08

0.08

1.0

mm

Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) Isolation Group

NA

NA

4.0

mm

CTI

200

200

200

Volts

Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Measured from input terminals to output terminals, along internal cavity. DIN IEC 112/VDE 0303 Part 1

IIIa

IIIa

IIIa

Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

1-152

VDE 0884 Insulation Related Characteristics (HCPL-2611 Option 060 Only)

Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I-IV I-III 55/85/21 2 630 1181 Units

VIORM VPR

V peak V peak

VPR

945

V peak

VIOTM

6000

V peak

TS IS,INPUT PS,OUTPUT RS

175 230 600 109

C mA mW

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only)

Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 600 V rms for rated mains voltage 1000 V rms Climatic Classification (DIN IEC 68 part 1) Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I-IV I-III 55/100/21 2 1414 2651 Units

VIORM VPR

V peak V peak

VPR

2121

V peak

VIOTM

8000

V peak

TS IS,INPUT PS,OUTPUT RS

150 400 700 109

C mA mW

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

1-153

Absolute Maximum Ratings* (No Derating Required up to 85C)

Parameter Storage Temperature Operating Temperature Average Forward Input Current Symbol TS TA IF Package** Min. -55 -40 Max. 125 85 20 Units C C mA Note

Reverse Input Voltage Input Power Dissipation Supply Voltage (1 Minute Maximum) Enable Input Voltage (Not to Exceed VCC by more than 500 mV) Enable Input Current Output Collector Current Output Collector Voltage (Selection for Higher Output Voltages up to 20 V is Available.) Output Collector Power Dissipation

VR PI VCC VE

Single 8-Pin DIP Single SO-8 Widebody Dual 8-Pin DIP Dual SO-8 8-Pin DIP, SO-8 Widebody Widebody

15 5 3 40 7 VCC + 0.5 V mW V V

1, 3 1

Single 8-Pin DIP Single SO-8 Widebody

IE IO VO

5 50 7

mA mA V

1 1

PO

Lead Solder Temperature (Through Hole Parts Only)

TLS

Single 8-Pin DIP Single SO-8 Widebody Dual 8-Pin DIP Dual SO-8 8-Pin DIP Widebody

85

mW

60 260C for 10 sec., 1.6 mm below seating plane 260C for 10 sec., up to seating plane See Package Outline Drawings section

1, 4

Solder Reflow Temperature Profile (Surface Mount Parts Only)

SO-8 and Option 300

*JEDEC Registered Data (for 6N137 only). **Ratings apply to all devices except otherwise noted in the Package column. 0C to 70C on JEDEC Registration.

Recommended Operating Conditions

Parameter Input Current, Low Level Input Current, High Level[1] Power Supply Voltage Low Level Enable Voltage High Level Enable Voltage Operating Temperature Fan Out (at RL = 1 k)[1] Output Pull-up Resistor Symbol IFL* IFH** VCC VEL VEH TA N RL Min. 0 5 4.5 0 2.0 -40 330 Max. 250 15 5.5 0.8 VCC 85 5 4k Units A mA V V V C TTL Loads

*The off condition can also be guaranteed by ensuring that VFL 0.8 volts. **The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband. For single channel products only.

1-154

Electrical Specifications
Over recommended temperature (TA = -40C to +85C) unless otherwise specified. All Typicals at VCC = 5 V, TA = 25C. All enable test conditions apply to single channel products only. See note 5.
Parameter High Level Output Current Input Threshold Current Low Level Output Voltage High Level Supply Current Sym. IOH* ITH Package All Single Channel Widebody Dual Channel 8-Pin DIP SO-8 Widebody Single Channel Dual Channel Low Level Supply Current ICCL Single Channel Dual Channel High Level Enable Current Low Level Enable Current High Level Enable Voltage Low Level Enable Voltage Input Forward Voltage IEH IEL* VEH VEL VF 8-Pin DIP SO-8 Widebody 8-Pin DIP SO-8 Widebody 8-Pin DIP SO-8 Widebody 8-Pin DIP SO-8 Widebody 1.4 1.3 1.25 1.2 5 3 -1.6 -1.9 60 70 pF f = 1 MHz, VF = 0 V 1 mV/C 1.5 1.64 2.0 0.8 1.75* 1.80 1.85 2.05 Single Channel Min. Typ. 5.5 2.0 2.5 0.35 0.4 7.0 6.5 10 9.0 8.5 13 -0.7 -0.9 10.0* 15 13.0* 21 -1.6 -1.6 mA mA V V V TA = 25C TA = 25C V IR = 10 A IR = 100 A, TA = 25C IF = 10 mA 7 1 1 IF = 10 mA 6, 7 1 mA mA 0.6 V Max. 100 5.0 Units A mA Test Conditions VCC = 5.5 V, VE = 2.0 V, VO = 5.5 V, IF = 250 A VCC = 5.5 V, VE = 2.0 V, VO = 0.6 V, IOL (Sinking) = 13 mA VCC = 5.5 V, VE = 2.0 V, IF = 5 mA, IOL (Sinking) = 13 mA VE = 0.5 V VCC = 5.5 V IF = 0 mA VE = VCC Both Channels VE = 0.5 V VCC = 5.5 V IF = 10 mA VE = VCC Both Channels VCC = 5.5 V, VE = 2.0 V VCC = 5.5 V, VE = 0.5 V 9 19 Fig. 1 2, 3 Note 1, 6, 19 19

VOL*

2, 3, 4, 5

1, 19

ICCH

Input Reverse Breakdown Voltage Input Diode Temperature Coefficient Input Capacitance

BVR*

VF / TA CIN

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0C to +70C. HP specifies -40C to +85C.

1-155

Switching Specifications (AC)

Over Recommended Temperature (TA = -40C to +85C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. All Typicals at TA = 25C, VCC = 5 V.
Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Skew Output Rise Time (10-90%) Output Fall Time (90-10%) Propagation Delay Time of Enable from VEH to VEL Propagation Delay Time of Enable from VEL to VEH Sym. tPLH Package** Min. Typ. 20 48 Max. 75* 100 75* 100 35 40 40 24 10 Single Channel 30 ns ns ns ns RL = 350 , CL = 15 pF, VEL = 0 V, VEH = 3 V 12 12 13, 14 Units Test Conditions Fig. ns TA = 25C RL = 350 8, 9, CL = 15 pF 10 ns TA = 25C Note 1, 10, 19 1, 11, 19 8, 9, 13, 19 10, 11 12, 13, 19 1, 19 1, 19 14

tPHL

25

50

|tPHL - tPLH|

8-Pin DIP SO-8 Widebody

3.5

ns

tPSK tr tf tELH

tEHL

Single Channel

20

ns

15

*JEDEC registered data for the 6N137. **Ratings apply to all devices except otherwise noted in the Package column.

Parameter Logic High Common Mode Transient Immunity

Logic Low Common Mode Transient Immunity

Sym. Device |CMH| 6N137 HCPL-2630 HCPL-0600/0630 HCNW137 HCPL-2601/2631 HCPL-0601/0631 HCNW2601 HCPL-2611/4661 HCPL-0611/0661 HCNW2611 |CML| 6N137 HCPL-2630 HCPL-0600/0630 HCNW137 HCPL-2601/2631 HCPL-0601/0631 HCNW2601 HCPL-2611/4661 HCPL-0611/0661 HCNW2611

Min.

Typ. Units 10,000 V/s

Test Conditions |VCM| = 10 V VCC = 5 V, IF = 0 mA, VO(MIN) = 2 V, RL = 350 , TA = 25C |VCM| = 50 V |VCM| = 1 kV

Fig. 15

Note 1, 16, 18, 19

5,000

10,000

10,000 15,000

10,000

V/s

|VCM| = 10 V

VCC = 5 V, IF = 7.5 mA, VO(MAX) = 0.8 V, RL = 350 , TA = 25C

15

1, 17, 18, 19

5,000

10,000

|VCM| = 50 V |VCM| = 1 kV

10,000 15,000

1-156

Package Characteristics
All Typicals at TA = 25C.
Parameter Input-Output Insulation Input-Output Momentary Withstand Voltage** Input-Output Resistance Input-Output Capacitance Input-Input Insulation Leakage Current Resistance (Input-Input) Capacitance (Input-Input) Sym. II-O* VISO Package Single 8-Pin DIP Single SO-8 8-Pin DIP, SO-8 Widebody OPT 020 8-Pin DIP, SO-8 Widebody 8-Pin DIP, SO-8 Widebody Dual Channel 2500 5000 5000 1012 1011 1012 1013 0.6 0.5 0.005 Min. Typ. Max. 1 Units A V rms Test Conditions 45% RH, t = 5 s, VI-O = 3 kV dc, TA = 25C RH 50%, t = 1 min, TA = 25C VI-O = 500 V dc TA = 25C TA = 100C pF 0.6 A RH 45%, t = 5 s, VI-I = 500 V f = 1 MHz, TA = 25C Fig. Note 20, 21 20, 21 20, 22 1, 20, 23 1, 20, 23 24

RI-O

CI-O II-I

RI-I CI-I

Dual Channel Dual 8-Pin DIP Dual SO-8

1011 0.03 0.25

pF f = 1 MHz

24 24

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0C to 70C. HP specifies -40C to 85C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled Optocoupler Input-Output Endurance Voltage. For 6N137, HCPL-2601/2611/2630/2631/4661 only.

Notes: 1. Each channel. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. 4. Derate linearly above 80C free-air temperature at a rate of 2.7 mW/C for the SOIC-8 package. 5. Bypassing of the power supply line is required, with a 0.1 F ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 A. HP guarantees a maximum IOH of 100 A. 7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. HP guarantees a maximum ICCH of 10 mA. 8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. HP guarantees a maximum ICCL of 13 mA. 9. The JEDEC registration for the 6N137 specifies a maximum IEL of 2.0 mA. HP guarantees a maximum IEL of -1.6 mA. 10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions. 13. See application section titled Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew for more information. 14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V). 17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V). 18. For sinusoidal voltages, (|dVCM | / dt)max = fCMVCM(p-p).

1-157

19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. For single channel products only. 20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only. 24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.

IOH HIGH LEVEL OUTPUT CURRENT A

15

6
VO OUTPUT VOLTAGE V
VCC = 5.5 V VO = 5.5 V VE = 2.0 V* IF = 250 A

8-PIN DIP, SO-8 VCC = 5 V TA = 25 C

6
VO OUTPUT VOLTAGE V

WIDEBODY VCC = 5 V TA = 25 C

5 4 3

5 4 3

10

* FOR SINGLE CHANNEL PRODUCTS ONLY

RL = 350 RL = 1 K

RL = 350 RL = 1 K

2 RL = 4 K 1 0

2 RL = 4 K 1 0

0 -60 -40 -20

20

40

60

80 100

TA TEMPERATURE C

IF FORWARD INPUT CURRENT mA

IF FORWARD INPUT CURRENT mA

Figure 1. Typical High Level Output Current vs. Temperature.

Figure 2. Typical Output Voltage vs. Forward Input Current.

ITH INPUT THRESHOLD CURRENT mA

6 5 4

ITH INPUT THRESHOLD CURRENT mA

8-PIN DIP, SO-8 VCC = 5.0 V VO = 0.6 V

WIDEBODY 6 5 4 3 RL = 1 K 2 1 RL = 4 K 0 -60 -40 -20 0 20 40 60 80 100 VCC = 5.0 V VO = 0.6 V

RL = 350 K 3 2 1 RL = 4 K 0 -60 -40 -20 0 20 40 60 80 100 RL = 1 K

RL = 350

TA TEMPERATURE C

TA TEMPERATURE C

Figure 3. Typical Input Threshold Current vs. Temperature.

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0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

IOL LOW LEVEL OUTPUT CURRENT mA

VOL LOW LEVEL OUTPUT VOLTAGE V

VOL LOW LEVEL OUTPUT VOLTAGE V

8-PIN DIP, SO-8 VCC = 5.5 V VE = 2.0 V* IF = 5.0 mA * FOR SINGLE CHANNEL PRODUCTS ONLY

WIDEBODY 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -60 -40 -20 0 20 40 60 80 100 IO = 9.6 mA IO = 6.4 mA IO = 16 mA IO = 12.8 mA VCC = 5.5 V VE = 2.0 V IF = 5.0 mA

70 VCC = 5.0 V VE = 2.0 V* VOL = 0.6 V 60 IF = 10-15 mA 50 * FOR SINGLE CHANNEL PRODUCTS ONLY

IO = 16 mA

IO = 12.8 mA

IO = 9.6 mA

IO = 6.4 mA

40

IF = 5.0 mA

0 -60 -40 -20

20

40

60

80 100

20 -60 -40 -20

20

40

60

80 100

TA TEMPERATURE C

TA TEMPERATURE C

TA TEMPERATURE C

Figure 4. Typical Low Level Output Voltage vs. Temperature.

Figure 5. Typical Low Level Output Current vs. Temperature.

1000
IF FORWARD CURRENT mA

8-PIN DIP, SO-8

IF FORWARD CURRENT mA

110 100 10 1.0 0.1 0.01

WIDEBODY TA = 25 C IF + VF

TA = 25 C 100 10 1.0 0.1 0.01 IF + VF

0.001 1.1

1.2

1.3

1.4

1.5

1.6

0.001 1.2

1.3

1.4

1.5

1.6

1.7

VF FORWARD VOLTAGE V

VF FORWARD VOLTAGE V

Figure 6. Typical Input Diode Forward Characteristic.

dVF/dT FORWARD VOLTAGE TEMPERATURE COEFFICIENT mV/C

-2.2 -2.0 -1.8 -1.6 -1.4 -1.2 0.1

dVF/dT FORWARD VOLTAGE TEMPERATURE COEFFICIENT mV/C

-2.4

8-PIN DIP, SO-8

-2.3

WIDEBODY

-2.2

-2.1

-2.0

-1.9 -1.8 0.1

10

100

10

100

IF PULSE INPUT CURRENT mA

IF PULSE INPUT CURRENT mA

Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.

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SINGLE CHANNEL PULSE GEN. ZO = 50 t f = t r = 5 ns IF 1 2 INPUT MONITORING NODE RM 3 4 VCC 8 7 6

PULSE GEN. Z O = 50 t f = t r = 5 ns

+5 V

DUAL CHANNEL IF 1 VCC 8

+5 V

0.1F BYPASS

RL

INPUT MONITORING NODE

RL 2 7 0.1F BYPASS C L* 4 GND 5

OUTPUT VO MONITORING NODE

*CL GND 5

OUTPUT VO MONITORING NODE

3 RM

*CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.

INPUT IF t PHL OUTPUT VO t PLH IF = 7.50 mA IF = 3.75 mA

1.5 V

Figure 8. Test Circuit for tPHL and tPLH.

100
tP PROPAGATION DELAY ns

tP PROPAGATION DELAY ns

VCC = 5.0 V IF = 7.5 mA tPLH , RL = 4 K

105

VCC = 5.0 V TA = 25C tPLH , RL = 4 K

80 tPHL , RL = 350 1 K 60 4 K 40

90

75 tPLH , RL = 350 tPLH , RL = 1 K tPHL , RL = 350 1 K 4 K 5 7 9 11 13 15

tPLH , RL = 1 K tPLH , RL = 350

60

20

45 30

0 -60 -40 -20

20

40

60

80 100

TA TEMPERATURE C

IF PULSE INPUT CURRENT mA

Figure 9. Typical Propagation Delay vs. Temperature.

Figure 10. Typical Propagation Delay vs. Pulse Input Current.

PWD PULSE WIDTH DISTORTION ns

40

30 VCC = 5.0 V IF = 7.5 mA 20 RL = 350

tr, tf RISE, FALL TIME ns

RL = 4 k

VCC = 5.0 V IF = 7.5 mA

tRISE tFALL

300 290 60

RL = 4 k

10

RL = 1 k 40 20 0 -60 -40 -20 RL = 350 RL = 350 , 1 k, 4 k 0 20 40 60 80 100

0 RL = 1 k -10 -60 -40 -20 0 20 40 60 80 100

TA TEMPERATURE C

TA TEMPERATURE C

Figure 11. Typical Pulse Width Distortion vs. Temperature.

Figure 12. Typical Rise and Fall Time vs. Temperature.

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PULSE GEN. Z O = 50 t f = t r = 5 ns

INPUT VE MONITORING NODE +5 V 1 VCC 8 0.1 F BYPASS RL OUTPUT VO MONITORING NODE INPUT VE t EHL OUTPUT VO t ELH 3.0 V 1.5 V

7.5 mA IF

6 *C L

1.5 V

GND

5 *C L IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.

Figure 13. Test Circuit for tEHL and tELH.

tE ENABLE PROPAGATION DELAY ns

120

VCC = 5.0 V VEH = 3.0 V VEL = 0 V 90 IF = 7.5 mA tELH, RL = 4 k 60 tELH, RL = 1 k

30

tELH, RL = 350

tEHL, RL = 350 , 1 k, 4 k 0 -60 -40 -20 0 20 40 60 80 100 TA TEMPERATURE C

Figure 14. Typical Enable Propagation Delay vs. Temperature.

IF
SINGLE CHANNEL IF B A VFF 2 3 4 GND VCM + PULSE GENERATOR Z O = 50 7 6 5 1 VCC 8 0.1 F BYPASS RL OUTPUT VO MONITORING NODE +5 V

B A 1 2 VFF 3 4

DUAL CHANNEL VCC 8 RL 7 6 GND VCM + PULSE GENERATOR Z O = 50 5 0.1 F BYPASS +5 V OUTPUT VO MONITORING NODE

VCM (PEAK) VCM VO 0V 5V SWITCH AT A: IF = 0 mA VO (MIN.) SWITCH AT B: IF = 7.5 mA VO (MAX.) 0.5 V CML

CMH

VO

Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.

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OUTPUT POWER PS, INPUT CURRENT IS

OUTPUT POWER PS, INPUT CURRENT IS

800 700 600 500 400 300 200 100 0 0 25

HCPL-2611 OPTION 060 PS (mW) IS (mA)

HCNWXXXX PS (mW) 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 IS (mA)

50

75 100 125 150 175 200

TS CASE TEMPERATURE C

TS CASE TEMPERATURE C

Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.

GND BUS (BACK) VCC BUS (FRONT)

NC ENABLE
0.1F

NC

OUTPUT

10 mm MAX. (SEE NOTE 5)

SINGLE CHANNEL DEVICE ILLUSTRATED.

Figure 17. Recommended Printed Circuit Board Layout.

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SINGLE CHANNEL DEVICE VCC1 5 V 470 IF + D1* VF 1 3 SHIELD VE 7 2 5 0.1 F BYPASS GND 2 2 6 8 390 5V VCC2

GND 1

*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.

DUAL CHANNEL DEVICE CHANNEL 1 SHOWN VCC1 5 V 470 IF + D1* VF GND 1 1 2 SHIELD 2 5 0.1 F BYPASS GND 2 1 7 8 390 5V VCC2

Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.

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Propagation Delay, PulseWidth Distortion and Propagation Delay Skew

Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure 8). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-l, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applica-

tions where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 19, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 20 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock

signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 20 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.

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DATA

IF

50%

INPUTS CLOCK

VO

1.5 V

IF

50%

DATA OUTPUTS

t PSK

VO

1.5 V t PSK

CLOCK

t PSK

Figure 19. Illustration of Propagation Delay Skew - tPSK.

Figure 20. Parallel Data Transmission Example.

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