Interconnect Scaling

Prof. Krishna Saraswat

Department of Electrical Engineering

Stanford University
Stanford, CA 94305
[email protected]

araswat
tanford University 1 EE311 / Interconnect Scaling

 Why should we look at interconnects?

 Basics and Background
 Interconnect Parameters: resistance, capacitance,inductance
 Interconnect Metrics: Delay and Area Calculations

 Scaling Related Issues: Delay

 Problems
 Solutions

 Scaling Related Issues: Power

 Current Interconnect Technology

araswat
tanford University 2 EE311 / Interconnect Scaling

1
 Scaling of Minimum Feature size and Chip
Area

104
Mimimum Geometry (µm)

10

Chip Area (mm2)

pr oduction
3
1 10

logic
de velopment
0.1 2
10
memor
memoryy

0.01
1970 1980 1990 2000 2010 1
10
Year 1970 1980 1990 2000 2010
Year
Ref. A. Loke, PhD Thesis, Stanford Univ. 1999

araswat
tanford University 3 EE311 / Interconnect Scaling

Scaling of a chip and interconnections

araswat
tanford University 4 EE311 / Interconnect Scaling

2
 Scaling of global interconnections

New (scaled)
Old

 Chip area increases with each node

 Device dimensions are scaled
 Scaled wires are:
• Longer (chip area scaling)
• Thinner (minimum dimension scaling)
araswat
tanford University 5 EE311 / Interconnect Scaling

On-chip wires are getting slower

Old New (scaled)

101
Delay Time (ns)

Longest Interconnect Delay Wire length Scaling

Global Local
100

10-1 Future

Typical Gate Delay

10-2 60 80 100 120 140 160 180
Technology Node (nm)

• Scaled devices are faster

• Scaled wires longer and thinner
⇒ Wire delays are deteriorating with scaling
araswat
tanford University 6 EE311 / Interconnect Scaling

3
  Why should we look at interconnects?
 Basics and Background
 Interconnect Parameters: resistance, capacitance,inductance
 Interconnect Metrics: Delay and Area Calculations

 Scaling Related Issues: Delay

 Scaling Related Issues: Power
 Current Interconnect Technology

araswat
tanford University 7 EE311 / Interconnect Scaling

Types of Interconnects
 Dimension based
• Local
• Intermediate/semiglobal
• Global
 Function based
• Signaling
• Clocking
• Power/ground distribution

Global Local

Cross Sectional View:

For Height, Width and Spacing

Top View: For Length

araswat
tanford University 8 EE311 / Interconnect Scaling

4
 Performance Metrics
• Signaling • Clocking
• Delay • Timing uncertainty
• Power dissipation (skew and jitter)
• Bandwidth • Power dissipation
• Data reliability (Noise) • Slew rate
• Cross talk • Area
• Impedance mismatch
• Area • Power Distribution
• Supply reliability
• Reliability
• Electromigration
• Depend on R, C and L !
• Function and length dictates relative importance

araswat
tanford University 9 EE311 / Interconnect Scaling

Line Resistance and Capacitance

L
R=!
WH

WL
CILD = K ox"o
X ox

HL
AR=H/W
CIMD = K ox"o
LS
!
• What metrics does Resistance impact????
•With scaling of technology L increases, Xox, LS W and H decrease
• As a result R, Cox and CI increase
araswat
!
tanford University 10 EE311 / Interconnect Scaling

5
 Capacitance in Multilayer Structures
500
CAPACITANCE
M3

Capacitance (fF/mm)
400 Line To Ground
Line To Line
CILD Total
300
H M2
Cintot
W CIMD 200
AR=H/W
CIMD CILD

M1
100

Capacitance (fF/mm)
In general 0
! ILD 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Cinttot =C ILD +C IMD =2l( +! IMD AR )
AR Space Width (!m) [=Line Width]

araswat
tanford University 11 EE311 / Interconnect Scaling

Capacitance: Impact on Interconnect Metrics

RC-Delay
* ' RCint tot
Power
P =)Cint totV 2 f ' Cint tot
Crosstalk Higher Packing Density
C 1 ⇓
X talk ' IMD = Decreased Space Between
Cint tot & ( ILD # Interconnects
$ ( IMD !"
1+ % ⇓
AR 2 Higher RC-Delay, power and
crosstalk

Capacitance Reduction is Important for Performance Enhancement

araswat
tanford University 12 EE311 / Interconnect Scaling

1
 What Capacitance to Use for Delay?
Depends on switching condition on adjacent wires
• Nominal
CILD
Cinttot=CIMD+CILD
SC
o o
IMD

Not only total capacitance

plays a role in delay, IMD
plays a very import. Role
• Worst Case
Cinttot=2CIMD+CILD S

CIMD ~ 70% of Cinttot

• Best Case
Cinttot=CILD
S

araswat
tanford University 13 EE311 / Interconnect Scaling

Interconnect Parameters at High Frequencies

• In general complicated: No dedicated return paths

• Resistance: R(f)
– Two components: signal and return path
– Frequency effects
– Current distribution in signal (Skin effect) s
– Return path choice, thus resistance

• Inductance: L(f)
– Self: Area enclosed between signal & return path Return
(larger area => larger L): Can effect delay path Current dist.
– Mutual: Effects crosstalk (long range)
in signal wire
• Capacitance: C(f)
– Relatively constant

How is current distribution in signal and its

return path determined ??
araswat
tanford University 14 EE311 / Interconnect Scaling

7
 Current Distribution and Return Path

• Impedance (Z) is minimized • At high frequency minimizes L

• Return path closer
• At lower frequency minimizes R
R + jwL
Z= • Return path could be far away
G + jwC if it lowers return resistance

S Higher S R
Frequency

L ~ 0.3-0.7 nH/mm
C ~ 0.15-0.25 pF/mm Z0= (L/C)1/2 ~ 35- 65Ω

araswat
tanford University 15 EE311 / Interconnect Scaling

What About Skin Effect for Resistance?

• Copper
1 2.1
Skin Depth = = f in GHz, S.D in µm
"µ#f f

• Be careful when comparing skin depth to dimensions

! • Which dimension?: tall vs. wide
• Depends on the return path
• Frequency of interest is not clock freq. But rise time associated freq.

• Example: f = 3GHz ⇒ skin depth = 1.2µm

1.2µm

1 µm

3 µm
Case 2: Not important
Case 1: Important (from sides)
(from vertical direction)
araswat
tanford University 16 EE311 / Interconnect Scaling

8
 Summary: R, L and C Parameters

 Can we not model anything because of complexity of R and L?

 No, there is a lot we can predict without frequency dependencies
Using Rdc and C
• Most interconnects are still not skin effect limited: Rdc ok
• L is not so important for delay
• Delay and power important for most interconnects
 Rdc, we need to model more accurately

araswat
tanford University 17 EE311 / Interconnect Scaling

Important Point About Interconnect Delay:

Don’t Neglect the Driver!
Zdr, Cdiff R w , Cw , L w , , l CL

l
Zdr : Driver resistance
• Driver Delay (
Z dr Cdiff + Cwl + CL ) Z0 : Characteristic impedance of wire
ν : Velocity
• Interconnect Delay
– LC regime l = l LwCw = Lw Cwl = Z0 ( Cwl )
v Cw
– RC regime ( 0.5 Rwl )( Cwl + C L )

• Total Delay combination of three delays

• Dominant component depends on
– wire dimensions
– driver size: larger =>lower Zdr & higher Cdiff
• Delay RC only under certain conditions !!!
araswat
tanford University 18 EE311 / Interconnect Scaling

9
 Delay: Local wires
Zdr>Z0 (slope)
Local wires

Delay Delay ~ Z dr ( Cdiff + Cwl + CL )

e la y
rD
iv e C LC
Dr R

Zdr(Cdiff+CL) Interconnect Delay

Length

• Driver small, wire length short, cross section small => Zdr>Z0
• Inductance (LC) almost never important
• Mostly driver delay dominates => want low Cw
• Power (CV2f) is dominated by the transistor capacitance for most
of the local wires

araswat
tanford University 19 EE311 / Interconnect Scaling

Delay: Semiglobal and Global Wires

Zdr < Z0
Zdr > Z0 (slope)
Global wires
global wires
RC
Delay
Delay

y
e la LC
rD elay
r iv
e
R
C LC Driver D
D

Interconnect Delay 2 Z0
Length
lcrit !
Length Rw

Case 1 (Small driver) Case 2a (Large driver) Case 2b (Large driver)

• Zdr> Z0 (same as local wire case) • Zdr < Z0 and l<lcrit (Rwl/2Z0 < 1) • Zdr < Z0 and l>lcrit (Rwl/2Z0 >1)
• Inductance not important • Inductance important • Inductance not important
• Entire RLC model must be • Slow diffused RC signal
Delay ! Z dr ( Cdiff + Cwl + CL ) + 0.5 RwCwl 2
considered
Delay ! 0.5 RwCwl 2
• Delay has another component
– number of round trips needed to ring up the line (Z0 >Zdr desirable)
• Inductance only important for case 2a
• Very long wires => RC delay conservative (diffuse RC transmission line model better)
• Power (CV2 f) dominated by the wire capacitance
araswat
tanford University 20 EE311 / Interconnect Scaling

10
 Delay: When is inductance important? (II)
Technology Node (µm)
0.18 0.15 0.12 0.1 0.07 0.05 0.035

ALD Kapur et. al. , IEEE Trans. Elec. Dev., April 2002
Resistive
Ideal Cu
Regime resistivity • Global wires are becoming more
RC in terms of delay in future
* L=2 nH/mm
L=1 nH/mm
L=0.2 nH/mm
• However L is still very important
in Cross talk (long range) and noise

Inductive Regime
• L also important in delay for wide
global wires

2.77 Lw Z
lcrit = = 2.77 0 J. A. Davis et. al. Proc. IEEE, March 2001
Rw Cw Rw
araswat
tanford University 21 EE311 / Interconnect Scaling

Chip Size

Memory: SRAM, DRAM Logic, e.g., µ-Processors

PMOS Μ3

Μ2

Μ1
NMOS

• Device Size Limited • Wire Pitch Limited

• Regular compact structure • irregular structure
• Needs fewer interconnect • Needs more interconnect
levels
levels
• Performance impacted more
by interconnects
araswat
tanford University 22 EE311 / Interconnect Scaling

11
 Wire-length distribution
1E8
Local Semiglobal Global
1E6
global
1E4 LSemi-global

1E2

2D semiglobal
1E0 LLocal

3D
1E-2
local
1E-4

1 10 100 1000
Interconnect Length, l (gate pitches)

• Wire-length distribution (in terms of gate pitches) for a futuristic logic circuit
with 180 million gates.
• Metal tiers determined by LLoc and LSemi-global boundaries defined by design
constraints, such as maximum allowable delay, current density, etc.
• More wires can be accommodated in the lower levels.
• By placing wires in higher levels design constraints can be met but will
need more metal levels
araswat
tanford University 23 EE311 / Interconnect Scaling

Rent’s Rule
1000

Rent's Rule fit

Intel Data

N gates
Number of I/O pins, T

100

T = k NP TT=2.09
= 2.09 N0.36
N^(0.36)
T = # of I/O terminals 10
N = # of gates
k = avg. I/O’s per gate
P = Rent’s exponent

1
1E+02 1E+04 1E+06
Number of Gates, N
araswat
tanford University 24 EE311 / Interconnect Scaling

12
 Determination of Wire-length Distribution

• Conservation of I/O’s
Block A with NA gates
TA + TB + TC = TA-to-B + TA-to-C + TB-to-C + TABC
TA-to-B = TA + TB -TAB
TB-to-C = TB+ TC -TBC Block B
• Values of T within a block or collection of
blocks are calculated using Rent’s rule,
e.g.,
TA = k (NA) P
TABC = k (NA+ NB+ NC) P
• Recursive use of Rent’s rule gives wire-
length distribution for the whole chip
Block C

Ref: Davis & Meindl, IEEE TED, March 1998

araswat
tanford University 25 EE311 / Interconnect Scaling

 Why should we look at interconnects?

 Basics and Background
 Scaling Related Issues: Delay
 Problems
 Solutions

 Scaling Related Issues: Power

 Current Interconnect Technology

araswat
tanford University 26 EE311 / Interconnect Scaling

13
 Future Problems (Delay)
Wire Cross section
Simple Scaling Scenarios Scaling Scenarios
• Local: Wires whose length shrinks
• S1: AR maintained (3D shrink) S1
• R up by α (worse) where α = scaling factor S2
• C down by α (geometrical effect)
• C down by low-k material
• RC delay down as low-k S3
• Delay going up compare to gate delay

• Semiglobal/Global: Length does not shrink Wire length Scaling

• Much worse than local Global Local

All types of signal wires delays

are deteriorating wrt gate delay Future
with scaling even with new
low-k materials !

.
araswat
tanford University 27 EE311 / Interconnect Scaling

Scaling of Interconnect Cross Section

Dimensions

ITRS ‘99 dimensions: local, semi-global, global wires

araswat
tanford University 28 EE311 / Interconnect Scaling

14
 Solutions to Mitigate the Interconnect
Problems
 Technological Solutions
 Material Solutions: Lower resistivity materials and lower-dielectric constant
(Existing Paradigm)
 Future Solutions: 3-D integration and Optical Interconnects
 Circuit Solutions
 Repeaters (Existing Paradigm)
 Future Solutions: Low-swing signaling and near speed of light electrical
interconnects
 Architectural/Combination Solutions

araswat
tanford University 29 EE311 / Interconnect Scaling

Impact of Interconnect Resistivity

Al

• Will superconductors really improve the circuit speed?

• Is Cooling conventional conductors to 77°K sufficient?
araswat
tanford University 30 EE311 / Interconnect Scaling

15
Interconnect and gate delay vs chip area and minimum
feature sizes for various interconnect materials

Si 2
W
Si 2
W

chip area
Delay calculated for the longest interconnect on a chip L=
2
araswat
tanford University 31 EE311 / Interconnect Scaling

Limits of 4 Commonly Used Materials for Interconnections

Copper

Maximum length limited by τG = τI

Ref. Gardner, et.al., IEEE Trans Electron Dev., March 1987.

araswat
tanford University 32 EE311 / Interconnect Scaling

16
 Why Cu and Low-k Dielectrics?
14
13
12 Al & SiO2 (! = 4)
11 Cu & SiO2 (! = 4) global
10
9
8
7
semiglobal
6
5
4 Al & low-! (! = 2) local
3
2 Cu & lo w- ! ( ! = 2)
1
0.09 0.13 0.18 0.25 0.35 µm
2007 2004 2001 1998 1995 Year
Tec hnology Generation Source: Y.Nishi T.I.

Reduced resistivity and dielectric constant results in reduction in number of

metal layers as more wires can by placed in lower levels of metal layers.
araswat
tanford University 33 EE311 / Interconnect Scaling

Low Dielectric Constant (Low-k) Materials

Oxide Derivatives
F-doped oxides (CVD) k = 3.3-3.9
C-doped oxides (SOG, CVD) k = 2.8-3.5
H-doped oxides (SOG) k = 2.5-3.3

Organics
Polyimides (spin-on) k = 3.0-4.0
Aromatic polymers (spin-on) k = 2.6-3.2
Vapor-deposited parylene; parylene-F k ~ 2.7; k ~ 2.3
F-doped amorphous carbon k = 2.3-2.8
Teflon/PTFE (spin-on) k = 1.9-2.1

Highly Porous Oxides

Xerogels k = 1.8-2.5

Air k=1

araswat
tanford University 34 EE311 / Interconnect Scaling

17
 Repeaters As a SOLUTION
Repeater
R/n
τG τL / n
C/n

Propagation delay of a long interconnect line is

3.56 " K o x# o $ 2
!L = L
%2
By breaking the long line into n smaller lines the delay of each line is
reduced quadratically
! L 3.56 " K o x# o $ & L ) 2
= ( +
n %2 ' n*
The total wire delay is thus reduced significantly as τG reduces with scaling
2
"$ ! L % 3.56 ( K o x) o * " L %
+ !G ' n = 2 $ ' + n! G
# n & + # n&
However, repeaters have power and area penalties
araswat
tanford University 35 EE311 / Interconnect Scaling

 Why should we look at interconnects?

 Basics and Background
 Scaling Related Issues: Delay
 Scaling Related Issues: Power
 Power Dissipation

 Power Removal (thermal Problem)

 Power Distribution

 Current Interconnect Technology

araswat
tanford University 36 EE311 / Interconnect Scaling

18
 Processor Power
100

10

Horowitz, IEDM 2005

1
85 87 89 91 93 95 97 99 01 03

 Power dissipation rising to exorbitant proportions !!!

 Need to come up with novel schemes to reduce power in each
department
araswat
tanford University 37 EE311 / Interconnect Scaling

Why Power Increased

10000

Clock Frequency (MHz)

1000

100

Horowitz, IEDM 2005

10
85 87 89 91 93 95 97 99 01 03 05

 Growing die size: increase in R,L,C

 Fast frequency scaling: CV2f
araswat
tanford University 38 EE311 / Interconnect Scaling

19
 Transistor Scaling: Bad News

Ed Nowak, IBM

• Voltage scaling has

stopped
– Subthreshold slope limit
• kT/q does not scale
– Vt scaling has power
consequences

• If Vdd does not scale

– Energy scales slowly

araswat
tanford University 39 EE311 / Interconnect Scaling

MOSFET Scaling Limit: Leakage

Gate Leakage Total Leakage Trend

S/D Leakage

Source: Marcyk, Intel

Lo et al.,IEEE EDL, May 1997.

 Ability to control Ioff will limit gate-length scaling

– Thermionic emission over barrier
– QM tunneling through barrier
– Band-to-band tunneling (BTBT) leakage
 To suppress D/S leakage, need to use:
– Higher body doping to reduce DIBL
 lower mobility, higher junction capacitance, increased BTBT leakage
– Thinner gate dielectric to improve gate control => higher gate leakage
araswat
tanford University 40 EE311 / Interconnect Scaling

20
 Transistor Power Trends

1000
 Dynamic Power: CV2f
er
ve Pow
Power Density (W/cm2 )

100
ActiveActi
Power  Leakage power: devices
10
Passive Power
 Analog components (sense
er

1
w

amps etc.): static power

Po
e
iv

0.1
ss

 Short circuit power during

Pa

0.01
switching
1994 2004 Wong
Courtesy: H.S.P
0.001
1 0.1 0.01
Gate Length (µm)

araswat
tanford University 41 EE311 / Interconnect Scaling

Chip Power: Breakdown

• Dynamic Power: CV2f
• Leakage power: devices
• Short circuit power during switching
• Analog components (sense amps etc.):static power

Dynamic Power

clocking Signaling I/O

Latches Clocking Devices Signaling Buffers Off-chip

Interconnects Interconnects load

Logic memory

• Interconnect power
• Due to Cint: dissipated in devices (predominant)
• Due to Rint: Joule heating (not as big but makes things worse)
araswat
tanford University 42 EE311 / Interconnect Scaling

21
 Local wires: Delay and Power
Delay
 Driver small, wire length short => Zdr>Z0
 Inductance (LC) almost never important
 Mostly driver delay dominates
=> want low Cw

Power
 Power ~Cw l*Vdd2*Fclock
⇒ Also want low Cw
 Typical Cw =0.15fF/µm (changes very slowly), Ctrans = 1.5fF/µm (Reducing very slowly)
⇒ lengths > 10µm, Cw dominates over 1um wide transistor => Most power is in interconnects
 Similar to delay, where wire delay dominates if l > Ctrans/Cw and Rdr > Rw
 Energy required to charge 10µm of local wire ~ 1fJ

araswat
tanford University 43 EE311 / Interconnect Scaling

Repeaters (Global Wires): How Good Is It?

Technology
TechnologyNode (µm)
node (µm)
A long global link w/o Repeaters 0.18 0.15 0.12 0.1 0.07 0.05 0.035

3.56 " K ox#o $ 2

Delay = L
%2
Wire Delay (in number
of clock cycles)

Driver Rec
d
a te

!
pe

lt y
re

na
n-

e
yp
No

3.56 " K ox#o $ & L2 ) la

De
Delay = ( + + n, G % d
%2 'n* 25 a te
pe
re
l
im a
Driver Rec opt
Delay
!
Year
• Even with repeaters, 7.5X Clock at 35nm node 8X increase
compared to 180nm node
• By increasing the distance between the repeaters power can
be reduced at the expense of delay
araswat
tanford University 44 EE311 / Interconnect Scaling

22
 Number of Repeaters Required
Technology Node ( µm) Technology Node
Technology Node(µm)
(µm)
0.18 0.15 0.12 0.1 0.07 0.05 0.18 0.15 0.12 0.1 0.07 0.05
Repeaters per Longest Global Line

Number of Repeaters
p = 0.6

p = 0.55
Rent’s exponent of
0.55 is reasonable in
microprocessors

Year Year

• ITRS wire dimensions: justified based on barely enough metal levels to fit the wires
• Separation of memory and logic area because different wire length distributions
• Rent’s rule based distribution for logic area
 A fraction of the chip area would be occupied by repeaters
 Additional power will be consumed by repeaters
araswat
tanford University 45 EE311 / Interconnect Scaling

Repeater Area Penalty

Fractional chip area occupied by repeaters Via blockage by repeaters on global wires

Technology Node (µm) Technology Node (µm)

0.1 0.07 0.05 0.18 0.15 0.12 0.1 0.07 0.05
0.18 0.15 0.12

Rent’s exponent
p = 0.6
Rent’s exponent

p = 0.6

p = 0.55
p = 0.55

 Significant area occupied by repeaters in future

 Via blockage non-negligible for wire-limited chips
araswat
tanford University 46 EE311 / Interconnect Scaling

23
 Global Wires (Repeated): Delay & Power

Barrier Effects
Delay
 Delay = 60-80ps/mm
•Speed of light in a
medium~10ps/mm

Power
Scattering Effects
 Energy Price for a Chip wide communications ~ 1000-1500 fJ
 Delay optimized: Repeaters dissipate same power as a wire
 Can trade a small amount of delay and reduce repeater power
to only 20% of interconnect power
• Energy efficiency ~ 1000fJ
araswat
tanford University 47 EE311 / Interconnect Scaling

Future Chip Power Trends and Breakdown

Repeaters
Distribution (Interconnects)
Global 5% 5%
Clo

Semi-global 5%
)

5%
Wires (27%

ck
Signaling

(28

23%
%)

12% Latches
Local wires
ITRS projections for total
power dissipation on chip 2% < 1% Memory

Logic Memory (dynamic)

Logic
(leakage) (leakage)
)

(Dynamic)
7%

17%
(1
Lo

25%
or
gi

em
c
(2

M
7%
)

50nm node

• Power dissipation rising to exorbitant proportions !!!

• Need to come up with novel schemes to reduce power in each department

Chandra, Kapur and Saraswat IITC, June 2002

araswat
tanford University 48 EE311 / Interconnect Scaling

24
 Thermal problem
I am Hot !

Higher T
4 1.2
Dielectric Constant

Thermal Conductivity
1
3
0.8

[ W / mK ]
2 0.6
0.4
1
0.2
0 0
35 50 70 100 130 180
Technology Node [nm]
Substrate Lower T
 Higher T ⇒
• higher R
• lower reliability
 Better circuit design techniques needed to reduce power
araswat
 Better cooling techniques needed
tanford University 49 EE311 / Interconnect Scaling

The problems Caused by Increased Power

RELIABILITY
Electromigration induced hillocks and voids
Metal
Void Dielectric
Hillock Metal

Mean time to failure

>100A will flow on these wires A "E %
MTF = m n
exp$ a '
r J # kT &

10°C ⇑ , MTF ⇓ 50%

PERFORMANCE
!
As T ⇑ R ⇑, RC delay ⇑
10°C ⇑ , Speed ⇓ 5%

araswat
tanford University 50 EE311 / Interconnect Scaling

25
 Impact of Vias on the Thermal
Characteristics of low-k Interconnects

n
tio
pa ia
Se V
ra
Mn

S W1 W2
Mn-1 Via

• Vias have much higher thermal conductivity than the dielectric

materials (ILD)
• Can be efficient thermal dissipation paths

araswat
tanford University 51 EE311 / Interconnect Scaling

Simulation of WireTemperature: Role of Vias

Case 1 Case 2 Case 3

200  Commonly used case 1

Temp. Rise ΔT [°C]

case1 model overestimates

150 interconnect temperature
100 case2
50 case3  Case 3 represents the
most realistic condition
0
0 1 2 3 4
Current Density, J [MA/cm2]
araswat
tanford University 52 EE311 / Interconnect Scaling

26
 3D Thermal Analysis of Interconnects
THERMAL-ELECTRICAL ANALOGY THERMAL ANALYSIS USING SPICE.
Thermal Electrical

Temperature Rise ΔT [°C]

18
Temperature T [K] Voltage V [V]
16
Heat q’ [J] Charge Q [C] 14
Heat flux q [W] Current I [A] 12 Polymer, ANSYS
Thermal resistance RT [K/W] Electrical resistance R [V/A] 10 Polymer, HSPICE
8 SiO2, ANSYS
Thermal capacitance CT [J/K] Electrical capacitance C [C/V]
6 SiO2, HSPICE
Heat diffusion RC transmission line
4
#T #V
" 2T = RT CT " 2V = RC 2
#t #t 0
0 20 40 60 80 100
3-D THERMAL CIRCUIT Location along metal wire [µm]
Via Via
EFFECT OF VIAS
100

[W/mK]
IMD 10
Mn+1 ILD: SiO2 kSiO2
1
ILD kpolymer

eff
polymer
0.1

kILD,
Mn kair
air
Via 0.01
0 100 200 300 400 500
Mn-1 Via Separation [µm]
araswat Chiang and Saraswat, VLSI Symp, June 2001
tanford University 53 EE311 / Interconnect Scaling

Wire Temperature vs. Low-k ILD

Top Metal Temp. Tm [°C]

300
air
aerogel
250
polyimide
HSQ
200 FSG 65nm
air-gap Node
150

100
0.5 1.5 2.5 3.5
Current Density, J [M A/cm2]
• Temperature of global interconnects rise sharply for low-k ILD
materials.
• Embedded low-k approach, e.g., air-gap shows excellent results
Chiang, Shieh and Saraswat, VLSI Symp, June 2002
araswat
tanford University 54 EE311 / Interconnect Scaling

27
 Embedded Low-k Dielectric Approach
Why embed Low-k dielectric
SiO2
(k~4.2) only between metal lines?

LOW
•Capacitance is dominated by
MET MET CIMD
k

V V •Use a low-k dielectric as IMD

I SiO2 I
A (k~4.2) A •Heat flows vertically
LOW • Use a high thermal
MET MET
k
conductivity material ⇒ SiO2
SiO2
(k~4.2)

Source: Y. Nishi
araswat
tanford University 55 EE311 / Interconnect Scaling

Impact of Joule Heating on RC Delay

140
RC [psec/mm]

120
100 65nm
80 Node
FSG
60 HSQ
air-gap
40 polyimide
aerogel
air
20
0.5 1.5 2.5 3.5
Current Density, J [M A/cm2]

• Resistivity increases with temperature rise

• RC delay is strong function of current density because of Joule
Heating
• Greater RC degradation for lower-k materials
Chiang, Shieh and Saraswat, VLSI Symp, June 2002
araswat
tanford University 56 EE311 / Interconnect Scaling

28
 Temperature in Multilevel Metal Layers
30
scenario (a) a)both j and kILD scale
Temperature Rise ΔT [°C]

25 scenario (b) according to ITRS.

20 scenario (c)
b) j scales with ITRS, but kILD
scenario (d) stops scaling at 65nm node.
15
c)j stops scaling at 65nm
10 node, while kILD continues
5 scaling.
0 d)both j and kILD stops scaling
130 90 65 45 22 at 65 nm node.
Technology Node [nm]

• With the help of vias as efficient thermal paths, the wire

temperature can be significantly lower than that predicted from
overly simplified 1-D thermal model.
• Therefore, the thermal problem associated with low-k insulators
is not as bad as it appears.
• Beyond 45nm node closer packing of vias will alleviate the
temperature rise problem.
araswat
tanford University 57 EE311 / Interconnect Scaling

Current Interconnect Technologies

Copper 6

Copper 5

Copper 4

Copper 3

Copper 2
Copper 1

Tungsten
Local Interconnect

Current Al technology Current Cu technology

(Courtesy of Motorola) (Courtesy of IBM)

araswat
tanford University 58 EE311 / Interconnect Scaling

29
DC Resistance Modeling with Scaling:Technology Impact (I)

Diffusion barrier
• Consumes progressively larger fractional area Future
• Barrier thickness (BT) doesn’t scale
• Higher AR => larger barrier area
• Technology dictates
• Minimum thickness: reliability constraints
• Profile: deposition technology ALD IPVD C-PVD

Electron surface scattering

• Reduced electron mobility with scaling
• Depends on
• Ratio of λmfp to thickness
• Interface quality: Roughness
• Technology dictates
• Temperature
• Copper/barrier interface quality (P)

Cu effective ρ increases in future

araswat
tanford University 59 EE311 / Interconnect Scaling

Problems in Scaling of Interconnections

Surrounded Interconnect
AS λ DECREASES
Cu Barrier
• Resistivity increases as
grain size decreases ρav Layered Interconnect

Al
Barrier
• Resistivity increases as
main conductor size Al
decreases but not the Pure Metal
Interconnect
surrounding film size Cu

Minimum Feature Size (λ)

araswat
tanford University 60 EE311 / Interconnect Scaling

30
 Interplay Between Signaling Metrics (II)
Fixed length & width
t
• Aspect ratio increase tradeoffs:
C to
α  Better delay and electromigration
er
Resi

P ow  Worse power and cross talk

s ta n

Delay
Arbitrary Units

• In future increasing aspect ratio may

ce

not help

lk
• Explains why AR dropped when
s ta Elect
romig Al to Cu switch
os c u rre ra
Cr nt de tio:n
nsity

Aspect Ratio (H/W)

• Pay attention to different metrics simultaneously rather than just delay

• Design window quite complex

araswat
tanford University 61 EE311 / Interconnect Scaling

Requirements of the interconnection materials

Electrical
• Low resistivity of conductors
• Low capacitance => low dielectric constant
– Low RC delay
– Low power dissipation (CV2f loss)
– Low cross talk
• Low contact resistance
Processing
• Ability to contact shallow junctions
• Ease of deposition of thin films of the material
• Ability to withstand the chemicals and high temperatures required in
the fabrication process
• Ability to be thermally oxidized
• Ability to be defined into fine patterns - dry etching
Reliability
• Resistance to electromigration
• Good adhesion to other layers - low physical stress
• Stability of electrical contacts to Si and other layers
• Good MOS properties

araswat
tanford University 62 EE311 / Interconnect Scaling

31
 Outline

•Interconnect scaling issues

•Aluminum technology
•Copper technology

araswat
tanford University 63 EE311 / Interconnect Scaling

32