Tda16846 2
Tda16846 2
Tda16846 2
0 , 3 1 J u l y 2 0 0 3
PWM-QR IC
TDA 16846/16846-2 TDA 16847/16847-2
Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
TDA 16846/TDA 16846-2/TDA 16847/TDA 16847 Revision History: Current Version: 2003-07-31 Previous Version Data Sheet TDA 16846: 2000-01-14 Previous Version Data Sheet TDA 16846-2: 2002-07-30 Page (in previous Version) 20 Page (in current Version) 20 Subjects (major changes since last revision) The data sheets for TDA 16846 and TDA 16846-2 have been combined in this version. Some measuring values are updated: Pin 1 basic value 1 V1B1 and V1B2 slightly changed. Pin 2 discharge current I2DC min changed from 0.5 mA to 0.6 mA. Pin 14 overvoltage V14OVmax threshold changed from 17.0 V to 17.1 V. Pin 3 delay to switch on t3d slightly decreased. Pin 4 charge current I4ch and discharge current I4DCH added. Pull high resistor R1min changed from 18kOhm to 15 kOhm according to the data sheet for TDA 16846. Pin 7 charge current I7 min and upper threshold V7Hmin small changed. Pin 13 rise and fall time adapted according to C13= 1nF (prev. 10 nF). V13aclow slightly decreased (only TDA 16846-2, TDA 16847-2).
21
21
22 23
22 23
TDA 16846-2/TDA 16847-2: Improvements of TDA 16846-2/TDA16847-2 compared with TDA 16846/TDA16847 Pin 5 Pin 7 Pin 11 Pin 13 Pin 14
Edition 07.03 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 Mnchen
Expanded input voltage range down to zero, series resistor between pin 5 and ground is no longer necessary. Improved startup to prevent the transformer from saturation also in fixed frequency and synchronized mode. Noise-immunity improved by spike blanking. Reduced output voltage level for off state. Noise-immunity improved by spike blanking.
Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction
1
1.1
Overview
Features
Line Current Consumption with PFC P-DIP-14-3 Low Power Consumption Stable and Adjustable Standby Frequency Very Low Start-up Current Soft-Start for Quiet Start-up Free usable Fault Comparators Synchronization and Fixed Frequency Circuits P-DSO-14-3 Over- and Undervoltage Lockout Switch Off at Mains Undervoltage Temporary High Power Circuit (only TDA 16847-2) Mains Voltage Dependent Fold Back Point Correction Continuous Frequency Reduction with Decreasing Load Adjustable and Voltage Dependent Ringing Suppression Time Ordering Code Q67000-A9377 Q67000-A9378 Q67006-A9430 Q67006-A9412 Q67040-S4494 Q67040-S4496 Q67040-S4495 Q67040-S4497 Package P-DIP-14-3 P-DIP-14-3 P-DSO-14-3 P-DSO-14-3 P-DIP-14-3 P-DIP-14-3 P-DSO-14-3 P-DSO-14-3
Type TDA 16846 TDA 16847 TDA 16846G TDA 16847G TDA 16846-2 TDA 16847-2 TDA 16846-2G TDA 16847-2G
1.2
Description
The TDA 16846-2 (this name is used in the description for all types) is optimized to control free running or fixed frequency flyback converters with or without Power Factor Correction (Current Pump). To provide low power consumption at light loads, this device reduces the switching frequency in small steps with load, towards an adjustable minimum (e. g. 20 kHz in standby mode). Additionally, the startup current is very low. To avoid switching stress on the power devices, the power transistor is always switched on at minimum voltage. A special circuit is implemented to avoid jitter. The device has
Version 2.0 3 31 Jul 2003
several protection functions: VCC over- and undervoltage, mains undervoltage, current limiting and 2 free usable fault comparators. Regulation can be done by using the internal error amplifier or an opto coupler feedback (additional input). The output driver is ideally suited for driving a power MOSFET. Fixed frequency and synchronized operation are also possible. The TDA 16846-2 is suited for TV-, VCR- sets, SAT receivers and other sets for consumer electronics. It also can be used in PC monitors. The TDA 16847-2 is identical with TDA 16846-2 but has an additional power measurement output (pin 8) which can be used as a Temporary High Power Circuit.
Figure 1
1.3
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Version 2.0
31 Jul 2003
1.4
Pin 1 2
6 7
9 10 11
12 13 14
Version 2.0
1.5
Block Diagrams
Figure 2
Version 2.0
TDA 16846-2
6 31 Jul 2003
Figure 3
Version 2.0
TDA 16847-2
7 31 Jul 2003
Functional Description
Start Up Behaviour (Pin 14) When power is applied to the chip and the voltage V14 at Pin 14 (VCC) is less than the upper threshold (VON) of the Supply Voltage Comparator (SVC), then the input current I14 will be less than 100 A. The chip is not active (off state) and driver output (Pin 13) and control output (Pin 4) will be actively held low. When V14 exceeds the upper SVC threshold (VON) the chip starts working and I14 increases. When V14 falls below the lower SVC threshold (VOFF) the chip starts again from its initial condition. Figure 4 shows the start-up circuit and Figure 5 shows the voltage V14 during start up. Charging of C14 is done by resistor R2 of the Primary Current Simulation (see later) and the internal diode D1, so no additional start up resistor is needed. The capacitor C14 delivers the supply current until the auxiliary winding of the transformer supplies the chip with current through the external diode D14. It is recommended to apply a small RF snubber capacitor of e.g. 100 nF parallel to the electrolytic capacitor at pin 14 as shown in the application circuits in Figures 15, 16 , and 17. To avoid multiple pulses during start up in fixed frequency mode (danger of transformer saturation), the IC works in freerunning mode until the pulses at pin 3 (RZI) exceed the 2.5 V threshold (only TDA 16846-2, TDA 16847-2).
Figure 4
Startup Circuit
Version 2.0
31 Jul 2003
Figure 5
Primary Current Simulation PCS (Pin 2) / Current Limiting A voltage proportional to the current of the power transistor is generated at Pin 2 by the RC-combination R2, C2 (Figure 4). The voltage at Pin 2 is forced to 1.5 V when the power transistor is switched off and during its switch on time C2 is charged by R2 from the rectified mains. The equation of V2 and the current in the power transistor (Iprimary) is
:
V 2 = 1,5 V +
Lprimary: Primary inductance of the transformer The voltage V2 is applied to one input of the On Time Comparator ONTC (see Figure 2). The other input is the control voltage. If V2 exceeds the control voltage, the driver
switches off (current limiting). The maximum value of the control voltage is the internal reference voltage 5 V, so the maximum current in the power transistor (IMprimary) is
:
3,5 V R 2 C 2 I Mprimary = -------------------------------------L primary The control voltage can be reduced by either the Error Amplifier EA (current mode regulation), or by an opto coupler at Pin 5 (regulation with opto coupler isolation) or by the voltage V11 at Pin 11 (Fold Back Point Correction).
Version 2.0 9 31 Jul 2003
V11 is derived from a voltage divider connected to the rectified mains and reduces the limit of the possible current maximum in the power transistor if the mains voltage increases. I.e. this limit is independent of the mains (only active in free running mode). The maximum current (IMprimary) depending on the voltage V11 at Pin 11 is
:
(4 V V 11 3 ) R 2 C 2 I Mprimary = -----------------------------------------------------------L primary Off-Time Circuit OTC (Pin 1) Figure 6 shows the Off-Time Circuit which determines the load dependent frequency curve. When the driver switches off (Figure 7) the capacitor C1 is charged first by current I1L (approx. 0.5 mA, for extended ringing suppression time). As soon as the voltage at pin 3 reaches the level V3L (2.5 V), the charging current is switched to the higher value I1H (approx. 1 mA, for normal ringing suppression time). This current flows until the capacitors voltage reaches 3.5 V. The charge time TC1 is
:
i.e. V1 is less than the limited control voltage. Output Power Off-time TD1 Low Medium High Constant (TD1MAX.), const. frequency stand by Decreasing Free running, switch-on at first minimum
Version 2.0
10
31 Jul 2003
If the control voltage is below 2 V (at low output power) the off-time is maximum and constant TD1 max 0, 56 R 1 C 1 During the discharge time tD1, V1 must not fall below the limit V1L, otherwise the function is not guaranteed.
Figure 6
Version 2.0
Off-Time-Circuit
11 31 Jul 2003
Figure 7
Figure 8 shows the converters switching frequency as a function of the output power.
Figure 8
Version 2.0
Error Amplifier EA / Soft-Start (Pin 3, Pin 4) Figure 9 shows the simplified Error Amplifier circuit. The positive input of the Error Amplifier (EA) is the reference voltage 5 V. The negative input is the pulsed output voltage from the auxiliary winding, divided by R31 and R32. The capacitor C3 is dimensioned only for delaying zero crossings and smoothing the first spike after switchoff. Smoothing of the regulation voltage is done with the soft start capacitor C4 at Pin 4. During start up C4 is charged with a current of approx. 2 A (Soft Start). For primary regulation C4 is charged and discharged with pulsed currents. Figure 10 shows the voltage diagrams of the Error Amplifier circuit.
Figure 9
Error Amplifier
Figure 10
Version 2.0
Fixed Frequency and Synchronization Circuit SYN (Pin 7) Figure 11 shows the Fixed Frequency and Synchronization Circuit. The circuit is disabled when Pin 7 is not connected or connected to pin 9 (Vref, to avoid noise sensitivity). With R7 and C7 at Pin 7 the circuit is working. C7 is charged fast with approx. 1 mA and discharged slowly by R7 (Figure 11). The power transistor is switched on at beginning of the charge phase. The switching frequency is (charge time ignored)
:
f -------------R7 C7
When the oscillator circuit is working the Fold Back Point Correction is disabled (not necessary in fixed frequency mode). Switch on is only possible when a zero crossing has occurred at Pin 3, otherwise switch-on will be delayed (Figure 12).
0, 8
Figure 11
Version 2.0
14
31 Jul 2003
Figure 12
Synchronization mode is also possible. The synchronization frequency must be higher than the oscillator frequency.
Figure 13
Version 2.0
Protection Functions
The chip has several protection functions: Current Limiting See Primary Current Simulation PCS (Pin 2) / Current Limiting and Fold Back Point Correction PVC (Pin 11). Over- and Undervoltage Lockout OV/SVC (Pin 14) When V14 at Pin 14 exceeds 16.5 V, e. g. due to a fault in the regulation circuit, the Error Flip Flop ERR is set and the output driver is shut-down. When V14 goes below the lower SVC threshold, ERR is reset and the driver output (Pin 13) and the soft-start (Pin 4) are shut down and actively held low. Primary Voltage Check PVC (Pin 11) When the voltage V11 at Pin 11 goes below 1 V the Error Flip Flop (ERR) is set. E.g. a voltage divider from the rectified mains at Pin 11 prevents high input currents at a too low input voltage. Free Usable Fault Comparator FC1 (Pin 10) When the voltage at Pin 10 exceeds 1 V, the Error Flip Flop (ERR) is set. This can be used e. g. for mains overvoltage shutdown. Free Usable Fault Comparator FC2 (Pin 6) When the voltage at Pin 6 exceeds 1.2 V, the Error Flip Flop (ERR) is set. A resistor between Pin 9 (REF) and ground is necessary to enable this fault comparator. Voltage dependent Ringing Suppression Time During start-up and short-circuit operation, the output voltage of the converter is low and parasitic zero crossings are applied for a longer time at Pin 3. Therefore the Ringing Suppression Time TC1 (see Off-Time Circuit OTC (Pin 1)) is extended with a factor of 2.2 at a low output voltage. The voltage at pin 1 must not fall below the limit V1L.
Version 2.0
16
31 Jul 2003
Temporary High Power Circuit FC2, PMO, REF (Pin 6, 8, 9, TDA 16847-2)
Figure 14 The Temporary High Power Circuit (THPC) consists of two parts: Firstly, a power measurement circuit is implemented: The capacitor C8 at Pin 8 is charged with a constant current I8 during the discharge time of the flyback transformer and grounded the other time. Thus the average of the sawtooth voltage V8 at Pin 8 is proportional to the converters output power (at constant output voltages). The charge current I8 for C8 is set by the resistor R9 at Pin 9:
I8 = 5 V/R9
Version 2.0
17
31 Jul 2003
Secondly, a High Power Shutdown Comparator (FC2) is implemented: When the voltage V6 at Pin 6 exceeds 1.2 V the Error Flip Flop (ERR) is set. The output voltage of the power measurement circuit (Pin 8) is smoothed by R8/C6 and applied to the high power shutdown input at Pin 6. The relation between this voltage V6 and the output power of the converter P is approximately:
V6 (P LSecondary 5 V)/(VOUT2 C8 R9) LSecondary: The transformers secondary inductance VOUT: The converters output voltage So the time constant of R9/C8 for a certain high power shutdown level PSD is: R9 C8 (PSD LSecondary 4.2)/VOUT2
The converters high power shutdown level can be adjusted lower (by R9, C8) than the current limit level (see current limiting). Thus because of the delay R8/C6, the converter can deliver maximum output power (current limit level) for a certain time (e. g. for power pulses like motor start current) and a power below the high power shutdown level for an unlimited time. This is of advantage because the thermal dimensioning of the power devices needs to be done for the lower power level only. Once the voltage V6 exceeds 1.2 V no more charging or discharging happens at Pin 8. The voltage V6 remains high due to the bias current out of FC2 and the converter remains switched-off. Reset can be done either by plugging-off the supply from the mains or by a high value resistor R6 (Figure 14). R6 causes a reset every few seconds. When Pin 9 is not connected or gets too little current (I9 < I9FC2), the temporary high power circuit is disabled.
Version 2.0
18
31 Jul 2003
5
5.1
Parameter
Electrical Characteristics
Absolute Maximum Ratings
Symbol Limit Values min. max. 17 6 17 1 6 10 1 100 100 2 V V V mA V mA mA mA mA kV 0.3 0.3 0.3 Unit Remarks
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Supply Voltage at Pin 14 Voltage at Pin 2, 8, 11 Startup current into Pin 2 Voltage at Pin 3 Current into Pin 3 Current into Pin 9 Current into Pin 13 ESD Protection
VCC
Voltage at Pin 1, 4, 5, 6, 7, 9, 10
I2
RZI
V3 < 0.3 V
IREF IOUT
65 25
C C
K/W P-DIP-14-3 C s
Note: Stress beyond the above listed values may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Version 2.0
19
31 Jul 2003
5.2
Parameter
Characteristics
Symbol Limit Values min. typ. max. Unit Test Condition
Supply Voltage and Startup Circuit VCC (Pin 14) Overvoltage threshold Turn-ON threshold Turn-OFF threshold Delta-OV-V14 ON Supply current, OFF Supply current, ON
16.5 15 8 40 5
V V V V A mA
I14OFF I14ON
Primary Current Simulation PCS (Pin 2) / Current Limiting Basic value Peak value Discharge current Bias current Pin 2
V2 V2 I2DC
1.5 5 1.0
V V mA A
1.0 0.3
Fold Back Point Correction PVC (Pin 11) Peak value Bias current Pin 11 Off-Time Circuit OTC (Pin 1) Charge current Charge current Peak value Basic value 1 Basic value 2
V5
3.8
4.1
4.3
V A
1.0 0.3
V1 Lower limit
Bias current Pin 1
mA mA V V V mV A
1.1 0.4
V1 = 2.2 V
31 Jul 2003
Version 2.0
20
5.2
Parameter
Characteristics (contd)
Symbol Limit Values min. typ. max. Unit Test Condition
Zero Crossing Input RZI (Pin 3) Zero crossing threshold (Pin 3) Delay to switch-on Bias current Pin 3 15 25 350 35 460 mV ns A
t3d
250 2
1.2
V3 = 0 V
Error Amplifier Input RZI (Pin 3) Input threshold (Pin 3) Bias current Pin 3
4.85 2.4
5 2.5
5.15 2.6
V V A
0.9
V3 = 3 V
Softstart and Regulation Voltage SRC (Pin 4) Soft-start charge current (Pin 4) Charge current Pin 4 Discharge current Pin 4
V4 = 2 V
Opto Coupler Input OCI (Pin 5) Input voltage range (TDA 16846, TDA 16847) Input voltage range (TDA 16846-2, TDA 16847-2) Pull high resistor to VREF
V5 V5 R1
0.3 0 15
20
6 6 28
V V k
Version 2.0
21
31 Jul 2003
5.2
Parameter
Characteristics (contd)
Symbol Limit Values min. typ. max. Unit Test Condition
Fixed Frequency and Synchronization Circuit SYN (Pin 7) Charge current Upper threshold Lower threshold Input voltage range Bias current Pin 7
mA V V V
V7 = 4 V
V11
0.95
1.06
V9 I9FC2
4.8 18
5 7
5.15
V A
I9 = 100 A
Version 2.0
22
31 Jul 2003
5.2
Parameter
Characteristics (contd)
Symbol Limit Values min. typ. max. Unit Test Condition
V6
1.12
1.2
1.28
V A
V6 = 0.8 V
V10
0.95 0.35
1 0.65
1.06 0.95
V A
V10 = 0.8 V
Power Measurement Output PMO (Pin 8, only TDA 16847, TDA 16847-2) Charge current Pin 8 Output Driver OUT (Pin 13) Output voltage low state Output voltage high state Output voltage during low V14 (TDA 16846, TDA 16847) Output voltage during low V14 (TDA 16846-2, TDA 16847-2) Rise time Fall time
I8
110 100 90
I9 = 100 A
V13 low 1.1 V13 high 9.2 V13 aclow 0.8 V13 aclow 0.5
1.8 10 1.8 1
V V V V
I13 = 100 mA I13 = 100 mA I13 = 10 mA, V14 = 7 V I13 = 10 mA, V14 = 7 V C13 = 1 nF, V13 = 2 8 V C13 = 1 nF, V13 = 2 8 V
30 10
50 20
100 50
ns ns
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Version 2.0
23
31 Jul 2003
Figure 15
Version 2.0
Figure 16
Version 2.0
Figure 17
Version 2.0
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm
Version 2.0
27
31 Jul 2003
GPD05584
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Version 2.0 28 31 Jul 2003
http://www.infineon.com