William Stallings Computer Organization and Architecture 7th Edition

Chapter 2 Computer Evolution () and Performance

Timeline of Computing History http://www.computer.org/computer/timeline/timeline.pdf

ENIAC - background
ENIAC
The first general-purpose electronic digital computer Electronic Numerical Integrator And Computer Mauchly & Eckert, at University of Pennsylvania

Trajectory () tables for weapons Started 1943 Finished 1946

Too late for war effort

Used until 1955

ENIAC - details
Decimal (not binary) 20 accumulators () of 10 digits Programmed manually by switches 18,000 vacuum tubes () 30 tons 15,000 square feet 140 kW power consumption () 5,000 additions per second

ENIAC

The von Neumann/Turing Machine

Stored-Program concept
John von Neumann, ENIAC consultant Alan Turing

IAS computer, at Princeton Institute for Advanced Studies, completed in 1952

Main memory storing programs and data ALU (Arithmetic and Logic Unit) operating on binary data Control unit interpreting instructions from memory and executing Input and output (I/O) equipment operated by control unit

Structure of von Neumann machine

The IAS Computer, 1952

http://americanhistory.si.edu/collections/comphist/objects/ias.htm

IAS - details
1000 x 40 bit words
Binary number 2 x 20 bit instructions

Set of registers (storage locations in CPU)

Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer Register Program Counter Accumulator Multiplier Quotient () Register:

IAS Memory Formats

Structure of IAS detail

MBR: Memory Buffer Register MAR: Memory Address Register IR: Instruction Register IBR: Instruction Buffer Register PC: Program Counter AC: Accumulator MQ: Multiplier Quotient

* Partial Flowchart

M(X) The content of the word in address X of Memory M(X, 0:19) The 0th~19th bits of the word in address X of Memory

IAS Instruction Set

M(X) The content of the word in address X of Memory M(X, 0:19) The 0th~19th bits of the word in address X of Memory

IAS Instruction Set (1/2)

IAS Instruction Set (2/2)

Commercial Computers
1947 - Eckert-Mauchly Computer Corporation UNIVAC I (Universal Automatic Computer) US Bureau of Census 1950 calculations () Became part of Sperry-Rand Corporation Late 1950s - UNIVAC II
Faster More memory

IBM
Punched ()-card processing equipment 1953 - the 701
IBMs first stored program computer Scientific calculations

1955 - the 702

Business applications

Lead to 700/7000 series

Transistors

-- 2nd Generation

Replaced vacuum tubes Smaller Cheaper Less heat dissipation () Solid State device Made from Silicon (Sand) Invented 1947 at Bell Labs William Shockley et al.

Transistor Based Computers

Second generation machines NCR & RCA produced small transistor machines IBM 7000 DEC - 1957
Produced PDP-1

IBM 700/7000 Series

Third Generation: Integrated Circuits

Microelectronics small electronics A computer is made up of gates, memory cells and interconnections These can be manufactured () on a semiconductor e.g. silicon wafer

Appendix B

Page 138

Fundamental Functions
Data Storage: Provided by memory cells Data Processing: Provided by gates Data Movement:
The paths between components From memory to memory From memory through gates to memory

Control:
The paths between components can carry control signals.

http://www.eingang.org/Lecture/

Wafer, Chip, & Gate

Generations of Computer
Vacuum tube - 1946-1957 Transistor - 1958-1964 Small scale integration - 1965 on
Up to 100 devices on a chip

Medium scale integration - to 1971

100-3,000 devices on a chip

Large scale integration - 1971-1977

3,000 - 100,000 devices on a chip

Very large scale integration - 1978 to date

100,000 - 100,000,000 devices on a chip

Ultra large scale integration

Over 100,000,000 devices on a chip

Computer Generations

Moores Law
Increased density of components on chip Gordon Moore - cofounder of Intel

Number of transistors on a chip will double every year

Since 1970s development has slowed a little Number of transistors doubles every 18 months Cost of a chip has remained almost unchanged Higher packing density means shorter electrical paths, giving higher performance Smaller size gives increased flexibility () Reduced power and cooling requirements Fewer interconnections increases reliability ()

Growth in CPU Transistor Count

IBM 360 series

1964 Replaced (& not compatible with) 7000 series First planned family of computers
Similar or identical instruction sets Similar or identical O/S Increasing speed Increasing number of I/O ports (i.e. more terminals) Increased memory size Increased cost

Multiplexed () switch structure

IBM 7094

DEC PDP-8
1964 First minicomputer (after miniskirt!) Did not need air conditioned room Small enough to sit on a lab bench $16,000
$100k+ for IBM 360

Embedded () applications & OEM BUS STRUCTURE

DEC - PDP-8 Bus Structure

Semiconductor Memory
1970 Fairchild Size of a single core
i.e. 1 bit of magnetic core storage

Holds 256 bits Non-destructive () read Much faster than core Capacity approximately doubles each year

Magnetic Core Memory

This is a stack of 13 x 4096 bits This stack is approx. 8 x 8 x 8 inch.

Intel
1971 - 4004
First microprocessor All CPU components on a single chip 4 bit (Data Bus Width)

Followed in 1972 by 8008

8 bit Both designed for specific applications

1974 - 8080
Intels first general purpose microprocessor

Speeding it up
Pipelining () On board cache On board L1 & L2 cache Branch prediction Data flow analysis Speculative () execution

L1 cache is a small, fast memory cache that is built in to a CPU. L2 cache resides on a separate chip from the microprocessor chip. More and more microprocessors are including L2 caches into their architectures.

Performance Mismatch
Processor speed increased Memory capacity increased Memory speed lags behind processor speed

Logic and Memory Performance Gap

Solutions
Increase number of bits retrieved at one time
Make DRAM wider rather than deeper

Change DRAM interface

Including a cache

Reduce frequency of memory access

More complex cache and cache on chip

Increase interconnection bandwidth

High speed buses Hierarchy of buses

I/O Devices
Peripherals with intensive I/O demands Large data throughput demands Processors can handle this Problem moving data Solutions:
Caching Buffering Higher-speed interconnection buses More elaborate() bus structures Multiple-processor configurations

Typical I/O Device Data Rates

bps : bits per second

Key is Balance
Processor components Main memory I/O devices Interconnection structures

Improvements in Chip Organization and Architecture Increase hardware speed of processor

Fundamentally due to shrinking logic gate size
More gates, packed more tightly, increasing clock rate Propagation time for signals reduced

Increase size and speed of caches

Dedicating part of processor chip
Cache access times drop significantly

Change processor organization and architecture

Increase effective speed of execution Parallelism

Problems with Clock Speed and Logic Density

Power
Power density increases with density of logic and clock speed Dissipating heat ()

RC delay
Speed at which electrons flow limited by resistance() and capacitance() of metal wires connecting them Delay increases as RC product increases Wire interconnects thinner, increasing resistance Wires closer together, increasing capacitance

Memory latency
Memory speeds lag processor speeds

Solution:
More emphasis on organizational and architectural approaches

Intel Microprocessor Performance

Increased Cache Capacity

Typically two or three levels of cache between processor and main memory Chip density increased
More cache memory on chip
Faster cache access

Pentium chip devoted about 10% of chip area to cache Pentium 4 devotes about 50%

More Complex Execution Logic

Enable parallel execution of instructions Pipeline works like assembly line
Different stages of execution of different instructions at same time along pipeline

Superscalar allows multiple pipelines within single processor

Instructions that do not depend on one another can be executed in parallel

Diminishing Returns
Internal organization of processors complex
Can get a great deal of parallelism Further significant increases likely to be relatively modest

Benefits from cache are reaching limit Increasing clock rate runs into power dissipation problem
Some fundamental physical limits are being reached

New Approach Multiple Cores

Multiple processors on single chip
chip-level multiprocessor, CMP With a large shared cache

Within a processor, increase in performance proportional to square root of increase in complexity. But, if software can use multiple processors, doubling number of processors almost doubles performance So, use two simpler processors on the chip rather than one more complex processor With two processors, larger caches are justified
Power consumption of memory logic less than processing logic

Example: IBM POWER4

Two cores based on PowerPC

POWER4 Chip Organization

Pentium Evolution (1)

8080
first general purpose microprocessor 8 bit data path Used in first personal computer Altair

8086
much more powerful 16 bit instruction cache, prefetch few instructions 8088 (8 bit external bus) used in first IBM PC

80286
16 Mbyte memory addressable up from 1Mb

80386
32 bit Support for multitasking

Pentium Evolution (2)

80486
sophisticated () powerful cache and instruction pipelining built in maths co-processor

Pentium
Superscalar () Multiple instructions executed in parallel

Pentium Pro
Increased superscalar organization Aggressive () register renaming branch prediction data flow analysis speculative execution

Pentium Evolution (3)

Pentium II
MMX technology graphics, video & audio processing

Pentium III
Additional floating point instructions for 3D graphics

Pentium 4
Note Arabic rather than Roman numerals Further floating point and multimedia enhancements

Itanium
64 bit see chapter 15

See Intel web pages for detailed information on processors

Internet Resources
http://www.intel.com/
Search for the Intel Museum

http://www.ibm.com http://www.dec.com Charles Babbage Institute PowerPC Intel Developer Home