Design and Simulation of 8 Bit Arithmetic Logic Unit
Design and Simulation of 8 Bit Arithmetic Logic Unit
Design and Simulation of 8 Bit Arithmetic Logic Unit
Submitted by:
1. SHIVANTH KUMAR(0282092807)
2. BHUVNESH KUMAR(0282092807)
3. MOHAMMAD IHTESHAM(0752092807)
of the degree of
BACHELOR OF TECHNOLOGY
IN
AT
NEW DELHI
DECEMBER 2010
DECLARATION
Name Signature
Mohammad Ihtesham
Shivnath Kumar
Bhuvnesh Kumar
This is to certify that the project entitled “Design and Simulation of 8 Bit
Arithmetic Logic Unit” is the bona fide work carried out by:
• Mohammad Ihtesham (0752092807)
(Lecturer)
E.C.E.
PLACE:
DATE: (SEAL OF THE
COLLEGE)
ACKNOWLEDGEMENT
First and foremost, we would like to express our sincere gratitude to our project
mentor Mr. ARUN PRAKASH. We were privileged to experience a sustained
enthusiastic and involved interest from her side. This fueled our enthusiasm even
further and encouraged us to boldly step into what was a totally dark and
unexplored expanse before us.
We would also like to thank our Friends who were ready with positive comments
all the time, whether it was an off-hand comment to encourage us or a constructive
piece of criticism and a special thanks to Mrs. Mamta Jain (HOD ECE) who
arranged the needed requirements for all of us.
Last but not least, we would like to thank the G.B Pant staff members and
Mr.Dhnanjay Kimothi, in particular, for extending a helping hand at every
juncture of need.
ABSTRACT
This project includes the designing of 8 –Bit Arithmetic Logic Unit and simulating
its components using VHSIC HDL. The implementation strategies have been
borrowed from most popular Xilinx ISE software. The method applied in this
project is to design and test all the wat through starting with discrete component
design and later VHDL based design on the FPGA.
An arithmetic logic unit (ALU) is the part of a computer processor (CPU) that
carries out arithmetic and logic operations on the operands in computer instruction
words. ALU performs operations such as addition, subtraction and multiplication
of integers and bitwise AND, OR, NOT, XOR and other Boolean operations. The
CPU's instruction decode logic determines which particular operation the ALU
should perform, the source of the operands and the destination of the result.
We have presented our work in the use of the VHDL environment. The work
included the development of a number of VHDL models and sequences of input
stimuli and the gathering of performance data from their execution. The instruction
set adopted here is extremely simple that gives an insight into the kind of
hardware, which should be able to execute the set of instructions properly. For
synthesis purpose the targeted FPGA device used is SPARTAN-3. The device can
accept two numbers of 8 bit binary data and can perform logical/arithmetic
operation depending on the 4 bit Operation code given.
8 BIT ALU DESIGN
CONTENTS
CHAPTER 1: INTRODUCTION TO VHDL
Overview of VHDL……………………………………………4
History of VHDL………………………………………………5
Process…………………………………………………………20
Hierarchical Design……………………………………………..24
Area Optimization………………………………………………25
8 BIT ALU DESIGN
Speed Optimization……………………………………………..26
Technology Mapping…………………………………………….26
Placement…………………………………………………….......27
Routing……………………………………………………….......27
Design Overview………………………………………………….36
Logical Unit……………………………………………………….40
Arithmetic Unit……………………………………………………44
Instruction Set…………………………………….……………….45
Design Implementation……………………………………………46
VHDL Code……………………………………………………….49
CHAPTER 5 : SYNTHESIS
Synthesis Report………………………………………………......52
2
8 BIT ALU DESIGN
Bitgen Report……………………………………………………...68
RTL Schematic…………………………………………………….73
Simulation Waveforms…………………………………………….76
Floorplan…………………………………………………………..78
CHAPTER 6 : EPILOGUE
Conclusion………………………………………………………….79
Bibliography………………………………………………………..80
3
8 BIT ALU DESIGN
CHAPTER 1
INTRODUCTION TO VHDL
1.1 OVERVIEW OF VHDL
VHDL can be used for documentation, verification, and synthesis of large digital
designs. This is actually one of the key features of VHDL, since the same VHDL
code can achieve all three of these goals, thus saving a lot of effort and reducing
the introduction of errors between translating a specification into an
implementation.
In addition to being used for each of these purposes, VHDL can be used to take
three different approaches to describing hardware. These three different
approaches are the structural, data flow, and behavioral methods of hardware
description. Most of the times a mixture of the three methods are employed and a
complete design will have different sections expressed in different ways. The terms
algorithmic and RTL (Register Transfer Language) are sometimes used for
behavioral and dataflow.
4
8 BIT ALU DESIGN
Alliance toolset for instance is a free VHDL compiler, simulator and synthesis tool
that runs on PCs; it has several restrictions. In practice such tools will still allow
useful work to be done, within their target environment so the restrictions are
rarely too severe.
VHDL is a standard (VHDL-1076) developed by the IEEE. The language has been
through a couple of revisions, the most widely used version is the 1987 (Std 1076-
1987) version, sometimes referred to as VHDL’87, but also just VHDL. However,
there is a newer revision of the language referred to as VHDL’93. VHDL’93
(adopted in 1994 of course) is fairly new and is still in the process of replacing
VHDL’87. The appendix at the end of this document lists further reading for these
standards and the library has some videotapes that describe the differences; they
are unlikely to be of concern to the neophyte VHDL programmer/designer.
The development of VHDL was initiated in 1981 by the United States Department
of Defence to address the hardware life cycle crisis. The cost of reprocuring
electronic hardware as technologies became obsolete was reaching crisis point,
because the function of the parts was not adequately documented, and the various
components making up a system were individually verified using a wide range of
different and incompatible simulation languages and tools. The requirement was
for a language with a wide range of descriptive capability that would work the
same on any simulator and was independent of technology or design methodology.
1.2.2 STANDARDIZATION
The standardization process for VHDL was unique in that the participation and
feedback from industry was sought at an early stage. A baseline language (version
7.2) was published 2 years before the standard so that tool development could
begin in earnest in advance of the standard. All rights to the language definition
were given away by the DoD to the IEEE in order to encourage industry
acceptance and investment.
5
8 BIT ALU DESIGN
DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with
every ASIC delivered to the DoD. The best way to provide the required level of
description is to use VHDL throughout the design process.
As an IEEE standard, VHDL must undergo a review process every 5 years (or
sooner) to ensure its ongoing relevance to the industry. The first such revision was
completed in September 1993, and this is still the most widely supported version of
VHDL.
One of the features that was introduced in VHDL-1993 was shared variables.
Unfortunately, it wasn’t possible to use these in any meaningful way. A working
group eventually resolved this by proposing the addition of protected types to
VHDL. VHDL 2000 Edition is simply VHDL-1993 with protected types.
1.2.6 VHPI
In 2007, an amendment to VHDL 2002 was created. This introduces the VHDL
Procedural Interface (VHPI) and also makes a few minor changes to the text of
VHDL 2002. Apart from the VHPI itself, no new features were added to VHDL.
The VHPI allows tools programmable access to a VHDL model before and during
simulation. In other words, you can write programs in a language such as C that
interact with a VHDL simulator.
1.2.7 VHDL-2008
6
8 BIT ALU DESIGN
Since the publication of the first IEEE standard in 1987 several revised versions
have appeared. The first, in 1993, had the most extensive changes. VHDL 2000
Edition introduced protected types and VHDL-2002 contains mainly minor
changes. VHDL-2008 is the name of the new version of VHDL. As with the earlier
revisions, this doesn’t radically alter the language, but it does provide a wider set
of modifications than previously.
A draft of the proposed revision (version 4.0) was delivered by Accellera to the
IEEE in 2008. The standard is now available from the IEEE and is known as IEEE
Std. 1076-2008.
For the use with Field Programmable Gate Arrays (FPGAs) several problems exist.
In the first step, 7ehavio equations are derived from the VHDL description, no
matter, whether an ASIC or a FPGA is the target technology. But now, this
7ehavio code has to be partitioned into the configurable logic blocks (CLB) of the
FPGA. This is more difficult than the mapping onto an ASIC library. Another big
problem is the routing of the CLBs as the available resources for interconnections
are the bottleneck of current FPGAs.
While synthesis tools cope pretty well with complex designs, they obtain usually
only suboptimal results. Therefore, VHDL is hardly used for the design of low
complexity Programmable Logic Devices (PLDs).
VHDL can be applied to model system 7ehavior independently from the target
technology. This is either useful to provide standard solutions, e.g. for micro
controllers, error correction (de-)coders, etc, or behavioural models of
microprocessors and RAM devices are used to simulate a new device in its target
environment.
7
8 BIT ALU DESIGN
If the model shows the desired behavior, the VHDL description will be
synthesized. A synthesis tool selects the appropriate gates and flip-flops from the
specified ASIC library in order to reproduce the functional description. It is
essential for the synthesis procedure that the sum of the resulting gate delays along
the longest paths (from the output to the input of every Flip Flop) is less than the
clock period.
The propagation delay along the signal wires have to be estimated first because the
real values are available after the layout is finished. The process of feeding these
values back into the VHDL model is called back annotation. Once again it must be
checked, whether the circuit fulfills the specified timing constraints.
8
8 BIT ALU DESIGN
EXECUTION OF STATEMENTS:
SEQUENTIAL
CONCURRENT
METHODOLOGIES
ABSTRACTION
MODULARITY
HIERARCHY
VHDL distinguishes itself from other languages by the way assignments are
executed because two basic types of statements are known:
9
8 BIT ALU DESIGN
Abstraction allows for the description of different parts of a system with different
amount of detail. Modules which are needed only for the simulation do not have to
be described as detailed as modules that might be synthesized.
Modularity enables the designer(s) to split big functional blocks and to write a
model for each part.
Hierarchy lets the designer build a design out of sub modules which may consist
of several sub modules, themselves. Each level of hierarchy may contain modules
of different abstraction levels. The sub modules of these models are present in the
next lower hierarchical level.
10
8 BIT ALU DESIGN
easier to write the code by hand. On the gate level, a schematic is modified as
VHDL netlist descriptions tend to become too complex pretty soon.
The transition from an upper abstraction level to a lower one is supported more or
less efficiently by software.
Logic synthesis, however, has been perfected in recent years. As long as the
designer confines himself to certain simple VHDL constructs that are sufficient for
RT level descriptions, the synthesis tools will be able to reproduce the behavior in
the logic level.
As a result of the ongoing research in efficient place and route algorithms the step
from the logic level to the final layout has been widely automated for digital
standard cell designs.
The designer has to take great care to find a consistent set of input stimuli that do
not contradict the specification. The responses of the model have to be compared
with the expected values which, in the simplest case, can be done with the help of a
waveform diagram that shows the simulated signal values.
11
8 BIT ALU DESIGN
On the RT level, the system is described in terms of registers and logic that
calculates the next value of the storage elements. It is possible to split the code into
two blocks (cf. process statement) that contain either purely combinational logic or
registers. The registers are connected to the clock signal and provide for
synchronous behavior. In practice, the strict separation of Flip Flops from
combinational logic is often annulated and clocked processes describe the registers
and the corresponding update functions.
The gate netlist is generated from the RT description with the help of a synthesis
tool. For this task, a cell library for the target technology which holds the
information about all available gates and their parameters (fan-in, fan-out, delay) is
needed.
Based upon this gate netlist the circuit layout is generated. The resulting wire
lengths can be converted into propagation delays which can be fed back into the
gate level model (back annotation). This allows for thorough timing simulations
without the need for additional simulator software.
12
8 BIT ALU DESIGN
guidelines for partitioning can differ from design to design. Most of the time
functional aspects are considered as partitioning constraint. The existence of well
defined subsystems allows several designers to work in parallel on the same
project as each designer will view his part as a new, complete system.
Hierarchy allows the building of a design out of modules which themselves may be
built out of (sub-) modules. One level of a hierarchical description contains one or
more modules; each module can even have different degrees of abstraction. These
modules can themselves contain sub modules which would be present the next
lower hierarchical level.
Statements are terminated in VHDL with a semicolon. That means as many line
breaks or other constructs as wanted can be inserted or left out. Only the
semicolons are considered by the VHDL compiler.
List are normally separated by commas. Signal assignments are notated with the
composite assignment operator ‘<=’. Self defined identifier as defined by the
VHDL 87 standard may contain letters, numbers and underscores and must begin
13
8 BIT ALU DESIGN
with a letter. Further no VHDL keywords may be used. The VHDL 93 standard
allows defining identifiers more flexible as the next slide will show.
14
8 BIT ALU DESIGN
The input and output signal names and their data types are defined in the port
statement which is initiated by the keyword ' port '. The list of ports is enclosed in a
'(' ')' pair. For each list element the port name(s) is given first, followed by a ':', the
port mode and the data type. Within the list, the ';' symbol is used to separate
elements, not to terminate a statement. Consequently, the last list element is not
followed by a ';'!
A, B: in bit;
end HALFADDER;
end ADDER;
Several ports with the same mode and data type can be declared by a single port
statement when the port names are separated by ','. The port mode defines the data
flow (in: input, i.e. the signal influences the module behavior; out: output, i.e. the
signal value is generated by the module) while the data type determines the value
range for the signals during simulation.
15
8 BIT ALU DESIGN
1.10.2 ARCHITECTURE
The architecture contains the implementation for an entity which may be either a
behavioral description (behavioral level or, if synthesizable, RT level) or a
structural netlist or a mixture of those alternatives. An architecture is strictly linked
to a certain entity. An entity, however, may very well have several architectures
underneath, e.g. different implementations of the same algorithm or different
abstraction levels. Architectures of the same entity have to be named differently in
order to be distinguishable. The name is placed after the keyword ‘ architecture ‘
which initiates an architecture statement. ‘RTL’ was chosen in this case.
16
8 BIT ALU DESIGN
end RTL;
It is followed by the keyword ‘ of ‘ and the name of entity that is used as interface
(‘HALFADDER’). The architecture header is terminated by the keyword ‘ is ‘, like
in entity statements. In this case, however, the keyword ‘ begin ‘ must be placed
somewhere before the statement is terminated. This is done the same way as in
entity statements: The keyword ‘ end ‘, followed by the architecture name. Once
again, the keyword ‘ architecture ‘ may be repeated after the keyword ‘ end ‘ in
VHDL’93. As the VHDL code is synthesizable, RTL was chosen as architecture
name. In case of this simple function, however, there is no difference to behavioral
(algorithmic) description. We will use ‘BEHAVE’, ‘RTL’, ‘GATE’, ‘STRUCT’
and ‘TEST’ to indicate the abstraction level and the implemented behavior,
respectively. The name ‘EXAMPLE’ will be used whenever the architecture shows
the application of new VHDL elements and is not associated with a specific entity.
keyword ' begin ' and holds concurrent statements. These can be simple signal
assignments, process statements, which group together sequential statements, and
component instantiations. Concurrency means that the order in which they appear
in the VHDL code is not important. The signal SUM, for example, gets always the
result of (3 + 7), independently of the location of the two assignments to the
signals DIGIT_A and DIGIT_B.
begin ...
Signal assignments are carried out by the signal assignment operator ' <= '. The
symbol represents the data flow, i.e. the target signal whose value shall be updated
is placed on the left side of the operator. The right side holds an expression that
evaluates to the new signal value. The data types on the left and on the right side
have to be identical. Please remember that the signals that are used in this example
were defined implicitly by the port declaration of the entity.
18
8 BIT ALU DESIGN
Multiple architectures can be created for a particular entity. For example, we might
wish to create several architectures for a particular entity with each architecture
optimized with respect to a design goal:
Performance
Area
Power consumption
Ease of simulation
1.11 PROCESS
19
8 BIT ALU DESIGN
Behavioral descriptions are supported with the process statement. The process
statement can appear in the body of an architecture declaration just as the signal
assignment statement does. The contents of the process statement can include
sequential statements like those found in software programming languages. These
statements are used to compute the outputs of the process from its inputs.
Sequential statements are often more powerful, but sometimes have no direct
correspondence to a hardware implementation. The process statement can also
contain signal assignments in order to specify the outputs of the process.
Begin
Z_OR <= A or B;
end RTL;
20
8 BIT ALU DESIGN
A process statement starts with an optional label and a ':' symbol, followed by the
process keyword. The sensitivity list is also optional and is enclosed in a '(' ')' pair.
Similar to the architecture statement, a declarative part exists between the header
code and the keyword ' begin '. The sequential statements are enclosed between
“begin” and ' end process '. The keyword ' process ' has to be repeated! If a label
was chosen for the process, it has to be repeated in the end statement, as well.
21
8 BIT ALU DESIGN
Several processes
run parallel
sequential execution of
statements
Process statements are concurrent statements while the instructions within each
process are executed sequentially, i.e. one after another. All processes of a VHDL
design run in parallel, no matter in which entity or hierarchy level they are located.
They communicate with each other via signals. These signals need to be ports of
the entities if processes from different architectures depend from another.
22
8 BIT ALU DESIGN
CHAPTER 2
INTRODUCTION TO SYNTHESIS
2.1 WHAT IS LOGIC SYNTHESIS?
Logic synthesis is the process of converting a high-level description of design into
an optimized gate-level representation. Logic synthesis uses standard cell library
which have simple cells, such basic logic gates like and , or and nor, or macro
cells, such as adder, muxes, memory, and flip-flops. Standard cells put together is
called technology library. Normally technology library is known by the transistor
size (0.18u, 90mm). A circuit description is written in Hardware Description
Language (HDL) such as VHDL. The designer should first understand the
architectural description. Then he should consider design constraints such as
timing area, testability, and power.
Synthesis is a broad term often used to describe very different tools. Synthesis can
include silicon compilers and function generators used by ASIC vendors to
produce regular RAM and ROM type structures. Synthesis in the context of this
tutorial refers to generating random logic structures from VHDL descriptions. This
is best suited to gate arrays and programmable devices such as FPGAs. Sy nthesis
is not an easy task. It is vital to tackle High Level Design using VHDL with
realistic expectations of synthesis. Other tools which use VHDL, such as synthesis,
23
8 BIT ALU DESIGN
will make their own interpretation of the VHDL language. This is an IEEE
standard for VHDL synthesis (IEEE Std. 1364.1-2002) but no vendor adheres
strictly to it. It is not sufficient that the VHDL is functionally correct, it must be
written in such a way that it directs the synthesis tool to generate good hardware,
and moreover, the VHDL must be matched to the idiosyncrasies of the particular
synthesis tool being used. We shall tackle some of these idiosyncrasies in this
VHDL tutorial.
24
8 BIT ALU DESIGN
25
8 BIT ALU DESIGN
As common approach is to identify the critical path and to work on reducing that a
simple optimization might be replaced each component on the critical path with a
higher rated (i.e. faster but more power intensive equivalent) but functionally
equivalent component from the library. Other optimization techniques might be to
strip out string inverters from a design where, e.g. AND gates are slower than Ors
gates. To attempt to replace all ANDs with OR.
Speed optimization is usually applied after area optimization has taken place. It
improves the performance, but only to a certain extent. If after speed optimization
the circuit still does not meet the required specifications, then the designer must go
back and restructure behavioral specifications with a structural or data flow.
2.8 PLACEMENT
The next step after technology mapping is placement of logic blocks. A number of
efficient techniques has been developed, which can be easily adopted to use for
FPGAs.
2.9 ROUTING
Routing refers to the process of inter-connecting the various logic block of the
FPGA. Some of the terms used in the routing are:
Net- a set of logic pins that are to be electrically connected. A net can be
divided into one or more connection.
Track- a straight section of wire that spans the entire width or length of a
routing channel. A track can be composed of a number of wire segments of
various lengths.
Routing channel- the rectangular area that lies between two rows or two
column of logic blocks. A routing channel contains a number of tracks.
27
8 BIT ALU DESIGN
CHAPTER 3
PROGRAMMABLE LOGIC DESIGN
3.1 HISTORY
By the late 1970s, standard logic devices were all the rage, and printed circuit
boards were loaded with them. Then someone asked, “What if we gave designers
the ability to implement different interconnections in a bigger device?” This would
allow designers to integrate many standard logic devices into one part.
To offer the ultimate in design flexibility, Ron Cline from Signetics (which was
later purchased by Philips and then eventually Xilinx) came up with the idea of
two programmable planes. These two planes provided any combination of “AND”
and “OR” gates, as well as sharing of AND terms across multiple ORs.
This architecture was very flexible, but at the time wafer geometries of 10 μm
made the input-to-output delay (or propagation delay) high, which made the
devices relatively slow. The features of the PLA were:
28
8 BIT ALU DESIGN
MMI (later purchased by AMD™) was enlisted as a second source for the PLA
array. After fabrication issues, it was modified to become the programmable array
logic (PAL) architecture by fixing one of the programmable planes.
This new architecture differed from that of the PLA in that one of the
programmable planes was fixed – the OR array. PAL architecture also had the
added benefit of faster tPD and less complex software, but without the flexibility of
the PLA structure. Other architectures followed, such as the PLD. This category of
devices is often called Simple PLD.
• Lower fuse count; faster than PLAs (at the time, fabricated on a 10 μM process)
29
8 BIT ALU DESIGN
The architecture had a mesh of horizontal and vertical interconnect tracks. At each
junction was a fuse. With the aid of software tools, designers could select which
junctions would not be connected by “blowing” all unwanted fuses. (This was done
by a device programmer, but more commonly these days is achieved with ISP).
Input pins were connected to the vertical interconnect. The horizontal tracks were
connected to AND-OR gates, also called “product terms”. These in turn connected
to dedicated flip-flops, whose outputs were connected to output pins.
PLDs provided as much as 50 times more gates in a single package than discrete
logic devices! This was a huge improvement, not to mention fewer devices needed
in inventory and a higher reliability over standard logic. PLD technology has
moved on from the early days with companies such as Xilinx producing ultra-low-
power CMOS devices based on flash memory technology.
30
8 BIT ALU DESIGN
• Easily routed
In 1985, Xilinx introduced a completely new idea: combine the user control and
time to market of PLDs with the densities and cost benefits of gate arrays.
Customers liked it, and the FPGA was born. Today Xilinx is the number one
FPGA vendor in the world. An FPGA is a regular structure of logic cells (or
modules) and interconnect, which is under your complete control. This means that
you can design, program, and make changes to your circuit whenever you wish.
With FPGAs now exceeding the 10 million gate limit (the Xilinx Virtex™-4 FPGA
is the current record holder), you can really dream big. FPGAs feature:
• Fine grained
32
8 BIT ALU DESIGN
In design implementation, the first step is translation of low level and generic
netlist file into device specific resources. After translation step, mapping step
checks the design according to device specific rules, add further logic or make
replications to meet the timing requirements using device resources. At last, in
place and route step, already allocated resources are distributed along FPGA taking
into account the physical constraints and routing resources. At this point physical
layout is determined and timing information for design entities and interconnects
(Back Annotation) is available. After routing, the device is ready to be
programmed. In device programming stage, the SRAM based FPGA’s
configuration, which is volatile after power on and also defining the logic and
interconnect, is programmed to a Programmable Read Only Memory (PROM)
device with part name xc18v02. Design specification is a parallel process to design
development. Design entry in either schematic or HDL form can be simulated
behaviorally, while it can be tested based on the code syntax. After synthesis
phase, generated netlist format can be simulated functionally by providing test
vectors and tested by checking the desired output vector. Timing simulation comes
after the place and route phase using back annotation.
33
8 BIT ALU DESIGN
CHAP
34
8 BIT ALU DESIGN
TER 4
DESIGN OF ARITHMETIC LOGIC UNIT
4.1 INTRODUCTION TO ALU:
An arithmetic logic unit (ALU) is the part of a computer processor (CPU) that
carries out arithmetic and logic operations on the operands in computer instruction
words. ALU performs operations such as addition, subtraction and multiplication
of integers and bitwise AND, OR, NOT, XOR and other Boolean operations. The
CPU's instruction decode logic determines which particular operation the ALU
should perform, the source of the operands and the destination of the result.
The width in bits of the words which the ALU handles is usually the same as that
quoted for the processor as a whole whereas its external buses may be narrower.
Floating point operations are usually done by a separate "floating point unit". Some
processors use the ALU for address calculations (e.g. incrementing the program
counter), others have separate logic for this.
In some processors, the ALU is divided into two units, an arithmetic unit (AU) and
a logic unit (LU). Some processors contain more than one AU for example, one for
fixed point operations and another for floating point operations. (In personal
computers floating point operations are sometimes done by a floating point unit on
a separate chip called a numeric coprocessor.)
Typically, the ALU has direct input and output access to the processor controller,
main memory (random access memory or RAM in a personal computer), and
35
8 BIT ALU DESIGN
input/output devices. Inputs and outputs flow along an electronic path that is called
a bus. The input consists of an instruction word (sometimes called a machine
instruction word) that contains an operation code (sometimes called an "op code"),
one or more operands, and sometimes a format code. The operation code tells the
ALU what operation to perform and the operands are used in the operation. (For
example, two operands might be added together or compared logically.) The
format may be combined with the op code and tells, for example, whether this is a
fixed point or a floating point instruction. The output consists of a result that is
placed in a storage register and settings that indicate whether the operation was
performed successfully. (If it isn't some sort of status will be stored in a permanent
place that is sometimes called the machine status word.)
In general, the ALU includes storage places for input operands, operands that are
being added, the accumulated result (stored in an accumulator), and shifted results.
The flow of bits and the operations performed on them in the subunits of the ALU
is controlled by gated circuits. The gates in these circuits are controlled by a
sequence logic unit that uses a particular algorithm or sequence for each operation
code. In the arithmetic unit, multiplication and division are done by a series of
adding or subtracting and shifting operations. There are several ways to represent
negative numbers. In the logic unit, one of 16 possible logic operations can be
performed such as comparing two operands and identifying where bits don't match.
The design of the ALU is obviously a critical part of the processor and new
approaches to speeding up instruction handling are continually being developed.
The Arithmetic and logic Unit has two eight-bit input signals Accumulator_in(7 -0)
and Data_in(7 -0) taken and controlled from trainer switches and loaded into
registers Accumulator and Data respectively.
clk- Clock Input: This is a signal from the FPGA internal clock.
4.2.3 MODULES
36
8 BIT ALU DESIGN
Figure shows the block diagram of the Arithmetic Logic Unit, which consists of
various modules interconnected by an 8-bit internal data bus. Each of these
modules along with its sub components is described in this section.
REGISTER FILE
Arithmetic and Logical instructions require three source registers and one
destination register. Of the two source registers, three are used as input registers
and the other is used as an instruction register. A total of 4 bits would be required
for any ALU instruction. The actual implementation of any instruction is done with
the instruction register and two 3:8 decoders. These decoder outputs can be used to
drive the required output.
37
8 BIT ALU DESIGN
Figure shows in detail the ALU, the 8-bit inputs A, B and the output Z. The ALU
takes two operands from the A and B registers. The result register Z is used to hold
the ALU output. The ALU has the capability to perform 9 operations as shown in
the figure. After every ALU instruction, the output register is updated.
Logical Unit: We provide all the possible logical operations (nand nor,
exor,not,and,or,xnor) in the ALU.
38
8 BIT ALU DESIGN
39
8 BIT ALU DESIGN
4.3.2 OR GATE:
41
8 BIT ALU DESIGN
`
4.3.6 NAND GATE:
42
8 BIT ALU DESIGN
43
8 BIT ALU DESIGN
Each XOR gate receives input M and one of the inputs of B, i.e., Bi. To understand
the behavior of XOR gate consider its truth table given below. If one input of XOR
gate is zero then the output of XOR will be same as the second input. While if one
input of XOR gate is one then the output of XOR will be complement of the
second input.
So when M = 0, the output of XOR gate will be Bi ⊕ 0 = Bi. If the full adders
receive the value of B, and the input carry C0 is 0, the circuit performs A plus B.
When M = 1, the output of XOR gate will be Bi ⊕ 1 = Bi’. If the full adders receive
the value of B’, and the input carry C0 is 1, the circuit performs A plus 1’s
complement of B plus 1, which is equal to A minus B.
0 0 0 0 Pass Data_in
0 0 0 1 Pass Accumulator_in
0 0 1 0 ADDITION
0 0 1 1 SUBTRACTION
0 1 0 0 AND
0 1 0 1 OR
0 1 1 0 XOR
0 1 1 1 NOT Accumulator_in
1 0 0 0 NOT Data_in
INCREMENT
1 0 0 1
Accumulator_IN
DECREMENT
1 0 1 0
Accumulator_in
1 0 1 1 MULTIPLICATION
1 1 0 0 NAND
1 1 0 1 NOR
1 1 1 0 XNOR
1 1 1 1 -
Our basic goal was to implement the design on FPGA. We have used Xilinx
Spartan 3 XC3S400 FPGA board mounted on FPGA trainer. Xilinx Spartan-3
FPGAs are ideal for low-cost, high-volume applications and are targeted as
replacements for fixed-logic gate arrays and ASSP products such as bus interface
chip sets. The Spartan-3 (1.2V, 90 nm) FPGA is not only available for a very low
cost, but it integrates many architectural features associated with high-end
programmable logic. This combination of low cost and features makes it an ideal
replacement for ASICs (gate arrays) and many ASSP devices. In order to interface
it with the parallel port of PC we have to setup the parallel port unidirectional
settings (EEP) with IRQ 278 from the bios setup of PC. For that, we first
implemented the design using the Xilinx-ISE simulator. The error free code for this
has been given in coming sections.
After synthesizing the code, we generated the bit stream file after assigning the
input and output ports for the FPGA XC3S400 board using XILINX PACE.
46
8 BIT ALU DESIGN
47
8 BIT ALU DESIGN
Then, we loaded the ALU.bit file on the FPGA using Xilinx- iMPACT.
Followed by, we provided the inputs using trainer switches (via Toggle
Switches) and displayed the outputs using LEDS on the trainer.
Following picture shows the whole design implemented with inputs and outputs.
48
8 BIT ALU DESIGN
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity minor_project is
end minor_project;
begin
begin
case Opcode_in is
-- result = Data_in
49
8 BIT ALU DESIGN
-- result = accumulator_in
-- result = not(accumulator_in)
-- result = not(Data_in);
--result=Accumulator_in
end case;
end Behavioral;
CHAPTER 5
51
8 BIT ALU DESIGN
SYNTHESIS
TABLE OF CONTENTS
2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
52
8 BIT ALU DESIGN
===========================================================
===========================================================
---- Source Parameters
Safe Implementation : No
53
8 BIT ALU DESIGN
Asynchronous To Synchronous : NO
Optimization Effort :1
Keep Hierarchy : NO
Hierarchy Separator :/
===========================================================
* HDL Compilation *
===========================================================
===========================================================
* HDL Analysis *
===========================================================
Multiplier, Multiplicand.
===========================================================
* HDL Synthesis *
===========================================================
Summary:
56
8 BIT ALU DESIGN
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
inferred 8 Multiplexer(s).
8-bit xor2 :1
Macro Statistics
8-bit addsub :1
4x4-bit multiplier :1
# Xors :1
# Multipliers :1
# Multiplexers :1
# Adders/Subtractors :1
===========================================================
===========================================================
57
8 BIT ALU DESIGN
===========================================================
Macro Statistics
# Multipliers :1
4x4-bit multiplier :1
# Adders/Subtractors :1
8-bit addsub :1
# Multiplexers :1
# Xors :1
8-bit xor2 :1
===========================================================
===========================================================
===========================================================
* Final Report *
58
8 BIT ALU DESIGN
===========================================================
Final Results
Keep Hierarchy : NO
Design Statistics
# IOs : 36
Cell Usage :
# BELS : 153
# GND :1
# LUT1 :8
# LUT3 : 64
# LUT4 :9
# MUXCY :7
# MUXF5 : 32
# MUXF6 : 16
# MUXF7 :8
# XORCY :8
# IO Buffers : 36
# IBUF : 28
# OBUF :8
59
8 BIT ALU DESIGN
# MULTs :1
# MULT18X18 :1
===========================================================
---------------------------
Number of IOs: 36
===========================================================
TIMING REPORT
--------------------------------------------------------------------------------
option. All paths that are not constrained will be reported in the
information. For accurate numbers, please refer to the post Place and Route
timing report.
a 50 Ohm transmission line loading model. For the details of this model,
-----------------
Pad to Pad
-----------------+---------------+---------+-------------
-----------------+---------------+---------+------------
Accumulator_in<0>|Result_out<0> | 7.985|
Accumulator_in<0>|Result_out<1> | 8.541|
61
8 BIT ALU DESIGN
Accumulator_in<0>|Result_out<2> | 8.925|
Accumulator_in<0>|Result_out<3> | 8.942|
Accumulator_in<0>|Result_out<4> | 9.136|
Accumulator_in<0>|Result_out<5> | 9.153|
Accumulator_in<0>|Result_out<6> | 9.347|
Accumulator_in<0>|Result_out<7> | 9.364|
Accumulator_in<1>|Result_out<1> | 8.165|
Accumulator_in<1>|Result_out<2> | 8.935|
Accumulator_in<1>|Result_out<3> | 8.952|
Accumulator_in<1>|Result_out<4> | 9.146|
Accumulator_in<1>|Result_out<5> | 9.163|
Accumulator_in<1>|Result_out<6> | 9.357|
Accumulator_in<1>|Result_out<7> | 9.374|
Accumulator_in<2>|Result_out<2> | 7.985|
Accumulator_in<2>|Result_out<3> | 8.541|
Accumulator_in<2>|Result_out<4> | 8.925|
Accumulator_in<2>|Result_out<5> | 8.942|
Accumulator_in<2>|Result_out<6> | 9.136|
Accumulator_in<2>|Result_out<7> | 9.153|
Accumulator_in<3>|Result_out<3> | 8.165|
Accumulator_in<3>|Result_out<4> | 8.935|
Accumulator_in<3>|Result_out<5> | 8.952|
Accumulator_in<3>|Result_out<6> | 9.146|
62
8 BIT ALU DESIGN
Accumulator_in<3>|Result_out<7> | 9.163|
Accumulator_in<4>|Result_out<4> | 7.985|
Accumulator_in<4>|Result_out<5> | 8.541|
Accumulator_in<4>|Result_out<6> | 8.925|
Accumulator_in<4>|Result_out<7> | 8.942|
Accumulator_in<5>|Result_out<5> | 8.165|
Accumulator_in<5>|Result_out<6> | 8.935|
Accumulator_in<5>|Result_out<7> | 8.952|
Accumulator_in<6>|Result_out<6> | 7.985|
Accumulator_in<6>|Result_out<7> | 8.541|
Accumulator_in<7>|Result_out<7> | 8.165|
-----------------+---------------+---------+
68
8 BIT ALU DESIGN
69
8 BIT ALU DESIGN
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
70
8 BIT ALU DESIGN
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | Auto** |
+----------------------+----------------------+
+----------------------+----------------------+
71
8 BIT ALU DESIGN
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
+----------------------+----------------------+
72
8 BIT ALU DESIGN
73
8 BIT ALU DESIGN
74
8 BIT ALU DESIGN
75
8 BIT ALU DESIGN
76
8 BIT ALU DESIGN
77
8 BIT ALU DESIGN
78
8 BIT ALU DESIGN
Data_in : 00101010
Operation: ADDITION
Data_in : 00101010
79
8 BIT ALU DESIGN
Operation: AND
80
8 BIT ALU DESIGN
81
8 BIT ALU DESIGN
CHAPTER 6
EPILOGUE
CONCLUSION
With the help of which we are able to successfully implement the Arithmetic Logic
Unit of a Microprocessor.
82
8 BIT ALU DESIGN
BIBLIOGRAPHY
Volnei A. Pedroni, Circuit Design with VHDL, Prentice Hall India 2005
www.xilinx.com
www.ieee.org
83