Micro-2407 User Must Read

MICRO - 2407
User Manual
Version 1.0
Technical Clarification /Suggestion :

N/F
Technical Support Division,
Vi Microsystems Pvt. Ltd.,
Plot No :75,Electronics Estate,
Perungudi,Chennai - 600 096,INDIA.
Ph: 91- 44-2496 1842, 91-44-2496 1852
Mail : [email protected],
Web : www.vimicrosystems.com
PREFACE
This manual is the user guide to the Micro-2407A kit. The primary objective of this manual is to
learn DSP fundamental and its Applications using MICRO-2407A processor based trainer kit.
This manual consists of seven chapters. In Chapter 1, the hardware features of the Digital
Signal Processor TMS320LF2407A is discussed. The complete technical aspects of
TMS320LF2407A can be had from "TMS320LF/LC240xA DSP Controllers Reference
Guide System and Peripherals " from Texas Instruments.
The Hardware configuration of TMS320LF2407A in Micro-2407A is explained in Chapter 2.

This chapter also gives the details of resources available in the Micro-2407A. Chapter3 describes
how to execute the program in the standalone mode using line assembler.
Example programs aimed at explaining the key software features of TMS320LF2407A using line
assembler are given in Chapter 4. These examples have been selected for a reasonable and
balanced exposure to the important aspects of TMS320LF2407A.
Chapter 5 describes how to execute the programs in the serial monitor mode using cross
assembler.
Chapter-6 describes how to generate various PWM outputs like Fixed Frequency PWM, Sine
Modulated PWM etc. These examples helps to study the generation of PWM signal using
TMS320LF2407A and useful in developing the real time application programs. For more
examples and application, refer the manual "Applications of Micro-2407A in Power Electronics"
We assume that the reader is familiar with the fundamentals of DSP. Further we assume that the
reader is familiar with the general ideas of assembly level programming. For the beginners of
DSP, it will be very helpful to refer the good fashioned DSP book "A Practical approach to
Digital Signal Processing" by Dr.K.Padmanabhan, B.E., M.Sc. (Engg), Ph.d., Dr.S. Ananthi, B.E.,
M.E., Ph.d., Mr.R.Vijayarajeswaran, B.E., M.E.
We shall be grateful to consider suggestions for further improvement of this manual.
Write to:
The Customer-Support Division,

Vi Microsystems Pvt. Ltd.,
Plot No.75, Electronics Estate,
Perungudi, Chennai - 600 096.
PHONE : # (044) 2496 3142.

FAX : # (044) 2496 1536.
Web : www.vimicrosystems.com
E-MAIL: [email protected]
Micro-2407A User Manual Digital Control for Electric Drives
CHAPTER – 1
DIGITAL CONTROL FOR ELECTRIC DRIVES
1.1. INTRODUCTION:
The Motor Control industry is a strong aggressive sector. Each industry to remain
competitive, must reduce costs but also has to answer to power consumption
reduction and EMI radiation reduction issues imposed by governments and power
plant lobbies. The results of these constraining factors are the need of enhanced
algorithms. DSP technology allows to achieve both, a high level of performance as
well as a system cost reduction. Texas Instruments launches a new DSP, referenced
TMS320C240, specifically designed for the Digital Motor Control segment. This
device combining a 16 bit fixed-point DSP core with microcontroller peripherals in a
single chip solution is part of a new generation of DSPs called the DSP controllers.
1.2. MOTOR CONTROL DRIVES:
Electric motors now form a big part in our daily life especially with domestic
applications like hairdryers, fans, mixers and drills …that we do not really pay any
attention to them. We just expect all these items to do their job without even giving a
thought to the motor itself and its rather complex electronics.
Among all the existing motors on the market there are three ‘classical’ motors: the
Direct Current with commutators (wound field) and two Alternative Current motors
the synchronous and the asynchronous motors. These motors, when properly
controlled, produce constant instantaneous torque (very little torque ripple) and
operate from pure DC or AC sine wave supplies.
Implementation of advanced motor drive systems requires the following features from
a typical motor controller
Vi Microsystems Pvt. Ltd., [1-1]

* Capability of generating multiple high frequency, high-resolution PWM

waveforms.
* Fast processing to implement advanced algorithms to minimize torque ripple,

on line parameter adaptation, precise speed control etc.
* Implementing multiple features using the same controller (motor control,

power factor correction, communication, etc.)
* Making the complete implementation as simple as possible (reduced

component count, simple board layout and manufacturing etc.)
* Implementing a flexible solution so that future modification can be realized by

changing software instead of redesigning a separate hardware platform.
A new class of DSP controllers has addressed these issues effectively. These
controllers provide the computational capability of a DSP core and integrate useful
peripherals on chip to reduce the total chip count.
1.3. THE DSP IN MOTOR CONTROL
Market analysis shows that most of all industrial motor applications use AC induction
motors. The reasons for this include high robustness, reliability, low price and high
efficiency (up to 80%). However, the use of induction motors also has its
disadvantages, these lie mostly in its difficult controllability, due to its complex
mathematical model, its non linear behaviour during saturation effect and the
electrical parameter oscillation which depends on the physical influence of the
temperature.
Traditionally motor control was designed with analog components, they are easy to
design and can be implemented with relatively inexpensive components. However,
there are several drawbacks with analog systems. Aging and temperature can bring
about component variation causing the system to need regular adjustment, as the parts
count increases the reliability of the system decreases. Analog components raise
tolerance issues and upgrades are difficult as the design is hardwired. Digital systems
offer improvements over analog designs. Drift is eliminated since most functions are
performed digitally, upgrades can easily be made in software and part count is also
reduced since digital systems can handle several functions on chip.
Digital Signal Processors go on further to provide high speed, high resolution and
sensor less algorithms in order to reduce system costs. Providing a more precise
control to achieve better consumption or radiation performances often means
performing more calculations, the use of some 1-cycle multiplication & addition
instructions included in a DSP speeds-up calculations. Generally fixed point DSPs are
preferred for motor control for two reasons. Firstly, fixed point DSPs cost much less
than the floating point DSPs. Secondly, for most application a dynamic range of 16
bits is enough. If and when needed, the dynamic range can be increased in a fixed-
point processor by doing floating-point calculations in software.

1.4. BENEFITS OF THE DSP CONTROLLERS
The performances of a motor are strongly dependent on its control. DSP controllers
enable enhanced real time algorithms as well as sensor less control. The combination
of both allows reducing the number of components and to optimize the design of
silicon, to achieve a system cost reduction. A powerful processor such as a DSP
controller does the following:
v Favours system cost reduction by an efficient control in all speed range

implying right dimensioning of power device circuits
v Performs high level algorithms due to reduced torque ripple, resulting in lower
vibration and longer life time
v Enables a reduction of harmonics using enhanced algorithms, to meet easier
requirements and to reduce filters cost
v Removes speed or position sensors by the implementation of sensorless
algorithms
v Decreases the number of look-up tables which reduces the amount of memory
required
v Real-time generation of smooth near-optimal reference profiles and move
trajectories, resulting in better-performing
v Controls power switching inverters and generates high-resolution PWM
outputs provides single chip control system
For advanced controls, DSPs controllers may also performs the following:
v Enables control of multi-variable and complex systems using modern

intelligent methods such as neural networks and fuzzy logic.
v Performs adaptive control. DSPs have the speed capabilities to concurrently
monitor the system and control it. A dynamic control algorithm adapts itself in
real time to variations in system behavior.
v Provides diagnostic monitoring with FFT of spectrum analysis. By observing
the frequency spectrum of mechanical vibrations, failure modes can be
predicted in early stages.
v Produces sharp-cut-off notch filters that eliminate narrow-band mechanical
resonance. Notch filters remove energy that would otherwise excite resonant
modes and possibly make the system unstable.
The TMS320C24x DSP includes the same advantages as the microcontroller but also
offers higher speed, higher resolution, and capabilities to implement the math-
intensive algorithms to lower the system cost. The high speed is attributable mainly to
the dual bus of the Harvard architecture as well as single-cycle multiplication and
addition instructions. One bus is used for data and the other is used for program
instructions. This saves time because each is utilized simultaneously. Traditionally,
cost has been a potential disadvantage of the DSP solution, but this aspect has
diminished with the continuing decline of DSP costs. DSP controllers enable
enhanced, real-time algorithms as well as sensor less control. The combination
reduces the number of components and optimizes the design of silicon to achieve a
system cost reduction.

DSPs are capable of processing data at much faster rates than microcontrollers. For
example, the speed of the DSP allows it to estimate motor velocity, a task
accomplished by a tachometer in analog and microcontroller systems.
1.5. APPLICATIONS
The target applications for a fixed point DSP controller having the necessary features
are where the above-mentioned advantages meet the customer’s needs. Typical end
equipment applications with an advanced control are:
v Appliances (washers, blowers, compressors)

v HVAC (heating, ventilation and air conditioning)
v Industrial servo drives (Motion control, Power supply inverters, Robotics)
v Automotive control (electric vehicles).
1.6. DIGITAL CONTROLLER REQUIREMENTS
The following list highlights the digital controller requirements.
v Calculations powerful enough to implement advanced and math-intensive

control algorithms, such as
v Fast response to events to obtain input signals and to unexpected events to
secure the system
v Accurate resolution to minimize quantization errors; therefore, a precise
digital control system is offered
v High sampling rate to avoid aliasing introduced by sampling effects
v Required peripherals to reduce CPU overhead and system cost
1.7. PROCESSOR REQUIREMENTS
The following list highlights the processor requirements.
v Strong calculating power for advanced and math-intensive control algorithms

v Capability to support large word lengths for required resolution and dynamic
range
v Small interrupt latency and fast branch operations capabilities to facilitate
quick response to events, including unexpected events
v High-MIPS CPU to increase the range of the sampling frequency
v Integrate the application-specific peripherals with the processor, such as
timers, A/D converters, PWM generators, and communication interfaces.
Hence, CPU overhead and total system costs are reduced.

1.8. TI TMS320C24X DSP FAMILY – the Optimal Digital Control System

Solution
A new class of DSP controllers is becoming a viable option for even the most cost
sensitive applications like appliances, HVAC systems etc. In addition to traditional
mathematical functions like digital filter, FFT implementations, this new class of
DSPs integrates all the important power electronics peripherals to simplify the overall
system implementation. This integration lowers over all part count of the system and
reduces the board size.
The TMS320C24x, the first single-chip DSP solution for the digital control system
market, integrates the TI 16 bit, fixed-point TMS320C2xLP DSP core with several
microcontroller peripherals. The DSP core itself has up to 20 MIPS (50 ns cycle time)
speed and can perform the useful multiply/accumulate instruction in a single cycle.
The DSP controller TMS320F240 from Texas Instruments is utilized to implement a

three-phase AC induction motor drive with multiple functions. These functions
include basic motor control with closed loop speed control, input power factor
correction using boost topology and serial communication. TMS320F40 has a 20MIPs
16 bit fixed point DSP core. It also integrates the following power electronics
peripherals – 12 PWM channels (out of which 9 are independent), three 16 bit multi-
mode general purpose timers, 16 channel 10 bit ADC with simultaneous conversion
capability, four capture pins, encoder interface capability, SCI, SPI, Watch Dog etc.
Six PWM channels (PWM1 through PWM6) control the three-phase voltage source
inverter. These six PWM channels are grouped in three pairs (PWM 1&2, PWM 3&4,
PWM 5&6). Three compare registers, called Full Compare, are associated with each
PWM channel pair. The compare register values are updated to obtain the proper
PWM output. The on-chip software programmable, dead band module provides
sufficient dead time to avoid shoot through fault. There are three more PWM channels
left to implement other functions like power factor correction.
1.9 3.3V DSP FOR DIGITAL MOTOR CONTROL
New generations of motor control digital signal processors (DSPs) lower their supply
voltages from 5V to 3.3V to offer higher performance at lower cost. Replacing
traditional 5V digital control circuitry by 3.3V designs introduce no additional system
cost and no significant complication in interfacing with TTL and CMOS compatible
components, as well as with mixed voltage ICs such as power transistor gate drivers.
Just like 5V-based designs, good engineering practice should be exercised to
minimize noise and EMI effects by proper component layout and PCB design when
3.3V DSP, ADC, and digital circuitry are used in a mixed signal environment, with
high and low voltage analog and switching signals, such as a motor control system. In
addition, software techniques such as Random PWM method can be used by special
features of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly
reduce noise effects caused by EMI radiation.

Block Diagram of a Typical DSP Motor Controller
The new TMS320LF2407A digital signal processor (DSP) controller, part of the
TMS320C2000 DSP platform of control-optimized DSPs, is ideal for space-
constrained applications that require the control peripherals and ease-of-use of a
traditional microcontroller and the processing power of a DSP. At only 49mm2, the
LF2407A DSP provides 150 MIPS of processing power for precise control in space
Constrained consumer and industrial applications. The detailed architecture of the
TMS320F2407 will be discussed in the next chapter.
The era of analog control systems for electric motor drives is definitely over, and a
wide array of digital devices is available for drive designers. Digital controllers allow
implementation of sophisticated operating algorithms, offering significant technical
advantages thanks to their ability of fast processing of vast data, high operational
flexibility, and ease of integration into automated industrial systems. If the digital
processors involved are so efficient that reserves of computing power remain after the
basic control algorithms have been realized, additional enhancing features can be
implemented, such as the self commissioning and auto tuning, efficiency
optimization, or automated fault diagnostics of the drives.

Micro-2407A User Manual TMS320F2407A Device Overview
CHAPTER – 2
TMS320F2407A DEVICE OVERVIEW
2.1 INTRODUCTION:
It is needless to say that in order to utilize the full feature of the DSP chip
TMS320LF2407A, the DSP engineer must have a complete knowledge of the DSP
device. This chapter gives you an introduction to the hardware aspects of the
TMS320LF2407A DSP processor.
2.2 THE DSC CHIP TMS320LF2407A
The new Texas Instruments TMS320LF2407A digital signal processor (DSP) controller,
part of the TMS320C2000 (24xx series) of control-optimized DSPs, is ideal for space-
constrained applications that require the control peripherals and ease-of-use of a
traditional microcontroller and the processing power of a DSP.
The TMS320LF2407A DSP contains the DSP core processor and useful peripherals
integrated onto a single piece of silicon. The TMS320F2407A combines the powerful
CPU with on-chip memory and peripherals. With the DSP core and control-oriented
peripherals integrated into a single chip, users can design very compact and cost effective
digital control systems, and so Texas named this family of chips are Digital Signal
Controllers (DSC).
The features of the TMS320F2407A are mentioned as below:
• Up to 40-MIPS operation
• Three power-down modes
• Code-compatible control-optimized DSPs
• JTAG scan-based emulation
• 3.3-V and 5-V designs
Texas Instruments offers various DSP processors in the 24xx series. In our trainer kit we
used the latest TMS320LF2407A for design purpose. The below table gives the detailed
information about 24xx family.
Note : TMS320LF2407A is mentioned as LF2407A in the forth coming pages.

2.3 TMS320LF2407A DSP CORE
The heart of the TMS320LF2407A DSP controller is the c2xx DSP core. This core is a
16-bit fixed-point processor, meaning that it works with 16-bit binary numbers. The C2xx
core has its own native instruction set of assembly mnemonics or commands. The user
can program either in assembly or ‘C’ language. However, to write compact, fast
executing programs, it is best to write code in assembly language.

The TMS320F2407A core contains the following units.
1. A 32-bit central arithmetic logic unit (CALU)

2. A 32-bit accumulator
3. Input and output data-scaling shifters for the CALU
4. A 16-bit by 16-bit multiplier
5. A product scaling shifter
6. Eight auxiliary registers (AR0 – AR7)
7. A auxiliary register arithmetic unit (ARAU)
The TMS320LF2407A block diagram is shown below.

2.3.1 Central Arithmetic Logic Unit (CALU)
The DSP core performs 2s-complement arithmetic using the 32-bit CALU. The CALU
uses 16-bit words taken from the data memory, derived from an immediate instruction, or
from the 32-bit multiplier result. In addition to arithmetic operations, the CALU can
perform Boolean operations.
2.3.2 32-BIT ACCUMULATOR:
The TMS320LF2407A contains a 32-bit ALU and accumulator for support of double
precision, two's complement arithmetic. The ALU is a general-purpose arithmetic unit
that operates on 16-bit words taken from the data RAM or derived from immediate
instructions. In addition to the usual arithmetic instructions, the ALU can perform
Boolean operations, providing the bit manipulation ability required of a high-speed
controller. The accumulator stores the output from the ALU and is often an input to the
ALU. Its word length is 32-bit. The accumulator is divided into a high-order word (bits
31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for
storing and loading the high and lower order accumulator words to memory.
2.3.3 SHIFTERS:
The core contains three 32-bit shifters that allow for scaling, bit extraction, extended
arithmetic, and overflow-prevention operations. The three shifters are mentioned below.
The scaling shifters make possible commands that shift data left or right.
* Input data-scaling shifter (input shifter) – This shifter left-shifts 16-bit input data
by 0 to 16 bits to align the data to the 32-bit input of the CALU.
* Output data-scaling shifter (output shifter) – This shifter left-shifts data from the
accumulator by 0 to 7 bits before the output is stored to data memory. The content
of the accumulator is remain unchanged.
• Product-scaling shifter (product shifter) – The product register (PREG) receives

the output of the multiplier. The product shifter shifts the output of the PREG
before that output is sent to the input of the CALU. The product shifter has four
product shift modes (no shift, left shift by one bit, left shift by four bits, and right
shift by six bits), which are useful for performing multiply/accumulate operations,
fractional arithmetic, or justifying fractional products.

2.3.4 16 x 16-BIT PARALLEL MULTIPLIER:
The multiplier performs a 16 x 16-bit two's complement multiplication with a 32-bit

result in a single instruction cycle. The multiplier consists of three units: the T-Register,
P-Register, and multiplier array. The 6-bit T-Register temporarily stores the multiplicand
and the P-Register stores the 32-bit product. Multiplier values either come from the data
memory or are derived immediately from the MPY (multiply immediate) instruction
word. The fast on-chip multiplier allows the device to perform fundamental operations
such as convolution, correlation, and filtering. Two multiply/accumulate instructions in
the instruction set fully utilize the computational bandwidth of the multiplier, allowing
both operands to be processed simultaneously.
2.3.5 Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers
The ARAU generates data memory addresses when an instruction uses indirect
addressing to access data memory. Eight auxiliary registers (AR0 through AR7) support
the ARAU, each of which can be loaded with a 16-bit value from data memory or
directly from an instruction. Each auxiliary registers are mainly used as “pointers” to data
memory locations to more easily facilitate looping or repeating algorithms. The auxiliary
register pointer (ARP) embedded in status register ST0 references the auxiliary register.
2.4 MEMORY
Memory is required to hold programs, perform operations, and execute programming

instructions. There are three main blocks of memory which are present on the LF2407
chip: B0, B1, and B2. Additionally, there are two different memory spaces (program,
data) in which blocks are used.
The LF2407A has 544 16-bit words on-chip dual access random access memory
(DARAM) that are divided into three main memory blocks named B0,B1, and B2.In
addition to the DARAM, there are also 2000 16-bit words of single access random access
memory (SARAM). The main difference between DARAM and SARAM is that
DARAM memory can be accessed twice per clock cycle and SARAM can only be
accessed once per cycle. Thus, DARAM reads and writes twice as fast as SARAM.
In addition to the RAM present on the LF2407A, there is also non-volatile flash memory
(32KW). Unlike RAM, the flash memory does not lose its contents when the LF2407
loses power. The flash memory of the LF2407A is used only to store a program that is to
be run. This flash memory is always enabled in devices that lack an external memory
interface. For the 2407A, which has an external memory interface, the MP/MC pin
determines whether the on-chip program memory (flash) or the off-chip program memory
(customer design specific) is accessed.

2.4.1 Memory Space and I/O Spaces
The 2407A design is based on an enhanced Harvard architecture. These devices have
multiple memory spaces accessible on three parallel buses: a program address bus (PAB),
a data-read address bus (DRAB), and a data-write address bus (DWAB). Each of the
three buses access different memory spaces for different phases of the device’s operation.
Because the bus operations are independent, it is possible to access both the program and
data spaces simultaneously. Within a given machine cycle, the CALU can execute as
many as three concurrent memory operations.
The 240xA address map is organized into three individually selectable spaces:
• Program memory (64K words) contains the instructions to be executed, as well

as immediate data used during program execution.
• Data memory (64K words) holds data used by the instructions.
• Input/output (I/O) space (64K words) interfaces to external peripherals and may
contain on-chip registers.
These spaces provide a total address space of 192K words. The advantage of operating
from external memory is the ability to access a larger address space.
2.5 EMBEDDED PERIPHERALS
While the brain of the TMS320LF2407A DSP is the C2xx core, the TMS320LF2407A
contains several control-oriented peripherals on-chip. The peripherals on the LF2407A
make virtually any digital control requirement possible. Their applications range from
analog to digital conversion (ADC) to pulse width modulation (PWM) generation.
Communication peripherals make possible the communication with external peripherals,
personal computers, or other DSP processors. The embedded peripherals inside the
LF2407A are listed below.
• Two Event Managers (A and B)

• General Purpose (GP) Timers
• Analog-to-Digital converter
• Controller Area Network (CAN) interface
• Serial Peripheral Interface (SPI) – synchronous serial port
• Serial Communication Interface (SCI) - asynchronous serial port
• General- Purpose bi-directional digital I/O (GPIO) pins
• Watchdog Timer
• Phase Locked Loop (PLL) module
• Interrupt module


2.5.1 Event Managers (EVA,EVB)
There are two Event Managers on the TMS320LF2407A, the EVA and EVB. The Event
Manger is the most important peripheral in digital motor control. It contains the necessary
functions needed to control electromechanical devices. Each EV is composed of
functional blocks including timers, comparators, capture units for triggering on an event,
PWM logic circuits, Quadrature-encoder-pulse (QEP) circuits, and interrupt logic.
2.5.2 Analog-to-Digital Converter (ADC)
The ADC on the TMS320LF2407A is used whenever an external analog signal needs to
be sampled and converted to a digital number. The following are the features of the on-
chip ADC.
• 10-bit ADC core with built-in Sample and Hold (S/H)

• Fast conversion time (S/H + Conversion) of 375 ns
• Sixteen (16) multiplexed analog inputs (ADCIN0 – ADCIN15)
• Auto sequencing capability – up to 16 “auto conversions” in a single session
• Two independent 8-state sequencers (SEQ1 and SEQ2) that can be operated
individually in dual-sequencer mode or cascaded into one large 16-state sequencer
(SEQ) in cascaded mode
• Four Sequencing Control Registers (CHSELSEQn) that determine the sequence
of analog channels that are taken up for conversion in a given sequencing mode
• Sixteen (individually addressable) result registers to store the converted values
(RESULT0 – RESULT15)
• Multiple trigger sources for start-of-conversion (SOC) sequence
• Software: Software immediate start (using SOC SEQn bit)
• EVA: Event manager A (multiple event sources within EVA)
• EVB: Event manager B (multiple event sources within EVB)
• External: ADCSOC pin
• Flexible interrupt control allows interrupt request on every end-of-sequence
(EOS) or every other EOS
• Sequencer can operate in start/stop mode, allowing multiple time sequenced
triggers to synchronize conversions
• EVA and EVB can independently trigger SEQ1 and SEQ2, respectively
• Sample-and-hold acquisition time window has separate prescale control
• Calibration mode
The ADC in the LF2407A is mainly used in control feedback loop to monitor motor
performance and the ADC also allows current sensing using a shunt resistor instead of an
expensive current sensor in motor control applications.

2.5.3 Controller Area Network Module
The controller area network (CAN) uses a serial multi-master communication protocol
that efficiently supports distributed real-time control with a very high level of data
integrity, and communication speeds of up to 1 Mbps. The CAN bus is ideal for
applications operating in noisy and harsh environments, such as in the automotive and
other industrial fields that require reliable communication. Prioritized messages of up to
eight bytes in data length can be sent on a multi-master serial bus using an arbitration
protocol and an error-detection mechanism for a high level of data integrity.
The CAN protocol supports four different frame types for communication:
• Data frames that carry data from a transmitter node to receiver node(s)
• Remote frames that are transmitted by a node to request the transmission of a
data frame with the same identifier
• Error frames that are transmitted by any node on a bus-error detection
• Overload frames that provide an extra delay between the preceding and the
succeeding data frames or remote frames
2.5.4 Serial Peripheral Interface (SPI) and Serial Communication Interface (SCI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input/ output (I/O)
port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally
used for communications between the DSP controller and external peripherals or another
controller. Typical applications include external I/O or peripheral expansion via devices
such as shift registers, display drivers, and analog-to-digital converters (ADCs).
The programmable SCI supports asynchronous serial (UART) digital communications

between the CPU and other asynchronous peripherals that use the standard NRZ (non-
return-to-zero) format. The SCI’s receiver and transmitter are double buffered, and each
has its own separate enable and interrupt bits. Both may be operated independently or
simultaneously in the full-duplex mode.
2.5.5 Watchdog Timer
The watchdog (WD) timer peripheral monitors software and hardware operations, and
implements system reset functions upon CPU disruption. The WD timer (when enabled)
will count for a specific amount of time. It is necessary for the user’s software to reset the
WD timer periodically so that an unwanted rest does not occur. If the software goes into
an improper loop, or if the CPU becomes temporarily disrupted, the WD timer overflows
to assert a system reset. Most conditions that temporarily disrupt chip operation and
inhibit proper CPU function can be cleared and reset by the watchdog function. By its
consistent performance, the watchdog increases the reliability of the CPU, thus ensuring
system integrity. All registers in this peripheral are eight bits in width and are attached to
the lower byte of the peripheral data bus of the 16-bit CPU.

2.5.6. General Purpose Bi-Directional Digital I/O (GPIO) Pins
Since there are only a finite number of pins available on the LF2407A device, many of
the pins are multiplexed to either their primary function or the secondary GPIO function.
The digital I/O ports module provides a flexible method for controlling both dedicated
I/O and shared pin functions. All I/O and shared pin functions are controlled using nine
16-bit registers. These registers are divided into two types:
• I/O MUX Control registers (MCRx) – Used to control the multiplexor selection
that chooses between the primary function of a pin or the general purpose I/O
function.
• Data and Direction Control registers (PxDATDIR) – Used to control the data and
data direction of bidirectional I/O pins.
2.5.7. Phase Locked Loop Module
The phased-locked loop (PLL) module contains a crystal oscillator, clock monitor circuit,
clock enable circuit, and prescaler unit. The purpose of using a PLL is to multiply the
external frequency reference to a higher frequency for use internally. This avoids having
high frequency signals sent to externally packaged pins, which could cause excessive
EMI. PLLs also avoid the use of crystals above 20 – 25 MHz. Such crystals usually
operate in overtone mode and require extra tank circuit components.
2.5.8. Interrupt Module
The interrupts on the LF2407A allow the device hardware to trigger the CPU of the
LF2407A (CPU=C2xx DSP core) to break from the current task, branch to a new section
of code and start a new task, then return back to the initial task. The new task refereed to
in the previous sentence is known as the Interrupt Service Routine (ISR).
The LF2407A CPU supports one non-maskable interrupt (NMI) and six maskable
prioritized interrupt requests (INT1–INT6) at the core level. The LF2407A devices have
many peripherals, and each peripheral is capable of generating one or more interrupts in
response to many events at the peripheral level. Because the LF2407A CPU does not
have sufficient capacity to handle all peripheral interrupt requests at the core level, a
centralized interrupt controller (PIE) is required to arbitrate the interrupt requests from
various sources such as peripherals and other external pins.
2.5.9. Joint Test Action Group (JTAG) Port
The JTAG port provides a standard method of interfacing a personnel computer with the
DSP controller for emulation and development. An external parallel port based emulation
pod provides the connection between the JTAG module on the LF2407A and the personal
computer. The JTAG module allows the PC to take full control over the DSP processor.
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MICRO - 2407A User Manual Hardware Overview
CHAPTER - 3
HARDWARE OVERVIEW
3.1. INTRODUCTION:
This chapter gives brief hardware features available on the Micro-2407A trainer kit. It has many
useful onboard features like a 16x2 LCD Display and IBM PC Keyboard interface to use the
trainer kit in stand alone mode. The student can use these hardware features to set maximum
knowledge on TMS320LF2407A and interface many hardware peripherals to it. The following
section describes the various interface used, memory configuration and I/O configuration available
in the trainer kit.
3.2. KEYBOARD AND DISPLAY INTERFACE:
Data entry to the kit can be done through 104 keys IBM PC/AT keyboard, interfaced to the CPU
TMS320LF2407A with the help of CD4015 keyboard controller. The 16x2 LCD display is
interfaced to the CPU through the 74LS244 latch.
3.3. MEMORY CONFIGURATION:
There are two ways of using the physical memory on board the LF2407A: storing a program or
storing a data. A program that is to be run must be stored in memory that is mapped to program
space. Likewise, only memory that is data space may be used to store data. Program memory is
written to when a program is loaded into the LF2407A. Data memory is normally written to
during the execution of a program, where the program might use the data memory as temporary
storage for calculation variables and results.
3.3.1. Program Memory:
When a program is loaded into the LF2407A, the code resides in and run from program memory
space. In addition to storing the user code, the program memory can also store immediate
operands and table information. The below table shows the program memory mapping for
LF2407A.

Micro-2407A program memory allocation table.
Starting Ending Description Memory

Address Address Type
0000H 1FFFH Monitor program Area EPROM
2000H BFFFH Serial Monitor, Assembler, EPROM

Dis-Assembler, Program Area
C000H FF00 User Program RAM Area RAM
FF01 FFFFH Re-mapped Interrupt Vector locations RAM

and monitor scratch pad area

3.3.2 Data Memory:
For the execution of a program, it is necessary to store calculation results or look up tables in
memory. The memory allocated for this function is called data memory. In order to store a value
to a data memory address, the corresponding memory block must reside in data memory space.
Block B1 and B2 permanently reside in data space, while block B0 and the SARAM are
configurable for either program or data using the CNF bit.
The data memory space has the second functionality of providing an easy way to access on-chip
configuration registers and peripherals. The internal data memory includes the memory mapped
registers, DARAM blocks, and peripheral memory-mapped registers. The remaining 32K words
of memory (8000 to FFFFh) form part of the external data memory. The data memory mapping
for the LF2407A is shown below.


Micro-2407A DATA MEMORY ALLOCATION TABLE:
Starting Ending Description

Address Address
0000H 005FH Mapped to CPU Internal Register
0060H 007FH On-chip block B2. Reserved in Micro-2407A
0080H 01FFH Reserved
0100H 02FFH On-chip block B0, Available for user.
0300H 04FFH On-chip block B1, Reserved in Micro-2407A
0800H 2BFFH User RAM area
2C00H 7FFFH On-Board user Data RAM Expansion
8000H 80FFH Reserved Area
9000H FFFFH On-Board user Data RAM
Note: During power-on reset all the three blocks are used for Micro-2407A initialization by
monitor.
3.3.3 I/O Memory:
I/O memory is solely used for accessing external peripherals such as the digital-to-analog
converter (DAC), LCD etc. The assembly instruction “OUT” is used to write to an address that is
mapped to I/O memory. It is important to make sure the Linker Command File is configured
properly and the correct Data Page (DP) is set to avoid in advertently writing to an undesired or
reserved memory address. The memory mapping for I/O spaces are given below.

MICRO-2407A I/O MEMORY ALLOCATION TABLE::
All the peripherals are I/O mapped. The I/O addresses are given in the table below.
I/O ADDRESS READ/WRITE PERIPHERAL USED

IN HEX
00 WRITE LCD Display, Serial

Port and
01 READ Bank Select Register
02 READ/WRITE LCD Display
03 READ IBM PC Keyboard
04 WRITE IBM PC Keyboard
DAC AD8582 CH1 select
05 WRITE address
DAC AD8582 CH2 select
06 Write address
Digital O/P lines
Refer to the technical reference for details of individual ports.

MICRO - 2407A User Manual Software Overview
CHAPTER - 4
SOFTWARE OVERVIEW
This chapter illustrates the use of program and execution mainly in the standalone mode. The
Micro-2407A has 3 software development tools namely
1. Standalone Mode
2. Monitor program
3. Serial Mode
In "Standalone Mode" the Micro-2407A works with a 104 keys keyboard and 16x2 LCD display
and line assembler. With this configuration, the user can enter these program through the
keyboard and edit and display it on the LCD display. The user can enter the Mnemonics using the
Line Assembler, and debug the program to run it on Micro-2407A.
"Monitor Program" is used to enter data directly into Data or Program memory, display the data
etc. It has several commands to enter the user program, for editing and debugging. In "Serial
Mode", it works with a IBM PC computer and program entry and debugging is done at the PC
level.
4.1. Program and Execution:
For program entry and execution the use can either use stand alone mode or serial mode facility
available in the trainer kit.
1. Stand Alone Mode:
In this stand alone mode user can follow the procedure given below to enter and execute the
program.
Program prepared can be entered by using Line assembler in the user program memory starting
from: C000H.
Caution: Line Assembler has the following limitations. Please take care of this while
entering your program under Line Assembler.
1. While using "SHIFT" key, press only once. Don't keep pressing "SHIFT" key with some
other keys at the same time.
2. If you happen to enter instructions like RETC cond, [cond], [...] where the conditions are EQ,
NEQ, LT, ... in the standalone mode, Do enter values as given below instead of condition like
EQ, NEQ, NT
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Microsystems Pvt. Ltd., [4-1]
Value Condition
0 EQ
1 NEQ
2 LT
3 LEQ
4 GT
5 GEQ
6 NC
7 C
8 NOV
9 OV
A BIO
B NTC
C TC
D UNC
for e.g., in Standalone mode, you can enter RETC 0 instead of entering RETC EQ
3. In Standalone mode, enter 0, 1, 2, 3, 4, 5, 6 and 7 instead of entering AR0, AR1.....AR7
E.g. LAR 1, #9000 (In Standalone Mode)

LAR AR1, #9000 (Serial Monitor Mode)
EXAMPLE:
The program can be entered through the Line Assemblers provided in the "Standalone Mode".
The line assembler takes directly mnemonics of TMS320LF2407A processor, like a Assembler.
But only one instruction can be assembled at a time, which in turn is converted to machine code.
This machine code is displayed in the LCD display for verification for the user. Any program can
be written like this and assembler using the "Line assembler" and the codes are loaded into the
memory of Micro-2407A. Then, the user can use the Debugger commands of monitor program
like Substitute Data, GO, and Fill etc for debugging the program and executing it.
The actual entry and corresponding LCD display for two instructions will be as follows.
First reset the Micro-2407A kit. LCD flashes as follows
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Pvt. Ltd. Chennai
Micro-2407A Trainer
#_
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Then enter "AS" for invoking Line Assembler.
Whereas the display will be as follows
Micro-2407A Trainer
#AS
Line Assembler
Start Address:
In the start address enter the starting address of the program to be loaded, usually "C000". Now
enter C000 and press the Enter key
The LCD display will be,
Start Address:
C000
Now we can start entering the mnemonics. We will enter 2 mnemonics for trial basis
i) LACC #2345, 0
ii) LAR 1, #2000
a) Enter the mnemonics LACC #2345, 0 as follows
C000-LACC #2345,0
C000
After pressing, "ENTER" key, the display will be as follows.
C002-
C000 BF80 2345
Whereas the Line Assembler assembles the mnemonics and generates the corresponding code.
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b) For this instruction "LAR 1, #2000",
C002 - LAR 1, #2000

C000 - BF80 2345
C004
C002 BF09 2000
Keep repeating this operation for the next mnemonic entry. To terminate the entering mnemonics,
enter the (.) and press enter key and display will be as follows
Micro-2407A Trainer
#
If you want to go in to dis-assembler to see mnemonics, which we have entered already through
assembler, Enter DS as follows
Micro-2407A Trainer
#DS
The display will be as follows,
Dis-assembler
Start:
Where as do enter the address (for e.g. C000) and it will appear as
Start: C000
End:
Where as enter end address (approximately the address which we need)
Start: C000
End: C003
After pressing the "ENTER" key, you can see the mnemonics with opcodes which we have
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already entered. That will be appearing in the display as follows
C000 BF80 2345

LACC #2345,0
Press "ENTER" key
C002 BF09 2000

LAR 1, #2000
Press "ENTER" key
Micro-2407A Trainer
#
EXAMPLE PROGRAM
The following sample program fills 16-bit data in data memory from 9000H to A000H. The data
to be filled in this example is 2345H.
Address Opcode Mnemonics Function

C000 BD20 LDP #120 ;DP = 120
C001 BF80 2345 LACC #2345 ; ACCL = 2345
C003 BF09 9000 LAR 1,#9000 ; AR1 = 9000
C005 BF0A 1000 LAR 2,#1000 ; AR2 = 1000
C007 8B89 MAR *, 1 ; ARP = AR1
C008 909A SACL *+, 0.2 ; *AR1+ = ACCL,
ARP = AR2
C009 7B90 C006 BANZ C007, *- ; Condition OK PC =
C007
Else PC = C00B
C00B 7980 C00B B C00B ; PC = C00B
Enter the above assembly program instructions one after another pressing enter key after the
completion of one line, once the program entry is completed, to terminate the entry mode, enter
dot (.) and press the enter key to come out to the command prompt.
To execute the program use the "GO" command given in the display below (Refer Technical
reference for more clarifications)
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Micro-2407A Trainer
#GO C000
Press the enter key, where C000H is the program starting address. Once GO command is given,
and then the following display is found in the screen.
Executing.....
To terminate the execution of the program press the "Reset" switch to come to the prompt screen.
Now verify the data "2345" is filled in data memory location 9000H to A000H using "SD"
(Substitute Data Memory) command.
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MICRO-2407A User Manual Examples on Standalone Mode
CHAPTER - 5
GETTING STARTED WITH BASIC EXAMPLES ON
STANDALONE MODE
This chapter mainly described about examples of TMS320LF2407A assembly program using line
assembler in the standalone mode for Arithmetic manipulations and usage of various instruction
of TMS320LF2407A processor. Since the user are in the beginning stage, the examples do not
involve much complexity. Each example is presented in the following format.
AIM:
This gives the primary objective of the example.
THEORY:
The underlying theory of the example is given in this part.
PROGRAM:
The complete assembly language program in TMS320LF2407A code is given for every
example. These programs will guide the user for understanding the instruction set of the DSP
TMS320LF2407A.
5.1 ARITHMETIC MANIPULATIONS:
EXAMPLE 1 - EXTENDED-PRECISION ADDITION:
AIM:
To illustrate the extended precision addition of two 64-bit numbers.
THEORY:
Numerical analysis, floating point computations or other operations may require arithmetic to be
executed with more than 32-bits of precision. Since, the TMS320LF2407A is 16-bit fixed-point
processor, software is required for the extended precision of arithmetic operations. For proper
operation, the overflow mode bit should be reset (OVM = 0) so that the accumulator result will
not be loaded with the saturation value.

In our example, two 64-bit numbers will be added as shown below:
X3 X2 X1 X0
+ Y3 Y2 Y1 Y0
))))))))))))))))
W3 W2 W1 W0
))))))))))))))))
Where all the numbers X3, X2, X1, X0, Y3, Y2, Y1 & Y0 are 16-bit numbers.
TMS320LF2407A has provision to add two 32-bit numbers, so we can add X1 X0 with Y1 Y0.
But how can we add 64-bit numbers X3 X2 X1 X0 with Y3 Y2 Y1 Y0.
TMS320LF2407A has two features that help to make extended precision calculation more
efficient. One of the feature is the carry status bit. The carry bit is set whenever the addition of
a value from the input scaling shifter or the P-register to the accumulator content generate a carry
out of bit 31. Otherwise, the carry bit is reset since the carry out of bit 31 is zero. One exception
to this case is that ADD 5,10h instruction which can only set the carry bit. This allows the
accumulator to generate proper single carry when either the addition to the lower or upper half
of the accumulator actually causes the carry.
The other feature which eases the extended-precision addition is the ADD7,10h instruction.
ADD7,10h instruction adds the 16-bit data memory content to the higher part of accumulator.
PROGRAM EXPLANATION:
In this example, the X operand X3 X2 X1 X0, is made of 16-bit numbers X3, X2, X1 and X0,
with X3 the most significant 16-bits and X0 the least significant 16-bits. The Y operand is Y3 Y2
Y1 Y0, where Y3 is the most significant 16-bits and Y0 is the least significant 16-bits. On
addition, both the operand results in W3 W2 W1 W0. For example the addition of
5432109876543210 and 0123456789012345 results in 555555FFFF555555, as shown:
X-Operand: X3 X2 X1 X0
5432 1098 7654 3210
Y-Operand: Y3 Y2 Y1 Y0
0123 4567 8901 2345
Result: W3 W2 W1 W0
5555 55FF FF55 5555
First load X1 in higher accumulator using LACC instruction and add X0 with accumulator by
using ADDS instruction. Now, the whole 32-bit of X1 X0 is in accumulator. Add Y0 with sign
extension suppressed using ADDS instruction and in the same way Y1 is added to the higher part
of accumulator using ADD instruction with shift. The result of 0-15 bits are stored in data
memory as W0 and 16-31 bits are stored in data memory as W1.

The next section adds the 32-bit numbers X2 X3 and Y2 Y3, and the result is stored in data
memory as W2 and W3.
Caution: We are giving the variables like X0, X1, X2... only for understanding the logic in
standalone mode. Do enter the address directly, as given below in the table instead
of entering variables in the standalone. In the case of serial monitor you can enter
variables like X0, X1, Y0, Y1 directly, since we have assembler directives in the cross
assembler.That will be described in coming chapters.
Enter the data as follows in data memory:
Data Memory Data

Address
9000 (X0) 3210
9001 (X1) 7654
9002 (X2) 1098
9003 (X3) 5432
9004 (Y0) 2345
9005 (Y1) 8901
9006 (Y2) 4567
9007 (Y3) 0123
To edit and execute the program, go through the topic chapter-4.
Caution:
By default,LDP #120H instruction considers address values 0000 ,0001,0002 ...which you
have entered in the programs as 9000, 9001, 9002,... respectively.
PROGRAM LISTING:
ADDRESS OPCO DES MNEMONICS FUNCTIONS
C000 BD20 LDP #120H ; DP = 120

C001 6A01 LACC 0001,10 ;ACC=X1 00
C002 6200 ADDS 0000 ;ACC=X1 X0
C003 6204 ADDS 0004 ;ACC=X1 X0 +00 Y0
C004 6105 ADD 0005, 10 ;ACC=X1 X0 +Y1 Y0
C005 9008 SACL 0008 ;W0 =ACCL
C006 9809 SACH 0009 ;W1 = ACCH
COO7 6A03 LACC 0003,10 ;ACC=X3 00
C008 6002 ADDC 0002 ;ACC=X3X2+CARRY
C009 6206 ADDS 0006 ;ACC=X3X2+00 Y2+CARRY

C00A 6107 ADD 0007, 10 ;ACC=X3X2+Y3Y2+CARRY

C00B 900A SACL 000A ;ACCL=W2
C00C 980B SACH 000B ;ACCH=W3
C00D 7980 B C00D ; PC = C00D
C00E C00D
RESULT:
Verify the following results in data memory using SD command.
Data Memory Data

Address
9008(w0) 5555
9009(w1) FF55
900A(w2) 55FF
900B(w3) 5555
EXAMPLE 2 - EXTENDED-PRECISION SUBTRACTION:
AIM:
To illustrate the extended-precision subtraction.
THEORY:
Similar to extended-precision addition, the carry bit of the TMS320LF2407A is reset whenever
the input scaling shifter or the P-register value subtracted from the accumulator content generates
a borrow into bit 31. Otherwise, the carry bit is set, since, no borrow into bit-31 is required.
One exception to this case is the SUB5,10h instruction which can only reset the carry bit. This
allows the generation of the proper single carry when either the subtraction from the lower or
upper half of the accumulator actually causes the borrow.
In this example two 64-bit numbers X and Y are subtracted to give the result W as:
X3 X2 X1 X0
- Y3 Y2 Y1 Y0
-------------------------------
W3 W2 W1 W0
-------------------------------

The following program implements the subtraction,
X3 X2 X1 X0
2222 2222 2222 2222
Y3 Y2 Y1 Y0
1111 1111 1111 1111
))))))))))))))))))))))))-)
W3 W2 W1 W0
1111 1111 1111 1111
)))))))))))))))))))))))-))
First, the X1 and X0 are loaded in accumulator using LACC and ADDS instruction then Y0 and
Y1 are subtracted with accumulator and the results are stored in W0 and W1. In the same fashion
Y3 Y2 is subtracted from X3 X2.
To edit and execute the program, go through chapter 3.
Fill the data memory using SD command as the values given below.
Data Memory Data

Address
9000(x0) 2222
9001(x1) 2222
9002(x2) 2222
9003(x3) 2222
9004(y0) 1111
9005(y1) 1111
9006(y2) 1111
9007(y3) 1111
PROGRAM LISTING:
ADDRESS OPCODES MNEMONICS FUNCTIONS
C000 BD00 LDP #120H ; DP = 120

C001 6A01 LACC 0001,10 ;ACC=X1 00
C002 6200 ADDS 0000 ;ACC=X1 X0
C003 6604 SUBS 0004 ;ACC=X1 X0 -00 Y0
C004 6505 SUB 0005,10 ;ACC=X1 X0 -Y1 Y0
C005 9008 SACL 0008 ;ACCL =W0
C006 9809 SACH 0009 ;ACCH=W1

;OPERATION UP TO 2ND 32 BITS

C007 1002 LACC 0002,0 ;ACC=00 X2
C008 6406 SUBB 0006 ;ACC=00X2-00 Y2-C
C009 6103 ADD 0003,10 ;ACC=X3X2-00 Y2-CARRY
C00A 6507 SUB 0007,10 ;ACC=X3X2-Y3Y2-CARRY
C00B 900A SACL 000A,0 ;ACCL=W2
C00C 980B SACH 000b,0 ;ACCH=W3
C00D 7980C00D B C00D ; PC = C00DFS
RESULT:
Verify the following results in data memory using SD command.
Data Memory Data

Address
9008(w0) 1111
9009(w1) 1111
900A(w2) 1111
900B(w3) 1111
EXAMPLE 3 - FRACTIONAL MULTIPLICATION:
AIM:
To illustrate the multiplication of two fractional numbers.
THEORY:
With fixed point DSP, the fractional numbers are represented in Q15 format. Q-format is a
number representation commonly used when performing operations on non-integer numbers. In
a Q-format, the Q-number (15 in Q15) denotes how many bits are located to the right of the
binary point.
For example a 16-bit Q number has a assumed binary point, a sign bit, i integer bits and 15-i
fractional bits as shown below:
0 0000010 10100000
* .))0))- * .)))0))-
* * * .)))))))) Fraction Part
* * .)))))))))))))) Binary Point
* .))))))))))))))))))) Integer Part
.))))))))))))))))))))))))) Sign

has a value of 2.625. This particular number is said to be represented in a Q8 format (8 factorial
bits). Its range is between - 128 (10000000000000000) and 127.996 (01111111111111111).
The factorial accuracy of a Q8 number is about 0.004 (one part in 28 or 256).
It is more common to work entirely with fractions represented in a Q15 format or integers in Q0
format. This is especially true for signal processing algorithms where multiply and accumulate
operations and dominant. The result of a fraction times a fraction remains a fraction and the result
of an integer times and integer remains an integer. No overflow occurs in this case. For example,
multiplication of two Q15 numbers result in a Q30 number.
The fraction 0.5 is represented as 9000 in Q15 format. The multiplication of two Q15 numbers
result in a Q30 number as shown below.
0100000000000000 = 0.5 in Q15

x 0100000000000000 = 0.5 in Q15
)))))))))))))))))))))))))))))))))))))))))))
00 01000000000000 0000000000000000 = 0.25 in Q30
*
.)))> Binary Point.
Two sign bits remain after multiply. Generally, a single precision (16-bit) result is saved, rather
than maintaining the full intermediate precision. The upper half of the result does not contain a
full 15-bits of fractional precision, since, the multiply operation actually creates a second sign bit.
In order to recover that precision, the product most be shifted left by one bit.
TMS320LF2407A supports the fractional multiplication. The multiplication of two Q15 numbers
is implemented in the same way as integer multiplication except that the result is left shifted by
one-bit left as shown in the following code excerpt:
LT OP1(0000h) * load first operand

MPY OP2(0001h) * multiply with second operand
APAC * store the product in accumulator
SACH MSB,1 * save ACCH with 1-bit left shift
PROGRAM DESCRIPTION:
The following program implement the multiplication 0.5 x 0.5 = 0.25. The fraction 0.5 is
represented in Q15 format and the result is in Q15 format.

PROGRAM LISTING:
C000 BD00 LDP #120 ; DP = 120

C001 BF80 LACC #04000,0 ; ACC2 = 4000
+02 4000
C003 9000 SACL 0000,0 ; 9000 = 4000
C004 9001 SACL 0001,0 ; 9001 = 4000
C005 7300 LT 0000 ;T=4000
C006 5401 MPY 0001 ;P=4000*4000 = 1000 0000
C007 BE03 PAC ;ACC=1000 0000
C008 9902 SACH 0002,1 ; 9002 = 2000
C009 7980C009 B C009 ; PC = C009
RESULT:
Verify the result in data memory location 9002.
Data Memory Data

Address
9002 2000
EXAMPLE 4 - INTEGER MULTIPLICATION:
AIM:
To perform multiplication of two integer numbers.
THEORY:
The TMS320LF2407A hardware multiplier normally perform two's complement 16-bit by 16-bit
multiplies and produces a 32-bit result in a single processor cycle. To multiply two operands, one
operand must be loaded into the T-register. The second operand is moved by the multiply
instruction to the multiplier, which then produces the product in the P-register. Before another
multiply can be performed, the content of the P-register should be moved to the accumulator or
should be stored in data memory.
The following program stores the data 37A at data memory 9000 and the data 12E at the data
memory address 9001. The instruction LT OP1(0000h) loads the first operand from dma 8000
to T register. The instruction MPY OP2(0001h) multiplies the content of dma 9001 with the T
register. The result is stored in P register. The instruction PAC transfers the content of P register

to accumulator. The SACL and SACH instructions store the lower and higher order results in
dma 9002 and 9003.
PROGRAM LISTING:
ADDRESS OPCODES MNEMONICS FUNCTION
C000 BD20 LDP #120 ;DP=120

C001 BF80 LACC #037A,0 ;ACCL=037A
C002 037A
C003 9000 SACL 0000,0 ;9000=037A
C004 BF80 LACC #012E,0 ;ACCL=012E
C005 012E
C006 9001 SACL 0001,0 ;9001=012E
C007 7300 LT 0000 ;T=37A ;T=037A
C008 5401 MPY 0001 ;P=37A*12E=0004 19EC
C009 BE03 PAC ;ACC=0004 19EC
C00A 9002 SACL 0002,0 ; 9002 = 19EC
C00B 9803 SACH 0003,0
C00C 7980 B COOC ; 9003 = 0004
C00D C00C
RESULT:
The results are stored in data memory locations 9002 and 9003 as shown below.
Data Memory Data

Address
9002 19EC
9003 0004

EXAMPLE 5
DIVISION
AIM:
To divide two binary two's complement numbers of any sign where the numerator is less than
denominator.
THEORY:
Binary division is the inverse of multiplication. Multiplication consists of a series of shift and add
operations, while division can be broken into a series of subtracts and shifts. Although the
TMS320LF2407A does not have an explicit divide instruction, it is possible to implement an
efficient, flexible divide capability using the conditional subtract instruction, SUBC.
SUBC implements binary division in the same manner as is commonly done in long division.
Given a 16-bit positive dividend and divisor, the repetition of the SUBC command 16 times
produces 16-bit quotient in the low accumulator and a 16-bit remainder in high accumulator.
With each SUBC, the divisor is left-shifted 15 bits and subtracted from the accumulator. For each
subtract not producing a negative answer, a one is put in the LSB of the quotient and then shifted.
For each subtract producing a negative answer, the accumulator is simply left-shifted. The
shifting of the remainder and quotient after each subtract produces the separation of the quotient
and remainder in the low and high halves of the accumulator. The similarities between long
division and the SUBC method of division are shown below where 33 is divided by 5.
Long Division:
0000000000000110 Quotient
+))))))))))))))))))))
0000000000000101 *0000000000100001
-101
))))
110
-101
))))
11 Remainder

SUBC Method:
HIGH ADC LOW ADC
000000000000000 0000000000100001 1) Dividend is loaded into ACC. The divisor

0 1000000000000000 is
-10 left shifted 15 and subtracted form ACC.
The subtraction is negative, so discard and
-10 0111111111011111 result and shift left the ACC one bit.
000000000000000
0 0000000000100010 2) 2nd subtract produces negative answer, so
-10 1000000000000000 discard result and shift ACC (dividend)
left
-10 . 0111111110111110
.
.
000000000000010 0010000000000000 14) 14th SUBC command. The result is

0 1000000000000000 positive
-10 Shift result left and replace LSB with "1"
000000000000000 1010000000000000
1
15) Result is again positive. Shift result left
000000000000001 0100000000000001 and replace LSB with 1.
1 1000000000000000
-10
000000000000000 1100000000000001
0
1000000000000011 16) Last subtract. Negative answer, so
000000000000000 1000000000000000 discard
1 result and shift ACC left.
-10
- 1111111111111101
000000000000001 0000000000000110 Answer reached after 16 SUBC instruction.

1
REMAINDER QUOTIENT
The condition of the divisor, less than the shifted dividend, is determined by the sign of the result.
The only restriction for the use of the SUBC instruction is that both the dividend and divisor
MUST be positive. Thus, the sign of the quotient must be determined and the quotient computed
using the absolute value of the dividend and divisor. In addition, when implementing a divide
algorithm, it is important to know if the quotient can be represented as a fraction and the degree
of accuracy to which the quotient is to be computed. Each of these considerations can affect how
the SUBC instruction is used. Not that the next instruction after SUBC cannot use the
accumulator.

The program given below checks the sign of the quotient and stores the sign in data memory.
After eliminating the sign make both operands positive by using ABS instruction. As explained
in theory part, execute SUBC instruction 15 times using RPT. Now the quotient is in lower
accumulator and remainder is in higher accumulator.
To edit and execute the program, go through the topic chapter 4.
Enter numerator value of 15 in data memory 9000 and denominator value as 24 in 9001 as:
Data Memory Data

Address
9000 15
9001 24
PROGRAM LISTING:
C000 BD20 LDP #120

C001 7301 LT 0001 ;GET SIGN OF QUOTIENT
C002 5400 MPY 0000
C003 BE03 PAC
C004 9804 SACH 0004,0 ;SAVE SIGN
C005 1000 LACC 0000 ;MAKE DENOMINATOR +'VE
C006 BE00 ABS
C007 9000 SACL 0000,0
C008 1001 LACC 0001,0 ;MAKE NUMERATOR +'VE
C009 BE00 ABS
;DIVIDE LOOP
C00A BB15 RPT #F ;16 CYCLE DIVIDE LOOP
C00B 0A00 SUBC 0000
C00C 9002 SACL 0002,0
C00D 9803 SACH 0003
C00E 1004 LACC 0004,0
C00F E38C BCND C014,5 ;TEST SIGN (the condition 0 consider asGEQ i.e.,
ACC $ 0)
C010 C014
C011 B900 LACL #0
C012 3002 SUB 0002 ;NEGATE QUOTIENT
C013 9002 SACL 0002,0 ;STORE QUOTIENT
C014 7980 B C014
C014

RESULT:
Verify the results as shown below using SD command.
Data Memory Data

Address
9002 1
9003 F
5.2. SPECIAL PROGRAMS FOR USAGE OF TMS320LF2407A

INSTRUCTION:
EXAMPLE 1 - STATUS REGISTER 0 INITIALIZATION:
AIM:
Initialize the status register 0.
THEORY:
TMS320LF2407A has three status registers called STS0, STS1 and PMST. All the three status
registers are of 16-bit wide. These registers contain the status of various conditions and modes
of TMS320LF2407A. The function of status register 0 bits is shown below:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARP OV OVM 1 INTM DP
STATUS REGISTER 0:
The bits 0-8 of STS0 are called Data Page Pointer. TMS320LF2407A can address 64KW of data
memory. This whole data memory is divided into 512 pages, with each page of length 128 words.
Out of the 512 pages only one page is active at a time. This active page concept is used only
when accessing the memory using the Direct addressing mode. The active page is indicated by
the Data Page Pointer. The Data Page Pointer can be loaded using the instruction LDP. The
LDP instruction loads an immediate value onto the Data Page Pointer.
Bit 9 of STS0 is Interrupt Mode bit (INTM). When this bit is 1, all maskable interrupts are
disabled. When this bit is 0, all maskable interrupts are disabled. This bit can be set by SETC
instruction and reset by CLRC instruction.
Bit 10 is always 1. Bit 11 controls the Overflow Mode of the accumulator. This bit is called
OVM bit. When 0, overflowed results overflow normally in accumulator. When this bit is 1, and

when overflow occur in accumulator, the accumulator is set to either most positive or negative
value upon encountering the overflow. This bit can be set to 1 by SOVM instruction and reset
to 0 by ROVM instruction.
Bit 12 of STS0 is overflow flag bit. This bit indicates the status of accumulator overflow. When
overflow occurs in accumulator this bit is set.
TMS320LF2407A have 8 auxiliary registers called AR0 to AR7. Out of the 8 auxiliary register
only one is active at a time. This active auxiliary register concept is used when accessing the
memory indirectly through auxiliary register. The current auxiliary register is indicated by the bits
13-15 of STS0. When bits 13-15 is 000 the active auxiliary register is AR0, when bits 13-15 is
111 the AR7 is the current auxiliary register and so on. These three bits are called auxiliary
register pointer. The auxiliary register pointer can be set using the instruction LARP. For
example LARP 3, selects AR3 as active auxiliary register.
The following program initializes the Status Register 0 of TMS320LF2407A. The Data page
pointer is set as 0. Overflow mode is disabled and the Auxiliary register 0 is selected as current
Auxiliary register.
To edit and execute the program, go through the chapter 4.
PROGRAM LISTING:
C000 BD 20 LDP #120 ; Set Data Page Pointer as 0

C0001 BE 41 SETC INTM ; Disable Interrupts
c002 BE 42 CLRC OVM ; Disable Overflow mode
c003 8B 88 MAR *,AR0 ; Select Auxillary Register 0
c004 BF 08 LAR AR0,#09000H ; Load AR0 with 9000
c005 90 00
c006 8E 80 SST #0,* ; Store Status Register 0
c007 79 80 C007: B C007 ; PC = C007
c008 C007
CONCLUSION:
Verify that the content of status register 0 is stored at data memory location 8000H.
Data Memory Data

Address
9000 0600e

AIM:
To initialize the status register-1.
THEORY:
The function of status register-1 bits is shown below:

15 14 13 12 11 10 9 8 7 6 5 4 3 2
1 0
ST1 ARB CNF TC SXM C 1 1 HM 1 XF 1 1 PM
STATUS REGISTER 1:
The bits 0-1 of STS1 are to set the Product Shift Mode (PM). In TMS320LF2407A, the output
of the multiplier is stored in P register. This P register is of 32-bit wide. The content of the P
register can be transferred to the accumulator. When the PM bits are 00, the content of P register
is transferred to accumulator as it is. When PM bits are 01, the content of P register is left shifted
by one-bit and the result is transferred to accumulator. When PM = 10, the P register is left
shifted by 4 bits and the results is transferred to accumulator. When PM = 11, the P register is
right shifted by six bits and the result is transferred to accumulator. The shifting of bits is useful
in DSP algorithms, which we will consider later. The instruction SPM will set the PM bits.
Bit 4 denoting `XF' indicates the status of the XF pin of the processor.
Bit 9 of STS1 is carry bit. This bit is set to 1 if the result of addition in accumulator generates a
carry or reset to 0 if the result of subtraction generates a borrow. The instruction SC sets the
carry bit deliberately and RC reset the carry bit.
Bit 10 of STS1 is Set Sign extension Mode bit (SXM). When the accumulator is loaded with data
from data memory, the data can shifted on-the-way. The SXM bit decides the mode of shifting.
When SXM is 1, the shifter extends the sign of the data. When SXM = 0, no extension occur.
The instruction SSXM set the SXM bit and the instruction RSXM reset the SXM bit.
Bit 11 of STS1 is Test/Control Flag bit. Bit 12 is Configure memory block bit (CNF). The on
chip data memory block 100 to 2FF can be configured as program memory also. When CNF bit
is 0 the data memory block 100 to 2FF is configured as data memory and when CNF is 1 the data
memory block can be accessed as program memory with address FF00 to FFFF. When mapped
as program memory user cannot use the data memory address 100 to 2FF. The instruction
"SETC CNF" configures the block as program memory and the instruction "CLRC CNF"
configures it as data memory.

Bit 13-15 of STS1 are the Auxiliary register buffer ARB. Whenever the ARP of STS0 is loaded,
the old value of ARP is copied to ARB.
The following program initializes the Status Register 1 of TMS320LF2407A. The SPM bits are
reset to 00, on-chip block of memory is configured as data memory and the sign extension mode
is set.
PROGRAM LISTING:
c000 BD 20 LDP #120H

c001 BF 00 SPM #0 ; Set PM mode to 0
c002 BE 45 SETC CNF ; Configure DARAM in
; Program Space
c003 BE 47 SETC SXM ; Set Sign Extension Mode
c004 8B 88 MAR *,AR0
c005 BF 08 LAR AR0,#09000H
c006 90 00
c007 8F 80 SST #1,* ; Store Status Register 1
c008 79 80 C008: B C008
C009 C008
CONCLUSION:
Verify that the content of status register 1 is stored at data memory location 9000. Verify that
the bits 0 and 1 of dma 8000 is 00, bit 10 is 1 and bit 12 is 1.
DMA CONTENT
9000 15AC

EXAMPLE 3 - DATA SCALING:
AIM:
To explain the importance of scaling in DSP algorithms.
THEORY:
Scaling is shifting the data right or left. Let us shift the constant 40. The left shift of one bit gives
the result 80 and right shift of one bit gives the result 20.
01000000 -> 40
Left Shift 10000000 -> 80
Right Shift 00100000 -> 20
Thus, the shift of a bit left is usually considered as multiplication by constant two and one bit right
shift is considered as division by constant two.
In TMS320LF2407A, accumulator is involved in all arithmetic and logic operations, say, for
example to add two numbers one number is in accumulator and the other number is in data
memory. After addition the result is stored in the accumulator. During addition overflow may
occur in accumulator. To prevent the overflow, shifter is provided in the accumulator input and
output. The accumulator input shifter left-shift the input data by a value of 0 to 16. The
accumulator is 32-bit width, and is spilt into two 16-bit registers using LACC THIRD(0002),F.
Shifters are available at the output of LACC THIRD(0002),F and LACC FIRST(0000),10. Both
the shifters shift the data by 0 to 7 places left.
The program given below add three number FFFE, 1 and 80. These numbers are stored in data
memory locations 9000, 9001 and 9002. The instruction LACC THIRD(0002),F loads the
accumulator with the third data 80 with 15-bit left shift. Note that the shifting of data 80 is done
on-the-way from data memory to accumulator. There is no need to implement a separate
instruction for shifting, the load instruction itself will do the shifting automatically. This is the
speciality of TMS320LF2407A. After shifting the data 80 by 15-bits left, the content of
accumulator is as shown below:
ACCH ACCL
+))))))))))))))))))), +))))))))))))))))))),
00000000 01000000 00000000 00000000
40 00

The higher-order accumulator holds the data 40 and the lower order accumulator holds the data
00. Thus the shifting of data 80 by 15-positions left is equivalent to shifting the data by 1-bit right
and storing the result in higher order accumulator. The data 40 in LACC THIRD(0002),F is
stored in data memory location 8003.
The next instruction LACC FIRST(0000), 0 loads the accumulator with data in data memory
8000 with no shift. The next instruction adds the accumulator with data in data memory 9001 and
store the result in accumulator. The accumulator content is stored in data memory location 9000.
The instruction LACC FIRST(0000),F loads the data at data memory location 9000 into
accumulator with 15 bit left shift. This amount to 1-bit right shift and storing the data in higher
order accumulator. Now the shifted data in higher order accumulator is added with the data at
location 9003. The ADD2,10H instruction adds the data memory content with theLACC
THIRD(0002),10H. The result is again stored back to data memory address 9000.
PROGRAM LISTING:
ADDRESS OPCODES MNEMONICS
c000 bd20 LDP #120 ; DP = 120

c001 bf80 LACC #0FFFEH,0 ; ACCL = FFFE
c002 fffe
c003 9000 SACL 0000,0 ; 9000 = FFFF
c004 b901 LACL #1 ; ACCL = 0001
c005 9001 SACL 0001,0 ; 9001 = 0001
c006 b980 LACL #080H ; ACCL = 0080
c007 9002 SACL 0002,0 ; 9002 = 0080
c008 1f02 LACC 0002,F ; ACC = 0040 0000
c009 9802 SACH 0002,0 ; 9002 = 0040 0000
c00a 1000 LACC 0000,0 ; ACCL = FFFE
c00b 2001 ADD 0001,0 ; ACCL = FFFF
c00c 9000 SACL 0000,0 ; 9000 = FFFF
c00d 6a00 LACC 0000,10 ; ACC = FFFF 0000
c00e 6102 ADD 0002,10 ; ACC = 003F FFFF
c00f 9800 SACH 0000,0 ; 9000 = 003F
c010 7980 B C010 ; PC = C010
C011 C010
RESULT:
The results are given in the table below:

Data Mem. Data

Address
9000 003F (Shifted Result)
EXAMPLE 4 - USAGE OF LTA INSTRUCTION:
AIM:
To illustrate the function of LTA instruction.
THEORY:
The LTA instruction is equivalent to two instructions: LT and APAC. The LT instruction loads
the T register from data memory and APAC instruction adds the content of P register with
accumulator and stores the result in accumulator. In DSP applications we usually encounter the
computation of following type:
Y = A*x1 + B*x2 + C*x3
With TMS320LF2407A the above computation is made as follows:
1. Clear the accumulator.

2. Load the constant A in T register.
3. Multiply T register with x1.
4. Load T register with constant B and add the P register to accumulator. These two steps can
be done by the single instruction LTA.
6. Load T register with constant C and add the P register to accumulator. We can use LTA
instruction here.
8. Add the product to accumulator.

The following program implements the multiplication A*x1 + B*x2 + C*x3. The constants A,
B, C, x1, x2 and x3 are to be stored in dma from 9000 to 9005 as shown below:
Data Memory Data

Address
9000 1
9001 2
9002 3
9003 4
9004 5
9005 6
PROGRAM LISTING:
C000 BD20 LDP #120 ; SSDP = 120

C001 B900 LACL #0 ; ACCL = 0000
C002 7300 LT 0000 ;T=1
C003 5403 MPY 0003 ;P=1*4=4
C004 7001 LTA 0001 ;ACC=4,T=2
C005 5404 MPY 0004 ;ACC=4,P=2*5=A
C006 7002 LTA 0002 ;ACC=E,T=3
C007 5405 MPY 0005 ;ACC=E,P=3*6=12
C008 BE04 APAC ;ACCL=0020
C009 9006 SACL 0006,0
C00A 7980 B C00A ; 9006 = 0020
C010 C00A ; PC = C00A
RESULT:
Verify the following result at data memory 9006.
Data Memory Data

Address
9006 0020

EXAMPLE 5 - USAGE OF LTD INSTRUCTION:
AIM:
To illustrate the function of LTD instruction.
THEORY:
The LTD instruction is equivalent to three instructions: LT, DMOV and APAC. The DMOV
instruction moves the content of dma to the next higher address. The LT instruction loads the
T register from data memory and APAC instruction adds the content of P register with
accumulator and stores the result in accumulator.
The LTD instruction is used to implement the Digital Filtering algorithms. The digital filtering
algorithm works with two set of data : one, the set of data to be filtered and the other, the filter
coefficients ( to be precise "impulse response coefficients"). For simplicity, let us assume that the
filter coefficients are of length 3. We call this coefficients as H(0), H(1) and H(2). We also
assume that the data to be filtered can be inputted from a port continuously. For the data to be
filtered, allocate three memory locations, let us call this X(0), X(1) and X(2).
The filtering action can be explained as follows:
Initialize the location X(0), X(1) and X(2) to zero. Input the data from port and store in X(0).
Multiply X(0) with H(0), X(1) with H(1) and X(2) with H(2) and sum up the results. This is our
first output. Before inputting the next data from port move, the content of X(1) to X(2) and X(0)
to X(1). The old value of X(2) is discarded. Input the data from port and store in X(0). Now
implement the multiplication and sum up and output the result. This process goes on continuing.
Note that in every loop, the location X(0) is always meant for new data from port. The old value
of X(0) is moved to X(1) and the old value of X(1) is moved to X(2) and the old value of X(2)
is discarded. Thus, in digital filtering three basic operations are involved: multiplication of input
data with coefficients, addition and the data movement.
With TMS320LF2407A all the three operations of multiplication, addition and data movement
can be implemented with two instructions: LTD and MPY instructions. While the multiplication
is implemented using MPY instruction, the addition and data movement can be done using LTD
instruction.
NOTE: Data memory will take place only in on-chip memory blocks.

In the following program, the data memory location XN(0000H) meant for the current sample,
XNM1(0001H) for the previous sample and XNM2(0002) for the sample previous to XNM1.
The first set of multiplication LT XNM2 and MPY H2 multiplies the two operands and the result
is in the P register. The next pair of instructions LTD XNM1 and MPY H1(0004H) multiplies
the two operands and add the result with the previous result with accumulator. Since initially the
accumulator is zero accumulator now holds the result of x(n-2)h(2). The LTD XNM1 instruction
also moves the content of XNM1 to XNM2. The next instruction pair LTD XN and MPY
H0(0005), first add the P register to accumulator so now accumulator holds the result of
x(n-2)h(2)+x(n-1)h(1), multiplies XN and H0 and moves the content of XN to XNM1. The
APAC result sum up the remaining product terms and the result is stored in data memory location
YN(0006).
Before the program execution set the data memory as follows:
Data Memory Data

Address
9000 1
9001 2
9002 3
9003 4
9004 5
9005 6
PROGRAM LISTING:
C000 BD20 LDP #120 ; DP = 120

C001 B900 LACL #0 ; ACCL - 000
C002 7302 LT 0002 ;X(N-2)H(2)
C003 5403 MPY 0003
C004 7201 LTD 0001 ;X(N-2)H(2)+X(N-1)H(1)
C005 5404 MPY 0004
C006 7200 LTD 0000 ;X(N-20H(2)+X(N-1)H91)+X(N)H(0)
C007 5405 MPY 0005
C008 BE04 APAC ; ACC = P + ACC;
C009 9006 SACL 0006,0 ; 9006 = 001C
C00A 7980 B C00A ; PC = C00A
C00B C00A

RESULT:
Data Memory Data

Address
(9006) 1C
EXAMPLE 6 - USAGE OF RPT INSTRUCTION:
AIM:
Repeat the execution of particular instruction upto "N" times using RPT instruction.
THEORY:
RPT instruction is an immediate addressing mode instruction. The eight bit constant N specified
by the RPT instruction is loaded in to the Repeat counter of TMS320LF2407A. This causes the
instruction following RPT instruction to be executed N+1 times. This instruction is especially
useful for repeating instructions, such as BLKP, BLKD, IN, MAC, MACD, NORM, OUT,
TBLR, TBLW, etc.
In order to illustrate the RPT instruction, in this example, the value 3 is added 10 times
continuously and the result is stored in data memory location 9000. Initially, the value 3 is stored
in data memory location 9000. The repeat counter is loaded with 9 using RPT instruction. The
following instruction adds content of data memory address 9000 with the accumulator ten times.
The result is stored in data memory address 9000.
Before executing the program set the data memory as given below.
Data Memory Data

Address
9000 0003

PROGRAM LISTING:
C000 BD20 LDP #120H ; DP = 120

C001 B903 LACL #3 ; ACCL = 003
C002 9000 SACL 0000,0 ; 9000 = 0003
C003 B900 LACL #0 ;CLEAR ACC ; ACCL = 0000
C004 BB09 RPT #9 ;SET REPEAT COUNT 9 TIMES
C005 2000 ADD 0000,0
C006 9000 SACL 0000,0 ; 9000 = 001E
C007 7980 B
C008 C007
RESULT:
Verify that the result in data memory location 9000 is 001E.
Data Memory Data

Address
9000 001E
EXAMPLE 7 - USAGE OF TBLW INSTRUCTION:
AIM:
Transfer of nine words from data memory to program memory using TBLW instruction.
THEORY:
The TBLW instruction transfers a word from a location in data memory to a program memory
location. In order to execute the transfer, the program memory and data memory address must
be specified. The program memory address is defined by accumulator. The data memory address
is directly or indirectly specified in the TBLW instruction.
When in the repeat mode, TBLW effectively becomes a single-cycle instruction. In repeat mode,
the content of the accumulator is incremented once each cycle, thus automatically pointing the
next program memory address.
In this program, the nine words of data memory from data memory address 9000 to 9008 is
transferred to the program memory D100 to D108.

The source and destination addresses are 9000 and D100. The auxiliary register 0 (AR0) is
loaded with data 8 for loop counting. AR1 is loaded with the source pointer 9000 and the
accumulator is loaded with the source address D100.
The instruction MAR *, AR1 select AR1 as current auxiliary register. The following instruction
TBLW *+,0 transfer the content of the data memory address specified by the current auxiliary
register (i.e., dma 9000)to program memory specified by the Accumulator (i.e., the address
D100). The instruction ADD #1, increment the accumulator by one, so that it point to next
program memory on next loop. The BANZ instruction implements the TBLW operation for 9
times.
Before executing the program, substitute the data memory with the data as shown below:
Data Memory Data

Address
9000 1234
9001 5678
9002 9012
9003 3456
9004 7890
9005 1234
9006 5678
9007 9012
9008 3456
PROGRAM LISTING:
C000 BD20 LDP #120

C001 B008 LAR 0,#8 ;LOAD COUNT IN AR0
C002 B900 LACL #0
C003 BF09 LAR 1,#9000 ;LOAD SOURCE ADD IN AR1
C004 9000
C005 BF80 LACC #D200 ;LOAD DEST ADDRESS IN ACC
C006 D200
C007 8B89 MAR *,1
C008 A7A8 TBLW *+, ;MOVE DATA FROM DM TO PM AND
;ARP=AR0
C009 B801 ADD #1 ;INCREMENT PMA

C00A 7B90 BANZ C007,*- ;BRANCH UNTILL AR0=0

C00B C007
C00C 7980 B C007
C00D C00C
RESULT:
After executing the program, check the program memory content from D200 to D208 USING
SP COMMAND for the following result.
Program Memory Data

Address
D200 1234
D201 5678
D202 9012
D203 3456
D204 7890
D205 1234
D206 5678
D207 9012
D208 3456
EXAMPLE 8 - FUNCTION OF BIT AND BCND INSTRUCTIONS:
AIM:
To explain the function of BIT and BCND instructions.
THEORY:
The BIT instruction copies the specified bit of the data memory content to the TC-bit of status
register STS1. The BCND instruction checks the TC-bit of STS1. If TC is set then the control
passes to the address specified by the BCND instruction otherwise the instruction next to BCND
is executed.
In this example, AR1 is selected as current auxiliary register and the data memory address 9000
is stored in AR1. The instruction BIT *,8, test the eighth bit of the content of data memory
location 9000. If the eighth bit is zero, then the program sequence jumps to the label NEXT and
the value 0 is stored onto the data memory location 9001. If the eighth bit of data memory
location is 1, then the instruction next to BCND is executed, which actually stores the data 1 in
data memory 9001.

Before executing the program,
To edit and execute the program, go through chapter 4. Verify the results for both cases.
CASE (i) : Set the data memory address 9000 with FFFF.
CASE (ii): Set the data memory address 9000H with FF7FH.
PROGRAM LISTING:
C000 BD20 LDP #120

C001 8B89 MAR *,1
C002 BF09 LAR 1,#09000
C003 9000
C004 4880 BIT *,8 ;CHECK THE 8 BIT STATUS
C005 E200 BCND C00B,0A (0A = NTC);IF TC=0 THEN BRANCH TONEXT
C006 C00B
C007 B901 LACL #1
C008 9001 SACL 0001,0
C009 7980 B C00D
C00A C00D
C00B B900 LACL #0
C00C 9001 SACL 0001,0
C00D 7980 B C00D
C00E C00D
RESULT:
Verify that the value 1 is stored in data memory location 9001, in case loading data in 9000H as
FFFF.
Verify that the value 0 is stored in data memory location 9001, in case loading data in 9000H as
FF7F.

EXAMPLE 9 - USAGE OF CMPL INSTRUCTION:
AIM:
To find the two's complement of a given number.
THEORY:
CMPL instruction replaces the content of accumulator with its logical inversion (one's
complement). By adding one with a one's complement number we will get the two's complement
of a number.
In this program, the accumulator is loaded with data 5. The CMPL instruction complements the
accumulator value and the result is FFFA. Now, add one with accumulator which gives the result
as FFFB. This is the two's complement of 5 and the result is stored in data memory location
9000.
PROGRAM LISTING:
C000 BD20 LDP #120

C001 B905 LACL #5 ;LOAD 5 TO ACC
C002 BE01 CMPL ;COMPLEMENT ACC
C003 B801 ADD #1
C004 9000 SACL 0000,0 ;STORE 2'S COMPLEMENT RES
C005 7980 B C005
C006 C005
RESULT:
Verify that the result at data memory location 9000 is FFFB.

MICRO - 2407A USER MANUAL EXAMPLES ON SERIAL MONITOR MODE
CHAPTER - 6
GETTING STARTED WITH BASIC EXAMPLES
ON SERIAL MONITOR MODE
This chapter mainly described about how to construct the TMS320LF24077A assembly program
in Serial Monitor Mode for Arithmetic manipulations and usage of instruction of
TMS320LF2407A processor.
Program and Execution:
1. Serial Monitor Mode:
Connect the serial monitor cable from COM2 (P2) of Micro-2407A kit to the serial port COM1
or COM2 of PC XT/AT (prefer COM1 for default selection). Now execute communication
software (XTALK.EXE) in PC.
Power on the Micro-2407A Kit with all its set up ready and enter the following command at the
prompt.
Micro-2407A Trainer
#SM
Press the enter key to enter into serial monitor mode and the screen displays the following
message
SERIAL MODE 1....
Now the following menu will appear on the monitor.
Micro-2407A Serial Monitor, Ver.1.0

(C) Copyright 2003 by Vi Microsystems (P) Ltd. Chennai.
#
Now enter "HE" to view the help menu of the serial monitor.
To assemble the program given in the examples enter "AS" at the prompt and press the Enter
Key, the screen displays the following message.
#Micro-2407A Line Assembler, Version 2.0

Enter Address:
Vi Microsystems
Now enter the program memory starting address "C000H" and press Enter Key. Now the screen
display next consequent message as
C000H
Enter the mnemonics of the program sequentially viewing opcodes of the respective mnemonics
after pressing enter key.
On completion of assembling enter dot (.) and press the enter key to come out to prompt.
To execute the program use the command "GO C000" and press the Enter Key, where C000 is
program memory starting address.
To abort the execution, press the reset switch once to reset the Micro-2407A Kit. Now enter
"SM" in Micro-2407A trainer to re-enter into serial mode. To verify the execution, dump the data
memory from 9000H to A000H using "DD" command. This operation is same as Line assembler
in standalone mode.
Note: 1) At any occasion to abort the serial monitor from the execution of the program press
the reset switch of Micro-2407A kit.
2) To quit of serial monitor mode enter "QU" at the prompt and press enter key.
Method 3:
Edit assembly program using any editor like Edit, Notepad etc., the program is then assembled
and converted to corresponding "BIN" and "ASC" formats, which can be transferred to the kit,
using serial communication packages like DATACOM.EXE, or XTALK.EXE etc.
Before going to download the program from the host to M2407A kit. We should have to convert
ASM files into ASCII files. The ways to use like that:
i) First edit ASM file using DOS editor/Notepad.
ii) Then, to convert “ASM” file into “ASCII” file type assemble test (if the file name is “test.asm
in dos mode). If the Assemble .Bat file which utilizes the DSPA.EXE, DSPLINK.EXE,
DSPHEX.EXE, MPOBIN.EXE and BIN2ASC files. More details, please refer Technical
Reference. Please make the path of the source program and conversion utilities in the same
folder before converting to ASCII file.
iii) To download ASC files to M2407A kit use XTALK.EXE communication software
XTALK:
i) Before going to communicate with a XTALK software, we must do some initial setup. The
ways to use like this
Vi Microsystems
a) Enter C:\>XTALK and you are viewing tree chart as shown below.
b) To change the contents in the scroll bar, which is under the Tree, chart, Enter ESC key
and enter the following commands respectively.
1. SP 96 <CR>
2. IN OFF <CR>
3. OU OFF <CR>
Finally 4. GO LO <CR>
c) After entering GO LO command in the scroll bar, In addition, to initiate serial mode of
M2407A, Enter `SM' command in the kit.
It will start to interact with host and M2407A kit. Then the following message with
prompt will be displayed in the monitor.
Vi Microsystems Pvt. Ltd.

Chennai
#
d) Then to download the ASC files intoM2407A kit, enter as #PI C000, in command
window.
e) In the monitor, it shows you as,
#PI C000.
Downloading from the host...
f) Next you have to send the ASC files as such away to enter ESC key and type the
command as SE TEST.ASC and enter it.
g) Then the monitor shows that,
#PI C000
Downloading from the host....
Sending TEST.ASC file
#
#
#
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h) After sending the ASC files into M2407A, enter GO C000 to execute the program
TEST.ASM
i) Reset the M2407A kit and to see the data which is stored in between 9000 to A000
memory location, enter as #SD 9000.
j) #HE command makes you to use of commands of M2407A.
Note:
To write the assembler directives, please refer TMS320LF2407ATechnical Reference
i) If you will happen to specify the sampling rate = 80 Khz in program for understanding
purpose
It must write as
* Sampling rate = 80 Khz. It is a single command line, which is used, in high-level

languages.
ii) In every program you should include the memory mapped registers as
.mmregs
.text
iii) To assign memory address for our convenient name, we just write as convenient name
.SET Address
iv) To assign the constant, .word constant format is used.
the way to write program like this
* TITLE of the program

* declarations for convenience
. mmregs
. text
Name . set address . or Constant
. word constant
START: Here program begins.

.
HERE B Here program ends
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M2407A Software Floppy Contains
M2407A software contains the following directories:

i) PWM:
PWM includes all assembly codes of PWM experiments
ii) ADC:
It contains the assembly codes of ADC
iii) Arithmat:
It has assembly codes of arithmatic manipulations and usage of instruction on

TMS320LF2407A.
iv) Assemble:
It contains all EXE files of cross assembler of TMS320LF2407A
v) Test:
It is only for user purpose, whereas the user can user this directory for their assemble
the assembly language of TMS320LF2407A processor using Cross assembler EXE
files and store the files in this directory.
ARITHMETIC MANIPULATIONS:
EXAMPLE 1 - EXTENDED-PRECISION ADDITION:
AIM:
To illustrate the extended precision addition of two 64-bit numbers.
THEORY:
Numerical analysis, floating point computations or other operations may require arithmetic to be
executed with more than 32-bits of precision. Since, the TMS320LF2407A is 16-bit fixed-point
processor, software is required for the extended precision of arithmetic operations. For proper
operation, the overflow mode bit should be reset (OVM = 0) so that the accumulator result will
not be loaded with the saturation value.
Vi Microsystems
In our example, two 64-bit numbers are added as shown:
X3 X2 X1 X0
+ Y3 Y2 Y1 Y0
W3 W2 W1 W0
Where all the numbers X3, X2, X1, X0, Y3, Y2, Y1 & Y0 are 16-bit numbers.
TMS320LF2407A has provision to add two 32-bit numbers, so we can add X1 X0 with Y1 Y0.
But how can we add 32-bit numbers X3 X2 X1 X0 with Y3 Y2 Y1 Y0.
TMS320LF2407A has two features that help to make extended precision calculation more
efficient. One of the feature is the carry status bit. The carry bit is set whenever the addition of a
value from the input scaling shifter or the P-register to the accumulator content generated a carry
out of bit 31. Otherwise, the carry bit is reset since the carry out of bit 31 is zero. One exception
to this case is that ADDH instruction which can only set the carry bit. This allows the
accumulator to generate proper single carry when either the addition to the lower or upper half of
the accumulator actually causes the carry.
The other feature which eases the extended-precision addition is the ADDH instruction. ADDH
instruction adds the 16-bit data memory content to the higher part of accumulator.
In this example, the X operand X3 X2 X1 X0, is made of 16-bit numbers X3, X2, X1 and X0,
with X3 the most significant 16-bits and X0 the least significant 16-bits. The Y operand is Y3 Y2
Y1 Y0, where Y3 is the most significant 16-bits and Y0 is the least significant 16-bits. On
addition, both the operands result in W3 W2 W1 W0.
For example the addition of 5432109876543210 and 0123456789012345 results in

555555FFFF555555, as shown:
X-Operand: X3 X2 X1 X0
5432 1098 7654 3210
Y-Operand: Y3 Y2 Y1 Y0
0123 4567 8901 2345
Result: W3 W2 W1 W0
5555 55FF FF55 5555
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First load X1 in higher accumulator using LACC instruction and add X0 with accumulator by
using ADDS instruction. Now, the whole 32-bit of X1 X0 is in accumulator. Add Y0 with sign
extension suppressed using ADDS instruction and in the same way Y1 is added to the higher part
of accumulator using ADDH instruction. The result of 0-15 bits are stored in data memory as
W0 and 16-31 bits are stored in data memory as W1.
The next section adds the 32-bit numbers X2 X3 and Y2 Y3, and the result is stored in data
memory as W2 and W3.
Enter the data as follows in data memory:
Data Memory Data

Address
9000 3210
9001 7654
9002 1098
9003 5432
9004 2345
9005 8901
9006 4567
9007 0123
To edit and execute the program, go through the topic program and execution.
PROGRAM LISTING:
;EXTENDED PRECISION ADDITION

X0 .SET 0
X1 .SET 1
X2 .SET 2
X3 .SET 3
Y0 .SET 4
Y1 .SET 5
Y2 .SET 6
Y3 .SET 7
W0 .SET 8
W1 .SET 9
W2 .SET 10
W3 .SET 11
.TEXT
.MMREGS
START: FUNCTION
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LDP #120H
;OPERATION UP TO 1'ST 32 BITS
LACC X1,16 ;ACC=X1 00
ADDS X0 ;ACC=X1 X0
ADDS Y0 ;ACC=X1 X0 +00 Y0
ADDH Y1 ;ACC=X1 X0 +Y1 Y0
SACL W0 ;ACCL =W0
SACH W1 ;ACCH=W1
ADDC X2 ;ACC=X3X2+CARRY
ADDS Y2 ;ACC=X3X2+00 Y2+CARRY
ADDH Y3 ;ACC=X3X2+Y3Y2+CARRY
SACL W2 ;ACCL=W2
SACH W3 ;ACCH=W3
H: B H
.END
RESULT:
Verify the following results in data memory.
Data Memory Data

Address
9008 5555
9009 FF55
900A 55FF
900B 5555
EXAMPLE 2 - EXTENDED-PRECISION SUBTRACTION:
AIM:
To illustrate the extended-precision subtraction.
THEORY:
Similar to extended-precision addition, the carry bit of the TMS320LF2407A is reset whenever
the input scaling shifter or the P-register value subtracted from the accumulator content generates
a borrow into bit 31. Otherwise, the carry bit is set, since, no borrow into bit-31 is required.
One exception to this case is the SUBH instruction which can only reset the carry bit. This allows
the generation of the proper single carry when either the subtraction from the lower or upper half
of the accumulator actually causes the borrow.
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In this example two 64-bit numbers X and Y are subtracted to give the result W as:
X3 X2 X1 X0
- Y3 Y2 Y1 Y0
-------------------------------
W3 W2 W1 W0
-------------------------------
The following program implements the subtraction,
X3 X2 X1 X0
2222 2222 2222 2222
Y3 Y2 Y1 Y0
1111 1111 1111 1111
-
W3 W2 W1 W0
1111 1111 1111 1111
-
First, the X1 and X0 are loaded in accumulator using LACC and ADDS instruction then Y0 and
Y1 are subtracted with accumulator and the results are stored in W0 and W1. In the same fashion
Y3 Y2 is subtracted from X3 X2.
Fill the data memory with the values given below.
Data Memory Data

Address
9000 2222
9001 2222
9002 2222
9003 2222
9004 1111
9005 1111
9006 1111
9007 1111
Vi Microsystems
PROGRAM LISTING:
;EXTENDED PRECISION SUBTRACTION

X0 .SET 0
X1 .SET 1
X2 .SET 2
X3 .SET 3
Y0 .SET 4
Y1 .SET 5
Y2 .SET 6
Y3 .SET 7
W0 .SET 8
W1 .SET 9
W2 .SET 10
W3 .SET 11
.TEXT
.MMREGS
START:
LDP #120H
;OPERATION UP TO 1'ST 32 BITS
ADDS X0 ;ACC=X1 X0
SUBS Y0 ;ACC=X1 X0 -00 Y0
SUBH Y1 ;ACC=X1 X0 -Y1 Y0
SACL W0 ;ACCL =W0
SACH W1 ;ACCH=W1
LACC X2,0 ;ACC=00 X2
SUBB Y2 ;ACC=00X2-00 Y2-C
ADDH X3 ;ACC=X3X2-00 Y2-CARRY
SUBH Y3 ;ACC=X3X2-Y3Y2-CARRY
SACL W2 ;ACCL=W2
SACH W3 ;ACCH=W3
H: B H
RESULT:
Verify the following results in data memory.

Data Memory Data
Address
9008 1111
9009 1111
900A 1111
900B 1111
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Microsystems Pvt. Ltd., [ 6 - 10 ]
EXAMPLE 3 - FRACTIONAL MULTIPLICATION:
AIM:
To illustrate the multiplication of two fractional numbers.
THEORY:
With fixed point DSP, the fractional numbers are represented in Q15 format. Q-format is a
number representation commonly used when performing operations on non-integer numbers. In a
Q-format, the Q-number (15 in Q15) denotes how many bits are located to the right of the binary
point.
For example a 16-bit Q number has a assumed binary point, a sign bit, i integer bits and 15-i
fractional bits as shown below:
0 0000010 10100000
Fraction Part
Binary Point
Integer Part
Sign
has a value of 2.625. This particular number is said to be represented in a Q8 format (8 factorial
bits). Its range is between - 128 (10000000000000000) and 127.996 (01111111111111111).
The factorial accuracy of a Q8 number is about 0.004 (one part in 28 or 256).
It is more common to work entirely with fractions represented in a Q15 format or integers in Q0
format. This is especially true for signal processing algorithms where multiply and accumulate
operations and dominant. The result of a fraction times a fraction remains a fraction and the result
of an integer times and integer remains an integer. No overflow occurs in this case. For example,
multiplication of two Q15 numbers result in a Q30 number.
The fraction 0.5 is represented as 8000 in Q15 format. The multiplication of two Q15 numbers
result in a Q30 number as shown below.
0100000000000000 = 0.5 in Q15

x 0100000000000000 = 0.5 in Q15
00 01000000000000 0000000000000000 = 0.25 in Q30
> Binary Point.

Two sign bits remain after multiply. Generally, a single precision (16-bit) result is saved, rather
than maintaining the full intermediate precision. The upper half of the result does not contain a
full 15-bits of fractional precision, since, the multiply operation actually creates a second sign bit.
In order to recover that precision, the product most be shifted left by one bit.
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TMS320LF2407A supports the fractional multiplication. The multiplication of two Q15 numbers
is implemented in the same way as integer multiplication except that the result is left shifted by
one-bit left as shown in the following code excerpt:
LT OP1 * load first operand

MPY OP2 * multiply with second operand
APAC * store the product in accumulator
SACH MSB,1 * save ACCH with 1-bit left shift
The following program implement the multiplication 0.5 x 0.5 = 0.25. The fraction 0.5 is
represented in Q15 format and the result is in Q15 format.
PROGRAM LISTING:
OP1 .SET 0
OP2 .SET 1
RES .SET 2
.TEXT
.MMREGS
START:
LDP #120H
LACC #04000H
SACL OP1
SACL OP2
LT OP1 ;T=4000
MPY OP2 ;P=4000*4000 = 1000 0000
PAC ;ACC=1000 0000
SACH RES,1 ;RES=2000
H: B H
.END
RESULT:
Verify the result in data memory location 8002.
Data Memory Data

Address
9002 2000
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EXAMPLE 4 - INTEGER MULTIPLICATION:
AIM:
To perform multiplication of two integer numbers.
THEORY:
The TMS320LF2407A hardware multiplier normally perform two's complement 16-bit by 16-bit
multiplies and produces a 32-bit result in a single processor cycle. To multiply two operands, one
operand must be loaded into the T-register. The second operand is moved by the multiply
instruction to the multiplier, which then produces the product in the P-register. Before another
multiply can be performed, the content of the P-register should be moved to the accumulator or
should be stored in data memory.
The following program stores the data 37A at data memory 9000 and the data 12E at the data
memory address 9001. The instruction LT OP1 loads the first operand from dma 8000 to T
register. The instruction MPY OP2 multiplies the content of dma 9001 with the T register. The
result is stored in P register. The instruction PAC transfers the content of P register to
accumulator. The SACL and SACH instructions store the lower and higher order results in dma
9002 and 9003.
PROGRAM LISTING:
;INTEGER MULTIPLICATION
OP1 .SET 0
OP2 .SET 1
RESL .SET 2
RESH .SET 3
.TEXT
.MMREGS
START:
LDP #120H
LACC #037AH
SACL OP1
LACC #012EH
SACL OP2
LT OP1 ;T=37A
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MPY OP2 ;P=37A*12E=0004 19EC

PAC ;ACC=0004 19EC
SACL RESL
SACH RESH
H: B H
.END
RESULT:
The results are stored in data memory locations 8002 and 8003 as shown below.
Data Memory Data

Address
9002 19EC
9003 0004
EXAMPLE 5 - DIVISION:
AIM:
To divide two binary two's complement numbers of any sign where the numerator is less than
denominator.
THEORY:
Binary division is the inverse of multiplication. Multiplication consists of a series of shift and add
operations, while division can be broken into a series of subtracts and shifts. Although the
TMS320LF2407A does not have an explicit divide instruction, it is possible to implement an
efficient, flexible divide capability using the conditional subtract instruction, SUBC.
SUBC implements binary division in the same manner as is commonly done in long division.
Given a 16-bit positive dividend and divisor, the repetition of the SUBC command 16 times
produces 16-bit quotient in the low accumulator and a 16-bit remainder in high accumulator.
With each SUBC, the divisor is left-shifted 15 bits and subtracted from the accumulator. For each
subtract not producing a negative answer, a one is put in the LSB of the quotient and then shifted.
For each subtract producing a negative answer, the accumulator is simply left-shifted. The
shifting of the remainder and quotient after each subtract produces the separation of the quotient
and remainder in the low and high halves of the accumulator. The similarities between long
division and the SUBC method of division are shown below where 33 is divided by 5.
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Long Division:
0000000000000110 Quotient
0000000000000101 0000000000100001
-101
110
-101
11 Remainder
SUBC Method:
HIGH ACC LOW ACC
000000000000000 0000000000100001 1) Dividend is loaded into ACC. The divisor is

0 1000000000000000 left shifted 15 and subtracted form ACC.
-10 The subtraction is negative, so discard and
result and shift left the ACC one bit.
-10 0111111111011111
000000000000000 0000000000100010 2) 2nd subtract produces negative answer, so

0 1000000000000000 discard result and shift ACC (dividend)
-10 left
.
-10 0111111110111110
.
. 14) 14th SUBC command. The result is
positive
Shift result left and replace LSB with "1"
000000000000010 0010000000000000
0 1000000000000000
-10
000000000000000 1010000000000000
1
15) Result is again positive. Shift result left
000000000000001 0100000000000001 and replace LSB with 1.
1 1000000000000000
-10
000000000000000 1100000000000001
0
1000000000000011 16) Last subtract. Negative answer, so discard
000000000000000 1000000000000000 result and shift ACC left.
1
-10
- 1111111111111101
000000000000001 0000000000000110 Answer reached after 16 SUBC instruction.

1
REMAINDER QUOTIENT
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The condition of the divisor, less than the shifted dividend, is determined by the sign of the result.
The only restriction for the use of the SUBC instruction is that both the dividend and divisor
MUST be positive. Thus, the sign of the quotient must be determined and the quotient computed
using the absolute value of the dividend and divisor. In addition, when implementing a divide
algorithm, it is important to know if the quotient can be represented as a fraction and the degree
of accuracy to which the quotient is to be computed. Each of these considerations can affect how
the SUBC instruction is used. Not that the next instruction after SUBC cannot use the
accumulator.
The program given below checks the sign of the quotient and stores the sign in data memory.
After eliminating the sign make both operands positive by using ABS instruction. As explained in
theory part, execute SUBC instruction 15 times using RPT. Now the quotient is in lower
accumulator and remainder is in higher accumulator.
Enter numerator value of 15 in data memory 9000 and denominator value as 24 in 9001 as:
Data Memory Data

Address
9000 15
9001 24
PROGRAM LISTING:
;ROUTINE TO DIVIDE 2'S COMPLEMENT NUMBER OF ANY SIGN

DMR .SET 0
NMR .SET 1
QUOT .SET 2
REM .SET 3
SIGN .SET 4
.TEXT
. mmregs.
START:
LDP #120H
LT NMR ;GET SIGN OF QUOTIENT
MPY DMR
PAC
SACH SIGN ;SAVE SIGN
LACC DMR ;MAKE DENOMINATOR +'VE
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ABS
SACL DMR
LACC NMR ;MAKE NUMERATOR +'VE
ABS
;DIVIDE LOOP
RPT #15 ;16 CYCLE DIVIDE LOOP
SUBC DMR
SACL QUOT
SACH REM
LACC SIGN
BCND H,GEQ ;TEST SIGN
LACL #0
SUB QUOT ;NEGATE QUOTIENT
SACL QUOT ;STORE QUOTIENT
H: B H
.END
RESULT:
Verify the results as shown below.
Data Memory Data

Address
9002 1
9003 F
6.2. SPECIAL PROGRAMS FOR USAGE OF TMS320LF2407A INSTRUCTION:
AIM:
Initialise the status register 0.
THEORY:
TMS320LF2407A has three status registers called STS0, STS1 and PMST. All the three status
registers are of 16-bit wide. These registers contain the status of various conditions and modes of
TMS320LF2407A. The function of status register 0 bits is shown below:
Vi Microsystems
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARP OV OVM 1 INTM DP
STATUS REGISTER 0:
The bits 0-8 of STS0 are called Data Page Pointer. TMS320LF2407A can address 64KW of data
memory. This whole data memory is divided into 512 pages, with each page of length 128 words.
Out of the 512 pages only one page is active at a time. This active page concept is used only
when accessing the memory using the Direct addressing mode. The active page is indicated by
the Data Page Pointer. The Data Page Pointer can be loaded using the instruction LDP. The
LDP instruction loads an immediate value onto the Data Page Pointer.
Bit 9 of STS0 is Interrupt Mode bit (INTM). When this bit is 1, all maskable interrupts are
disabled. When this bit is 0, all maskable interrupts are disabled. This bit can be set by SETC
instruction and reset by CLRC instruction.
Bit 10 is always 1. Bit 11 controls the Overflow Mode of the accumulator. This bit is called
OVM bit. When 0, overflowed results overflow normally in accumulator. When this bit is 1, and
when overflow occur in accumulator, the accumulator is set to either most positive or negative
value upon encountering the overflow. This bit can be set to 1 by SOVM instruction and reset to
0 by ROVM instruction.
Bit 12 of STS0 is overflow flag bit. This bit indicates the status of accumulator overflow. When
overflow occurs in accumulator this bit is set.
TMS320LF2407A have 8 auxiliary registers called AR0 to AR7. Out of the 8 auxiliary register
only one is active at a time. This active auxiliary register concept is used when accessing the
memory indirectly through auxiliary register. The current auxiliary register is indicated by the bits
13-15 of STS0. When bits 13-15 is 000 the active auxiliary register is AR0, when bits 13-15 is
111 the AR7 is the current auxiliary register and so on. These three bits are called auxiliary
register pointer. The auxiliary register pointer can be set using the instruction LARP. For
example LARP 3, selects AR3 as active auxiliary register.
The following program initializes the Status Register 0 of TMS320LF2407A. The Data page
pointer is set as 0. Overflow mode is disabled and the Auxiliary register 0 is selected as current
Auxiliary register.
PROGRAM LISTING:
Vi Microsystems
; Status register 0 initialization

.mmregs
.text
START:
LDP #0 ; Set Data Page Pointer as 0

SETC INTM ; Disable Interrupts
CLRC OVM ; Disable Overflow mode
MAR *,AR0 ;Select Auxillary Register 0
LAR AR0,#09000H ;Load AR0 with 9000
SST #0,* ; Store Status Register 0
H: B H
.end
CONCLUSION:
Verify that the content of status register 0 is stored at data memory location 8000H.
Data Memory Data

Address
9000 0600H
AIM:
To initialize the status register-1.
THEORY:
The function of status register-1 bits is shown below:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1 ARB CNF TC SXM C 1 1 HM 1 XF 1 1 PM
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STATUS REGISTER 1:
The bits 0-1 of STS1 are to set the Product Shift Mode (PM). In TMS320LF2407A, the output
of the multiplier is stored in P register. This P register is of 32-bit wide. The content of the P
register can be transferred to the accumulator. When the PM bits are 00, the content of P register
is transferred to accumulator as it is. When PM bits are 01, the content of P register is left shifted
by one-bit and the result is transferred to accumulator. When PM = 10, the P register is left
shifted by 4 bits and the results is transferred to accumulator. When PM = 11, the P register is
right shifted by six bits and the result is transferred to accumulator. The shifting of bits is useful in
DSP algorithms, which we will consider later. The instruction SPM will set the PM bits.
Bit 4 denoting `XF' indicates the status of the XF pin of the processor.
Bit 9 of STS1 is carry bit. This bit is set to 1 if the result of addition in accumulator generates a
carry or reset to 0 if the result of subtraction generates a borrow. The instruction SC sets the
carry bit deliberately and RC reset the carry bit.
Bit 10 of STS1 is Set Sign extension Mode bit (SXM). When the accumulator is loaded with data
from data memory, the data can shifted on-the-way. The SXM bit decides the mode of shifting.
When SXM is 1, the shifter extends the sign of the data. When SXM = 0, no extension occur.
The instruction SSXM set the SXM bit and the instruction RSXM reset the SXM bit.
Bit 11 of STS1 is Test/Control Flag bit. This bit is explained in Example-13.
Bit 12 is Configure memory block bit (CNF). The on chip data memory block 100 to 2FF can be
configured as program memory also. When CNF bit is 0 the data memory block 100 to 2FF is
configured as data memory and when CNF is 1 the data memory block can be accessed as
program memory with address FF00 to FFFF. When mapped as program memory user cannot
use the data memory address 100 to 2FF. The instruction "SETC CNF" configures the block as
program memory and the instruction "CLRC CNF" configures it as data memory.
Bit 13-15 of STS1 are the Auxiliary register buffer ARB. Whenever the ARP of STS0 is loaded,
the old value of ARP is copied to ARB.
The following program initializes the Status Register 1 of TMS320LF2407A. The SPM bits are
reset to 00, on-chip block of memory is configured as data memory and the sign extension mode
is set.
Vi Microsystems
PROGRAM LISTING:
; Status register 1 initialization

.mmregs
.text
START:
LDP #0
SPM #0 ; Set PM mode to 0
SETC CNF ;Configure DARAM in
; Program Space
SETC SXM ; Set Sign Extension Mode
MAR *AR0
LAR AR0,#09000H
SST #1,* ; Store Status Register 1
HERE: B HERE
.end
CONCLUSION:
Verify that the content of status register 1 is stored at data memory location 8000. Verify that the
bits 0 and 1 of dma 8000 are 00, bit 10 is 1 and bit 12 is 1.
DMA CONTENT
9000 15AC
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EXAMPLE 3 - DATA SCALING:
AIM:
To explain the importance of scaling in DSP algorithms.
THEORY:
Scaling is shifting the data right or left. Let us shift the constant 40. The left shift of one bit gives
the result 80 and right shift of one bit gives the result 20.
01000000 -> 40
Left Shift 10000000 -> 80
Right Shift 00100000 -> 20
Thus, the shift of a bit left is usually considered as multiplication by constant two and one bit right
shift is considered as division by constant two.
In TMS320LF2407A, accumulator is involved in all arithmetic and logic operations, say, for
example to add two numbers one number is in accumulator and the other number is in data
memory. After addition the result is stored in the accumulator. During addition overflow may
occur in accumulator. To prevent the overflow, shifter is provided in the accumulator input and
output. The accumulator input shifter left-shift the input data by a value of 0 to 16. The
accumulator is 32-bit width, and is spilt into two 16-bit registers using LACC address, shift value:
. Shifters are available at the output of LACC FIRST,16 and LACC THIRD,15. Both the shifters
shift the data by 0 to 7 places left.
The program given below adds three number FFFE, 1 and 80. These numbers are stored in data
memory locations 9000, 9001 and 9002. The instruction LACC THIRD,15 loads the accumulator
with the third data 80 with 15-bit left shift. Note that the shifting of data 80 is done on the way
from data memory to accumulator. There is no need to implement a separate instruction for
shifting; the load instruction itself will do the shifting automatically. This is the speciality of
TMS320LF2407A. After shifting the data 80 by 15-bits left, the content of accumulator is as
shown below:
ACCH ACCL
00000000 01000000 00000000 00000000
40 00
Vi Microsystems
The higher-order accumulator holds the data 40 and the lower order accumulator holds the data
00. Thus the shifting of data 80 by 15-positions left is equivalent to shifting the data by 1-bit right
and storing the result in higher order accumulator. The data 40 in ACCH is stored in data memory
location 9003.
The next instruction LACC FIRST, 0 loads the accumulator with data in data memory 8000 with
no shift. The next instruction adds the accumulator with data in data memory 8001 and store the
result in accumulator. The accumulator content is stored in data memory location 8000.
The instruction LACC FIRST, 15 loads the data at data memory location 8000 into accumulator
with 15 bit left shift. This amount to 1-bit right shift and storing the data in higher order
accumulator. Now the shifted data in higher order accumulator is added with the data at location
8003. The ADDH instruction adds the data memory content with the LACC FIRST,16. The
result is again stored back to data memory address 8000.
PROGRAM LISTING:
; CONCEPT OF SCALING
FIRST .set 0
SECOND .set 1
THIRD .set 2
.mmregs
.text
START:
LDP #120H
LACC #0FFFEH
SACL FIRST
LACL #1
SACL SECOND
LACL #080H
SACL THIRD
LACC THIRD,15 ; ACC = 0040 0000
SACH THIRD
LACC FIRST ; ACCL = FFFE
ADD SECOND ; ACCL = FFFF
SACL FIRST
LACC FIRST,16 ; ACC = FFFF 0000
ADDH THIRD ; ACC = 003F FFFF
SACH FIRST
HERE: B HERE
.end
Vi Microsystems
RESULT:
The results are given in the table below:
Data Mem. Data

Address
9000 003F (Shifted Result)
EXAMPLE 4 - USAGE OF LTA INSTRUCTION:
AIM:
To illustrate the function of LTA instruction.
THEORY:
The LTA instruction is equivalent to two instructions: LT and APAC. The LT instruction loads
the T register from data memory and APAC instruction adds the content of P register with
accumulator and stores the result in accumulator. In DSP applications we usually encounter the
computation of following type:
Y = A*x1 + B*x2 + C*x3
With TMS320LC2407A the above computation is made as follows:
1. Clear the accumulator.

2. Load the constant A in T register.
3. Multiply T registers with x1.
4. Load T register with constant B and add the P registers to accumulator. These two steps can
be done by the single instruction LTA.
5. Multiply T registers with x2.
6. Load T register with constant C and add the P registers to accumulator. We can use LTA
instruction here.
8. Add the product to accumulator.
The following program implements the multiplication A*x1 + B*x2 + C*x3. The constants A, B,
C, x1, x2 and x3 are to be stored in dma from 9000 to 9005 as shown below:
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Data Memory Data

Address
9000 1
9001 2
9002 3
9003 4
9004 5
9005 6
PROGRAM LISTING:
; USAGE OF LTA INSTRUCTION

A .SET 0
B .SET 1
C .SET 2
X1 .SET 3
X2 .SET 4
X3 .SET 5
RES .SET 6
.MMREGS
.TEXT
START:
LDP #120H
LACL #0
LT A ;T=1
MPY X1 ;P=1*4=4
LTA B ;ACC=4,T=2
MPY X2 ;ACC=4,P=2*5=A
LTA C ;ACC=E,T=3
MPY X3 ;ACC=E,P=3*6=12
APAC ;ACCL=0020
SACL RES
H: B H
.END
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RESULT:
Data Memory Data

Address
9006 20
EXAMPLE 5 - USAGE OF LTD INSTRUCTION:
AIM:
To illustrate the function of LTD instruction.
THEORY:
The LTD instruction is equivalent to three instructions: LT, DMOV and APAC. The DMOV
instruction moves the content of dma to the next higher address. The LT instruction loads the T
register from data memory and APAC instruction adds the content of P register with accumulator
and stores the result in accumulator.
The LTD instruction is used to implement the Digital Filtering algorithms. The digital filtering
algorithm works with two set of data : one, the set of data to be filtered and the other, the filter
coefficients ( to be precise "impulse response coefficients"). For simplicity, let us assume that the
filter coefficients are of length 3. We call this coefficients as H(0), H(1) and H(2). We also
assume that the data to be filtered can be inputted from a port continuously. For the data to be
filtered, allocate three memory locations, let us call this X(0), X(1) and X(2).
The filtering action can be explained as follows:
Initialize the location X(0), X(1) and X(2) to zero. Input the data from port and store in X(0).
Multiply X(0) with H(0), X(1) with H(1) and X(2) with H(2) and sum up the results. This is our
first output. Before inputting the next data from port move, the content of X(1) to X(2) and X(0)
to X(1). The old value of X(2) is discarded. Input the data from port and store in X(0). Now
implement the multiplication and sum up and output the result. This process goes on continuing.
Note that in every loop, the location X(0) is always meant for new data from port. The old value
of X(0) is moved to X(1) and the old value of X(1) is moved to X(2) and the old value of X(2) is
discarded. Thus, in digital filtering three basic operations are involved: multiplication of input
data with coefficients, addition and the data movement.
With TMS320LF2407A all the three operations of multiplication, addition and data movement
can be implemented with two instructions: LTD and MPY instructions. While the multiplication
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is implemented using MPY instruction, the addition and data movement can be done using LTD
instruction.
NOTE: Data memory will take place only in on-chip memory blocks.
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In the following program, the data memory location XN meant for the current sample, XNM1 for
the previous sample and XNM2 for the sample previous to XNM1. The first set of multiplication
LT XNM2 and MPY H2 multiplies the two operands and the result is in the P register. The next
pair of instructions LTD XNM1 and MPY H1 multiplies the two operands and add the result with
the previous result with accumulator. Since initially the accumulator is zero accumulator now
holds the result of x(n-2)h(2). The LTD XNM1 instruction also moves the content of XNM1 to
XNM2. The next instruction pair LTD XN and MPY H0, first add the P register to accumulator
so now accumulator holds the result of x(n-2)h(2)+x(n-1)h(1), multiplies XN and H0 and moves
the content of XN to XNM1. The APAC result sum up the remaining product terms and the
result is stored in data memory location YN.
Before the program execution set the data memory as follows:
Data Memory Data

Address
9000 1
9001 2
9002 3
9003 4
9004 5
9005 6
PROGRAM LISTING:
; USAGE OF LTDINSTRUCTION
XN .SET 0
XNM1 .SET 1
XNM2 .SET 2
H2 .SET 3
H1 .SET 4
H0 .SET 5
YN .SET 6
.MMREGS
.TEXT
START:
LDP #120H
LACL #0
LT XNM2 ;X(N-2)H(2)
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MPY H2
LTD XNM1 ;X(N-2)H(2)+X(N-1)H(1)
MPY H1
LTD XN ;X(N-20H(2)+X(N-1)H91)+X(N)H(0)
MPY H0
BE04 APAC
SACL YN
H: B H
.END
RESULT:
Data Memory Data

Address
9006 1C
EXAMPLE 6 - USAGE OF RPT INSTRUCTION:
AIM:
Repeat the execution of particular instruction upto "N" times using RPT instruction.
THEORY:
RPT instruction is an immediate addressing mode instruction. The eight-bit constant N specified
by the RPT instruction is loaded in to the Repeat counter of TMS320LF2407A. This causes the
instruction following RPT instruction to be executed N+1 times. This instruction is especially
useful for repeating instructions, such as BLKP, BLKD, IN, MAC, MACD, NORM, OUT,
TBLR, TBLW, etc.
In order to illustrate the RPT instruction, in this example, the value 3 is added 10 times
continuously and the result is stored in data memory location 9000. Initially, the value 3 is stored
in data memory location 9000. The repeat counter is loaded with 9 using RPT instruction. The
following instruction adds content of data memory address 9000 with the accumulator ten times.
The result is stored in data memory address 9000. To edit and execute the program, go through
the topic program and execution.
Before executing the program set the data memory as given below.
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Data Memory Data

Address
9000 0003
PROGRAM LISTING:
;USAGE OF RPT INSTRUCTION

SUM .SET 0
START:
LDP #120H
LACL #3
SACL SUM
LACL #0 ;CLEAR ACC
RPT #9 ;SET REPEAT COUNT 9 TIMES
ADD SUM
SACL SUM
H: B H
.END
RESULT:
Verify that the result in data memory location 8000 is 001E.
Data Memory Data

Address
9000 001E
EXAMPLE 7 - USAGE OF TBLW INSTRUCTION:
AIM:
Transfer of nine words from data memory to program memory using TBLW instruction.
THEORY:
The TBLW instruction transfers a word from a location in data memory to a program memory
location. In order to execute the transfer, the program memory and data memory address must be
specified. The program memory address is defined by accumulator. The data memory address is
directly or indirectly specified in the TBLW instruction.
When in the repeat mode, TBLW effectively becomes a single-cycle instruction. In repeat mode,
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the content of the accumulator is incremented once each cycle, thus automatically pointing the
next program memory address.
In this program, the nine words of data memory from data memory address 9000 to 9008 is
transferred to the program memory D100 to D108.
The source and destination addresses are 9000 and D100. The auxiliary register 0 (AR0) is
loaded with data 8 for loop counting. AR1 is loaded with the source pointer 9000 and the
accumulator is loaded with the source address D100.
The instruction MAR *, AR1 select AR1 as current auxiliary register. The following instruction
TBLW *+,0 transfer the content of the data memory address specified by the current auxiliary
register (i.e., dma 9000)to program memory specified by the Accumulator (i.e., the address
D100). The instruction ADD #1, increment the accumulator by one, so that it point to next
program memory on next loop. The BANZ instruction implements the TBLW operation for 9
times.
Before executing the program, substitute the data memory with the data as shown below:
Data Memory Data

Address
9000 1234
9001 5678
9002 9012
9003 3456
9004 7890
9005 1234
9006 5678
9007 9012
9008 3456
PROGRAM LISTING:
;USAGE OF TBLW INSTRUCTION

SOURCE .SET 9000H
DEST .SET 0D200H
START:
LDP #120H
LAR AR0,#8 ;LOAD COUNT IN AR0
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LACL #0
LAR AR1,#SOURCE ;LOAD SOURCE ADD IN AR1
LACC #DEST ;LOAD DEST ADDRESS IN ACC
NEXT: MAR *,AR1
TBLW *+,AR0 ;MOVE DATA FROM DM TO PM AND
;ARP=AR0
ADD #1 ;INCREMENT PMA
BANZ NEXT,*- ;BRANCH UNTILL AR0=0
H: B H
.END
RESULT:
After executing the program, check the program memory content from D100 to D108 for the
following result.
Program Memory Data

Address
D200 1234
D201 5678
D202 9012
D203 3456
D204 7890
D205 1234
D206 5678
D207 9012
D208 3456
EXAMPLE 8 - FUNCTION OF BIT AND BCND INSTRUCTIONS:
AIM:
To explain the function of BIT and BCND instructions.
THEORY:
The BIT instruction copies the specified bit of the data memory content to the TC-bit of status
register STS1. The BCND instruction checks the TC-bit of STS1. If TC is set then the control
passes to the address specified by the BCND instruction otherwise the instruction next to BCND
is executed.
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In this example, AR1 is selected as current auxiliary register and the data memory address 9000 is
stored in AR1. The instruction BIT *,8, test the eighth bit of the content of data memory
location 9000. If the eighth bit is zero, then the program sequence jumps to the label NEXT and
the value 0 is stored onto the data memory location 8001. If the eighth bit of data memory
location is 1, then the instruction next to BCND is executed, which actually stores the data 1 in
data memory 9001.
Before executing the program,
To edit and execute the program, go through the topic program and execution.. Verify the
results for both cases.
CASE (i) : Set the data memory address 9000 with FFFF.
CASE (ii): Set the data memory address 9000H with FF7FH.
PROGRAM LISTING:
;USAGE OF BIT AND BCND INSTRUCION

RES .SET
.MMREGS 1
.TEXT
START:
LDP #120H
MAR *,AR1
LAR AR1,#09000H
BIT *,8 ; CHECK THE 8 BIT STATUS

BCND ;NEXT,NTC ;IF TC=0 THEN BRANCH TONEXT
LACL #1
SACL RES
B H
NEXT: LACL #0
SACL RES
H: B H
.END
RESULT:
Verify that the value 1 is stored in data memory location 9001, in case loading data in 9000 as
FFFF.
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Verify that the value 0 is stored in data memory location 9001, in case loading data in 9000 as
FF7F.
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EXAMPLE 9 - USAGE OF CMPL INSTRUCTION:
AIM:
To find the two's complement of a given number.
THEORY:
CMPL instruction replaces the content of accumulator with its logical inversion (one's
complement). By adding one with a one's complement number we will get the two's complement
of a number.
In this program, the accumulator is loaded with data 5. The CMPL instruction complements the
accumulator value and the result is FFFA. Now, add one with accumulator which gives the result
as FFFB. This is the two's complement of 5 and the result is stored in data memory location
9000.
PROGRAM LISTING:
USAGE OF CMPL INSTRUCTION

RES .SET 0
.MMREGS
.TEXT
START:
LDP #120H
LACL #5 ;LOAD 5 TO ACC
CMPL ;COMPLEMENT ACC
ADD #1
SACL RES ;STORE 2'S COMPLEMENT RES
H: B H
.END
RESULT:
Verify that the result at data memory location 9000 is FFFB.
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MICRO - 2407A USER MANUAL PWM GENERATION WITH LF2407A
CHAPTER - 7
PWM GENERATION WITH LF2407A
INTRODUCTION:
This chapter describes the LF2407A Event Manager (EV) Module, and also explain how to
generate PWM outputs (Symmetric and Asymmetric) using EV Module. The EV Manager
provides a broad range of functions and features that are particularly useful in motion control and
motor control applications. In this chapter programs are given for PWM signal generation. The
PWM signal is used to control the speed of the motors. The Analog-to Digital Converter (ADC)
is also dependent with motor control applications and so ADC is also described in this chapter.
Before going to in-depth of the event manager module, the PWM generation methods are
discussed.
PULSE WIDTH MODULATION (PWM):
For any analog or digital industrial drive, the desired voltage across the motor phases relates to
the output signals of the controller. “Pulse Width Modulation” is a technique to recreate these
desired waveforms from a DC voltage using a direct converter. The control technique consists in
first, changing the turn on and turn off time of this converter’s power switches but also in
controlling the strategy modifying these times. For the controller to generate the correct PWM
output that mimics a sine wave for example, it must use a carrier wave. In motor control
applications, the carrier wave is the signal used to generate the PWM signal (either triangular or
sawtooth). The PWM signal results from the comparison between the carrier wave and the
reference signal.
Figure

In the above figure, the current of a motor is converted into a controlled pulse width that is
proportional to the amplitude of the sine wave, so that it may become a sine wave on the average.
Figure shows the principle of the method. A comparator compares a triangular carrier wave
oscillating with constant frequency and amplitude, and the sine wave output from the current
amplifier.
As shown in the figure, extracting the portions where the value of the sine wave exceeds those of
the carrier wave outputs pulses of unequal widths. The duty ratio of the pulse width is increased
or decreased, centering around 50 percent by the sine wave and modulated to make a sine wave
on the average, because the inverter output is 0V when the duty ratio is 50 percent. It is
important to decide the method of selecting the oscillating frequency of the chopping waveform.
As the carrier frequency equals the switching frequency of the power transistor, it increases the
switching loss proportionally as it is made higher and it reduces the speed of response of the
motor as it is made lower. Further more, ripples appear more frequently, and the torque change
and the core losses are increased.
Generally, a carrier frequency of 1-3KHz is selected when the inverter consist of bipolar
transistors, and that of 5-20KHz when it consists of FETs. The current ripples developed at these
levels of frequency make the iron core of the motor vibrate. This generates unpleasant noises
when the frequency is within audio range.
In order to solve this problem, the carrier frequency is made 16KHz or more by using FETs.
Another means to solve the problem the generation of noises by moulding the iron core and the
coil of a motor into one body.
The shape and frequency of the phase currents and voltages and the amount of energy delivered to
the motor windings control the required speed and torque of the motor. The command voltage or
current to be applied to the motor is the modulating signal. The frequency of the modulating
signal is typically much lower than the PWM carrier frequency.
SINUSOIDAL PULSE WIDTH MODULATION
In many industrial applications, Sinusoidal Pulse Width Modulation (SPWM), also called Sine
coded Pulse Width Modulation, is used to control the inverter output voltage. SPWM maintains
good performance of the drive in the entire range of operation between zero and 78 percent of the
value that would be reached by square-wave operation. If the modulation index exceeds this
value, linear relationship between modulation index and output voltage is not maintained and the
over-modulation methods are required.

SPACE VECTOR PULSE WIDTH MODULATION
For efficient energy delivery to the motor, it is important that the correct inverter-switching
scheme is employed. Space vector pulse width modulation is one such switching scheme that
offers definite benefits over simpler and less efficient schemes like Sine PWM. It has been shown
that SVPWM has a higher DC bus utilization and reduced harmonic copper losses. For a given
DC link voltage output, SVPWM has the effect of boosting power output of a three-phase motor
by 16% as compared to a Sine PWM fed motor.
A different approach to SPWM is based on the space vector representation of voltages in the d, q
plane. The d, q components are found by Park transform, where the total power, as well as the
impedance, remains unchanged. Fig. 1 shows 8 space vectors in according to 8 switching
positions of inverter, V* is the phase-to-center voltage which is obtained by proper selection of
adjacent vectors V1 and V2.
The reference space vector V* is given by Equation (1), where T1, T2 are the intervals of
application of vector V1 and V2 respectively, and zero vectors V0 and V7 are selected for T0.
V* Tz = V1 *T1 + V2 *T2 + V0 *(T0/2) + V7 *(T0/2)
Fig. 3(a) shows that the inverter switching state for the period T1 for vector V1 and Fig. 3(b) is
for vector V2, resulting switching patterns of each phase of inverter are shown in Fig. 4.

In the above shown figure, U is the phaseto- center voltage containing the triple order harmonics
that are generated by space vector PWM, and U1 is the sinusoidal reference voltage. But the triple
order harmonics are not appeared in the phase-to-phase voltage as well. This leads to the higher
modulation index compared to the SPWM.
Comparison of SPWM and Space Vector PWM
As mentioned above, SPWM only reaches to 78 percent of squarewave operation, but the
amplitude of maximum possible voltage is 90 percent of square-wave in the case of space vector
PWM. The maximum phase-to-center voltage by sinusoidal and space vector PWM are
respectively;

This means that Space Vector PWM can produce about 15 percent higher than Sinusoidal PWM
in output voltage.
Simulation results in Figure show that the higher modulation index is, the less the harmonics of
current and torque by space vector PWM are than those of sinusoidal PWM.

EVENT MANAGER MODULES IN LF2407A
Event Manager A (EVA) Block Diagram

There are two identical event managers (EVA & EVB) on-chip in the LF2407A. All control
oriented features of the LF2407A are centered in the EV. The event manager peripheral is made
up of components such as timers and pulse width modulation generators. Since the two EVs
(EVA/EVB) are identical to one another in terms of functionality and register/bit definition, only
the EVA will be explained detail. The main difference between two EV module is both have
different register names and addresses.
Each EV module in the LF207A contains the following sub-components:
• Two general purpose (GP) timers

• Three compare units
• PWM circuits that include space vector PWM circuits, dead-band generation units, and
output logic
• Three capture units
• Quadrature encoder pulse (QEP) circuit
• Interrupt logic
Figure shows above the block diagram of EVA module. Like all peripherals, the EV registers
occupy a range of 16-bit memory addresses in data memory space. Most of these registers are
programmable control and data registers, but read only status registers are also present. EVA
registers are located in the data memory range 7400h to 7431h. EVB registers are located in the
range of 7500h to 7531h.
EVENT MANAGER INTERRUPTS:
The event manager interrupt sub-system is slightly different from that of the main interrupt
system. Each EV has its own local interrupt sub-system which includes its own interrupt mask and
flag registers. After the EV interrupt pass through the sub-system, they flow into the PIE just like
any other interrupt on the LF2407A. The EV interrupts are arranged into three groups (A,B,C).
Each group is assigned one CPU interrupt (INT2, 3 or 4). The EV interrupts table for EVA
module is shown below.

EVA Interrupts
GENERAL PURPOSE TIMERS:
A General Purpose (GP) timer is simply a 16-bit counter, which may be configured to count up,
down, or continuously up and down. There are two GP timers in each EV: Timer 1 and Timer 2
for EVA and Timer 3 and Timer 4 for EVB. All timers use the CPU clock as general timing
reference, but each individual timer may use a pre-scaled or frequency reduced time base which is
specified in each timer’s control register.
A GP timer may also be configured to generate an interrupt or trigger another peripheral on

certain events such as a timer overflow (timer reached period value), underflow (timer reached
zero), or compare (timer value reached compare value). The general purpose timer block diagram
is shown below.
Each timer consists of the following components:
• One readable and writeable (RW) 16-bit up and up/down counter register TxCNT (x = 1,
2, 3, 4). This register stores the current value of the counter and keeps incrementing or
decrementing depending on the direction of counting
• One RW 16-bit timer compare register TxCMPR (x = 1, 2, 3, 4)
• One RW 16-bit timer period register TxPR (x = 1, 2, 3, 4)
• RW 16-bit individual timer control register, TxCON (x = 1, 2, 3, 4)
• Programmable prescaler applicable to both internal and external clock inputs

• Control and interrupt logic

• One GP timer compare output pin, TxCMP (x = 1, 2, 3, 4)
• Output conditioning logic
General-Purpose Timer Block Diagram (x = 2 or 4)

[when x = 2: y = 1 and n = 2; when x = 4: y = 3 and n = 4]
GP Timer Control Register (TxCON)
The operational mode of a timer is controlled by its individual control register TxCON. Bits in the
TxCON register determine:
• Which of the four counting modes the timer is in

• Whether an internal or external clock is to be used by the GP timer
• Which of the eight input clock prescale factors (ranging from 1 to 1/128) is used
• On which condition the timer compare register is reloaded

• Whether the timer is enabled or disabled

• Whether the timer compare operation is enabled or disabled
• Which period register is used by timer 2, its own, or timer 1’s period register (EVA)
Which period register is used by timer 4, its own, or timer 3’s period register (EVB)
Overall GP Timer Control Register (GPTCONA/B)
The control register GPTCONA/B specifies the action to be taken by the timers on different timer
events and indicates their counting directions.
GP Timer Compare Registers (TxCMPR), x = 1,2,3,4
The compare register associated with a GP timer stores the value to be constantly compared with
the counter of the GP timer. When a match happens, the following events occur:
• A transition occurs on the associated compare output according to the bit pattern in
GPTCONA/B
• The corresponding interrupt flag is set
• A peripheral interrupt request is generated if the interrupt is unmasked The compare
operation of a GP timer can be enabled or disabled by the appropriate bit in TxCON.
GP Timer Period Register (TxPR), x = 1,2,3,4
The value in the period register of a GP timer determines the period of the timer. A GP timer
resets to 0, or starts counting downward when a match occurs between the period register and the
timer counter, depending on which counting mode the timer is in.
GP Timer Interrupts:
There are 16 combined interrupt flags in the EVAIFRA, EVAIFRB, EVBIFRA, EVBIFRB
registers for the GP timers. Each of the GP timers has the capability to generate up to four
interrupts on the events listed below.
GP PURPOSE TIMER INTERRUPTS
Interrupt Interrupt Name (x = condition for Generation
Event 1, 2, 3, 4)
Underflow TxUFINT When the counter reaches
0000h
Over flow TxOFINT When the counter reaches
FFFFh
Compare TxCINT When the counter register
match contents match that of
the compare register
Period TxPINT When the counter register
Match contents match that of
the period register

Timer Counting Direction
The counting directions of the GP timers are reflected by their respective bits in GPTCONA/B
during all timer operations as follows:
Ø 1 represents the up-counting direction

Ø 0 represents the down-counting direction
The input pin TDIRA/B determines the direction of counting when a GP timer is in directional
up-/down-counting mode. When TDIRA/B is high, upward counting is specified; when TDIRA/B
is low, downward counting is specified.
GP Timer Counting Operation
Each GP timer has four possible modes of operation:
• Stop/Hold mode
• Continuous Up-Counting mode
• Directional Up-/Down-Counting mode
• Continuous Up-/Down-Counting mode
The bit pattern in the corresponding timer control register TxCON determines the counting mode
of a GP timer. The timer enabling bit, TxCON, enables or disables the counting operation of a
timer. When the timer is disabled, the counting operation of the timer stops and the prescaler of
the timer is reset to x/1. When the timer is enabled, the timer starts counting according to the
counting mode specified by other bits of TxCON. Continuous Up-Counting mode and Continuous
Up-/Down Counting mode is mainly used for motor control applications and so these two
methods are only discussed below.
Continuous Up-Counting Mode
The GP timer in this mode counts up according to the scaled input clock until the value of the
timer counter matches that of the period register. On the next rising edge of the input clock after
the match, the GP timer resets to zero and starts counting up again. The period interrupt flag of
the timer is set one clock cycle after the match between the timer counter and period register. A
peripheral interrupt request is generated if the flag is not masked. An ADC start is sent to the
ADC module at the same time the flag is set, if the period interrupt of this timer has been selected
by the appropriate bits in GPTCONA/B to start the ADC.
One clock cycle after the GP timer becomes 0, the underflow interrupt flag of the timer is set. A
peripheral interrupt request is generated by the flag if it is unmasked. An ADC start is sent to the
ADC module at the same time if the underflow interrupt flag of this timer has been selected by
appropriate bits in GPTCONA/B to start ADC. The overflow interrupt flag is set one clock cycle
after the value in TxCNT matches FFFFh. A peripheral interrupt request is generated by the flag if
it is unmasked.

The duration of the timer period is (TxPR) + 1 cycles of the scaled clock input except for the first
period. The duration of the first period is the same if the timer counter is zero when counting
starts. The initial value of the GP timer can be any value between 0h and FFFFh inclusive. When
the initial value is greater than the value in the period register, the timer counts up to FFFFh,
resets to zero, and continues the operation as if the initial value was zero. When the initial value in
the timer counter is the same as that of the period register, the timer sets the period interrupt flag,
resets to zero, sets the underflow interrupt flag, and then continues the operation again as if the
initial value was zero. If the initial value of the timer is between zero and the contents of the
period register, the timer counts up to the period value and continue to finish the period as if the
initial counter value was the same as that of the period register.
The counting direction indication bit in GPTCONA/B is one for the timer in this mode. Either the
external or internal device clock can be selected as the input clock to the timer. TDIRA/B input is
ignored by the GP timer in this counting mode.
The continuous up-counting mode of the GP timer is particularly useful for the generation of
edge-triggered or asynchronous PWM waveforms and sampling periods in many motor and
motion control systems. Figure shows the continuous up-counting mode of the GP timer.
GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2)
Continuous Up-/Down-Counting Mode
The continuous up/down counting mode is useful in generating symmetric PWM waveforms.
The counting direction only changes from up to down when the timer reaches the period value (or
FFFFh if the initial timer value is greater than the period). The timer direction only changes from
down to up when the timer reaches zero. The period of the timer in this mode is 2*(TxPR) cycles
of the scaled clock input, except for the first period. The duration of the first counting period is
the same if the timer counter is zero when counting starts.

The initial value of the GP timer counter can be any value between 0h and FFFFh inclusive. When
the initial value is greater than that of the period register, the timer counts up to FFFFh, resets to
zero, and continues the operation as if the initial value was zero. When the initial value in the
timer counter is the same as that of the period register, the timer counts down to zero and
continues again as if the initial value was zero. If the initial value of the timer is between zero and
the contents of the period register, the timer counts up to the period value and continues to finish
the period as if the initial counter value was the same as that of the period register.
The period, underflow, and overflow interrupt flags, interrupts, and associated actions are
generated on respective events in the same manner as they are generated in continuous up-
counting mode. The counting direction indication bit for this timer in GPTCONA/B is one when
the timer counts upward and zero when the timer counts downward. Either the external clock
from the TCLKINA/B pin or the internal device clock can be selected as the input clock. DIRA/B
input is ignored by the timer in this mode. Figure shows the continuous up-/down-counting mode
of the GP timer.
GP Timer Continuous Up-/Down-Counting Mode (TxPR = 3 or 2)
Generation of PWM Outputs Using the GP Timers
Each GP timer can independently be used to provide a PWM output channel. Thus, up to two
PWM outputs may be generated by the GP timers. To generate a PWM output with a GP timer, a
continuous up- or up-/down counting mode can be selected. Edge-triggered or asymmetric PWM
waveforms are generated when a continuous-up count mode is selected. Centered or symmetric
PWM waveforms are generated when a continuous-up/-down mode is selected. To set up the GP
timer for the PWM operation, do the following configuration:
1. Note what the PLL module is set to. The PLL provides the clock signals to the DSP
and hence to the EV. In the timer control registers we have the option of pre-scaling
(dividing) the clock signal to choose a time base for the GP timers.

2. The corresponding EV pins need to be configured for their primary function in the
appropriate MCRx register.
3. Initialize TxCNT (usually set the count value to zero)
4. Initialize TxCMPR to first desired compare value
5. To create a PWM signal, the registers GPTCONA/B and TxCON need to be
configured for TxCMP enabled, desired counting mode etc.
6. To create an asymmetric PWM signal, the timer is set to the continuous up count
mode. If a symmetric PWM is desired, then the timer should be set to the continuous
up/down counting mode.
7. During run time, the GP timer compare register (TxCMPR) will need to be
periodically updated with new compare values corresponding to the modulation signal
or new duty cycle. This can be done during an interrupt service routine.
Compare Units
There are three (full) compare units (compare units 1, 2, and 3) in the EVA module and three
(full) compare units (compare units 4, 5, and 6) in the EVB module. Each compare unit has two
associated PWM outputs. The time base for the compare units is provided by GP timer 1 (for
EVA) and by GP timer 2 (for EVB).
The compare units in each EV module include:
• Three 16-bit compare registers (CMPR1, CMPR2, and CMPR3 for EVA; and CMPR4,
CMPR5, and CMPR6 for EVB), all with an associated shadow register, (RW)
• One 16-bit compare control register (COMCONA for EVA, and COMCONB for EVB),
(RW)
• One 16-bit action control register (ACTRA for EVA, and ACTRB for EVB), with an
associated shadow register, (RW)
• Six PWM (3-state) output (compare output) pins (PWMy, y = 1, 2, 3, 4, 5, 6 for EVA
and PWMz, z = 7, 8, 9, 10, 11, 12 for EVB)
• Control and interrupt logic
The functional block diagram of a compare unit is shown below.
The time base for the compare units and the associated PWM circuits is provided by GP timer 1
(for EVA) or GP timer 2 (for EVB), which can be in any of its counting modes when the compare
operation is enabled. Transitions occur on the compare outputs.
The inputs to a compare unit include:

• Control signals from control registers
• GP timer 1/3 (T1CNT/T3CNT) and its underflow and period
• RESET
The output of a compare unit is a compare match signal. If the compare operation is enabled, this
match signal sets the interrupt flag and causes on the two output pins associated with the compare
unit.

Compare Unit Block Diagram (For EVA: x = 1, 2, 3; y = 1, 3, 5; z = 1)

(For EVB: x = 4, 5, 6; y = 7, 9, 11; z = 2)
Compare Operation Modes
The operation mode of the compare units is determined by the bits in COMCONx. These bits
determine:
• Whether the compare operation is enabled
• Whether the compare outputs are enabled
• The condition on which the compare registers are updated with the values in their shadow
registers
• Whether space vector PWM mode is enabled
EVA compare unit Operation
The value of the GP timer 1 counter is continuously compared with that of the compare register.
When a match is made, a transition appears on the two outputs of the compare unit according to
the bits in the action control register (ACTRA). The bits in ACTRA can individually specify each
output to be toggle active high or toggle active-low (if not forced high or low) on a compare
match. The compare interrupt flag associated with a compare unit is set when a compare match is
made between GP timer 1 and the compare register of this compare unit, if compare is enabled. A
peripheral interrupt request is generated by the flag if the interrupt is unmasked. The timing of
output transitions, setting of interrupt flags, and generation of interrupt requests are the same as
that of the GP timer compare operation. The outputs of the compare units in compare mode are
subject to modification by the output logic, dead band units, and the space vector PWM logic.

Register Setup for Compare Unit Operation
The register setup sequence for compare unit operation requires:
For EVA For EVB

Setting up T1PR Setting up T3PR
Setting up ACTRA Setting up ACTRB
Initializing CMPRx Initializing CMPRx
Setting up COMCONA Setting up COMCONB
Setting up T1CON Setting up T3CON
Compare Action Control Registers (ACTRA and ACTRB)
The compare action control registers (ACTRA and ACTRB) control the action that takes place
on each of the six compare output pins (PWMx, where x = 1–6 for ACTRA, and x = 7–12 for
ACTRB) on a compare event, if the compare operation is enabled by COMCONx[15]. ACTRA
and ACTRB are doublebuffered. The condition on which ACTRA and ACTRB is reloaded is
defined by bits in COMCONx. ACTRA and ACTRB also contain the SVRDIR, D2, D1, and D0
bits needed for space vector PWM operation.
PWM Circuits Associated With Compare Units
The PWM circuits associated with compare units make it possible to generate six PWM output
channels (per EV) with programmable dead-band and output polarity. The EVA PWM circuits
functional block diagram is shown in Figure below. It includes the following functional units:
• Asymmetric/Symmetric Waveform Generators

• Programmable Dead-Band Unit (DBU)
• Output Logic
• Space Vector (SV) PWM State Machine
The EVB PWM circuits functional block diagram is identical to that of the EVA’s with the
corresponding change of configuration registers. The asymmetric/symmetric waveform generators
are the same as those of the GP timers.

PWM Circuits Block Diagram
The PWM circuits are designed to minimize CPU overhead and user intervention when generating
pulse width modulated waveforms used in motor control and motion control applications. PWM
generation with compare units and associated PWM circuits are controlled by the following
control registers: T1CON, COMCONA, ACTRA, and DBTCONA (in case of EVA); and
T3CON, COMCONB, ACTRB, and DBTCONB (in case of EVB).
Programmable Dead-Band (Dead-Time) Unit
In many motion/motor and power electronics applications, two power devices, an upper and a
lower, are placed in series on one power converter leg. The turn-on periods of the two devices
must not overlap with each other in order to avoid a shoot-through fault. Thus, a pair of non-
overlapping PWM outputs is often required to properly turn on and off the two devices. A dead
time (deadband) is often inserted between the turning-off of one transistor and the turning- on of
the other transistor. This delay allows complete turning-off of one transistor before the turning-on
of the other transistor. The required time delay is specified by the turning-on and turning-off
characteristics of the power transistors and the load characteristics in a specific application.
EVA and EVB have their own programmable dead-band units (DBTCONA and DBTCONB,
respectively). The programmable dead-band unit features:
• One 16-bit dead-band control register, DBTCONx (RW)

• One input clock prescaler: x/1, x/2, x/4, etc., to x/32
• Device (CPU) clock input
• Three 4-bit down-counting timers
• Control logic

The Programmable Dead band can be calculated using the following formula:
Bits [8611] in DBTCONx

Dead Band (# of CPU clock cycles) = --------------------------------
Clock prescale value
Please refer TMS320LF2407A user guide for bit values.
Dead-Band Timer Control Registers A and B (DBTCONA and DBTCONB)
The operation of the dead-band unit is controlled by the dead-band timer control registers
(DBTCONA and DBTCONB).
Generation of PWM Outputs With Event Manager
Each of the three compare units, together with GP timer 1 (in the case of EVA) or GP timer 3 (in
the case of EVB), the dead-band unit, and the output logic in the event manager module, can be
used to generate a pair of PWM outputs with programmable dead-band and output polarity on
two dedicated device pins. There are six such dedicated PWM output pins associated with the
three compare units in each EV module. These six dedicated output pins can be used to
conveniently control 3-phase AC induction or brushless DC motors. The flexibility of output
behavior control by the compare action control register (ACTRx) also makes it easy to control
switched reluctance and synchronous reluctance motors in a wide range of applications. The
PWM circuits can also be used to conveniently control other types of motors such as DC brush
and stepper motors in single or multi-axis control applications. Each GP timer compare unit, if
desired, can also generate a PWM output based on its own timer.
Asymmetric and Symmetric PWM Generation
Both asymmetric and symmetric PWM waveforms can be generated by every compare unit on the
EV module. In addition, the three compare units together can be used to generate 3-phase
symmetric space vector PWM outputs.
Register Setup for PWM Generation
All three kinds of PWM waveform generations with compare units and associated circuits require
configuration of the same Event Manager registers. The setup process for PWM generation
includes the following steps:
• Setup and load ACTRx

• Setup and load DBTCONx, if dead-band is to be used
• Initialize CMPRx
• Setup and load COMCONx
• Setup and load T1CON (for EVA) or T3CON (for EVB) to start the operation
• Rewrite CMPRx with newly determined values

Asymmetric PWM Waveform Generation
The edge-triggered or asymmetric PWM signal is characterized by modulated pulses which are
not centered with respect to the PWM period, as shown in Figure. The width of each pulse can
only be changed from one side of the pulse.
Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits
(x = 1, 3, or 5)
To generate an Asymmetric PWM signal, GP timer 1 is put in the continuous up-counting mode
and its period register is loaded with a value corresponding to the desired PWM carrier period.
The COMCONx is configured to enable the compare operation, set the selected output pins to be
PWM outputs, and enable the outputs. If dead-band is enabled, the value corresponding to the
required dead-band time should be written by software into the DBT(3:0) bits in
DBTCONx(11:8). This is the period for the 4-bit dead-band timers. One deadband value is used
for all PWM output channels. By proper configuration of ACTRx with software, a normal PWM
signal can be generated on one output associated with a compare unit while the other is held low
(or off) or high (or on), at the beginning, middle, or end of a PWM period. Such software
controlled flexibility of PWM outputs is particularly useful in switched reluctance motor control
applications.
Symmetric PWM Waveform Generation
A centered or symmetric PWM signal is characterized by modulated pulses which are centered
with respect to each PWM period. The advantage of a symmetric PWM signal over an asymmetric
PWM signal is that it has two inactive zones of the same duration: at the beginning and at the end
of each PWM period. This symmetry has been shown to cause less harmonics than an asymmetric
PWM signal in the phase currents of an AC motor, such as induction and DC brushless motors,
when sinusoidal modulation is used. Figure shows two examples of symmetric PWM waveforms.

Symmetric PWM Waveform Generation With Compare Units and PWM

Circuits (x = 1, 3, or 5)
The generation of a symmetric PWM waveform with a compare unit is similar to the generation of
an asymmetric PWM waveform. The only exception is that GP timer 1 (or GP timer 3) now needs
to be put in continuous up-/down-counting mode.
Space Vector PWM Waveform Generation with Event Manager
The EV module has built-in hardware to greatly simplify the generation of symmetric space vector
PWM waveforms. Software is used to generate space vector PWM outputs.
To generate space vector PWM outputs, the user software must:
• Configure ACTRx to define the polarity of the compare output pins

• Configure COMCONx to enable compare operation and space vector PWM mode, and
set the reload condition for CMPRx to be underflow
• Put GP timer 1 (or GP timer 3) in continuous up-/down-counting mode to start the
operation
The user software then needs to determine the voltage Uout to be applied to the motor phases in
the two-dimensional d-q plane, decompose Uout, and perform the following for each PWM
period:
• Determine the two adjacent vectors, Ux and Ux+60
• Determine the parameters T1, T2, and T0
• Write the switching pattern corresponding to Ux in ACTRx[14–12] and 1 in ACTRx[15],
or the switching pattern of Ux+60 in ACTRx[14–12] and 0 in ACTRx[15]
• Put (1/2 T1) in CMPR1 and (1/2 T1 + 1/2 T2) in CMPR2

The space vector PWM hardware in the EV module does the following to complete a space
vector PWM period:
• At the beginning of each period, sets the PWM outputs to the (new) pattern Uy defined by
ACTRx[14–12]
• On the first compare match during up-counting between CMPR1 and GP timer 1 at (1/2
T1), switches the PWM outputs to the pattern of Uy+60 if ACTRx[15] is 1, or to the
pattern of Uy if ACTRx[15] is 0 (U0–60 = U300, U360+60 = U60)
• On the second compare match during up-counting between CMPR2 and GP timer 1 at
(1/2 T1 + 1/2 T2), switches the PWM outputs to the pattern (000) or (111), whichever
differs from the second pattern by one bit
• On the first compare match during down-counting between CMPR2 and GP timer 1 at
(1/2 T1 + 1/2 T2), switches the PWM outputs back to the second output pattern
• On the second compare match during down-counting between CMPR1 and GP timer 1 at
(1/2 T1), switches the PWM outputs back to the first pattern

Space Vector PWM Waveforms
The space vector PWM waveforms generated are symmetric with respect to the middle of each
PWM period; and for this reason, it is called the symmetric space vector PWM generation
method. Figure below shows examples of the symmetric space vector PWM waveforms.
Symmetric Space Vector PWM Waveforms

Capture Units
Capture units enable logging of transitions on capture input pins. There are six capture units, three
is each EV module. Capture Units 1, 2, and 3 are associated with EVA and Capture Units 4, 5,
and 6 are associated with EVB. Each capture unit is associated with a capture input pin. Each
EVA capture unit can choose GP timer 2 or 1 as its time base; however, CAP1 and CAP2 cannot
choose a different timer between themselves as their time base. Each EVB capture unit can
choose GP timer 4 or 3 as its time base; however, CAP4 and CAP5 cannot choose a different
timer between themselves as their time base. The value of the GP timer is captured and stored in
the corresponding 2-leveldeep FIFO stack when a specified transition is detected on a capture
input pin (CAPx).
The capture units are useful in applications where the time of an external trigger needs to be
captured. For example, if we want to measure the time between the rising edges of two pulses, we
would configure the appropriate registers for capture operation on a specific capture pin. At each
rising edge, the capture unit would then store the corresponding timer values. The user program
could then subtract the second capture value from the first value and determine the time between
the pulses.
Quadrature Encoder Pulse (QEP) Circuit
QEPs are two sequences of pulses which have a variable frequency and are 900 out of phase with
one another. QEP signals are usually generated by a position/ speed sensing device such as a
rotary optical encoder. When the encoder is rotated, the direction can be determined by which
sequence of pulses leads the other. Rotational speed and position can be determined from the
count and frequency of the pulses.
Each Event Manager module has a quadrature encoder pulse (QEP) circuit. The QEP circuit,
when enabled, decodes and counts the quadrature encoded input pulses on pins CAP1/QEP1 and
CAP2/QEP2 (in case of EVA) or CAP4/QEP3 and CAP5/QEP4 (in case of EVB). The QEP
circuit can be used to interface with an optical encoder to get position and speed information from
a rotating machine. When the QEP circuit is enabled, the capture function on CAP1/CAP2 and
CAP4/CAP5 pins is disabled.
Interfacing to DSP’s ADC Inputs
The analog to digital converter (ADC) on the LF2407A allows the DSP to sample analog
voltage signals. The output of the ADC is integer number which represents the voltage level
sampled. The resolution of the ADC is 10 bits, meaning that the ADC will generate a 10-bit
number for every conversion it performs. However, the ADC stores the conversion results in
registers that are 16 bits wide. The 10 most significant bits are the ADC result, while the least
significant bits are filled with “0”s. We usually want to truncate the useless zeros, so the value
in the result register is simply right shifted by six places.

TMS320LF2407A ADC FEATURES
• 10-bit ADC core with built-in Sample and Hold (S/H)

• Fast conversion time (S/H + Conversion) of 375 ns
• Sixteen (16) multiplexed analog inputs (ADCIN0 – ADCIN15)
• Auto sequencing capability – up to 16 “autoconversions” in a single session. Each
conversion session can be programmed to select any one of the 16 input channels
• Two independent 8-state sequencers (SEQ1 and SEQ2) that can be operated individually
in dual-sequencer mode or cascaded into one large 16-state sequencer (SEQ) in cascaded
mode
• Four Sequencing Control Registers (CHSELSEQn) that determine the sequence of analog
channels that are taken up for conversion in a given sequencing mode
• Sixteen (individually addressable) result registers to store the converted values
(RESULT0 – RESULT15)
• Multiple trigger sources for start-of-conversion (SOC) sequence
Software: Software immediate start (using SOC SEQn bit)
EVA: Event manager A (multiple event sources within EVA)
EVB: Event manager B (multiple event sources within EVB)
External: ADCSOC pin
• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or
every other EOS
• Sequencer can operate in start/stop mode, allowing multiple timesequenced triggers to
synchronize conversions
• EVA and EVB can independently trigger SEQ1 and SEQ2, respectively. (This is
applicable for dual-sequencer mode only.)
• Sample-and-hold acquisition time window has separate prescale control
• Built-in Calibration mode and built-in self test mode
OPERATION OF THE ADC
For using the ADC the user first needs to configure the ADC for the desired operation. Like all
peripherals, all registers relating to ADC operation have addresses in data memory space. The first
step in configuring the ADC should be to reset the ADC. After the ADC is reset, the next step is
configure the main ADC control registers (ADCTRL1, ADCTRL2) for desired ADC operation.
Then, load the MAXCONV register with the desired number of automatic conversion minus 1.
For example, if seven auto conversions are required, MAXCONV would be loaded with 6. The
desired input channels and their order of conversion need to be specified in the CHSELSEQn
registers. Finally, a SOC trigger will start the sampling process.
After the conversion process is complete, each 10-bit result can be read from the result registers
RESULTn. The conversion results are stored sequentially in result registers RESULT0 to
RESULT15. The first result is stored in RESULT0, the second result in RESULT1, and so on.

The ADC sequencer consists of two independent 8-state sequencers (SEQ1 and SEQ2) that can
also be cascaded together to form one 16-state sequencer (SEQ). The word “state” represents the
number of autoconversions that can be performed with the sequencer. Block diagrams of the
single (16-state, cascaded) and dual (two 8-state, separated) sequencer modes are shown in
Figures.
Block Diagram of Autosequenced ADC in Cascaded Mode
In both cases, the ADC has the ability to autosequence a series of conversions. For every
conversion, any one of the available 16 input channels can be selected through the analog mux.
After conversion, the digital value of the selected channel is stored in the appropriate result
register (RESULTn). It is also possible to sample the same channel multiple times, allowing the
user to perform “over-sampling”, which gives increased resolution over traditional single sampled
conversion results.

Block Diagram of Autosequenced ADC With Dual Sequencers

Comparison of Single and Cascaded Operating Modes
Addresses of ADC Registers

EVENT MANAGER A (EVA)
Pin Name Description

CAP1 / QEP1 Capture Unit 1 input, QEP circuit input 1
CAP3 Capture Unit 3 input
PWM1 Compare Unit 1 output 1
T1CMP / T1PWM Timer 1 compare / PWM output
TCLKINA External clock-in for timers in EVA (when configured to operate
from external clock)
TDIRA External timer direction input in EVA (when timer is in directional
up / down mode)
EVENT MANAGER B (EVB) PINS
Pin Name Description

CAP6 Capture Unit 6 input
TCLKINB External clock-in for timers in EVB (when configured to operate
from external clock)
TDIRB External timer direction input in EVB (when timer is in directional
up / down mode)

EVENT MANAGER (EV) REGISTER ADDRESS
ADDRESSES OF EVA TIMER REGISTERS
ADDRESS REGISTER NAME
7400h GPTCONA GP Timer control register A

7401h TICNT Timer 1 counter register Timer 1
7402h TICMPR Timer 1 compare register
7403h TIPR Timer 1 period register

7404h TICON Timer 2 control register
7405h T2CNT Timer 2 counter register
7406h T2CMPR Timer 2 compare register Timer 2
7407h T2PR Timer 2 period register
7408h T2CON Timer 2 control register
ADDRESSES OF EVB TIMER REGISTER
7500h GPTCONB GP Timer control register B

7501h T3CNT Timer 3 counter register Timer 3
7502h T3CMPR Timer 3 compare register
7405h T4CNT Timer 4 counter register

7406h T4CMPR Timer 4 compare register Timer 4
ADDRESSES OF EVA COMPARE CONTROL REGISTERS
7411h GPTCONA GP Timer control register A

7413h ACTRA Compare action control register
7415h DBTCONA Dead-band timer control register
7417h CMPR1 Compare register 1

ADDRESS OF EVB COMPARE CONTROL REGISTERS
7511h COMCONB Compare control register

7513h ACTRB Compare action control register
7515h B3TCONB Dead-band timer control register
ADDRESS OF EVA CAPTURE REGISTERS
7420h CAPCONA Capture control register

7422h CAPFIFOA Capture FIFO status register
7423h CAPIFIFO Two-level-deep capture FIFO stack 1
7424h CAP2FIFO Two-level-deep capture FIFO stack 2
7427h CAP1FBOT Bottom registers of FIFO stack,
Allows most recent CAPTURE value
to be read
7428h CAP2FBOT
7429h CAP3FBOT
ADDRESSES OF EVB CAPTURE REGISTERS
7520h CAPCONB Capture control register

7522h CAPFIFOB Capture FIFO status register
7523h CAPIFIFO Two-level-deep capture FIFO stack 4
7527h CAP1FBOT Bottom registers of FIFO stack,
Allows most recent CAPTURE value
to be read
7528h CAP2FBOT
7529h CAP3FBOT

ADDRESSES OF EVA INTERRUPT REGISTERS
742Ch EVAIMRA Interrupt mask register A

742Dh EVAIMRB Interrupt mask register B
742Eh EVAIMRC Interrupt mask register C
742Fh EVAIFRA Interrupt flag register A
7430h EVAIFRB Interrupt flag register B
7431h EVAIFRC Interrupt flag register C
ADDRESSES OF EVB INTERRUPT REGISTERS
752Ch EVBIMRA Interrupt mask register A

752Dh EVBIMRB Interrupt mask register B
752Eh EVBIMRC Interrupt mask register C
752Fh EVBIFRA Interrupt flag register A
7530h EVBIFRB Interrupt flag register B
7531h EVBIFRC Interrupt flag register C

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MICRO - 2407

Technical Clarification /Suggestion :

The Hardware configuration of TMS320LF2407A in Micro-2407A is explained in Chapter 2.

We shall be grateful to consider suggestions for further improvement of this manual.

The Customer-Support Division,

PHONE : # (044) 2496 3142.

1.2. MOTOR CONTROL DRIVES:

Vi Microsystems Pvt. Ltd., [1-1]

* Capability of generating multiple high frequency, high-resolution PWM

* Fast processing to implement advanced algorithms to minimize torque ripple,

* Implementing multiple features using the same controller (motor control,

* Making the complete implementation as simple as possible (reduced

* Implementing a flexible solution so that future modification can be realized by

1.3. THE DSP IN MOTOR CONTROL

Vi Microsystems Pvt. Ltd., [1-2]

1.4. BENEFITS OF THE DSP CONTROLLERS

v Favours system cost reduction by an efficient control in all speed range

v Enables control of multi-variable and complex systems using modern

Vi Microsystems Pvt. Ltd., [1-3]

v Appliances (washers, blowers, compressors)

1.6. DIGITAL CONTROLLER REQUIREMENTS

The following list highlights the digital controller requirements.

v Calculations powerful enough to implement advanced and math-intensive

1.7. PROCESSOR REQUIREMENTS

The following list highlights the processor requirements.

v Strong calculating power for advanced and math-intensive control algorithms

Vi Microsystems Pvt. Ltd., [1-4]

1.8. TI TMS320C24X DSP FAMILY – the Optimal Digital Control System

The DSP controller TMS320F240 from Texas Instruments is utilized to implement a

1.9 3.3V DSP FOR DIGITAL MOTOR CONTROL

Vi Microsystems Pvt. Ltd., [1-5]

Block Diagram of a Typical DSP Motor Controller

Vi Microsystems Pvt. Ltd., [1-6]

2.2 THE DSC CHIP TMS320LF2407A

The features of the TMS320F2407A are mentioned as below:

Note : TMS320LF2407A is mentioned as LF2407A in the forth coming pages.

Vi Microsystems Pvt. Ltd., [2-1]

2.3 TMS320LF2407A DSP CORE

Vi Microsystems Pvt. Ltd., [2-2]

The TMS320F2407A core contains the following units.

1. A 32-bit central arithmetic logic unit (CALU)

The TMS320LF2407A block diagram is shown below.

Vi Microsystems Pvt. Ltd., [2-3]

2.3.1 Central Arithmetic Logic Unit (CALU)

2.3.2 32-BIT ACCUMULATOR:

• Product-scaling shifter (product shifter) – The product register (PREG) receives

Vi Microsystems Pvt. Ltd., [2-4]

2.3.4 16 x 16-BIT PARALLEL MULTIPLIER:

The multiplier performs a 16 x 16-bit two's complement multiplication with a 32-bit

2.3.5 Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers

Memory is required to hold programs, perform operations, and execute programming

Vi Microsystems Pvt. Ltd., [2-5]

2.4.1 Memory Space and I/O Spaces

• Program memory (64K words) contains the instructions to be executed, as well

2.5 EMBEDDED PERIPHERALS

• Two Event Managers (A and B)

Vi Microsystems Pvt. Ltd., [2-6]

Vi Microsystems Pvt. Ltd., [2-7]

2.5.1 Event Managers (EVA,EVB)