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    Department of Electrical and Electronics Engineering

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    Venkata Subramanian
    This document is an internal assessment test for a digital logic circuits course. It contains 3 parts: classifications of binary codes and conversions between numbering systems are tested in Part A. Part B involves binary, BCD, gray code conversions and arithmetic, as well as explaining the operation of logic gates from different families like RTL, DTL, TTL, and CMOS. The last question compares various digital logic families or performs 2's complement subtraction. The test was administered on August 4, 2015 for second year EEE students, with A. Ramanathan as the question paper setter.

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    Department of Electrical and Electronics Engineering

    Uploaded by

    Venkata Subramanian
    130 views1 page
    This document is an internal assessment test for a digital logic circuits course. It contains 3 parts: classifications of binary codes and conversions between numbering systems are tested in Part A. Part B involves binary, BCD, gray code conversions and arithmetic, as well as explaining the operation of logic gates from different families like RTL, DTL, TTL, and CMOS. The last question compares various digital logic families or performs 2's complement subtraction. The test was administered on August 4, 2015 for second year EEE students, with A. Ramanathan as the question paper setter.

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    DLC IA-I

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    This document is an internal assessment test for a digital logic circuits course. It contains 3 parts: classifications of binary codes and conversions between numbering systems are tested in Part A. Part B involves binary, BCD, gray code conversions and arithmetic, as well as explaining the operation of logic gates from different families like RTL, DTL, TTL, and CMOS. The last question compares various digital logic families or performs 2's complement subtraction. The test was administered on August 4, 2015 for second year EEE students, with A. Ramanathan as the question paper setter.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    130 views1 page

    Department of Electrical and Electronics Engineering

    Uploaded by

    Venkata Subramanian
    This document is an internal assessment test for a digital logic circuits course. It contains 3 parts: classifications of binary codes and conversions between numbering systems are tested in Part A. Part B involves binary, BCD, gray code conversions and arithmetic, as well as explaining the operation of logic gates from different families like RTL, DTL, TTL, and CMOS. The last question compares various digital logic families or performs 2's complement subtraction. The test was administered on August 4, 2015 for second year EEE students, with A. Ramanathan as the question paper setter.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 1

    DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

    SHANMUGANATHAN ENGINEERING COLLEGE


    ARASAMPATTI 622 507

    Branch
    Year/Sem
    Date
    Duration

    :
    :
    :
    :

    INTERNAL ASSESSMENT - I
    EEE
    Sub Code
    :
    II/III
    Sub Title
    :
    04/08/15
    Q.P. Setter :
    9.15a.m 10.55a.m
    Max. Marks :

    EE6301
    DIGITAL LOGIC CIRCUITS
    A.RAMANATHAN AP/EEE
    50

    PART A (5 x 2 = 10)
    1.
    2.
    3.
    4.
    5.

    Give the classifications of binary codes.


    Convert the (153.513)10 to octal.
    What is the purpose of Hamming code?
    Define fan-in and fan-out.
    Give the classifications of digital logic families.
    PART B (40 Marks)

    6.

    a (i)

    (ii)

    b (i)

    (ii)

    7.

    a (i)
    (ii)
    b (i)
    (ii)

    8.

    a
    b

    Covert the following numbers with the indicated base to decimal


    a).(735)8 b).(16.5)16 c).(1010.1010)2 d). (525)6
    Obtain the 1s and 2s compliment of the following numbers:
    a)10000000 b)11111111 c) 11011010 d)01110110
    OR
    Perform each of the following decimal additions in BCD
    a) 24 + 18 b) 48+58
    a) Convert (10111011)2 into its equivalent gray code.
    b) Convert gray code 101011 into its binary equivalent

    (4)
    (4)

    Explain the operation of 2 input RTL NOR gate.


    Draw and explain the operation of 2 input DTL NAND gate.
    OR
    Draw and explain the operation of 2 input TTL totem pole NAND gate.

    (8)

    Draw the circuit diagram of a CMOS two input NAND gate and explain its operation.

    (8)

    Compare the various digital logic families.


    OR
    Perform (42)10-(68)10 using 2s complement binary arithmetic.

    (8)

    Staff in charge

    (8)

    HOD/EEE

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