Amplifier With Buffer Configuratoin: KLE Society's B.V. Bhoomaraddi College of Engineering and Technology, Hubli

1
KLE Societys
B.V. Bhoomaraddi College of Engineering and Technology,
Hubli
2/6/15
AMPLIFIER WITH BUFFER CONFIGURATOIN

Under the guidance of
Dr. R B Shettar
Mentor :
Mr. Charan & Mr. Sourab
By,
Mr. Abhishek C Math
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Overview
Introduction
Objective
Literature survey
Methodology
Results
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INTRODUCTION
A buffer amplifier is one that provides electrical impedance

transformation from one circuit to another.
Two main types of buffer exist:
1. voltage buffer
2. current buffer
Voltage buffer having a high output impedance level to a low input
impedance level.
Current buffer having a low output impedance level to a high input
impedance level.
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Objective
To design the amplifier as a buffer to achieve the
high open loop gain and a unity gain bandwidth
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Specification
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Literature survey
Different types of architecture
1.Single stage op amp
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2. Cascoded op amp
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Proposed Architecture
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Differential amplifier
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Design of CMOS differential amplifier
The output resistance of diff amp
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The differential voltage gain is
When the transistor is in the

saturation
For L=2u
,
0.05V-1
0.02V-1,
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Impact of Pole
Vi
Vo
1
Vo
sC
Vi R 1
sC
Vo
1
Vi 1 s
1 RC
The pole is on the left half of s plane (i.e. s=-1/RC stable system)
|Av|
The pole frequency p=1/RC
1
0.707
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CMOS Frequency response
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Evaluation of device
For L=2u,W=18u & Idc=20uA
parameter
N_33_MM
N_18_MM
Beta
1.59m
2.65m
Gds
261.98n
1.8u
gm
134.78u
168.58u
Vth
0.7
0.4
parameter
P_33_MM
P_18_MM
Beta
448.89u
712.6u
Gds
92.1n
266.6n
gm
80.11u
99.66u
Vth
-0.7
-0.4
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Differential amplifier schematic
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Dimensions
Devices
Values
(W/L)1=(W/L)2
19u/2u
(W/L)3=(W/L)4
13u/2u
(W/L)5
9u/2u
(W/L)6
1u/2u
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Results Analysis
PVT analysis
For 1.8V
Process
27
Temperature
-40
125
UGB(MHz)
DC
GAIN(db)
UGB(MH
z)
DC
GAIN(db)
UGB(M
Hz)
DC
GAIN(db)
tt
10
50.33
12.18
51.22
8.284 49.38
ff
10.28
50.49
12.4
51.35
8.512
49.55
ss
9.82
50.17
11.97
51.9
8.7
49.2
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For 1.62V
temp
27
-40
125
Process
UGB(MHz)
DC
GAIN(d
b)
UGB(MHz
)
DC
GAIN(db)
UGB(MHz
)
DC
GAIN(db)
tt
9.98
47.86
12.16
49.1
8.52
46.66
ss
10.42
48.4
12.88
49.55
8.04
47.24
ff
9.77
47.23
11.91
48.57
7.931
45.92
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For 1.92V
temp
27
-40
125
Process
UGB(MHz)
DC
GAIN(d
b)
UGB(MHz
)
DC
GAIN(db)
UGB(MHz
)
DC
GAIN(db)
tt
10
50.98
12.1
51.74
7.948
50.14
ss
10.29
51.05
12.31
51.81
8.678
50.19
ff
9.739
50.92
12.25
51.71
7.881
40.07
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Amplifier in buffer configuration
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waveform
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RESULTS
specification
parameter
target
Simulated
value
DC gain (dB)
50
50.28
UGB(MHz)
10
10.24
Settling time(ns)
80
85
23
2/6/15
THANK YOU

Amplifier With Buffer Configuratoin: KLE Society's B.V. Bhoomaraddi College of Engineering and Technology, Hubli

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1

AMPLIFIER WITH BUFFER CONFIGURATOIN

A buffer amplifier is one that provides electrical impedance

Design of CMOS differential amplifier

The output resistance of diff amp

The differential voltage gain is

When the transistor is in the

CMOS Frequency response

For L=2u,W=18u & Idc=20uA

Differential amplifier schematic

Amplifier in buffer configuration

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