Data Sheet No.

PD60028-L

IR2111(S)
HALF-BRIDGE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels Internally set deadtime High side output in phase with input

Product Summary
VOFFSET IO+/VOUT ton/off (typ.) Deadtime (typ.) 600V max. 200 mA / 420 mA 10 - 20V 750 & 150 ns 650 ns

Description
The IR2111(S) is a high voltage, high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels designed for half-bridge applications. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic input is compatible with standard CMOS outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Internal deadtime is provided to avoid shoot-through in the output half-bridge. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Packages

8-Lead PDIP

8-Lead SOIC

Typical Connection
up to 600V VCC

VCC
IN

VB HO VS
TO LOAD

IN COM LO

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

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IR2111(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in figures 7 through 10.

Symbol
VB VS VHO VCC VLO VIN dVs/dt PD RthJA TJ TS TL

Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Allowable offset supply voltage transient (figure 2) Package power dissipation @ TA +25C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 Lead PDIP) (8 lead SOIC) (8 lead PDIP) (8 lead SOIC)

Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -55

Max.
625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300

Units

V/ns W C/W

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol
VB VS VHO VCC VLO VIN TA

Definition
High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature

Min.
VS + 10 Note 1 VS 10 0 0 -40

Max.
VS + 20 600 VB 20 VCC VCC 125

Units

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

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IR2111(S)
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in figure 3.

Symbol
ton toff tr tf DT MT

Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Deadtime, LS turn-off to HS turn-on & HS turn-off to LS turn-on Delay matching, HS & LS turn-on/off

Min. Typ. Max. Units Test Conditions

550 480 750 150 80 40 650 30 950 180 130 65 820 ns VS = 0V VS = 600V

Static Electrical Characteristics

VBIAS (VCC, VBS) = 15V and TA = 25C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol
VIH

Definition
Logic 1 input voltage for HO & logic 0 for LO

Min. Typ. Max. Units Test Conditions

6.4 9.5 12.6 50 70 30 8.6 8.2 8.6 8.2 250 500 3.8 6.0 8.3 100 100 50 100 180 50 1.0 9.6 9.2 9.6 9.2 mA VO = 0V, VIN = VCC PW 10 s VO = 15V, VIN = 0V PW 10 s V A mV V VCC = 10V VCC = 15V VCC = 20V VCC = 10V VCC = 15V VCC = 20V IO = 0A IO = 0A VB = VS = 600V VIN = 0V or VCC VIN = 0V or VCC VIN = VCC VIN = 0V

VIL

Logic 0 input voltage for HO & logic 1 for LO

VOH VOL ILK IQBS IQCC IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO-

High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic 1 input bias current Logic 0 input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current

7.6 7.2 7.6 7.2 200 420

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IR2111(S)
Functional Block Diagram
VB UV DETECT DEAD TIME PULSE GEN IN UV DETECT
HV LEVEL SHIFT

R Q R S VS HO

PULSE FILTER

VCC

LO DEAD TIME COM

Lead Definitions
Symbol Description
IN VB HO VS VCC LO COM Logic input for high side and low side gate driver outputs (HO & LO), in phase with HO High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return

Lead Assignments

8 Lead DIP

8 Lead SOIC

IR2111 Part Number

4

IR2111S

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IR2111(S)
IN

HO

LO

Figure 1. Input/Output Timing Diagram

Figure 2. Floating Supply Voltage Transient Test Circuit

IN(LO)
50% 50%

IN(HO)
ton tr 90% toff 90% tf

LO HO
Figure 3. Switching Time Test Circuit

10%

10%

Figure 4. Switching Time Waveform Definition

50%

50%

IN (LO)
50% 50%

IN

IN (HO)
90%

LO

HO
10%

HO LO
90%

10% DT
MT

MT 90%

10%
Figure 5. Deadtime Waveform Definitions

LO

HO

Figure 6. Delay Matching Waveform Definitions

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IR2111(S)
1500

1500 Turn-On Delay Time (ns)

M ax. T yp. M i n.

Turn-On Delay Time (ns)

1250 1000 750 500 250 0 -50 -25 0 25 50

o

1250 Max. 1000 750 500 250 0 Typ. Min.

75

100

125

10

12

14

16

18

20

Temperature ( C)

V BIA S Supply V oltage (V)

Figure 11A Turn-On Time vs Temperature

400 Turn-Off Delay Time (ns)

Figure 11B Turn-On Time vs Voltage

400 Turn-Off Delay Time (ns) 350 300 250 200 150 100 50 0 10 12 14 16 18 20
Typ Max

350 300 250 200 150 100 50 0 -50 -25 0 25 50 Temperature (C) 75 100 125
Typ Max

VBIAS Supply Voltage (V)

Figure 12A Turn-Off Time vs Temperature

400 350 Turn-On rise Time (ns) 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125
Typ Max

Figure 12B Turn-Off Time vs Voltage

400 350 Turn-On Rise Time (ns) 300 250 200 150 100
Typ Max

50 0 10 12 14 16 18 20 V B IA S Supply V oltage (V )

Temperature (C)

Figure 13A Turn-On RiseTime vs Temperature

Figure 13B Turn-On RiseTime vs Voltage

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IR2111(S)
200 Turn -Off Fall Time (ns)

200

100

Turn-Off Fall Time (ns)

150

150

Max

100
Max

50
Typ

50
Typ

0 -50 -25 0 25 50 75 Temperature (C) 100 125

0 10 12 14 16 18 20 VBIAS Supply Voltage (V)

Figure 14A Turn-Off Fall Time vs Temperature

Figure 14B Turn-Off Fall Time vs Voltage

1250 1000 Deadtime (ns) 750 500 250 0 -50

M ax.

1250 1000 Deadtime (ns) 750 500 250 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 VBIAS Supply Voltage (V)
Figure 15B Dead Time vs Voltage
15 Logic " 1 " Input Treshold (V) 12

Max. Typ. Min.

Typ. Mi n.

Temperature (oC)
Figure 15A Dead Time vs Temperature
Logic "1" Input Threshold (V) 15 12
Min

Min

0 -50 -25 0 25 50 75 100 125 Temperature (C)

0 10

12

14

16

18

20

Figure 16A Logic I Input voltage for HO & Logic 0 for LO vs Temperature

Figure 16B Logic I Input voltage for HO & Logic 0 for LO vs Voltage

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IR2111(S)
Logic " 0 " Input Treshold (V)
15 Logic "0" Input Threshold (V) 12 9
Max

12

15

Max

6 3 0 -50 -25 0 25 50 Temperature (C) 75 100 125

0 10

12

14

16

18

20

VCC Logic Supply Voltage (V)

Figure 17A Logic 0 Input voltage for HO & Logic I for LO vs Temperature

Figure 17B Logic 0 Input voltage for HO & Logic I for LO vs Voltage
1 H igh Level O utput V oltage (V ) 0.8 0.6 0.4 M ax. 0.2 0

1 H igh Level O utput V oltage (V ) 0.8 0.6 0.4 M ax. 0.2 0 -50 -25 0 25 50 75 100 125

10

12

14

16

18

20

T e m p e ra tu re
Figure 18A. High Level Output vs. Temperature
Low Level Output Voltage (V)
Low Level Output Voltage (V)

V B A IS S upply V otage (V )

Figure 18B. High Level Output vs. Voltage

1 0.8 0.6 0.4 Max. 0.2 0 10 12 14 16 18 20

1 0.8 0.6 0.4

Max.
0.2 0 -50

-25

25

50

75

100

125

Temperature (C)

VBIAS Supply Votage (V)

Figure 19B. Low Level Output vs. Voltage

Figure 19A. Low Level Output vs. Temperature

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IR2111(S)
Offset Supply Leakage Current (uA) Offset Supply Leakage Current (uA) 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 Max. 500 400 300 200 M ax . 100 0 0 100 200 300 400 500 600

Temperature (C)

V B B oos t V oltage (v)

Figure 20A Offset Supply Current vs Temperature

200 VBS Supply Current (uA)

Figure 20B Offset Supply Current vs Voltage

200 VBS Supply Current (uA)

150 Max. 100 Typ. 50

150 Max. 100 Typ. 50

0 -50 -25 0 25 50 75 100 125 Temperature (C)

0 10 12 14 16 18 20

VBS Floating Supply Voltage (V)

Figure 21A VBS Supply Current vs Temperature

500 Vcc Supply Current (uA)

Figure 21B VBS Supply Current vs Voltage

500 V cc S upply C urrent (uA ) 400 300 200 100
Typ Max

400 300 Max . 200 100 0 -50 -25 0 25 50 75 100 125 Temperature (C) Typ.

0 10 12 14 16 18 20

V cc F ixed S upply V oltage (V )

Figure 22A VCC Supply Current vs Temperature

Figure 22B VCC Supply Current vs Voltage

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IR2111(S)
Logic "1 " Input Bias Current (uA) 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 Temperature (C) Logic " 1" Input Bias Current (uA) 120 100 80 60 40 20 0 10 12 14 16 18 20 VCC Supply Voltage (V) Typ. Max.

Figure 23A Logic 1 Input Current vs Temperature

5 Logic "0" Input Bias Current (uA) 4 3 2

Figure 23B Logic 1 Input Current vs VCC Voltage

Logic "0" Input Current (uA) 5 4 3 2 1 0 10 12 14 16 18 20 Max.

Max.
1 0 -50 -25 0 25 50 75 100 125

Temperature (C)

VCC Supply Voltage (V)

Figure 24A. Logic 0 Input Current vs. Temperature

12 VBS UVLO Threshold +(V)

Figure 24B. Logic 0 Input Current vs. VCC Voltage

12 V B S U V LO Threshol d -(V ) 11 10 9 8 7 6 Mi n. M ax . Typ.

11 Max . 10 9 8 7 6 -50 -25 0 25 50 75 100 125 Temperature (C) Min. Typ.

-50

-25

25

50

75

100

125

Tem perature (C )

Figure 25 VBS Undervoltage Threshold (+) vsTemperature

Figure 26 VBS Undervoltage Threshold (-) vsTemperature

10

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IR2111(S)
11 Vcc Undervoltage Lockout +(V) 10 9 8 7 6 -50
VCC Undervoltage Lockout - (V) 11 10

Max. Typ. Min.

Max.
9

Typ.
8

Min.
7 6

-25

25

50

75

100

125

-50

-25

25

50

75

100

125

Temperature (C)
Figure 27 VCC Undervoltage (-) vs Temperature
500

Temperature (C)

Figure 28 VCC Undervoltage (-) vs Temperature

500 Output source Current (mA) 400

Typ.

Output source Current (mA)

400 300

300 200 100 0

Min.

Typ.
200

Min.
100 0 -50 -25 0 25 50 75 100 125 Temperature (C)

10

12

14

16

18

20

VBIAS Supply Voltage (V)

Figure 29B Output Source Current vs Voltage
750 Output Sink Current (mA) 600

Figure 29A Output Source Current vs Temperature

750 Output Sink Current (mA) 600

Typ.
450 300 150 0 -50 -25 0 25 50 75 100 125 Temperature (C)

Typ.
450 300 150 0 10 12 14 16 18 20 VBIAS Supply Voltage (V)

Min.

Min.

Figure 30A Output Sink Current vs Temperature

Figure 30B Output Sink Current vs Voltage

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IR2111(S)
320V 160V

150 Ju n ctio n T e m p e ratu re (C ) 125 100 75 50 25 0 1E+2

320 Ju n ctio n T e m p e ratu re (C )

150 125

160 30V

100 30V 75 50 25 0 1E+2

1E+3

1E+4
Frequency (Hz)

1E+5

1E+6

1E+3

1E+4
Frequency (Hz)

1E+5

1E+6

Figure 31. IR2111 TJ vs. Frequency (IRFBC20) RGATE = 33, VCC = 15V

Figure 32. IR2111 TJ vs. Frequency (IRFBC30) RGATE = 22, VCC = 15V

150 Ju n ctio n T e m p e ratu re (C ) 125 100 75 50 25 0 1E+2

320V 160V 30V

Ju n ctio n T e m p e ratu re (C )

150 125 100 75 50 25 0 1E+2

320V 160V 30V

1E+3

1E+4
Frequency (Hz)

1E+5

1E+6

1E+3

1E+4
Frequency (Hz)

1E+5

1E+6

Figure33. IR2111 TJ vs. Frequency (IRFBC40) RGATE = 15, VCC = 15V

Figure 34. IR2111 TJ vs. Frequency (IRFPC50) RGATE = 10, VCC = 15V

12

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IR2111(S)
320V 150 125 Ju n ctio n T e m p e ratu re (C )
Ju n ctio n T e m p e ratu re (C ) 320V 140V

160

150 125 100 75 50 25 0 1E+2 30V

100 75 50 25 0 1E+2 30V

1E+3

1E+4

1E+5

1E+6

1E+3

1E+4

1E+5

1E+6

Frequency (Hz)

Frequency (Hz)

Figure 35. IR2111S TJ vs. Frequency (IRFBC20) RGATE = 33, VCC = 15V

Figure 36. IR2111S TJ vs. Frequency (IRFBC30) RGATE = 22, VCC = 15V

320V 140V 150 125 Ju n ctio n T e m p e ratu re (C ) 100 75 50 25 0 1E+2

Ju n ctio n T e m p e ratu re (C )

320V 140V 30V

30V

150 125 100 75 50 25 0 1E+2

1E+3

1E+4

1E+5

1E+6

1E+3

1E+4

1E+5

1E+6

Frequency (Hz)

Frequency (Hz)

Figure 37. IR2111S TJ vs. Frequency (IRFBC40) RGATE = 15, VCC = 15V

Figure 38. IR2111S TJ vs. Frequency (IRFPC50) RGATE = 10, VCC = 15V

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13

IR2111(S)
Case outlines

8-Lead PDIP
D A 5 B
FOOTPRINT 8X 0.72 [.028]

01-6014 01-3003 01 (MS-001AB)

INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00

DIM A b c D

A1 .0040

6 E

5 H 0.25 [.010] A

E
6.46 [.255]

e e1 H K L
8X 1.78 [.070]

.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8

1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8

6X

e e1

3X 1.27 [.050]

A C 0.10 [.004] y

K x 45

8X b 0.25 [.010]
NOTES:

A1 C A B

8X L 7

8X c

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.

5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.

8-Lead SOIC
14

01-6027 01-0021 11 (MS-012AA)

Data and specifications subject to change without notice.

4/18/2003

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