A

Model Name:
PCB NO:
BOM P/N:

KML50 DIS
LA-4595PR04
DA80000DR00

Half Penny Bridge 15.4

Compal Confidential

Schematic Document

Cantiga + ICH9
2009 / 02 / 17

Rev:1.0(A00)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Sheet
Size Document Number
Custom

Rev
1.0

LA-4595P

Date:

Tuesday, February 17, 2009

Sheet
E

of

49

Half Penny Bridge 15.4 DIS

Compal confidential
File Name : LA-4595P
ZZZ1

Thermal Sensor
EMC1402-2-ACZL-TR

PCB

CRT

+CRT_VCC

Penryn -4MB (Socket P)

uFCPGA-478 CPU

+VCCP

P.16

P.4

+3VS

P.4,5,6

+1.5VS

LVDS Panel Interface

+B+
+3VS
+LCDVDD

Fan conn

H_A#(3..35)

P.16

VRAM x 2

+1.8VS

P.35

+1.05VS_CK505

DDR2 667/800MHz 1.8V

+1.05VS_DPLLA

+1.1V_GFX_PCIE

+1.05VS_DPLLB

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
+1.8V

1329pin BGA

+VCCP

+VGA_CORE

+3VS

800/1066MHz 1.05V

Intel Cantiga MCH

+1.8VS

Clock Generator
ICS9LPRS387AKLFT

FSB

H_D#(0..63)

nVidia
NB9M-GS

+3VS_DAC_BG

USB conn x 4

P.7,8,9,10,11,12

+USB_AS

PCI -E BUS

FingerPrinter

C-Link

Intel ICH9-M

Media Card

+RTCVCC
+1.5VS

Mini-Card-2
(WLAN)
+1.5VS

Mini-Card-1
(WWAN)
+1.5VS

+3VS

+3VS

Felica Conn

P.23

P.29

+5VS

Azalia

BT Conn

P.29

+3VS

676pin BGA

+VCCP
+3VALW

SATA 0
SATA 1

Camera

P.17,18,19,20

+3VS

Express Card

P.16

+5VS

Express Card

+1.5VS

+3VS

P.26

+1.5VS

P.26

+3VS

SIM CON

+UIM_PWR

LPC BUS

Mini-Card-1

P.23

Mini-Card-2

P.23

+3VS

P.21

P.29

P.29

+3VS

USB2.0

+3VS_CR

RJ45/11 CONN

+USB_CS

DMI X4

P.30

P.23

+USB_BS

P.31,32,33,34

PCI-E BUS
10/100/1000 LAN
REALTEK
RTL8111DL P.21
+LAN_IO

P.15

+3VS_CK505

P.13,14

Dual Channel

+1.8VS_CB

1394

+0.9VS

+3VS_DAC_CRT

+1.8V_TXLVDS

CardBus Controller
O2MICRO OZ888

+3VS_PHY

TSSOP-64

CK505

P.4

+5VS

+CPU_CORE

+3VS

+1.5VS

+1.5VS

Digi Mic
Mini-Card-2
+3VS

+1.5VS

P.23

+3VALW

TPM
SLB 9635

ENE KB926

P.24

+MIC1_VREFO

P.28

+3VS

P.16

Audio Jack

+5VS +3VS

+3VALW

P.27

+EC_AVCC

+3VS

Audio CODEC
IDT92HD81 P.24
SATA HDD Connector

Touch Pad CONN.

Power On/Off CKT.

+3VALW

+5VS

P.28

P.28

Int.KBD
P.28

+5VS

BIOS(System/EC)
+3VALW

P.27

CDROM Conn.
+5VS

DC/DC Interface CKT.

+3VS

+5VS

P.36

P.22

RTC CKT.
+RTCVCC

P.18
Compal Secret Data

Security Classification

Power Circuit DC/DC

2007/1/15

Issued Date

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P.39~P.49
A

P.22

Title

Compal Electronics, Inc.

Block diagram

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
E

of

49

Symbol Note :
O MEANS ON

Voltage Rails

X MEANS OFF

: means Digital Ground

+5VS
+3VS
+1.5VS

power
plane

: means Analog Ground

+0.9VS
+VCCP
+1.8V

+5VALW
+B

@ : means just reserve , no build

CON@ : means ME connectors
TPM@ : means TPM function

+CPU_CORE
+VGA_CORE
+1.8VS

+3VALW

+1.1V_GFX_PCIEP
State

PCI EXPRESS

DESTINATION

SATA

DESTINATION

Lane 1

MINI CARD-1 WWAN

Lane 0

HDD

Lane 2

GLAN RTL8111DL

Lane 1

ODD

S0

Lane 3

MINI CARD-2 WLAN

Lane 4

NA

S1

Lane 4

EXPRESS CARD

Lane 5

NA

S3

Lane 5

CARD READER OZ888

S5 S4/AC

Lane 6

NA

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

X
SMBUS Control Table

USB PORT#

ICH9-M

DESTINATION

SOURCE

INVERTER

BATT

SERIAL
EEPROM

THERMAL
SENSOR
(CPU)

JUSBP1

CAMERA

SMB_EC_CK1
SMB_EC_DA1

KB926

JUSBP3 TOP

SMB_EC_CK2
SMB_EC_DA2

KB926

Felica

SMB_CK_CLK1
SMB_CK_DAT1

Blue Tooth

LCD_CLK
LCD_DAT

Finger Printer

JMINI2-WLAN

Express card
DEVICE

HEX

ADDRESS

JUSBP3 BOT

DDR SO-DIMM 0

A0

10100000

JMINI1-WWAN

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

LED panel

58

01011000

10

JUSBP4

11

NA

SODIMM

CLK CHIP

MINI CARD

LCD

X
X

V
X

V
X

X
V

X
X

X
X

X
X

X
X

ICH9

Cantiga

I2C / SMBUS ADDRESSING

Compal Secret Data

Security Classification
2005/03/10

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet

of

49

+VCCP

XDP_TDI

R5

54.9_0402_1%

XDP_TMS

R4

54.9_0402_1%

K3
H2
K2
J3
L1

<7> H_ADSTB#1

H_STPCLK#
H_INTR
H_NMI
H_SMI#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A6
A5
C4

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

A20M#
FERR#
IGNNE#

F1

H_BR0#

D20
B3

H_IERR#
H_INIT#

LOCK#

H4

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

G6
E4

H_HIT#
H_HITM#

IERR#
INIT#

HIT#
HITM#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

H_A20M#
H_FERR#
H_IGNNE#

H5
F21
E1

H_DEFER#
H_DRDY#
H_DBSY#

BR0#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

THERMAL
PROCHOT#
THERMDA
THERMDC

ICH

<18> H_A20M#
<18> H_FERR#
<18> H_IGNNE#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H_ADS#
H_BNR#
H_BPRI#

DEFER#
DRDY#
DBSY#

ADDR GROUP_1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H1
E2
G5

ADS#
BNR#
BPRI#

54.9_0402_1%

R35

54.9_0402_1%

THERMTRIP#

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0#

<7>

H_INIT#

<18>

H_LOCK# <7>
H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>
H_HIT# <7>
H_HITM# <7>

+3VS

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

T84
XDP_DBRESET# <19>

H_PROCHOT#
D21
A24
B25

H_THERMDA_R
H_THERMDC_R

C7

H_THERMTRIP#

R146
R57
R53

1
1

68_0402_1%~D
2 100_0402_5%
2 100_0402_5%

C5
1

+VCCP
H_THERMDA
H_THERMDC

H_THERMTRIP# <7,18>
+3VS

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

H CLK
BCLK[0]
BCLK[1]

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

0.1U_0402_16V4Z

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

CONTROL

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

XDP/ITP SIGNALS

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

A22
A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_BCLK <15>
CLK_CPU_BCLK# <15>

Thermal Sensor EMC1402-1-ACZL-TR

1
C13
2
U2
1
H_THERMDA

H_THERMDC
2
2200P_0402_50V7K
L_THERM#

R16
1
2
10K_0402_5%

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <16,27,31>
EC_SMB_DA2 <16,27,31>

6
5

EMC1402-2-ACZL-TR MSOP 8P

Address:100_11000

C76
10U_1206_16V4Z~N
2
1
+5VS
C88
1000P_0402_50V7K~N
2
1

FAN Control circuit

RESERVED

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]

<18>
<18>
<18>
<18>

R11

XDP_TCK

This shall place near CPU

ADDR GROUP_0

<7> H_ADSTB#0
<7>
<7>
<7>
<7>
<7>
<7>

XDP_TRST#

CONN@
JCPU1A

<7> H_A#[3..16]

1
C77

2
10U_1206_16V4Z~N

U3
1
2
3
4

FAN1_POWER
EN_DFAN1

<27> EN_DFAN1

+3VS

8
7
6
5

JFAN1

40mil

R61
10K_0402_5%

1
2
3

1
2
3

4
5

GND
GND

<27> FAN_SPEED1

C94
0.01U_0402_16V7K

@
R17
56_0402_5%

D61
PJSOT24C_SOT23-3
@

H_PROCHOT#

OCP#
3
1
@ Q2
MMBT3904_SOT23

ACES_85205-03001
conn@

FAN1

2 2

+VCCP

GND
GND
GND
GND

RT9027BPS SO 8P

Penryn

VEN
VIN
VO
VSET

OCP#

<19>

+VCCP
A

R18
56_0402_5%

Compal Secret Data

Security Classification

H_IERR#

2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

+CPU_CORE

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

MISC

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>

H_DPRSTP# <7,18,47>
H_DPSLP# <18>
H_DPWR# <7>
H_PWRGOOD <18>
H_CPUSLP# <7>
H_PSI#
<47>

Penryn

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL

CPU_BSEL1

CPU_BSEL0

166

200

266

R24

R25

R26

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

+VCCP

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

1
+
2

+1.5VS

AD6
AF5
AE5
AF4
AE3
AF3
AE2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

<47>
<47>
<47>
<47>
<47>
<47>
<47>

1
C12
2

VCCSENSE <47>

1
C11
2

Near pin B26

VSSSENSE <47>
B

Penryn

For 8 layer condition

Length match within 25 mils.Z0=27.4 ohm
The trace width/space/other is 20/7/25.

+VCCP
1

CPU_BSEL2

R23

27.4_0402_1%
2
1

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

DATA GRP 2

+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

54.9_0402_1%
2
1

T50
T51
T2
T3
T4
T5
T6
<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

C10
220U_D2_4VY_R15M

<7> H_DSTBN#1
<7> H_DSTBP#1
<7> H_DINV#1

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

27.4_0402_1%
2
1

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

54.9_0402_1%
2
1

<7>
<7>
<7>
<7>

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

+CPU_CORE
CONN@
JCPU1C

H_D#[32..47] <7>

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

0.01U_0402_16V7K

CONN@
JCPU1B

H_D#[0..15]

DATA GRP 3

<7>

10U_0805_6.3V6M

R27
1K_0402_1%

+CPU_CORE

+V_CPU_GTLREF

R28

2 100_0402_1%

VCCSENSE

R30

2 100_0402_1%

VSSSENSE

R29
2K_0402_1%

Close to CPU pin AD26

within 500mils.
A

Close to CPU pin

within 500mils.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

Place these caps inside

the CPU socket.

+CPU_CORE

Place these caps inside

the CPU socket cavity.

( Left side on Top ).

1
C204
10U_0805_6.3V6M

1
C205
10U_0805_6.3V6M

1
C529
10U_0805_6.3V6M

1
C232
10U_0805_6.3V6M

1
C258
10U_0805_6.3V6M

1
C505
10U_0805_6.3V6M

1
C504
10U_0805_6.3V6M

1
C257
10U_0805_6.3V6M

1
C261
10U_0805_6.3V6M

( Left side on Top ).

C214
10U_0805_6.3V6M

CONN@
JCPU1D

( Right side on Top side).

1
C178
10U_0805_6.3V6M

1
C202
10U_0805_6.3V6M

1
C254
10U_0805_6.3V6M

1
C190
10U_0805_6.3V6M

1
C203
10U_0805_6.3V6M

1
C200
10U_0805_6.3V6M

1
C182
10U_0805_6.3V6M

1
C199
10U_0805_6.3V6M

1
C208
10U_0805_6.3V6M

( Right side on Top ).

C226
10U_0805_6.3V6M

+CPU_CORE

Place these caps inside

the CPU socket cavity.

( Left side on Bottom ).

1
C501
10U_0805_6.3V6M

1
C508
10U_0805_6.3V6M

1
C514
10U_0805_6.3V6M

1
C519
10U_0805_6.3V6M

1
C522
10U_0805_6.3V6M

C533
10U_0805_6.3V6M

+CPU_CORE

Place these caps inside

the CPU socket cavity.

( Right side on Bottom ).

1
C502
10U_0805_6.3V6M

1
C510
10U_0805_6.3V6M

1
C515
10U_0805_6.3V6M

1
C520
10U_0805_6.3V6M

1
C526
10U_0805_6.3V6M

C532
10U_0805_6.3V6M

+CPU_CORE

1
+
2

1
+
2

1
C255

+
2

330U_D2E_2.5VM_R9

( Left side on Top ).

C259

Place these caps inside

the CPU socket.

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

Penryn

Place these caps inside

the CPU socket.

+CPU_CORE

Place these caps inside

the CPU socket cavity.

C198

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

330U_D2E_2.5VM_R9

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

C196

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

ESR <= 1.5m ohm

Place these caps inside

the CPU socket.

Capacitor > 880 uF

( Right side on Top side).

Place these inside

socket cavity on L8
(North side
Secondary)
+VCCP

C213
0.1U_0402_10V6K

C209
0.1U_0402_10V6K

C212
0.1U_0402_10V6K

C185
0.1U_0402_10V6K

C183
0.1U_0402_10V6K

C184
0.1U_0402_10V6K

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0#
<4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

PM_EXTTS#0

<5>
<5>
<5>
<5>

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<5>
<5>
<5>
<5>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<4>
<4>
<4>
<4>
<4>

H_RS#0
H_RS#1
H_RS#2

<4>
<4>
<4>

<15> MCH_CLKSEL0
<15> MCH_CLKSEL1
<15> MCH_CLKSEL2
PAD T8
PAD T9
<9>
CFG5
<9>
CFG6
<9>
CFG7
PAD T37
<9>
CFG9
PAD T65
PAD T40
PAD T67
PAD T47
PAD T10
PAD T66
<9>
CFG16
PAD T68
PAD T39
<9>
CFG19
<9>
CFG20

within 100 mils from NB

CRB-no stuff
Checklist-no
10/16 5

R323

C386

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
PLT_RST#_NB
H_THERMTRIP#
DPRSLPVR

1
+V_DDR_MCH_REF

R29
B7
N33
P32
AT40
AT11
T20
R32

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

221_0603_1%
2
1

CFG19
CFG20

R43
1K_0402_1%

C121
2

R324

CFG16

R42
1K_0402_1%

0.1U_0402_16V4Z

C391

H_SWNG
0.1U_0402_16V4Z

H_RCOMP

100_0402_1%
2
1

R46

0.1U_0402_16V4Z

24.9_0402_1%
2
1

1K_0402_1%
1
2
2K_0402_1%
2
1

+H_VREF

CFG12
CFG13

+1.8V

R322

BC28
AY28
AY36
BB36

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

BA17
AY16
AV16
AR13

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

BD17
AY17
BF15
AY13

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BG22
BH21

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

+SMRCOMP_VOH
+SMRCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

+V_DDR_MCH_REF

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

R328
R329

SM_REXT
TP_SM_DRAMRST#

R40

<13>
<13>
<14>
<14>

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<13>
<13>
<14>
<14>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

<13>
<13>
<14>
<14>

M_ODT0
M_ODT1
M_ODT2
M_ODT3

<13>
<13>
<14>
<14>

+1.8V

2 80.6_0402_1%
2 80.6_0402_1%

1
1

1
T29 PAD

2 499_0402_1%

B38
A38
E41
F41
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

AE35
AE43
AE46
AH42

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

AD35
AE44
AF46
AH43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>
C

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

<13>
<13>
<14>
<14>

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

F43
E43

PEG_CLK
PEG_CLK#

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

PM_PWROK_R

2
0_0402_5%
2
0_0402_5%

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

<13,14> +V_DDR_MCH_REF

CFG9

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

NC

1
R408
1
@ R407

1
2
R523 100_0402_5%

CFG5
CFG6
CFG7

<19,27,47> VGATE

R45

PLT_RST#

<17,27,30,31> PLT_RST#
<4,18> H_THERMTRIP#
<19,47> DPRSLPVR

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

PM

<19> PM_BMBUSY#
<5,18,47> H_DPRSTP#
<13> PM_EXTTS#0
<14> PM_EXTTS#1

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

10K_0402_5%

CANTIGA_1p0

<19,27> ICH_PWROK

R83
1

PM_EXTTS#1

H_AVREF
H_DVREF

H_RCOMP Dual core 24.9 ohm_1% pull down

Quad core 16.9 ohm_1% pull down
H_SWNG Dual core 100 ohm_1% pull down
Quad core 75 ohm_1% pull down

10K_0402_5%

<5>
<5>
<5>
<5>

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

R82
1

AR24
AR21
AU24
AV20

CLK

L10
M7
AA5
AE6

+VCCP

RSVD22
RSVD23
RSVD24
RSVD25

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

B33
B32
G33
F33
E33

T30
T31
T32
T33
T34

C34

T35

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

<19>
<19>
<19>
<19>

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

<19>
<19>
<19>
<19>

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

<19>
<19>
<19>
<19>

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

<19>
<19>
<19>
<19>

+VCCP
1

1
2

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

DMI

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

+VCCP

T41
T44
T73
T74

BG23
BF23
BH18
BF18

RSVD20

R333
1K_0402_1%

AP24
AT21
AV24
AU20

AH37
AH36
AN36
AJ35
AH34

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF

R100
1K_0402_1%

CL_CLK0 <19>
CL_DATA0 <19>
M_PWROK <19>
CL_RST# <19>

J8
L3
Y13
Y1

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

AY21

DDR CLK/ CONTROL/COMPENSATION

1
2

2.2U_0603_6.3V4Z
C398

C400
C404

0.01U_0402_25V7K

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

A11
B11

T28

RSVD15
RSVD16
RSVD17

+3VS

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

+H_VREF

+SMRCOMP_VOL

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_CPURST#
H_CPUSLP#

T25
T26
T27

B31
B2
M1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

N28
M28
G36
E36
K36
H36
B12

CLKREQ#_7
MCH_ICH_SYNC#

T36
T48
T63
T64

R99
511_0402_1%

CLKREQ#_7 <15>
MCH_ICH_SYNC# <19>

2 R1071 1
56_0402_5%

B28
B30
B29
C29
A28

C181
0.1U_0402_16V4Z

C12
E11

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

GRAPHICS VID

H_RESET#
H_CPUSLP#

H_RESET#
H_CPUSLP#

H_SWING
H_RCOMP

R331
1K_0402_1%

R332
3.01K_0402_1%

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

+SMRCOMP_VOH

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

+1.8V

T7
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T24

ME

C5
E3

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

CFG

H_SWNG
H_RCOMP

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

MISC

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

2.2U_0603_6.3V4Z
C403

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6

RSVD

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U4B

0.01U_0402_25V7K

U4A

H_D#[0..63]

<4>
<5>

H_A#[3..35] <4>

HOST

<5>

HDA

+VCCP

T99
T100
T101
T102
T103

CANTIGA_1p0

Compal Secret Data

Security Classification

Near B3 pin

2008/09/24

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

<14> DDR_B_D[0..63]

BB20
BD20
AY20

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

SA_RAS#
SA_CAS#
SA_WE#

DDR_A_RAS# <13>
DDR_A_CAS# <13>
DDR_A_WE# <13>
DDR_A_DM[0..7]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS#0 <13>
DDR_A_BS#1 <13>
DDR_A_BS#2 <13>

<13>

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

<13>

<13>

DDR_A_MA[0..14] <13>

CANTIGA_1p0

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

BC16
BB17
BB33

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AU17
BG16
BF14

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

MEMORY

BD21
BG18
AT25

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDR

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U4E

SYSTEM

U4D

DDR

<13> DDR_A_D[0..63]

DDR_B_BS#0 <14>
DDR_B_BS#1 <14>
DDR_B_BS#2 <14>
DDR_B_RAS# <14>
DDR_B_CAS# <14>
DDR_B_WE# <14>

DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

<14>

<14>

DDR_B_MA[0..14] <14>

CANTIGA_1p0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

U4C

R56 within 500 mils from

pin T37,T36

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

M29
C44
B43
E37
E38
C41
C40
B37
A37

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

T38

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

T46

H48
D45
F40
B40

A41
H38
G37
J37

T49

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

F25
H25
K25

TVA_DAC
TVB_DAC
TVC_DAC

E28

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_GREEN

J28

CRT_RED

H32
J32
J29
E29
L29

CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

VGA

G28

G29

TV

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

C31
E32

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

B42
G38
F37
K37

H24

GRAPHICS

M33
K33
J33

PCI-EXPRESS

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

LVDS

L32
G32
M32

PEGCOMP

R95
1
2
49.9_0402_1%

+VCC_PEG

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_NRX_GTX_N0
PEG_NRX_GTX_N1
PEG_NRX_GTX_N2
PEG_NRX_GTX_N3
PEG_NRX_GTX_N4
PEG_NRX_GTX_N5
PEG_NRX_GTX_N6
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
PEG_NRX_GTX_N9
PEG_NRX_GTX_N10
PEG_NRX_GTX_N11
PEG_NRX_GTX_N12
PEG_NRX_GTX_N13
PEG_NRX_GTX_N14
PEG_NRX_GTX_N15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_NRX_GTX_P0
PEG_NRX_GTX_P1
PEG_NRX_GTX_P2
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
PEG_NRX_GTX_P5
PEG_NRX_GTX_P6
PEG_NRX_GTX_P7
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
PEG_NRX_GTX_P10
PEG_NRX_GTX_P11
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13
PEG_NRX_GTX_P14
PEG_NRX_GTX_P15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

C568
C537
C538
C539
C540
C541
C542
C543
C544
C545
C546
C547
C548
C549
C550
C551

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4
PEG_NTX_GRX_N5
PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
PEG_NTX_GRX_N11
PEG_NTX_GRX_N12
PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C552
C553
C554
C555
C556
C557
C558
C559
C560
C561
C562
C563
C564
C565
C566
C567

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_NTX_GRX_P0
PEG_NTX_GRX_P1
PEG_NTX_GRX_P2
PEG_NTX_GRX_P3
PEG_NTX_GRX_P4
PEG_NTX_GRX_P5
PEG_NTX_GRX_P6
PEG_NTX_GRX_P7
PEG_NTX_GRX_P8
PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

000 = FSB 1066MHz

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

CFG[2:0] FSB Freq select

PEG_COMPI
PEG_COMPO

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

Strap Pin Table

PEGCOMP trace width

and spacing is 20/25 mils.

T37
T36

PEG_NRX_GTX_N[0..15]

PEG_NRX_GTX_N[0..15]

<31>

CFG[4:3]

Reserved

CFG5 (DMI select)

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

CFG6

1 = The iTPM Host Interface is disable

PEG_NRX_GTX_P[0..15]

<31>

1 =(TLS)chiper suite with confidentiality

<31>

Reserved

CFG9

0 = Reverse Lane,15->0, 14->1

(PCIE Graphics Lane Reversal)

1 = Normal Operation,Lane Number in order

0 = Enable
1 = Disable

CFG11

Reserved

CFG[13:12] (XOR/ALLZ)

00
01
10
11

CFG[15:14]

Reserved

CFG16 (FSB Dynamic ODT)

0 = Disabled

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation(Default)

1 = Enabled

PEG_NTX_GRX_P[0..15] <31>

CFG8

CFG10 (PCIE Lookback enable)

PEG_NTX_GRX_N[0..15]

0 =(TLS)chiper suite with no confidentiality

CFG7 (Intel Management

Engine Crypto strap)

PEG_NRX_GTX_P[0..15]

CFG[18:17]

Reserved

CFG19 (DMI Lane Reversal)

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane
CFG20 (PCIE/SDVO concurrent)

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

CANTIGA_1p0

<7>

CFG5

<7>

CFG6

<7>

CFG7

<7>

CFG9

<7>

CFG16

@ R66

2 2.21K_0402_1%~D

@ R58

2 2.21K_0402_1%~D

@ R59

2 2.21K_0402_1%~D

@ R55

2 2.21K_0402_1%~D

@ R70

2 2.21K_0402_1%~D

CFG[5:16] have internal pullup

+3VS
<7>

CFG19

<7>

CFG20

@ R72

2 4.02K_0402_1%~D

@ R73

2 4.02K_0402_1%~D

CFG[19:20] have internal pulldown

Compal Secret Data

Security Classification
Issued Date

2006/02/13

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

of

49

+VCCP
+VCCP
R101
1
2
0_0805_5%

+V1.05VS_AXF
U4H

VCCA_PEG_PLL

1
C387

C373

VTT

C383

CRT
PLL
A LVDS

AA48

VCCD_LVDS_1
VCCD_LVDS_2

AXF
SM CK

HV
PEG
DMI

L12

105.3mA

V48 1732mA
U48
V47
U47
U46

+VCC_PEG

AH48 456mA
AF48
AH47
AG47

+1.05VS_DMI

+1.05VS_DMI

+VCCP

+VCC_PEG
R112
1
2
0_0805_5%

2
BLM21PG221SN1D_0805~D

20mils
VTTLF1
VTTLF2
VTTLF3

A8
L1
AB2

+1.5VS_QDAC

C98

+1.5VS
R69
BLM18PG181SN1_0603~D
2
1

0.1U_0402_16V4Z

C97

0.01U_0402_25V7K~N

0.47U_0603_10V7K
C65

0.47U_0603_10V7K
C385

CANTIGA_1p0

A CK

TV
HDA

VCCD_PEG_PLL

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF

M38
L37

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

+1.05VS_PEGPLL
+3VS

0.1U_0402_16V4Z
C116

AA47

VCCD_HPLL

118.8mA

10U_0805_4VAM~D

50mA
60.31mA
2

VCCD_QDAC

VCC_HV_1
VCC_HV_2
VCC_HV_3

C35
B35
A35

+1.8V_SM_CK

C179

AF1

K47

0.47U_0603_10V7K
C382

C233 0.1U_0402_16V4Z

C251 0.1U_0402_16V4Z

L28

157.2mA

VCC_TX_LVDS

R123

+1.05VS_PEGPLL

48.363mA

VCCD_TVDAC

BF21
BH20
BG20
BF20

C176

+1.5VS_QDAC
+1.05VS_HPLL

M25

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

0.1U_0402_16V4Z

VCC_HDA

124mA

C410

58.67mA

A32

0.1U_0402_16V4Z

+V1.05VS_AXF

1_0402_5%~D

50mA

VCCA_TV_DAC_1
VCCA_TV_DAC_2

B22
B21
A21

0.1U_0402_16V4Z

HDMI disable connected to GND

B24
A24

D TV/CRT

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

4.7U_0805_10V4Z

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

1
220U_D2_4VY_R15M

C123
0.1U_0402_16V4Z~D

C104

22U_0805_6.3V6M~D

AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

C389

+1.05VS_A_SM_CK

321.35mA

LQH32CNR15M33L_1210~D

C95
C117

C63

26mA AP28

+VCCP
PJP13
JUMP_43X39
1 1
2 2

22U_0805_6.3V6M~D

L9
1

C62

2
4.7U_0805_10V4Z

+VCCP

22U_0805_6.3V6M~D

+1.05VS_MPLL

R74

R71
1
2
0_0603_5%

C83

C72
1U_0603_10V4Z~D

C82

22U_0805_6.3V6M~D

0_0805_5%
2

+VCC_PEG

POWER

0_0603_5%

+1.05VS_A_SM
R50

1
C68

100U_D2E_6.3VM_R15M~D

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

LVDS

+VCCP

AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

720mA AR20

+1.05VS_PEGPLL

A SM

50mA

C175

A PEG

1 0.1U_0402_16V4Z~D

C102

VCCA_PEG_BG

L29
1
2
MBK2012121YZF_0805

0.1U_0402_16V4Z

AD48

C69

414uA
+1.5VS

+1.8V
R102
1
2
0_0805_5%

+VCCP

C96

VSSA_LVDS

+1.8V_SM_CK
+1.05VS_HPLL

4.7U_0805_10V4Z

VCCA_LVDS

C388

J47

+1.5VS_PEG_BG

VCCA_MPLL

0.1U_0402_16V4Z

13.2mA J48

R124

139.2mA AE1

VCCA_HPLL

1_0402_5%~D 10U_0805_4VAM~D

+1.05VS_MPLL

VCCA_DPLLB

C56
2.2U_0603_10V7K~D

24mA AD1

4.7U_0805_10V4Z

64.8mA L48
+1.05VS_HPLL

VCCA_DPLLA

0.47U_0603_10V7K

64.8mA F47

VCCA_DAC_BG
VSSA_DAC_BG

1U_0603_10V4Z

A25
B25
D

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

C113

2.68mA

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

C384

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

4.7U_0805_10V4Z

B27
A26

C370
220U_D2_4VY_R15M

73mA

10U_0805_4VAM~D

852mA

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Size Document Number

Custom LA-4595P
Date:

Rev
1.0
Sheet

Tuesday, February 17, 2009

1

10

of

49

U4G

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

6326.84mA

VCC GFX NCTF

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

BA36
BB24
BD16
BB21
AW16
AW13
AT13

CANTIGA_1p0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

1U_0603_10V4Z

1U_0603_10V4Z

C163

0.47U_0402_6.3V6K

C145

C146

0.22U_0603_10V7K

0.22U_0603_10V7K

0.1U_0402_16V4Z

C81

C67

AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7

0.1U_0402_16V4Z

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

C71

AJ14
AH14

C70

CANTIGA_1p0

PAD T42
PAD T43

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

VCC GFX

VCC NCTF

POWER

+VCCP

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC SM LF

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

POWER

VCC CORE

VCC_35

C164
0.1U_0402_10V7K~D

T32

C147

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

22U_0805_6.3V6M~D

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

C165

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

22U_0805_6.3V6M~D

C148 330U_V_2.5VM

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
C120

0.1U_0402_16V4Z
C119

0.22U_0402_10V4Z
C143

0.22U_0402_10V4Z
C118

22U_0805_6.3V6M~D

C374
220U_D2_4VY_R15M

+1.8V

U4F

+VCCP
D

3000mA
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

VCC SM

Extnal Graphic: 1210.34mA

integrated Graphic: 1930.4mA

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

11

of

49

U4J

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

BA16

VSS_235

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

CANTIGA_1p0

VSS

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS_351
VSS_352
VSS_353
VSS_354

VSS NCTF

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS SCB

AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

NC

U4I

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

CANTIGA_1p0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

12

of

49

Close to VREF pins of SO-DIMM

+1.8V
<8> DDR_A_DQS#[0..7]

+V_DDR_MCH_REF <7,14>

DDR_A_D8
DDR_A_D9

Layout Note:
Place near JDIM1

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D14
DDR_A_D15

+1.8V
DDR_A_D16
DDR_A_D17
330U 2.5V Y D2

DDR_A_DQS#2
DDR_A_DQS2

1
+

C84

C108

0.1U_0402_16V4Z

C130

0.1U_0402_16V4Z

C131

C154

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C169

2.2U_0603_6.3V6K

C166

C149

2.2U_0603_6.3V6K

C124

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C105

2.2U_0603_6.3V6K

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_CKE0_DIMMA

<7> DDR_CKE0_DIMMA

DDR_A_BS#2

<8> DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

<8> DDR_A_BS#0
<8> DDR_A_WE#

+0.9VS

DDR_A_CAS#
DDR_CS1_DIMMA#

<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#

M_ODT1

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

C234

C168

C153

C152

C129

C128

C107

C167

C151

C150

C127

C126

C125

C106

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7>

DDR_A_D35
DDR_A_D34
DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41
DDR_A_D46

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

DDR_A_D49
DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

+0.9VS

DDR_A_D54
DDR_A_D50

DDR_A_MA5
DDR_A_MA8

RP14
1
2

DDR_A_MA1
DDR_A_MA3

RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA7
2
3
3
2 DDR_A_MA6

4
3

4
3

DDR_A_D61
DDR_A_D60

RP22 56_0404_4P2R_5%
1 DDR_A_MA12
2 DDR_CKE0_DIMMA

DDR_A_DM7
DDR_A_D59
DDR_A_D58

RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5%

DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_BS#2
RP6
A

DDR_A_BS#0
DDR_A_MA10
RP5

56_0404_4P2R_5%
1 DDR_A_MA0
2 DDR_A_BS#1

RP1 56_0404_4P2R_5% RP2

DDR_CS1_DIMMA# 2
3
4
M_ODT1
1
4
3

56_0404_4P2R_5%
1 M_ODT0
2 DDR_A_MA13

DDR_A_CAS#
DDR_A_WE#

+3VS

56_0404_4P2R_5% RP16 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2
56_0404_4P2R_5% RP8
1
4
4
2
3
3

C58
0.1U_0402_16V4Z

C59
2.2U_0603_6.3V6K

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

FOX_ASOA426-M2RN-7F

SO-DIMM A
REVERSE

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D6
DDR_A_D7

DDR_A_D13
DDR_A_D12

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_A_D11
DDR_A_D10

DDR_A_D20
DDR_A_D21
DDR_A_DM2

PM_EXTTS#0 <7>

DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA14

DDR_CKE1_DIMMA <7>

DDR_A_MA14 <8>

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0

<7>

DDR_A_D32
DDR_A_D33
DDR_A_DM4
DDR_A_D39
DDR_A_D38
DDR_A_D45
DDR_A_D47
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Bottom side
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

56_0404_4P2R_5% RP23 56_0404_4P2R_5%

DDR_CKE1_DIMMA 1
2
4
1 DDR_A_MA14
R96 56_0402_5%
3
2 DDR_A_MA11

ICH_SM_DA
ICH_SM_CLK

<14,15,19> ICH_SM_DA
<14,15,19> ICH_SM_CLK

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_DM0

R32
10K_0402_5%
2
1

DDR_A_D5
DDR_A_D0

R31
10K_0402_5%
2
1

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C220

DDR_A_DQS#0
DDR_A_DQS0

<8> DDR_A_MA[0..13]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C201

DDR_A_D4
DDR_A_D1

<8> DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

<8> DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JDIM2

<8> DDR_A_D[0..63]

2007/1/15

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

DDR2 SO-DIMM I
Size Document Number
Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet
1

13

of

49

Close to VREF pins of SO-DIMM

<8> DDR_B_DQS#[0..7]
+1.8V
<8> DDR_B_D[0..63]

+V_DDR_MCH_REF

<8> DDR_B_DM[0..7]

DDR_B_D10
DDR_B_D11

+1.8V

330U 2.5V Y D2

DDR_B_D17
DDR_B_D20

1
+
2

C189

C155

C133

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C132

0.1U_0402_16V4Z

C109

C177

0.1U_0402_16V4Z

C138

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C160

2.2U_0603_6.3V6K

C139

2.2U_0603_6.3V6K

C112

2.2U_0603_6.3V6K

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_B_D30
DDR_B_D31
<7> DDR_CKE2_DIMMB
<8> DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9VS
<8> DDR_B_BS#0
<8> DDR_B_WE#

<7>

M_ODT3

DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33

2
C159

C172

C137

C158

C136

C111

C171

C170

C157

C156

C135

C134

C110

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_DM5

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49

+0.9VS

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_MA1
DDR_B_MA3

RP18
1
2

DDR_B_MA10
DDR_B_BS#0

RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5%

DDR_B_MA14
1
4
4
1
DDR_B_MA11
2
3
3
2

DDR_B_BS#1
DDR_B_MA0

4
3

4
3

DDR_B_D51
DDR_B_D50

RP24 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58

RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5%

DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

<13,15,19> ICH_SM_DA
<13,15,19> ICH_SM_CLK

+3VS

RP9
DDR_B_CAS#
DDR_B_WE#

1
2

56_0404_4P2R_5% RP20 56_0404_4P2R_5%

DDR_B_MA4
4
4
1
DDR_B_MA2
3
3
2

0.1U_0402_16V4Z

RP3
DDR_CS3_DIMMB# 2
M_ODT3
1

56_0404_4P2R_5% RP4
3
4
4
3
56_0404_4P2R_5% RP25
4
3

DDR_CKE3_DIMMB 1
2
R335 56_0402_5%

56_0404_4P2R_5%
DDR_B_MA13
1
M_ODT2
2

2.2U_0603_6.3V6K

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

DDR_B_D14
DDR_B_D15

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D21
DDR_B_D16
PM_EXTTS#1 <7>

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA14

DDR_B_MA14 <8>

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2
DDR_B_MA13

M_ODT2

<7>

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R33
1

SO-DIMM B
REVERSE

+3VS

10K_0402_5%
A

Bottom side

DDR_B_BS#2
DDR_CKE2_DIMMB

Issued Date

2007/1/15

Deciphered Date

Compal Electronics, Inc.

2008/1/15

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

56_0404_4P2R_5%

M_CLK_DDR2
M_CLK_DDR#2

FOX_AS0A426-NARN-7F~N

C60

DDR_B_DM1

Compal Secret Data

Security Classification
1
2

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

R34

C61

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D12
DDR_B_D13

10K_0402_5%

RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5%

DDR_B_RAS#
DDR_B_MA7
1
4
4
1
DDR_CS2_DIMMB# 2
DDR_B_MA6
3
3
2

ICH_SM_DA
ICH_SM_CLK

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D6
DDR_B_D7

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_DM0

DDR_B_D8
DDR_B_D9

DDR_B_D5
DDR_B_D4

C222

DDR_B_D2
DDR_B_D3

Layout Note:
Place near JDIM2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C221

DDR_B_DQS#0
DDR_B_DQS0

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

<8> DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> DDR_B_DQS[0..7]

+V_DDR_MCH_REF <7,13>

JDIM1

DDR2 SO-DIMM II
Size Document Number
Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet
1

14

of

49

+3VS_CK505

FSA

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

REF
MHz

DOT_96 USB
MHz
MHz

266

100

33.3

14.318

96.0

48.0

133

100

33.3

14.318

96.0

48.0

200

100

33.3

14.318

96.0

48.0

166

100

33.3

14.318

96.0

48.0

333

100

33.3

14.318

96.0

+3VS

CLK_XTAL_OUT

R971
1
2
0_0805_5%

Routing the trace at least 10mil

100

100

33.3

14.318

96.0

48.0

400

100

33.3

14.318

96.0

48.0

C1189

C1190

C1191

C1192

C1193

C1194

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1195
0.1U_0402_16V4Z

14.31818MHZ_16P

0905 Connect to +VCCP

Y7
2

+1.05VS_CK505

+VCCP

Place close to U55

2
C1196
22P_0402_50V8J

48.0

CLK_XTAL_IN
R986

FSB

0_0402_5%
1
2

FSC
CLKSEL2

R972
1
2
0_0805_5%

2
C1197
22P_0402_50V8J
+1.05VS_CK505

0.1U_0402_16V4Z
1
C1198
C1199

2
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C1201
C1202
C1203

C1200

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

C1204

2
0.1U_0402_16V4Z

+3VS_CK505

Reserved

MEDIA_REQ#32
R1019 1
R1021 1

NB
R983
1
2
2.2K_0402_5%

CPU

<7>
<7>
<4>
<4>

R976
R978
R980
R982

CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK

1
1
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2
1
1

R_MCH_BCLK#
R_MCH_BCLK
R_CPU_BCLK#
R_CPU_BCLK

GND
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_IO
SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
VDD_SRC

U55

+3VS_CK505

C1209
2
22P_0402_50V8J

For SED TEST

<13,14,19> ICH_SM_DA
<13,14,19> ICH_SM_CLK

R1001
R1004
R1006
R1008

2 33_0402_1% FSC
PAD T120
ICH_SM_DA
ICH_SM_CLK

C1207

C1208

22P_0402_50V8J

1
1
1
1

22P_0402_50V8J

For SED TEST

C1206

CLK_DEBUG_PORT
CLK_PCI_EC
CLK_PCI_TPM
PCI_CLK
C1205

<23>
<27>
<28>
<17>

CPU_BSEL1

22P_0402_50V8J

1K_0402_1%
<5>

MCH_CLKSEL1 <7>

22P_0402_50V8J

2
2
2
2

FSC

C1251
2

R1013

MCH_CLKSEL2 <7>
<31> CLK_PCIE_VGA
CLK_PCIE_VGA#

VGA (Discrete)<31>

CPU_BSEL2

1
1
R51

<7> CLKREQ#_7

PCI2_TME
R_CLK_PCI_EC
27_SEL
ITP_EN

@
1
22P_0402_50V8J

R47

R1016
1
2
10K_0402_5%

1K_0402_1%
<5>

33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%

CKPWRGD/PD#
FS_B/TEST_MODE
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF_0/FS_C/TEST_
REF_1
SDA
SCL
NC
VDD_PCI
PCI_1
PCI_2
PCI_3
PCI_4/SEL_LCDCL
PCIF_5/ITP_EN
VSS_PCI

<19> CLK_48M_ICH
B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

CLK_XTAL_OUT
CLK_XTAL_IN

R991

<19> CLK_14M_ICH

SB, MINI PCI

@
1

VDD_48
USB_0/FS_A
USB_1/CLKREQ_A#
VSS_48
VDD_IO
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO
VDD_PLL3
LCDCLK/27M
LCDCLK#/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRC_2
SRC_2#
VSS_SRC
SRC_3
SRC_3#

CK_PWRGD
CPU_BSEL1

<19> CK_PWRGD

CPU_BSEL1

OZ888

EXPCARD_REQ#16 <26>
CLK_PCIE_EXPR <26> Express
CLK_PCIE_EXPR# <26>

Card

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

CPU_BSEL0

R39

2 0_0402_5%
2 0_0402_5%

MEDIA_REQ#32 <30>
CLK_PCIE_Media <30>CardBus
CLK_PCIE_Media# <30>

+3VS_CK505

MCH_CLKSEL0 <7>

1K_0402_1%
<5>

EXPCARD_REQ#16
R_PCIE_EXPR
R979 1
R_PCIE_EXPR#
R981 1

R1024
R1026

2
2

+3VS_CK505

2 33_0402_1%

FSA

2
475_0402_1%~D

R_CLKREQ#_7

1 0_0402_5%
1 0_0402_5%

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

FSA

R37

2 0_0402_5%
2 0_0402_5%

+1.05VS_CK505

+1.05VS_CK505

PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#

H_STP_PCI#
H_STP_CPU#

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

H_STP_PCI# <19>
H_STP_CPU# <19>

R_CLK_WWAN#
R_CLK_WWAN
WWAN_REQ#10
R_PCIE_SATA
R_PCIE_SATA#
R_CLKSATAREQ#
R_CLK_PCIE_LAN#
R_CLK_PCIE_LAN
GLAN_REQ#9

CPU_STP

R988 1
R989 1

2 0_0402_5%
2 0_0402_5%

R992
R994
R56
R996
R997

2 0_0402_5%
2 0_0402_5%
2475_0402_1%~D
2 0_0402_5%
2 0_0402_5%

1
1
1
1
1

WLAN_REQ#4
R_CLK_PCIE_MCARD# R1005 1
R_CLK_PCIE_MCARD
R1007 1

CLK_PCIE_WWAN# <23>
CLK_PCIE_WWAN <23> MiniCard_WWAN
WWAN_REQ#10 <23>
CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18> ICH_SATA
CLKSATAREQ# <19>
CLK_PCIE_LAN# <21>
GLAN
CLK_PCIE_LAN <21>
GLAN_REQ#9 <21>
WLAN_REQ#4 <23>
CLK_PCIE_MCARD# <23>
CLK_PCIE_MCARD <23>MiniCard_WLAN

2 0_0402_5%
2 0_0402_5%

S IC ICS9LPRS387AKLFT MLF 72P CLK GEN

R_PCIE_ICH#
R_PCIE_ICH

R1010 1
R1012 1

2
2

0_0402_5%
0_0402_5%

R_MCH_3GPLL#
R_MCH_3GPLL

R1015 1
R1018 1

2
2

0_0402_5%
0_0402_5%

CLK_PCIE_ICH# <19>
CLK_PCIE_ICH <19>

ICH

CLK_MCH_3GPLL# <7>
CLK_MCH_3GPLL <7>

NB_3GPLL

+1.05VS_CK505

R_MCH_DREFCLK
R_MCH_DREFCLK#

SSCDREFCLK#
SSCDREFCLK

R1067
R1195

1
1

2 33_0402_1%
2 33_0402_1%

CLK_NVSS_27M <31>
CLK_NV_27M <31> VGA_27M

(DIS)

+3VS

* 01

ITP_EN

= SRC8/SRC8#
= ITP/ITP#

0 = Enable DOT96 & SRC1(UMA)

= Enable SRC0 & 27MHz(DIS)

*1

= Overclocking of CPU and SRC NOT allowed

+3VS_CK505

+3VS_CK505

R1031
10K_0402_5%

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

R1030
10K_0402_5%

27_SEL

PCI2_TME

ITP_EN

EXPCARD_REQ#16 1
R90
WWAN_REQ#10
1
R89
CLKSATAREQ#
1
R88
GLAN_REQ#9
1
R87
WLAN_REQ#4
1
R85
CLKREQ#_7
1
R60
MEDIA_REQ#32
1
R80

= Overclocking of CPU and SRC Allowed

PCI2_TME

* 10

27_SEL

2006/02/13

Issued Date

2
5

Compal Secret Data

Security Classification

R1032
10K_0402_5%

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.

Clock Generator CK505

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

15

of

49

+CRT_VCC +CRT_VCC

C48

C49
2

4.7P_0402_50V8C

L11
2
0.1U_0402_16V4Z

2
R62

L13

P
OE#

VGA_HSYNC

<31> VGA_HSYNC

HSYNC_L

+CRT_VCC

P
OE#

C144
2

C54

U63
74AHCT1G125GW_SOT353-5

<31>

VGA_DDCCLK

<31>

Q5
SSM3K7002FU_SC70-3

16
17

SUYIN_070549FR015S208CR
CONN@
VGA_DDC_DATA_C
1

@2

VGA_DDC_CLK_C

@
C140

D_CRT_VSYNC

VGA_VSYNC

<31> VGA_VSYNC

5
1

2
0.1U_0402_16V4Z

C53

1
C55

1
C115

U62
74AHCT1G125GW_SOT353-5

VSYNC_L

1
2
0_0603_5%

D_CRT_HSYNC

C51

4.7P_0402_50V8C

1
2
0_0603_5%

1
10K_0402_5%

5
1

C52

4.7P_0402_50V8C

+CRT_VCC

DDC_MD2

1
C50

VGA_DDCDATA

100P_0402_50V8J

For EMI
2

100P_0402_50V8J

@
C47

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

100P_0402_50V8J

100P_0402_50V8J

@
C46

15P_0402_50V8J

22P_0402_50V8J

@
C45

22P_0402_50V8J

R64
150_0402_1%
2
1
R65
150_0402_1%
2
1
R63
150_0402_1%
2
1

22P_0402_50V8J

VGA_CRT_B

<31> VGA_CRT_B

15P_0402_50V8J

VGA_CRT_G

<31> VGA_CRT_G

1
2 CRT_R_L
L8
BK1608LL121-T 0603
1
2 CRT_G_L
L10
BK1608LL121-T 0603
1
2 CRT_B_L
L14
1 BK1608LL121-T 0603

Q3
1
3
SSM3K7002FU_SC70-3

VGA_DDC_CLK_C
JCRT1

VGA_CRT_R

<31> VGA_CRT_R

1
2.2K_0402_5%

VGA_DDC_DATA_C
@

R103

2
G

MSEN#

MSEN#

+3VS

1
2.2K_0402_5%

R77

2
G

C43
0.1U_0402_16V4Z

R6

R7

W=40mils

RB411DT146 SOT23
1

+3VS

1
2K_0402_5%

0_1210_5%~D
@

2
D14

2+5VS_CRTVCC 2

R140

+5VS

1
2K_0402_5%

For NVidia

+3VS

+CRT_VCC

W=40mils

C44

+5VS

0.1U_0402_16V4Z

CRT

<27>

D11
D18
D20
DAN217_SC59-3 DAN217_SC59-3 DAN217_SC59-3

+3VS
1

LCD

R21

W=60mils

R75
47K_0402_5%

2
2
R68

1
1K_0402_5%

1
3

1
2 R662
1
0_0402_5%

+LCDVDD
C174

4.7U_0805_10V4Z
2

3
INVT_PWM

+LCDVDD
+3VS
<31> VGA_CLK_LCD
<31> VGA_LVDSA0-

0.1U_0402_16V4Z
2

VGA_CLK_LCD
VGA_LVDSA0-

<31> VGA_LVDSA1+
<31> VGA_LVDSA2-

VGA_LVDSA1+
VGA_LVDSA2-

<31> VGA_LVDSAC+
<31> VGA_LVDSB0-

VGA_LVDSAC+
VGA_LVDSB0-

<31> VGA_LVDSB1+
<31> VGA_LVDSB2-

VGA_LVDSB1+
VGA_LVDSB2-

<31> VGA_LVDSBC+

VGA_LVDSBC+
EC_SMB_CK2_R
+B+
INVT_PWM
DAC_BRIG

INVT_PWM
DAC_BRIG

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

ACES_88242-4001

C6
100P_0402_25V8K

C17

C4
100P_0402_25V8K

100P_0402_25V8K C14

C3
100P_0402_25V8K

100P_0402_25V8K

PJSOT24C_SOT23-3
@

<4,27,31>
<4,27,31>

EC_SMB_CK2

EC_SMB_DA2

1
@ R19
1
@ R12

LCD_CBL_DET#
LCD_TST
VGA_DAT_LCD
VGA_LVDSA0+
VGA_LVDSA1-

L42

L43

MBK1608221YZF_0603
2
MIC_SIG
R81
MBK1608221YZF_0603
2
MIC_CLK1
2
MIC_DIAG0_0603_5%

+LCDVDD
LCD_CBL_DET# <27>
LCD_TST <27>
VGA_DAT_LCD <31>
VGA_LVDSA0+ <31>
VGA_LVDSA1- <31>

VGA_LVDSA2+
VGA_LVDSAC-

VGA_LVDSA2+
VGA_LVDSAC-

VGA_LVDSB0+
VGA_LVDSB1-

VGA_LVDSB0+ <31>
VGA_LVDSB1- <31>

VGA_LVDSB2+
VGA_LVDSBC-

VGA_LVDSB2+
VGA_LVDSBC-

Issued Date

<31>
<31>

<31>
<31>

EC_SMB_DA2_R
+B+

DISPOFF#

C32

EC_SMB_CK2_R
2
0_0402_5%
EC_SMB_DA2_R
2
0_0402_5%

2
C34

0.1U_0603_50V4Z
4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EMI

MIC_SIG

1
2
3
4
5
6
7
8
9
10
GND
GND

CAMERA

ESD

USB20_N1

<24> MIC_CLK
<27> MIC_DIAG

JLVDS1

<27>
<27>

<19>
<24>

1
2
3
4
5
6
7
8
9
10
11
12

ACES_88460-1001

C41

LCD_TST
LCD_CBL_DET#
INVT_PWM
DAC_BRIG
DISPOFF#

D60
1

USB20_P1

+3VS

@
C38
1
2
0.1U_0402_16V4Z

0.047U_0402_16V7K

R15
10K_0402_5%
2

LCD_VCC_TEST_EN

2
G

<19>

<27> LCD_VCC_TEST_EN

JCA1
DISPOFF#

R652
2.2K_0402_5%

W=60mils

C173

4.7K_0402_5%

+LCDVDD

7.3

SSM3K7002FU_SC70-3
D

D8
<31> VGA_LVDDEN

Q9

D26
CH751H-40_SC76
1
2
D25
CH751H-40_SC76
1
2

+5VS

SI2301BDS-T1-E3 1P SOT23
Q6

VGA_LVDDEN
2
CH751H-40PT_SOD323-2

G7X_ENBKL

<27,31> G7X_ENBKL
3

100_0603_1%

R67
1 1

2
G

BKOFF#

BKOFF#

D
Q7
SSM3K7002FU_SC70-3

<27>

+3VS

+5VALW

0.1U_0603_50V4Z

+LCDVDD

Title

CRT CONN/LCD CONN

Size Document Number
Custom LA-4595P
Date:

Rev
1.0
Sheet

Tuesday, February 17, 2009

E

16

of

49

+3VS

R1035 1

2 8.2K_0402_5%

PCI_DEVSEL#

R1036 1

2 8.2K_0402_5%

PCI_STOP#

R1037 1

2 8.2K_0402_5%

PCI_TRDY#

R1038 1

2 8.2K_0402_5%

PCI_FRAME#

R1039 1

2 8.2K_0402_5%

PCI_PLOCK#

R1040 1

2 8.2K_0402_5%

PCI_IRDY#

R1041 1

2 8.2K_0402_5%

PCI_SERR#

R1042 1

2 8.2K_0402_5%

PCI_PERR#

U56B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

+3VS

R1043 1

2 8.2K_0402_5%

PCI_PIRQA#

R1044 1

2 8.2K_0402_5%

PCI_PIRQB#

R1045 1

2 8.2K_0402_5%

PCI_PIRQC#

R1046 1

2 8.2K_0402_5%

PCI_PIRQD#

R1047 1

2 8.2K_0402_5%

PCI_PIRQE#

R1048 1

2 8.2K_0402_5%

PCI_PIRQF#

R1049 1

2 8.2K_0402_5%

PCI_PIRQG#

R1050 2

1 8.2K_0402_5%

PCI_PIRQH#

R1051 1

2 8.2K_0402_5%

PCI_REQ0#

R1052 1

2 8.2K_0402_5%

PCI_REQ1#

R1053 1

2 8.2K_0402_5%

PCI_REQ2#

R1054 1

2 8.2K_0402_5%

PCI_REQ3#

2 10K_0402_5%

PME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

J5
E1
J6
C4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ3#
PCI_GNT3#

D8
B4
D6
A5
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PCI_IRDY#

PLTRST#
PCICLK
PME#

C14
D4
R2

PCI_PLTRST#
PCI_CLK
PME#

H4
K6
F2
G2

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_REQ2#

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#

F1
G4
B6
A7
F13
F12
E6
F6

PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_CLK

<15>

ICH9M REV 1.0

C2
2
@
R20 1

1
R10

2
@

PCI_CLK
33_0402_5%

+3VALW

22P_0402_50V8J
1
C78
0.1U_0402_16V4Z

B
A

A16 swap override Strap

Low= A16 swap override Enble
PCI_GNT3# High= Default*

@R1055
@R1055
1

PCI_RST#

PCI_RST# <21,23,26,28>

MC74VHC1G08DFT2G SC70 5P

R1094
0_0402_5%
1

Boot BIOS Strap

B

PCI_GNT0#

PCI_GNT3#

@ U61
Y

PCI_PCIRST#

2
1K_0402_5%

SPI_CS#1

Boot BIOS Location

SPI

PCI

LPC

+3VALW
1
C57
0.1U_0402_16V4Z

PCI_GNT0#

@ R1058
1
@ R1060
1

2
1K_0402_5%

2
1K_0402_5%

@ U58
Y

<19> SPI_CS1#_R

SPI_CS1#_R

PCI_PLTRST#
+3VALW

PLT_RST#

PLT_RST# <7,27,30,31>

MC74VHC1G08DFT2G SC70 5P

R1061
0_0402_5%
1

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

17

of

49

+RTCVCC
+3VS
1

2
1M_0402_5%

R1062

SM_INTRUDER#
GATEA20

R1063
1
2
10K_0402_5%

KB_RST#

R1066
1
2
10K_0402_5%

LAN100_SLP_INTVRMEN
332K_0402_1%~D

R1064

+RTCVCC

R1069
1

2 R984
1
0_0402_5%

ICH_RTCX2

C1211
12P_0402_50V8J

C1212
12P_0402_50V8J

+1.5VS

LAN_RXD0
LAN_RXD1
LAN_RXD2

D13
D12
E13

LAN_TXD0
LAN_TXD1
LAN_TXD2

B10

R1073

1
IN

OUT

R1074
R1076

33_0402_5%
33_0402_5%

1
1

R1077

33_0402_5%

GLAN_COMP

R1079

<24> ACZ_SDOUT
+3VS

1
R1080

2
10K_0402_5%

2
2

AF6
AH4

HDARST#

AE7

ADC_ACZ_SDIN0

AF4
AG4
AH3
AE5

C1321 15P_0402_50V8J @
ACZ_BITCLK
1
2
C1307 15P_0402_50V8J @
ACZ_SDOUT
1
2

ODD

<22>
<22>
<22>
<22>
<22>
<22>
<22>
<22>

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0
PSATA_ITX_DRX_P0
ODD_IRX_DTX_N0_C
ODD_IRX_DTX_P0_C
ODD_ITX_DRX_N0
ODD_ITX_DRX_P0

HDA_SDOUT

AG5
AG7
AE8

PAD T123
PAD T124
SATA_LED#

<28> SATA_LED#

HDD

33_0402_5%

B28
B27

HDA_BITCLK
HDA_SYNC

<24> ADC_ACZ_SDIN0

32.768KHZ_12.5P_1TJS125BJ2A251

NC

NC

<24> ACZ_RST#

<24> ACZ_BITCLK
<24> ACZ_SYNC
Y8

24.9_0402_1% 1

AG8

AJ16
0.01U_0402_50V7K
AH16
PSATA_ITX_DRX_N0C1213 1
PSATA_ITX_DRX_N0_C AF17
2
PSATA_ITX_DRX_P0C1214 1
PSATA_ITX_DRX_P0_C AG17
2
0.01U_0402_50V7K
0.01U_0402_50V7K
ODD_ITX_DRX_N0 C1215 1
2 ODD_ITX_DRX_N0_C
ODD_ITX_DRX_P0
1
2 ODD_ITX_DRX_P0_C
C1216
0.01U_0402_50V7K

AH13
AJ13
AG14
AF14

LPC_FRAME#

J3
J1

LPC_DRQ0#

N7
AJ27

GATEA20
H_A20M#

AJ25
AE23

H_DPRSTP#
H_DPSLP#

FERR#

AJ26

R_H_FERR#

CPUPWRGD

AD22

H_PWRGOOD

A20GATE
A20M#

LAN_RSTSYNC

F14
G13
D14

10M_0402_5%
1

GLAN_CLK

K3

LDRQ0#
LDRQ1#/GPIO23

GPIO56
GLAN_COMPI
GLAN_COMPO
HDA_BIT_CLK
HDA_SYNC

DPRSTP#
DPSLP#

AF25

H_IGNNE#

AE22
AG25
L3

H_INIT#
H_INTR
KB_RST#

NMI
SMI#

AF23
AF24

H_NMI
H_SMI#

IGNNE#
INIT#
INTR
RCIN#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

R1072

+VCCP
C

H_NMI <4>
H_SMI# <4>

H_STPCLK#
THRMTRIP_ICH#

TP12

AG27

SATARBIAS#
SATARBIAS

H_FERR# <4>

H_PWRGOOD <5>

H_INIT# <4>
H_INTR <4>
KB_RST# <27>

AG26

SATA_CLKN
SATA_CLKP

H_FERR#
2
56_0402_5%

H_IGNNE# <4>

AH27

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATALED#

R1070
56_0402_5%
H_DPRSTP# <5,7,47>
H_DPSLP# <5>

STPCLK#

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

+VCCP

GATEA20 <27>
H_A20M# <4>

THRMTRIP#

HDA_RST#

LPC_FRAME# <23,27,28>
T121 PAD
T122 PAD

E25
C13

FWH4/LFRAME#

Need to place JMINI1

ICH_RTCX1

INTVRMEN
LAN100_SLP

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LAN100_SLP_INTVRMEN B22
LAN100_SLP_INTVRMEN A22

RTCRST#
SRTCRST#
INTRUDER#

RTC
LPC

A25
F20
C22

K5
K4
L6
K2

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

R1075
56_0402_5%

H_STPCLK# <4>
R1078

2 54.9_0402_1%

JOPEN1
@

ICH_RTCRST#
SRTCRST#
SM_INTRUDER#

RTCX1
RTCX2

LAN / GLAN
CPU

JOPEN2
@
1U_0603_10V4Z

C1210

C23
C24

IHDA

ICH_RTCX1
ICH_RTCX2

SATA

1U_0603_10V4Z

C1220

R1109

LPC_AD[0..3] <23,27,28>

U56A

2
20K_0402_5%
2
20K_0402_5%

1
R1068

H_THERMTRIP# <4,7>

T52 PAD

AH11
AJ11
AG12
AF12
AH9
AJ9
AE10
AF10
AH18
AJ18
AJ7
AH7

CLK_PCIE_SATA#
CLK_PCIE_SATA
R1081

CLK_PCIE_SATA# <15>
CLK_PCIE_SATA <15>
2

24.9_0402_1%

Within 500 mils

ICH9M REV 1.0

For EMI TEST

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

@ R1082
1

@ R1083
1

ACZ_SDOUT

2
1K_0402_5%

ICH_RSVD
2
1K_0402_5%

ICH_RSVD <19>

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

18

of

49

2 2.2K_0402_5%
2 2.2K_0402_5%

T125

<4> XDP_DBRESET#

@
<7> PM_BMBUSY#
<27> EC_LID_OUT#

ICH_PCIE_WAKE# 1 R658

<21,23,26,27> ICH_PCIE_WAKE#

High -->No boot

<27,28> SERIRQ
<27> EC_THERM#
1
R1099
2
PAD T128
100K_0402_5%

<7,27,47> VGATE
+3VS

R1101
@

1
2
10K_0402_5%

GPIO49

1
R1102
@

<27>
<27>

M6

EC_LID_OUT#

A17

H_STP_PCI#
R_STP_CPU#

A14
E19

2 VRMPWRGD
0_0402_5%

EC_SMI#
EC_SCI#

EC_SMI#
EC_SCI#
PAD T130

PAD T131
PAD T132
<15> CLKSATAREQ#

CLKSATAREQ#

GPIO49
R1108
R1110
R1111
R1113
R1114
R1115
R1116
R1117
R1119

1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%

CL_RST#1
ICH_LOW_BAT#

<24>

<7> MCH_ICH_SYNC#
<18> ICH_RSVD
PAD T133
PAD T134
PAD T135

ICH_RI#
XDP_DBRESET#

R113
1
R114
1
R125
USB_OC#2_#8 1
R129
USB_OC#4
1
R130
USB_OC#7
1
R132
USB_OC#9
1
R134
USB_OC#0
1
R135
USB_OC#3
1
R136
USB_OC#5
1
R137
USB_OC#10
1
R138
USB_OC#11
1
USB_OC#1

SMBALERT#/GPIO11
STP_PCI#
STP_CPU#
CLKRUN#
WAKE#
SERIRQ
THRM#
VRMPWRGD
TP11

AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8

GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

M7
AJ24
B21
AH20
AJ20
AJ21

SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

CLK_14M_ICH
CLK_48M_ICH

P1

ICH_SUSCLK

C16
E16
G17

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

C10

PWROK

G20

DPRSLPVR/GPIO16
BATLOW#
PWRBTN#

ICH_LOW_BAT#

R3

PBTN_OUT#

R_EC_RSMRST# 1

R5

CK_PWRGD_R

R6

M_PWROK

2 10K_0402_5%
R1105 1

B16

CL_DATA0
CL_DATA1

F22
C19

CL_DATA0

C25
A19

CL_VREF0_ICH

F21
D18

CL_RST#

CK_PWRGD <15>

+3VS

T129 PAD
CL_CLK0

A16
C18
C11
C20

2 0_0402_5%

M_PWROK <7>

F24
B19

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

CL_CLK0

<7>

CL_DATA0 <7>

C1219

2
CL_RST#

0_0402_5%

0.1U_0402_16V4Z

R1106
2
3.24K_0402_1%

R1107
453_0402_1%
NA lead free
C

<7>

ACIN
<27,39,40>
LAN_CABDT <21>

LAN_CABDT
R657

RSMRST circuit
U56D

ME_EC_DATA1

N29
N28
P27
P26

EC_LID_OUT#
EC_SMI#

10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2

<21> GLAN_RXN
<21> GLAN_RXP
<21> GLAN_TXN
<21> GLAN_TXP

Express Card

+3VALW

Card Reader
WWAN

0.1U_0402_16V7K~N2
0.1U_0402_16V7K~N2

GLAN_RXN
GLAN_RXP
1 C1221GLAN_TXN_C
1 C1222GLAN_TXP_C

L29
L28
M27
M26

0.1U_0402_16V7K~N2
0.1U_0402_16V7K~N2

PCIE_RXN3
PCIE_RXP3
1 C1223PCIE_C_TXN3
1 C1224PCIE_C_TXP3

J29
J28
K27
K26

PERN3
PERP3
PETN3
PETP3

<26>
<26>
<26>
<26>

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

0.1U_0402_16V7K~N2
0.1U_0402_16V7K~N2

PCIE_RXN4
PCIE_RXP4
1 C1225PCIE_C_TXN4
1 C1226PCIE_C_TXP4

G29
G28
H27
H26

PERN4
PERP4
PETN4
PETP4

<30>
<30>
<30>
<30>

PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5

0.1U_0402_16V7K~N2
0.1U_0402_16V7K~N2

1 C1228
1 C1227

E29
E28
F27
F26

<23>
<23>
<23>
<23>

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

0.1U_0402_16V7K~N2
0.1U_0402_16V7K~N2

PCIE_RXN1
PCIE_RXP1
1 C1309PCIE_C_TXN1
1 C1308PCIE_C_TXP1

C29
C28
D27
D26

SPI_CS1#_R

D23
D24
F23
D25
E23

<29> USB_OC#2_#8

2.2K_0402_5% R1123

<27>

Q106
SSM3K7002FU_SC70-3
ICH_SMBDATA
1
D

1ICH_SMBCLK

USBRBIAS
ICH_SMBDATA <26>

+3VS

AG2
AG1

Within 500 mils

Y27
Y26
W29
W28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

DMI_MTX_IRX_N1 <7>
DMI_MTX_IRX_P1 <7>
DMI_MRX_ITX_N1 <7>
DMI_MRX_ITX_P1 <7>

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

DMI_MTX_IRX_N2 <7>
DMI_MTX_IRX_P2 <7>
DMI_MRX_ITX_N2 <7>
DMI_MRX_ITX_P2 <7>

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

DMI_MTX_IRX_N3 <7>
DMI_MTX_IRX_P3 <7>
DMI_MRX_ITX_N3 <7>
DMI_MRX_ITX_P3 <7>

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

PERN5
PERP5
PETN5
PETP5

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#

USB

AF29
AF28
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

DMI_IRCOMP

DMI_MTX_IRX_N0 <7>
DMI_MTX_IRX_P0 <7>
DMI_MRX_ITX_N0 <7>
DMI_MRX_ITX_P0 <7>

@
1

R656
0_0402_5%
2

POK

<41>

R_EC_RSMRST#
<27> EC_RSMRST#

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
R1120
1

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

24.9_0402_1%
2

Within 500 mils

+1.5VS

USB20_N0 <29>
USB20_P0 <29>JUSBP1
USB20_N1 <16>
USB20_P1 <16>Camera
USB20_N2 <29>
USB20_P2 <29>JUSBP3
USB20_N3 <29>
USB20_P3 <29>Felica
USB20_N4 <29>
USB20_P4 <29>BlueTooth
USB20_N5 <29>
USB20_P5 <29>FingerPrinter
USB20_N6 <23>
USB20_P6 <23>Mini Card
USB20_N7 <26>
USB20_P7 <26>Express Card
USB20_N8 <29>
USB20_P8 <29>JUSBP3
USB20_N9 <29>
USB20_P9 <29>JUSBP4
USB20_N10 <23>
Mini Card2
USB20_P10 <23>
A

ICH9M REV 1.0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

R1103
0_0402_5%
2

Q107
SSM3K7002FU_SC70-3

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

R1125
22.6_0402_1%

ICH_SMBCLK <26>

<13,14,15> ICH_SM_CLK

<29> USB_OC#9

2.2K_0402_5%
R1124

<13,14,15> ICH_SM_DA

EC_SWI#

+3VS

USB_OC#0
USB_OC#1
USB_OC#2_#8
USB_OC#3
USB_OC#4
USB_OC#5
EC_SWI#
USB_OC#7
USB_OC#2_#8
USB_OC#9
USB_OC#10
USB_OC#11

V27
V26
U29
U28

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

PERN2
PERP2
PETN2
PETP2

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

<17> SPI_CS1#_R

PERN1
PERP1
PETN1
PETP1

<23>
<23>
<23>
<23>

<29> USB_OC#0

4.7P_0402_50V8C

R1104

CL_CLK0
CL_CLK1

CL_RST0#
CL_RST1#

PBTN_OUT# <27>

D22

CL_VREF0
CL_VREF1

4.7P_0402_50V8C

ICH_PWROK <7,27>
1
2
R1097
10K_0402_5%

DPRSLPVR <7,47>

RSMRST#

SLP_M#

1 @
C1218

R695 100_0402_5%
M_PWROK
1
2

T127 PAD
ICH_PWROK

D20

CLPWROK

<27>
<27>
<27>

@
R1092
10_0402_5%

1 @
C1217

SLP_S3#
SLP_S4#
SLP_S5#

B13

@
R1091
10_0402_5%

T126 PAD

M2

CLK_14M_ICH

+3VS

CLK_14M_ICH <15>
CLK_48M_ICH <15>

LAN_RST#

CK_PWRGD

1
2
8.2K_0402_5%

H1
AF3

R1089

GPIO21
GPIO19
GPIO36
GPIO37

ICH9M REV 1.0

WLAN
EC_SWI#

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

AH23
AF19
AE21
AD20

ME_EC_CLK1

GLAN

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

SB_SPKR

ICH_PCIE_WAKE#_R

CLK14
CLK48

PMSYNC#/GPIO0

A20

T53

+3VALW

SUS_STAT#/LPCPD#
SYS_RESET#

D21

OCP#
LAN_LOPWEN

<4>
OCP#
<21> LAN_LOPWEN

checklist pull hi

PM_BMBUSY#

RI#

PCI_CLKRUN#
L4
0_0402_5%
2 @ ICH_PCIE_WAKE#_R E20
SERIRQ
M5
EC_THERM#
AJ23

<27,28> PCI_CLKRUN#

low-->default

R4
G19

PCI-Express

1
R1096

+3VS

<15> H_STP_PCI#
<15> H_STP_CPU#

2 SB_SPKR
@ 10K_0402_5%

F19

SUS_STAT#
XDP_DBRESET#

Direct Media Interface

ICH_RI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

PAD

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

SPI

R1095

EC_SCI#

G16
A13
E17
C17
B18

ICH_SMBCLK
ICH_SMBDATA
CL_RST#1
ME_EC_CLK1
ME_EC_DATA1

<26> ICH_SMBCLK
<26> ICH_SMBDATA

OCP#

SATA
GPIO

EC_THERM#

Place closely pin H1

CLK_48M_ICH

U56C

R1085 1
R1087 1

+3VALW

PCI_CLKRUN#

1
2 LAN_CABDT
R310 10K_0402_5%
1
2
8.2K_0402_5%

Place closely pin AF3

SMB

R1090

Clocks

@R1088
@
R1088

SYS GPIO
Power MGT

R1086

SERIRQ

MISC
GPIO
Controller Link

R1084

1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%

+3VS

Title

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

19

of

49

+RTCVCC

1
C1236

C1237

2.2U_0603_6.3V4Z

22U_0805_6.3V6M~D

R1127
100_0402_5%~D

D45

CH751H-40PT_SOD323-2
+ICH_V5REF_RUN

20 mils

10U_0805_10V4Z

C1254

1U_0603_10V4Z

C1255

+1.5VS

1U_0603_10V4Z

VCC1_5_A[9]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC21
C1262

0.1U_0402_16V4Z

+1.5VS
C1263

G10
G9

AC12
AC13
AC14

11mA

AJ5

11mA

+VCCGLANPLL

80mA
1

C1269

2.2U_0603_6.3V4Z

1
2
L100
1UH_20%_0805~D

10U_0805_10V4Z

0.1U_0402_16V4Z

2
0_0603_5%

23mA
+1.5VS

+1.5VS
1

C1270

1
C1271

1mA
2

+3VS

A12
B12
A27
D28
D29
E26
E27

VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

VCCCL1_05
VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]

11mA

0.1U_0402_16V4Z
1
C1252
+3VALW

1
T140
T141

C1253

+3VS

2
T142

+VCCSUS1_5_ICH_2

+3VALW
2

T143
C1257
0.1U_0402_16V4Z

212mA
+3VALW

G22

+VCCCL1_05_ICH

G23

+VCCCL1_5_ICH

T144
C1264

19/73/73mA
A24
B24

+3VS

2
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

0.1U_0402_16V4Z

GLAN POWER

1
R1129

A10
A11

VCCUSBPLL

AF1

(DMI)

VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

0.1U_0402_16V4Z

C1266 0.1U_0402_16V4Z~D

C1268

VCC_LAN1_05_INT_ICH_1
1
2
C1267
0.1U_0402_16V4Z~D
+VCCLAN3_3
19/78/78mA

VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]

C1265 1U_0603_10V4Z

+3VS

AA7
AB6
AB7
AC6
AC7

VCC1_5_A[21]
VCC1_5_A[22]

USB CORE

0.1U_0402_16V4Z

VCC1_5_A[20]

11mA

A18
D16
D17
E22

VCCSUS3_3[5]

C1261
0.022U_0402_16V7K~D

+1.5VS

VCC1_5_A[18]
VCC1_5_A[19]

+3VS

AD8 +VCCSUS1_5_ICH_1
F18

+3VS
1

+3VS

308mA

AJ4

AC8
F17

+3VS

C1260
0.022U_0402_16V7K~D

AC18
AC19

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]

0.1U_0402_16V4Z 1

C1259
0.1U_0402_16V4Z~D

1342mA

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

VCCSUS1_5[1]
VCCSUS1_5[2]

ATX

C1258

VCCSUS1_05[1]
VCCSUS1_05[2]

0.1U_0402_16V4Z
0.1U_0402_16V4Z 1

B9
F9
G3
G6
J2
J7
K7

AJ3

+VCCP

C1244

VCCSUSHDA

AD19
AF20
AG24
AC20

C1240

C1243

1U_0603_10V4Z

VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCHDA

VCCSATAPLL
VCC1_5_A[1]
VCC1_5_A[2]
VCC1_5_A[3]
VCC1_5_A[4]
VCC1_5_A[5]
VCC1_5_A[6]
VCC1_5_A[7]
VCC1_5_A[8]

AC10

+VCC_DMI

5ohm@100MHz
1
2
+VCCP
L98
BLM18PG181SN1_0603~D

0.1U_0402_16V4Z

C1256

VCC3_3[7]

C1242

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

+1.5VS

2mA

AJ6

+1.5VS

C1239
10U_0805_10V4Z

C1250

AJ19

ARX

47mA
+VCCSATAPLL

AG29

VCC3_3[2]

C1238

0.1U_0402_16V4Z

L99
10UH_LB2012T100MR_20%_0805~D
1
2

VCC3_3[1]

C1249

+1.5VS

C1306
1U_0603_10V6K~D

V_CPU_IO[1]
V_CPU_IO[2]

48mA

0.1U_0402_16V4Z

23mA

C1248

W23
Y23
AB23
AC23

0.1U_0402_16V4Z

20 mils

L97
BLM18PG181SN1_0603~D
1
2

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]

0.1U_0402_16V4Z

+ICH_V5REF_SUS

R29 +VCCDMIPLL

C1246

CH751H-40PT_SOD323-2

VCCDMIPLL

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]
VSS_NCTF[9]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH9M REV 1.0

A

A26

VCCGLAN3_3
2
ICH9M REV 1.0
4.7U_0603_6.3V6M~D

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
C1232
C1233

C1245

R1128
100_0402_5%~D
C

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C1247

D46

VCCA3GP

+5VALW +3VALW

VCC1_5_B[1]
VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]
VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

4.7U_0603_6.3V6M

C1241
1U_0603_10V6K~D

V5REF_SUS

CORE

22U_0805_6.3V6M~D646mA

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

V5REF

VCCP_CORE

2mA AE1

VCCRTC

PCI

+VCC1_5_B
1
1
+ C1235

+ICH_V5REF_SUS

A6

VCCPSUS

2mA

VCCPUSB

+3VS

1634mA

U56F
A23

+ICH_V5REF_RUN

22U_0805_6.3VAM

C1234
220U_D2_4VM

+5VS

C1230
0.1U_0402_16V4Z

C1229
0.1U_0402_16V4Z

40 mils

1
2
+1.5VS
BLM21PG600SN1D_0805~D

C1231
1U_0603_10V4Z~D

L96

U56E

0.01U_0402_16V7K

G3: 6uA

20 mils
1

+VCCP

Title

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

Size Document Number

Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

20

of

49

W=60mils

W=60mils

+3VALW

+LAN_IO

Q58
SSM3K7002FU_SC70-3

These caps close to U64: Pin 30, 36,13,10,39

These caps close to U64: Pin 29, 37, 44, 45

R1240
1.5M_0402_5%

0.1U_0402_10V7K~N C1467

0.1U_0402_10V7K~N C1466

C1462

0.1U_0402_10V7K~N C1465

C1461

+LAN_DVDD12

2
R1238
0_0603_5%

0.1U_0402_10V7K~N C1464

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

C1460

0.1U_0402_10V7K~N

C1459

0.1U_0402_10V7K~N

C1458

0.1U_0402_10V7K~N

S
1

EN_WOL
D

2
G

<27> EN_WOL#

C1457

R1239
470K_0402_5%

22U_1206_6.3V6M

+B+_BIAS

22U_1206_6.3V6M

S
4 +LAN_IO_R 2
1
L109
1
C1456
0_1210_5%~D
SI3456BDV-T1-E3 1N TSOP6
@

+LAN_VDD

1.5A

6
5
2
1

0.1U_0402_10V7K~N C1463

Q128

C1455
1U_0603_10V6K

+LAN_IO

+LAN_IO

These caps close to U64: Pin 4

+LAN_DVDD12

U64

GLAN_TXN

<19> GLAN_TXN

16

<15> CLK_PCIE_LAN
<15> CLK_PCIE_LAN#
<15> GLAN_REQ#9
PCI_RST#

<17,23,26,28> PCI_RST#

R1245
<19,23,26,27> ICH_PCIE_WAKE#
1
2
1K_0402_5%

2
2.49K_0402_1%

<19> LAN_LOPWEN

26
28

MDIP0
MDIN0
MDIP1
MDIN1
MDI P2
MDI N2
MDI P3
MDI N3

PERSTB
RSET

FB12

LANWAKEB
ISOLATEB

SROUT12
EVDD12
DVDD12
DVDD12
DVDD12
AVDD12

CKTAL1
CKTAL2

AVDD12

2
2

25MHZ_20P_1BX25000CK1A

7
14
31
47

C1489
27P_0402_50V8J

C1488
27P_0402_50V8J

CLKREQB

23
24

R1253
0_0402_5%
<19> LAN_CABDT

Y9
2

RTL8111DL

25

41
42
R1246
15K_0402_5%

LED0
HSIN
REFCLK_P
REFCLK_M

46

ISOLATEB

HSIP

17
18

27

+3VS

1
R1244

HSON

22

NC
NC

VDDSR
VDDSR

GND
GND
GND
GND

VDD33
VDD33
AVDD33
AVDD33
ENSR

EGND

33
34
35
32

LAN_LED3
LAN_LED2
LAN_LED1

38

LAN_LED0

2
3
5
6
8
9
11
12

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

3.6K_0402_5%
2

+LAN_VDD

W=60mils
L107
1

48

+LAN_SROUT12

19
30
36
13
10

+LAN_EVDD12

( Should be place within 200 mils )

2

W=60mils

+LAN_DVDD12

C1479

These components close to U64: Pin 48

( Should be place within 200 mils )
L110
0_0603_5%
2
1

W=30mils
1
C1484
1
C1485

W=30mils
+LAN_VDD

2
1U_0402_6.3V6K~D
2
1U_0402_6.3V6K~D

These caps close to U64: Pin 19

+LAN_IO

29
37
1
40
43

0_0603_5%
2

+LAN_AVDD33
1
C1486
1
C1487
1
C1477
1
C1480

+LAN_IO

RTL8111DL-GR_LQFP48

These caps close to U64: Pin 44,45

39
44
45

L108
1

+LAN_IO

2
JLAN1

2
0.1U_0402_16V7K~N
2
0.1U_0402_16V7K~N
2
0.1U_0402_10V7K~N
2
0.1U_0402_10V7K~N

LAN_LED0

R1247
1

220_0402_5%
2 LAN_ACTIVITY#

13

Yellow LED-

12

+LAN_IO

These caps close to U64: Pin 1,29,37,40

RJ45_TX3-

RJ45_TX3+

RJ45_RX1-

RJ45_TX2-

RJ45_TX2+

RJ45_RX1+

RJ45_TX0-

PR1-

RJ45_TX0+

PR1+

PR4PR4+
PR2PR3PR3+

7
8
9

+V_DAC
LAN_MDIN0
LAN_MDIP0

2 0.01U_0402_16V7K

MCT2
MX2+
MX2-

RJ45_TX2RJ45_TX2+

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_RX1RJ45_RX1+

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

CH751H-40PT_SOD323-2
D55
LAN_LED3 1

RP42

LED2_LED3 1 R1251 2 LINK_10_1000#

220_0402_5%
LED1_LED3 1 R1252 2 LINK_100_1000#
220_0402_5%

CH751H-40PT_SOD323-2
2

C1493
1000P_1206_2KV7K
LAN_LED1 1

D57
LAN_LED3 1

CH751H-40PT_SOD323-2
BOTH_GST5009-LF
CM1293-04SO_SOT23-6
RJ45_TX0-

RJ45_TX0+

CH1

Vn

CH2

@ D28

CM1293-04SO_SOT23-6

CH4

Vp

CH3

RJ45_RX1-

RJ45_TX2-

+3VS

RJ45_RX1+

RJ45_TX2+

CH1

Vn

CH2

@ D29
5

CH4

Vp

CH3

RJ45_TX3-

+3VS

RJ45_TX3+

2008/03/21

2009/03/21

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

15

GND

14

Green LED-

Orange LEDGreen-Orange LED+

C-1775553
CONN@

2
A

Compal Secret Data

Security Classification
Issued Date

GND

LED1_LED3

CH751H-40PT_SOD323-2
RJ45_TX0RJ45_TX0+

11

10

+LAN_IO

D56

PR2+

C1481

+V_DAC
LAN_MDIN1
LAN_MDIP1

TCT2
TD2+
TD2-

21
20
19

RJ45_TX3RJ45_TX3+

C1472

4
5
6

24
23
22

220P 25V K NPO 0402

C1494 1

2 0.01U_0402_16V7K

+V_DAC
LAN_MDIN2
LAN_MDIP2

MCT1
MX1+
MX1-

TCT1
TD1+
TD1-

220P 25V K NPO 0402

C1492 1

2 0.01U_0402_16V7K

1
2
3

LED2_LED3

C1471

C1491 1

+V_DAC
LAN_MDIN3
LAN_MDIP3

2 0.01U_0402_16V7K

220P 25V K NPO 0402

C1490 1

LAN_LED2 1

75_1206_8P4R_5%
5
4
6
3
7
2
8
1

Yellow LED+

D54
TS1

C1475

4.7UH_1008HC-472EJFS-A_5%_1008
1
C1478

+LAN_DVDD12

0_0402_5%
ISOLATEB
2

LAN_LOPWEN
1
@ R1374

R1241
1

C1469 220P 25V K NPO 0402

15

LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS

C1470 220P 25V K NPO 0402

21

HSOP

0.1U_0402_10V7K
C1743

20

22U_1206_6.3V6M

<19> GLAN_RXN
<19> GLAN_TXP

GLAN_RXP_C
1
0.1U_0402_16V7K~N
GLAN_RXN_C
1
0.1U_0402_16V7K~N
GLAN_TXP

0.1U_0402_10V7K~N

2
C1473
2
C1476

<19> GLAN_RXP

0.1U_0402_10V7K~N

22U_1206_6.3V6M

C1474

Title

Compal Electronics, Inc.

Gigabit LAN_RTL8111C

Size Document Number

Custom

Rev
1.0

LA-4595P

Date:

Tuesday, February 17, 2009

Sheet
1

21

of

49

SATA HDD CONN

JSATA1
D

1
2
3
4
5
6
7

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

<18> PSATA_ITX_DRX_P0
<18> PSATA_ITX_DRX_N0

<18> PSATA_IRX_DTX_N0_C

C393
1

<18> PSATA_IRX_DTX_P0_C

C392

PSATA_IRX_DTX_N0
0.01U_0402_50V7K
PSATA_IRX_DTX_P0
2
0.01U_0402_50V7K
2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VS

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND GND
Reserved
GND GND
V12
V12
V12

SATA ODD CONN

JODD2

close JODD2
ODD_ITX_DRX_P0
ODD_ITX_DRX_N0

<18> ODD_ITX_DRX_P0
<18> ODD_ITX_DRX_N0
<18> ODD_IRX_DTX_N0_C
<18> ODD_IRX_DTX_P0_C

C327
C326

ODD_IRX_DTX_N0
2
2 0.01U_0402_50V7K ODD_IRX_DTX_P0
0.01U_0402_50V7K

1
1

GND
RX+
RXGND
TXTX+
GND

8
9
10
11
12
13

DP
5V
5V
MD
GND
GND

23
24

+5VS

SUYIN_127043FR022G226ZL_NR
+5VS

1
2
3
4
5
6
7

CONN@

GND
GND

14
15

SUYIN_127382FR013S52_NR
10U_0805_10V4Z~N

0.1U_0402_16V7K~N

1
C

C574

C296
2

1
C377

2
0.1U_0402_16V7K~N

1
C

C376
2

+5VS

1000P_0402_50V7K~N
10U_0805_10V4Z
1

Close to SATA HDD

0.1U_0402_16V4Z
1

1
C503

C506

C498

1U_0603_10V4Z

C499

2
1000P_0402_50V7K~N

Close to ODD Conn

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDD/CDROM
Size Document Number
Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

22

of

49

WWAN

+3VS

+1.5VS

0.01U_0402_16V7K~N

0.01U_0402_16V7K~N

4.7U_0805_10V4Z~N

1
1

C294

C321

C86

C316

C298

@
2
330U 2.5V Y D2

C312

C320

0.1U_0402_16V4Z~N 4.7U_0805_10V4Z~N

0.1U_0402_16V4Z~N
U23

+1.5VS
+3VS

1
2

JMINI1
ICH_PCIE_WAKE#
WWAN_REQ#10

<15> WWAN_REQ#10

CLK_PCIE_WWAN#
CLK_PCIE_WWAN

<15> CLK_PCIE_WWAN#
<15> CLK_PCIE_WWAN
PCI_RST#

1
2
R288
1 0_0402_5%
2
R287
@ 0_0402_5%
PCIE_RXN1
PCIE_RXP1

<27> EC_RX_P80_DATA
<19> PCIE_RXN1
<19> PCIE_RXP1

+3VS

53

GND1

GND2

54

CH2 CH3

6
5
4

+UIM_PWR

+3VS

S DIO(BR) NUP4301MR6T1 TSOP-6

UIM_DATA
UIM_CLK
UIM_RST

JSIM2

UIM_VPP
R2851
0_0402_5%
2
@ R2861
0_0402_5%
2
WL_OFF# <27>
PCI_RST# <17,21,26,28>
+3VALW

WL_OFF#
+3VALW_R 1

D9 @

+UIM_PWR

2
0_0402_5% R284

EC_TX_P80_DATA <27>

<27>

2
4
6
7
8

UIM_VPP
UIM_DATA
UIM_DET

UIM_DET

C571
100P_0402_25V8K
USB20_N10
USB20_P10
LED_WWAN#

GND
VPP
I/O
DET
DET

VCC
RST
CLK

1
3
5

GND
GND

9
10

UIM_RST
UIM_CLK

2
DAN217_SC59-3

C573 C329

SUYIN_254070FB008H505ZL

USB20_N10 <19>
USB20_P10 <19>

T23 PAD

C571 & C573 as close as JSIM1

C330
0.1U 16V K X7R 0402

2
1
R141 100K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Vp

4.7U 10V Z Y5V 0805

<19> PCIE_TXN1
<19> PCIE_TXP1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Vn

100P_0402_25V8K

PCIE_TXN1
PCIE_TXP1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

CH1 CH4

FOX_AS0B226-S52N-7F~N

Power status(Left)
LED1
12-21-BHC-ZL1M2RY-2C BLUE
<27,28> PWR_BLUE_LED#

PWR_BLUE_LED#

1 R472

+5VALW
2

200_0603_5%

Mini-Express Card---WLAN
+5VALW

LED2
+3V_WLAN
+3V_WLAN

0.01U_0402_16V7K~N

@
1
R411
1
R412

+1.5VS

2
0_0805_5%
2
0_0805_5%
@

4.7U_0805_10V4Z~N

<27> BATT_LOW_LED#
<27> BATT_CHG_LED#

BATT_LOW_LED#

3 Y

BATT_CHG_LED#

C500

C489

C456

200_0603_5%

B
12-22/Y2BHC-A30/2C_Y/B~D

+3VALW
+3VS

1 R471

JMINI2

PCIE_TXN3
PCIE_TXP3

+3V_WLAN

54

R86

SI3456BDV-T1-E3 1N TSOP6

R1242
470K_0402_5%
USB20_N6 <19>
USB20_P6 <19>
LED_WLAN# <28>
+3V_WLAN
+1.5VS

<27> WLANPW_EN#

WLANPW_EN#

WLANPW_DIS
D
Q59
SSM3K7002FU_SC70-3

2
G

R1243
1.5M_0402_5%
@

+3V_WLAN

Rename

ACES_88910-5204

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Issued Date

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+B+_BIAS

T61 PAD
1

GND2

2
100K_0402_5%

C485

0.01U_0402_16V7K~N

+1.5VS

USB20_N6
USB20_P6

C1468
1U_0603_10V6K

GND1

C488

6
5
2
1

53

WL_OFF#

LED_WLAN#

Q130

0.01U_0402_16V7K~N

LPC_AD[0..3] <18,27,28>
WL_OFF# <27>
PCI_RST# <17,21,26,28>
+3V_WLAN

+3V_WLAN

+3VALW

+1.5VS

LPC_FRAME# <18,27,28>

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

PCIE_C_RXN3
2
20_0402_5% PCIE_C_RXP3
0_0402_5%

0.1U_0402_16V4Z~N

<19> PCIE_TXN3
<19> PCIE_TXP3

PCIE_RXN3
1
PCIE_RXP3 R4031
R404

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

<19> PCIE_RXN3
<19> PCIE_RXP3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

<15> CLK_DEBUG_PORT

PCI_RST# 1
2
R445 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<15> CLK_PCIE_MCARD#
<15> CLK_PCIE_MCARD

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

ICH_PCIE_WAKE#
CH_DATA @ R380 1 0_0402_5%
2 MINI_PIN3
CH_CLK @ R381 1 0_0402_5%
2 MINI_PIN4
WLAN_REQ#4

,21,26,27> ICH_PCIE_WAKE#
<29> CH_DATA
<29> CH_CLK
<15> WLAN_REQ#4

Title

Mini-Card/LED
Size Document Number
Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
E

23

of

49

+3VS
+AVDD_HD

VREFFILT
VVREG

0.1U_0402_10V6K

10K_0402_5%
2

10K_0402_5%
2

R524

10K_0402_5%

R522

R515

R514

10K_0402_5%

1U_0402_6.3V
C1407

22

For IDT

21
34

C141
4.7U_0603_6.3V

MIC_RIGHT
U18

GAIN0
GAIN1

17

RINROUT+

C650 1
0.47U_0603_10V7K

AMP_LEFT
C636 1
0.47U_0603_10V7K

ROUT-

2 10K_0402_5%
2 10K_0402_5%

LINLOUT-

R513 1

2 10K_0402_5%

@ R521 1

2 10K_0402_5%

18

SPK_R1

1
R505

INTSPK_R1
2
0_0603_5%

14

SPK_R2

1
R504

INTSPK_R2
2
0_0603_5%

SPK_L1

1
R502

INTSPK_L1
2
0_0603_5%

NC

SPK_L2

1
R503

INTSPK_L2
2
0_0603_5%

BYPASS

GND1
GND2
GND3
GND4

1
3

SSM3K131TU_UFM-3
Q134
2

@ C525

@ C524

D16
@

BEEP

C1412 0.1U_0402_16V4Z
1
2

2
0_0805_5%

2
0_0805_5%

R1183
MONO_IN

ICH Beep
<19>

SB_SPKR

R1188

C1416 0.1U_0402_16V4Z
1
2

499K_0402_1%~D

GAIN0

Q10
2N7002_SOT23-3
@
@
2N7002_SOT23-3
Q16

GNDA

GAIN1

GAIN

PACDN042Y3R_SOT23-3

D12

Speaker Connector

@
2

6dB

10dB

15.6dB

21.6dB

3
2
1

INTSPK_L2
INTSPK_L1
INTSPK_R2
INTSPK_R1

R1425
100K_0402_5%
2

Q135
SSM3K7002FU_SC70-3

PACDN042Y3R_SOT23-3

D17

4
3
2
1

ACES_88266-04001
6
4 G2
5
3 G1
2
1
JSPK1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Issued Date

For pop/click noise from S3/S4/cold boot/warm boot

2008/05/07

Deciphered Date

2009/05/07

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HD CODEC 92HD81
Size

Document Number

Rev
1.0

LA-4595P
Date:

JMIC1

2
G
S SSM3K131TU_UFM-3S
3

2 SSM3K131TU_UFM-3
Q133

3
3

D
Q132

2
G

2
G

HPL

HPR

GND

20
13
11
1

21
1

GND

2
0_0805_5%

R118 1

EC_MUTE 2
G

@
R117 1

3
6
2
1

499K_0402_1%~D

2
0_0805_5%

R116 1
C654

2 1U_0603_10V4Z

Q131
2
G SSM3K131TU_UFM-3

@
2N7002_SOT23-3
Q11

2
BLM18BD601SN1D_0603~D
2
BLM18BD601SN1D_0603~D

P3017THF TSSOP 20P

@S

R1424
10K_0402_1%

<27>

2
0_0805_5%

R115 1

Q15
2N7002_SOT23-3

1
L34
1
L35

12

D
+5VALW

2.2U_0402_6.3V6

EC Beep
1

10

SHUTDOWN

19

2.2U_0402_6.3V6

C25

R14

EC_MUTE

C24
MIC_LEFT

LIN+
LOUT+

AMP_L

R520 1
@ R512 1

FOX_JA6333L-B3S0-7F
5
MIC_JD

100P_0402_25V8K
INTSPK_L2
C16
@

AMP_R

100P_0402_25V8K
INTSPK_L1
C15
@

100P_0402_25V8K
INTSPK_R1
C9
@

AMP_RIGHT
C638 1
0.47U_0603_10V7K

JHP1

100P_0402_25V8K
INTSPK_R2
C8
@

RIN+

100P_0402_25V8K

D23

100P_0402_25V8K

C642 1
0.47U_0603_10V7K

MICROPHONE IN JACK

PACDN042Y3R_SOT23-3
2
1
3

+5VS

C651
10U_0805_10V4Z

VDD
PVDD1
PVDD2

2
+5VS
0_0603_5%

R537

16
15
6

C648
0.1U_0402_16V4Z

+MIC1_VREFO

For SED TEST

W=40Mil

37

GNDA

3
6
2
1

0.01U_0402_16V7K

1
R516

25

0.01U_0402_16V7K

HPR
HPL

BLM18BD601SN1D_0603~D

MONO_IN
2
0_0402_5%

1
R1189

12

HP_R 1
2
L22
BLM18BD601SN1D_0603~D
HP_L 1
2

1
2
R360 56_0402_5%
1
2
R361 56_0402_5%

HP_LEFT

C252

1
R517

2
R518

17
18

L23
HP_RIGHT

C100

INTSPK_R2
INTSPK_R1

2
0_0603_5%
2
@ 0_0603_5%
@

C99

R698 1
R699 1

5
HP_JD

C260

DVSS
PVSS
AVSS
AVSS
AVSS
GND

INTSPK_L1
INTSPK_L2

2
0_0603_5%
2
@ 0_0603_5%

PACDN042Y3R_SOT23-3
2
1
3

CAP2

SPR_R1
SPR_R2

92HD81B1X5NLGXA1X8 48P
C1322 15P_0402_50V8J
@
1
2 ACZ_SDOUT

10U_0603_6.3V
C1406

2
PC_BEEP
MONO_OUT

SENSE_A

7
42
26
30
33
49

0.1U_0402_10V6K
C1405

C1403

SENSE_B

13

1U_0402_6.3V
C1404

39
45

27
38

PORT_F_L
PORT_F_R

FOX_JA6333L-B3S0-7F
R696 1
R697 1

1000P_0402_50V7K~N

PORT_E_L
PORT_E_R

CAP+

14

2
2.49K_0402_1%
2
20K_0402_1%
2
10K_0402_1%
1
1000P_0402_50V7K~N

EAPD

15
16

HEADPHONE OUT JACK

R3491
2
4.7K_0402_5%

1
100K_0402_5%

1
R915
HP_JD
1
R13
MIC_JD
1
R892
2
C114

43
44

1000P_0402_50V7K~N

2
R139

+AVDD_HD

SPR_L1
SPR_L2

R3481
2
4.7K_0402_5%

+AVDD_HD

40
41

+MIC1_VREFO

DMIC1/GPIO0/SPDIF_OUT_1
SPKR_PORT_D_RSPDIF_OUT_0
SPKR_PORT_D_R+

CAP-

36

MIC_LEFT
MIC_RIGHT

C7

19
20
24

@
SPR_L1
SPR_L2
SPR_R1
SPR_R2

1U_0402_6.3V

46

48
@
2
47
0_0402_5%
35

2.2U_0603_6.3V6K

SPKR_PORT_D_L+
SPKR_PORT_D_L-

DMIC0/GPIO2

HP_LEFT
HP_RIGHT

2
10K_0402_5%

EC_MUTE

DMIC_CLK/GPIO1

31
32

2
10K_0402_5%

<27>

1
R1190
C1421

PORT_C_L
PORT_C_R
VREFOUT_C

HDA_RST#

For IDT
EC_MUTE

HDA_SYNC

AMP_LEFT
AMP_RIGHT

1
10K_0402_5%

<16> MIC_SIG

2
0_0603_5%
2
0_0603_5%

HP1_PORT_B_L
HP1_PORT_B_R

28
29
23

2
R519

1
R126
1
R127

+AVDD_HD

1
10K_0402_5%

<18> ACZ_RST#

11

C1413

10

HDA_SDO

1U_0402_6.3V

<18> ACZ_SYNC

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_or_F

HDA_SDI

2
0_0805_5%

10U_0603_6.3V

<16> MIC_CLK

HDA_BITCLK

C66

6
1 33_0402_5%

1
L6

2.2U_0603_6.3V6K

2 R8

<18> ACZ_SDOUT

C1414

ACZ_BITCLK

<18> ADC_ACZ_SDIN0

10U_0603_6.3V

C796

@ 10_0402_5%
1

AVDD
AVDD

C23 @ 10P_0402_50V8J R41

1
2
2
<18> ACZ_BITCLK

DVDD_IO

U60

+AVDD_HD

DVDD_CORE

DVDD

0.1U_0402_10V6K

+5VS

40mil

+DVDD_IO
1U_0402_6.3V
C1397

C1399

0.1U_0402_10V6K
C1398

2
0_0603_5%
1

PVDD
PVDD

40mil

1
R128

Tuesday, February 17, 2009

Sheet
1

24

of

49

FD5
FIDUCAL
@

FD6
FIDUCAL
@
1

FD4
FIDUCAL
@
1

FD3
FIDUCAL
@

FD2
FIDUCAL
@

FD1
FIDUCAL
@

H17
@ HOLEA

H18
@ HOLEA

H25
@ HOLEA

H22
@ HOLEA

H23
@ HOLEA

H21
@ HOLEA

H20
@ HOLEA

H16
@ HOLEA

H15
@ HOLEA

H29
@ HOLEA

H12
@ HOLEA

H11
@ HOLEA

H10
@ HOLEA

H9
@ HOLEA

H8
@ HOLEA

H7
@ HOLEA

H_3P0

H27
@ HOLEA

H_3P2

H30
@ HOLEA

H_3P1

H26
@ HOLEA

H_3P7

H3
@ HOLEA

H4
@ HOLEA

H5
@ HOLEA

H6
@ HOLEA

H1
@ HOLEA

H_4P2

H2
@ HOLEA

H_4P5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Screws
Size Document Number
Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

25

of

49

Express card

+1.5VS
C91

1
0.1U_0402_16V4Z~N

1.5Vin
1.5Vin

1.5Vout
1.5Vout

11
13

2
4

3.3Vin
3.3Vin

3.3Vout
3.3Vout

3
5

+3VS
C74
C85

2
2

<17,21,23,28> PCI_RST#
<27,36,43> SYSON

1
0.1U_0402_16V4Z~N
+3VALW
1
0.1U_0402_16V4Z~N
PCI_RST#
SYSON

17
6

CPPE#

AUX_OUT

SYSRST#

OC#

20

SHDN#

PERST#

STBY#

NC

10

CPPE#

GND

SUSP#

<27,30,36,42,44,46> SUSP#

AUX_IN

EXPR_CPUSB#

9
18

4.7U_0805_10V4Z~N

+1.5VS_PEC

U11

12
14

+3VS_PEC

1
C90
0.1U_0402_16V4Z~N

<19>
<19>

USB20_N7
USB20_P7

USB20_N7
USB20_P7

EXPR_CPUSB#

C89

+3V_PEC

<19,21,23,27> ICH_PCIE_W AKE#

+3V_PEC

+3V_PEC
4.7U_0805_10V4Z~N

19
PERST#
C92
0.1U_0402_16V4Z~N

PERST#

+3VS_PEC
EXPCARD_REQ#16
CPPE#
CLK_PCIE_EXPR#
CLK_PCIE_EXPR

<15> EXPCARD_REQ#16

1
16

ICH_SMBCLK
ICH_SMBDATA

<19> ICH_SMBCLK
<19> ICH_SMBDATA
+1.5VS_PEC
+1.5VS_PEC

15

JEXP1

+1.5VS_PEC

Express Card Power Switch

1
<15> CLK_PCIE_EXPR#
<15> CLK_PCIE_EXPR

C93

RCLKEN

PCIE_TXN4
PCIE_TXP4

<19> PCIE_TXN4
<19> PCIE_TXP4

+3VS_PEC
4.7U_0805_10V4Z~N

P2231NF_QFN20

PCIE_RXN4
PCIE_RXP4

<19> PCIE_RXN4
<19> PCIE_RXP4

CPUSB#

+1.5V_CARD Max. 650mA, Average 500mA

+3V_CARD Max. 1300mA, Average 1000mA

1
C75
0.1U_0402_16V4Z~N

1
C73

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

27
28
29
30

GND
GND
GND
GND

GND
GND

31
32

FOX_1CX41202-KH_26P
conn@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Issued Date

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

EXPRESS CARD
Size
Document Number
Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet
1

26

of

49

+3VALW

<18>
<18>
<19,28>
<18,23,28>
<18,23,28>
<18,23,28>
<18,23,28>
<18,23,28>

CLK_PCI_EC
R272
@ 10_0402_5%

<19>
EC_SCI#
<19,28> PCI_CLKRUN#

47K_0402_5%

15P_0402_50V8J

C268
0.1U_0402_16V4Z

<28>

KSI[0..7]

<28>

KSO[0..15]

R263 2

1 4.7K_0402_5%

EC_SMB_CK1

R262 2

1 4.7K_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO[0..15]

+3VS
EC_SMB_DA2

R264 2

EC_SMB_CK2
LCD_TST

1 4.7K_0402_5%

R265 2

1 4.7K_0402_5%

R269 2

1 4.7K_0402_5%

LCD_CBL_DET#

R276 2

1 4.7K_0402_5%

MIC_DIAG

R308 1

2 10K_0402_5%

EC_FB_SDATA

R303 2

1 4.7K_0402_5%

EC_FB_SCLK

R304 2

1 4.7K_0402_5%

MSEN#

R309 1

2 10K_0402_5%

TP_DATA
TP_CLK

<23> UIM_DET
<48>
<48>
<4,16,31>
<4,16,31>

<19>
<19>
<19>
<28>

+5VS
R271
4.7K_0402_5%
<28> EC_FB_SCLK
1
2
<28> EC_FB_SDATA
1
2
R270
4.7K_0402_5%

+3VALW

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

<31> VGA_THER
<4> FAN_SPEED1
<28> TOUCHKEY_TINT
<23> EC_TX_P80_DATA
<23> EC_RX_P80_DATA
<28> ON_OFF
<23,28> PWR_BLUE_LED#
<28> NUMLED#

KSO1

R76

KSO2

R78

XCLKI
XCLKO

10K_0402_5%

122
123

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

1
71.5K_0402_1%
1
2
2

67

PS2 Interface

BEEP
W_DISABLE#
ACOFF

63
64
65
66
75
76

C273 1
BATT_TEMP
BATT_OVP
ADP_I
AD_BID
MIC_DIAG
POW_MON

2 0.01U_0402_16V7K

3.3V+/-5%

Ra

100k

C79
BATT_OVP

ECAGND

83
84
85
86
87
88

EC_MUTE
LCD_TST
VGA_ON
LCD_CBL_DET#
TP_CLK
TP_DATA

97
98
99
109

SPI_PULLDOWN 2 R274
1 4.7K_0402_5%
EN_WOL#
EN_WOL# <21>
BT_OFF#
BT_OFF# <29>
VGATE
VGATE
<7,19,47>

0.8519
1.0459

56.2K +/-1%

1.1873

71.5K +/-1%

100P_0402_50V8J

0.683

46.4K +/-1%

1.3758

91K +/-1%

DAC_BRIG <16>
EN_DFAN1 <4>
IREF
<40>

0.6V~1.6V

Rb
26.1K +/-1%
34.8K +/-1%

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

1.5723

CHGVADJ <40>
EC_MUTE <24>
LCD_TST <16>
VGA_ON <45>
LCD_CBL_DET# <16>
TP_CLK
<28>
TP_DATA <28>

SPI Flash (8Mb*1)

@ C507
1
2 0_0402_5%

0.1U_0402_16V4Z~N

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

C314
1
2

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

WLANPW_EN#
MSEN#
FSTCHG
BATT_CHG_LED#
CAPSLED#
BATT_LOW_LED#
SCRLED#
SYSON
VR_ON
ACIN

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
ICH_PWROK
BKOFF#
WL_OFF#
LCD_VCC_TEST_EN
PSID_DISABLE#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

SLP_S4#
G7X_ENBKL
USB_EN
EC_THERM#
SUSP#
PBTN_OUT#
PS_ID

XCLK1
XCLK0

V18R

2
R419

SPI_CLK_R

+3VALW
119
120
126
128

GPI

VCC

Board ID

MIC_DIAG <16>
POW_MON <47>

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

GPIO

ECAGND

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

SPI Flash ROM

C272
0.1U_0402_16V4Z

M/B rev:0.1; 0.2; 0.3; 1.0

Voltage:0.0; 0.4; 0.8; 1.0

BATT_TEMP <48>
BATT_OVP <48>
ADP_I
<40>

DAC_BRIG
EN_DFAN1
IREF
M_PWROK_EC

SPI Device Interface

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

INVT_PWM <16>
BEEP
<24>
W_DISABLE# <28>
ACOFF
<40>

68
70
71
72

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SM Bus

KB926QFA1_LQFP128

21
23
26
27

AD_BID
1

20mils
2 R437

0.1U_0402_16V4Z~N

1
10K_0402_5%
U37

124

+V18R

WLANPW_EN# <23>
MSEN#
<16>
FSTCHG <40>
BATT_CHG_LED# <23>
CAPSLED# <28>
BATT_LOW_LED# <23>
SCRLED# <28>
SYSON
<26,36,43>
VR_ON
<47>
ACIN
<19,39,40>

FSEL#SPICS# 2
1 SPI_CS#
R439
15_0402_5%
FRD#SPI_SO 1
2 SPI_SO
15_0402_5% R275

1
2
3
4

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_CLK_R 1
15_0402_5%
SPI_SI 1
MX25L1605AM2C-12G_SO8 15_0402_5%

EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON
<28>
EC_SWI# <19>
ICH_PWROK <7,19>
BKOFF#
<16>
WL_OFF# <23>
LCD_VCC_TEST_EN <16>
PSID_DISABLE# <39>

SPI_CLK
2
R420
2 FWR#SPI_SI
R438

C1323
SPI_CLK

For SED TEST

1
22P_0402_50V8J

SLP_S4# <19>
G7X_ENBKL <16,31>
USB_EN <29>
EC_THERM# <19>
SUSP#
<26,30,36,42,44,46>
PBTN_OUT# <19>
PS_ID
<39>
1
2 1U_0603_10V4Z
C322
C270 2

1 0.1U_0402_16V4Z

ECAGND

47K_0402_5%

1
IN

32.768KHZ_12.5P_1TJS125BJ2A251

OUT

C297
22P_0402_50V8J

NC

C292
22P_0402_50V8J

2
4

NC

47K_0402_5%
1

77
78
79
80

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output

R231

For ENE D2

R277
0_0402_5%

AD

R312 1

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

SLP_S3#
6
SLP_S5#
14
EC_SMI#
15
LID_SW#
16
EC_FB_SCLK
17
EC_FB_SDATA
18
PCIE_PME#_R 19
VGA_THER
25
FAN_SPEED1 28
TOUCHKEY_TINT
29
EC_TX_P80_DATA 30
EC_RX_P80_DATA31
ON_OFF
32
PWR_BLUE_LED# 34
NUMLED#
36

1 R278
2 XCLKI
XCLKO@ 20M_0603_5%
EC_MUTE

PWM Output

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

R232
100K_0402_5%

Rb

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

KSI[0..7]

+5VALW
EC_SMB_DA1

12
13
37
20
38

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

GND
GND
GND
GND
GND

1
2
3
4
5
7
8
10

11
24
35
94
113

2
1
@ C282

CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
PCI_CLKRUN#

<15> CLK_PCI_EC
<7,17,30,31> PLT_RST#

R228
+3VALW

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VALW

Ra

AGND

0_0402_5%
1

Board ID

69

R281
2

<19,21,23,26> ICH_PCIE_WAKE#

VCC
VCC
VCC
VCC
VCC
VCC

U29

+EC_AVCC

AVCC

L18

2
1
+3VALW
2 FBM-11-160808-601-T_0603
C481
C482
1000P_0402_50V7K~N
0.1U_0402_16V4Z~N
12
ECAGND2
1
FBM-11-160808-601-T_0603 L19

9
22
33
96
111
125

2
1

C291
1000P_0402_50V7K~N

C269
1000P_0402_50V7K~N

C493
0.1U_0402_16V4Z~N

PCIE_PME#_R

C277
0.1U_0402_16V4Z~N

R405
10K_0402_5%

C285
0.1U_0402_16V4Z~N

C281
0.1U_0402_16V4Z~N

+3VALW

+EC_AVCC

X2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BIOS & EC I/O Port

Size Document Number
Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet

27

of

49

INT_KBD CONN.
<27>

R297
1

D15
PWR_ON-OFF_BTN#

KSO[0..15]

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

100K_0402_5%

Power Button

KSI[0..7]

<27> KSO[0..15]

+3VALW

2
1

51ON#

ON_OFF

<27>

51ON#

<39>

CHN202UPT SC-70
1

+3VALW
2

2
R296
4.7K_0402_5%
1

Q26
S SSM3K7002FU_SC70-3

EC_ON

EC_ON

D13
RLZ20A_LL34

@
<27>

C313
1000P_0402_50V7K~N

1
2
R291
0_0402_5%

2
G

SW3
SW_1BT002-0121L_4P
3

@ C449

100P_0402_25V8K

KSI7

@ C235

100P_0402_25V8K

KSI3

@ C239

100P_0402_25V8K

KSI6

@ C236

100P_0402_25V8K

JKB1

KSO9

@ C249

100P_0402_25V8K

KSI5

@ C237

100P_0402_25V8K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
G1
G2

KSI2

@ C240

100P_0402_25V8K

KSO0

@ C441

100P_0402_25V8K

KSI1

@ C241

100P_0402_25V8K

KSO1

@ C442

100P_0402_25V8K

KSO10 @ C248

100P_0402_25V8K

KSO2

@ C443

100P_0402_25V8K

KSO11 @ C247

100P_0402_25V8K

KSI4

@ C238

100P_0402_25V8K

KSI0

@ C242

100P_0402_25V8K

KSO3

@ C444

100P_0402_25V8K

KSO12 @ C246

100P_0402_25V8K

KSO4

@ C445

100P_0402_25V8K

KSO13 @ C245

100P_0402_25V8K

KSO5

@ C446

100P_0402_25V8K

KSO14 @ C244

100P_0402_25V8K

KSO6

@ C447

100P_0402_25V8K

KSO15 @ C243

100P_0402_25V8K

KSO7

@ C448

100P_0402_25V8K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

For EMI

Function/B CONN.
C80

+3VS_FUN
+3VS

Regulator for ENE sensor

C250

10K_0603_1%

2
1

RT9198-33PBR SOT-23 5P
SHDN#
BP 4

U54

D59
<27> W_DISABLE#

FB_SCLK

C27
VOUT

18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

BLUETOOTH_LED#

<29> BLUETOOTH_LED#
<23,27>
<27>
<27>
<27>
<27>

CONN@
ACES_88512-1641_16P

2 R_SATA_LED#
0_0402_5%
PWR_ON-OFF_BTN#
LED_WLAN#
FB_SDATA
FB_SCLK

<23> LED_WLAN#
2
1
0402
2KC FBMA-11-100505-301T
1
KC FBMA-11-100505-301T 0402

FB_SDATA

GND
VIN

L3

+3VS_FUN

33P_0402_50V8J

R901
1
1U_0402_6.3V4Z

<27> EC_FB_SDATA
<27> EC_FB_SCLK

Adjustable Output

+5VS

+3VALW

R623 1

<18> SATA_LED#
L2

SW1
1BS003-1211L_3P
1

+5VS

R881 @
0_0603_5%
1
2

Wireless_BTN

ACES_88514-2601_26P
CONN@

POWER SWITCH

5
6

PWR_ON-OFF_BTN#

KSO8

KSI[0..7]

10U_0603_6.3V

PWR_BLUE_LED#
TOUCHKEY_TINT 1
NUMLED#
CAPSLED#
SCRLED#
BTOP_BTN#

PWR_BLUE_LED#
TOUCHKEY_TINT
NUMLED#
CAPSLED#
SCRLED#

2 R607
0_0402_5%

C28
33P_0402_50V8J
@ For ENE

GND
GND
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

JFN1

near JFN1

W_DISABLE# 2
1
3

TPM 1.2

LID_SW#

VOUT

VDD

<27>

PESD24VS2UT_SOT23-3~D
@

LID_SW#

LID_SW#

C29

TP/B TO M/B

13
14
15
16
17
18

ACES_88018-124L
CONN@

Base I/O Address

0 = 02Eh
1 = 04Eh

Issued Date

2007/1/15

G2
G1
4
3
2
1
JP1

D24
PACDN042Y3R_SOT23-3
@

Compal Electronics, Inc.

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Secret Data

Security Classification

C26

LPC_AD0 <18,23,27>
LPC_AD1 <18,23,27>
LPC_AD2 <18,23,27>
LPC_AD3 <18,23,27>
CLK_PCI_TPM <15>

C309

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLK_PCI_TPM

100P_0402_25V8K

12mA

2
4
6
8
10
12

CONN@
ACES_85201-0405N
6
5
4
3
2
1

TP_CLK
TP_DATA

TP_CLK
TP_DATA

GND
GND
GND
GND
GND
GND

+3VS
+3VALW

C300
0.01U_0402_16V7K

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

JTPM1

<27>
<27>

100P_0402_25V8K C310

1
3
5
7
9
11

VDD

+5VS

LPC_FRAME#
PCI_RST#
SERIRQ
PCI_CLKRUN#

VOUT

Touch PAD/B CONN.

<18,23,27> LPC_FRAME#
<17,21,23,26> PCI_RST#
<19,27> SERIRQ
<19,27> PCI_CLKRUN#

+3VALW

0.1U_0402_16V4Z

GND

BTOP_BTN#
3

U9
APX9132ATI-TRL_SOT23-3

0.1U_0402_16V4Z

PWR_ON-OFF_BTN#

GND

@
U10
+3VALW
APX9132ATI-TRL_SOT23-3

D58

PJSOT24C_SOT23-3
@

Title

PWR_OK/BTN/TP
Size Document Number
Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
E

28

of

49

+USB_AS
+5VALW
0.1U_0402_16V4Z

GND
IN
IN
EN#

C434

8
7
6
5

OUT
OUT
OUT
OC#

C223

150U_B2_6.3VM_R45M

R155
470_0603_5%

RT9711PS SO 8P
2

USB_EN#
USB_OC#0 <19>

Q14
SSM3K7002FU_SC70-3

2
G

0.1U_0402_16V4Z

1 1

C228

1
2
3
4

USB_EN#

80 mils
1

U12

R154
100K_0402_5%
@
2

+USB_AS

<19>
<19>

USB20_N0
USB20_P0

USB20_N0

1
0_0402_5%
1
0_0402_5%

R1
2

USB20_P0

R3

JUSBP1

W=60mils

1
2
3
4
5
6
7
8

USB_N0
USB_P0

+USB_CS
+5VALW

U14

C253

1
2
3
4

USB_EN#

GND
IN
IN
EN#

SUYIN_020133MR004S536ZL
CONN@

8
7
6
5

OUT
OUT
OUT
OC#

80 mils

RT9711PS SO 8P

R38
470_0603_5%

0.1U_0402_16V4Z

CM1293-04SO_SOT23-6
USB_OC#2_#8 <19>

USB_EN#

Q13
SSM3K7002FU_SC70-3

2
G

+USB_BS

+5VALW

CH1

CH4

Vn

Vp

CH2

CH3

CM1293-04SO_SOT23-6
4

USB_P0

+USB_AS

USB_N0

@ D19

GND
IN
IN
EN#

OUT
OUT
OUT
OC#

8
7
6
5

0.1U_0402_16V4Z
+

C435

Fingerprint

CH2

CH3

+USB_BS

USB20_N9

150U_B2_6.3VM_R45M
R36
470_0603_5%

CH4

Vn

Vp

CH2

CH3

W=60mils

1
4

JUSBP4

USB20_P5

<19>

USB20_N9

<19>

USB20_P9

USB20_N9

USB_OC#9 <19>
5

+3VS

USB_EN#

CH1

Vp

+USB_BS

C224

CM1293-04SO_SOT23-6
1

Vn

USB20_P9

@D27
@
D27

RT9711PS SO 8P
0.1U_0402_16V4Z

CH4

1
2
3
4

USB_EN#

CH1

U13

80 mils
C64

VCC
USB_N
USB_P
GND
GND
GND
GND
GND

1
0_0402_5%
1
0_0402_5%

1
2
3
4
5
6
7
8

USB_P9USB_P9+

Q8
SSM3K7002FU_SC70-3

2
G

USB20_N5

USB20_P9

2
R1410
2
R1411

VCC
USB_N
USB_P
GND
GND
GND
GND
GND
SUYIN_020133MR004S536ZL
CONN@

D21
JFP1

6
5
4
3
2
1

USB20_N5
USB20_P5

+3VS

6 G1
5 G2
4
3
2
1

7
8

+3VS
10K_0402_5%
1
2
R282

<19>
<19>

ACES_88512-0641_6P
CONN@

Felica Conn

Bluetooth
JBT1
<19>
<19>

<23>
BT_OFF#

<27> BT_OFF#

<23>

1
2
3
4
5 G2
6 G1
JFE1

+5VALW
8
7

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
GND
GND

+USB_CS

W=80mils
<30>
<30>
<30>
<30>

ACES_88460-1001

C315
10U_0805_10V4Z 2

<27>

USB_EN

USB_EN

IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0
<19> USB20_P2
<19> USB20_N2
<19>
<19>

R222
10K_0402_5%

USB20_P8
USB20_N8

13
14

USB_EN#
D

JUSBP3
1
2
3
4
5
6
7
8
9
10
11
12

CONN@

LEC

TP1

1
2
3
4
5
6

USB20_N3
USB20_P3

USB20_N3
USB20_P3

CH_DATA

<28> BLUETOOTH_LED#

<19>
<19>

BT_ACTIVE

+3VS

CONN@
ACES_88512-0641_6P

+5VS

USB20_P4
USB20_N4
PAD T62
CH_CLK

GND1
GND2
ACES_87213-1200G
CONN@

Q4
SSM3K7002FU_SC70-3

2
G

1
2
3
4
5
6
7
8
9
10
11
12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

USB/BlueTooth/FP/Felcia
Size Document Number
Custom LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet

29

of

49

+1.8VS_CB

+1.8VS_CB
R1375

R1384
1
2
10K_0402_5%

1
1
R1409
100K_0402_5%

Layout Note: Place close to

OZ888 and Shield GND.

C1763 2
C1764 2

OZ888XI

15P_0402_50V8J

7
14
17

1 0.1U_0402_10V6K
1 0.1U_0402_10V6K

<15> MEDIA_REQ#32
PLT_RST#

C1745

X3
24.576MHz_16P_X5H024576FG1H-H
C1749

1
2
0_0402_5%
@

<15> CLK_PCIE_MEDIA
<15> CLK_PCIE_MEDIA#

<7,17,27,31>

C217
22U_0805_6.3V6M~D

1
4
18
24
41
64

PE_VCCA
PE_VCCA
PE_VCCA
VCCA_OUT

VCCD_OUT
VCCD_OUT

44
27
19

3.3VCCD
3.3VCCD
3.3VCCD

2
40
35

3.3VCCA
3.3VCCA
3.3VCCA

1394_TPAN
1394_TPAP

POWER

PLL_REF_RETURN
PE_RTERM2
PE_RTERM1
PE_RXP
PE_RXN

15
16

PE_TXP
PE_TXN

5
6

PE_REFCLKP
PE_REFCLKN

32

PE_CLKREQ#

31

PE_RST#

65

DGND

PCIe

IEEE1394_TPBN0
IEEE1394_TPBP0

36
37

IEEE1394_TPAN0
IEEE1394_TPAP0

38

IEEE1394_TPBIAS0

1394_XI
1394_XO

42
43

1394_REF

39

OZ888XI
OZ888XO
R1378
1
2
5.9K_0402_1%

MMI_VCC

26

MMI_XD_CD#
MMI_MS_CD#
MMI_SD_MMC_CD#

25
29
30

XD_CD#
MS_CD#
SD_CD#

MS_CLK/XD_CE#
SD_MMC_CLK
MMI_WPI#
MMI_XD_WPO
MMI_XD_RE#
MMI_XD_RB#
MMI_XD_CLE
SD_MMC_CMD
MMI_XD_WE#
MS_BS/XD_ALE

45
46
61
63
62
23
22
48
21
47

MSCLK_XDCE#
SD_CLK_R
MMI_WPI#
MMI_XD_WPO
XD_RE#
XD_RB#
XD_CLE
SD_CMD
XD_WE#
MSBS_XDALE

MMC_MS_XD_D7
MMC_MS_XD_D6
MMC_MS_XD_D5
MMC_MS_XD_D4

49
50
51
52

MMC_XD_D7
MMC_XD_D6
MMC_XD_D5
MMC_XD_D4

53
54
55
56
57
58
59
60

MS_XD_D3
MMC_SD_D3
MS_XD_D2
MMC_SD_D2
MS_XD_D1
MMC_SD_D1
MS_XD_D0
MMC_SD_D0

1394_TPBIAS

IEEE1394

PE_3.3VCCA

12
13

33
34

1394_TPBN
1394_TPBP

CORE_VCCD
CORE_VCCD
CORE_VCCD
CORE_VCCD
CORE_VCCD

20
28

+PE_3.3VCCA
3
C1758 4.7U_0603_6.3V6K~D
R1423
0_0402_5%
1
2
1
2
C1759 0.1U_0402_10V6K
1
2
1
2
11
R1422
0_0402_5%
@
@ @
@
2
1
9
R1382
1.2K_0402_1%
5.1K_0402_1% 2 R1383 1
10

<19> PCIE_RXP5
<19> PCIE_RXN5

U46

<19> PCIE_TXP5
<19> PCIE_TXN5
+3VS

R1379

+3VS_PHY

0_0603_5%
1
2
R1380

R1376
61.9K +-1% 0402

RT9043-GB_SOT23-5~D
R1421
10K_0402_5%

+VCCD_OUT

4.7U_0603_6.3V6K~D

C1757

C1755
0.1U_0402_10V6K

C1756
0.1U_0402_10V6K

1
C1762

C1760

4.7U_0603_6.3V6K~D

0.1U_0402_10V6K

C1761
0.1U_0402_10V6K

O2 recommend

0_0603_5%
1
2
R1381

+3VS

+3VS_PHY
+3VS

CardReader
MS_XD_D3
SD_MMC_D3
MS_XD_D2
SD_MMC_D2
MS_XD_D1
SD_MMC_D1
MS_XD_D0
SD_MMC_D0

GND

2
C1754
0.01U_0402_16V7K

0.1U_0402_10V6K

C1753
0.1U_0402_10V6K

C1752
0.1U_0402_10V6K

C1750

C1751
4.7U_0603_6.3V6K~D

100K_0402_5%

FB

@ R1377
1

VOUT

+VCCA_OUT

SUSP

O2 recommend

<36,46>

+1.8VS_CB

VIN
GND
EN

Q129
AO3413_SOT23
+1.8V

@
D

SUSP#
C218
1U_0402_6.3V6K~D

SUSP#

0_0402_5%

<26,27,36,42,44,46>

R1023

0.1U_0402_10V6K

C1771
0.1U_0402_10V6K

U16
1
2
3

+3VALW
1

C1748
0.1U_0402_10V6K

C1747
4.7U_0603_6.3V6K~D

C1746

+1.8PE_VCCA

1
2
0_0402_5%

R1408
OZ888XO_L

18P_0402_50V8J

OZ888XO

0_0402_5%

FOR DELL TEST

+3VS_CR

2
R1420
2

C1772
4.7U_0603_6.3V6K~D
C

1SD_CLK
+3VS_CR

0_0402_5%

For EMI TEST

1
C1768
1U 10V Z Y5V 0603

1
C1767
1U 10V Z Y5V 0603

C1765
1U 10V Z Y5V 0603

R1418
2

SD_CLK

AGND

@
1

0_0402_5%
R1419
MSCLK_XDCE#
2

@
1

0_0402_5%

C1766
1
2

10P_0402_50V8J~D
C1773
@
1
2
10P_0402_50V8J~D

For EMI TEST and Colse to J8IN1

OZ888GS0L1N_QFN64_8X8
+3VS_CR

+3VS_CR

JSD1
3

IEEE1394_TPBIAS0

C1770
1U_0402_6.3V6K

R1386
56.2_0402_1%
2

R1385
56.2_0402_1%

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0

<29>

IEEE1394_TPAN0

<29>

IEEE1394_TPBP0

<29>

IEEE1394_TPBN0

<29>

R1387
R1388
R1389
R1390
R1391
R1392
R1393
R1394

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

XDD0_MSD0
XDD1_MSD1
XDD2_MSD2
XDD3_MSD3
XDD4_MMCD4
XDD5_MMCD5
XDD6_MMCD6
XDD7_MMCD7

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD_WE#
MMI_XD_WPO
MSBS_XDALE
XD_CD#
XD_RB#
XD_RE#
MSCLK_XDCE#
XD_CLE

R1395
R1396
R1397
R1399
R1402
R1403
R1404
R1405

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
33_0402_5%~D
0_0402_5%

XDWE
XDWP
XDALE_MSBS
XDCD
XDRB
XDRE
XDCE_MSCLK
XDCLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31
41
42

7in1-GND
7in1-GND
7in1-GND
7in1-GND

IEEE1394_TPBN0

IEEE1394_TPAP0

R1400
56.2_0402_1%

7 IN 1 CONN

SD-VCC
MS-VCC
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

20
14
12
30
29
27
23
18
16

SDCLK
R1093
SDDAT0
R1412
SDDAT1
R1413
SDDAT2
R1414
SDDAT3
R1415
XDD4_MMCD4
XDD5_MMCD5
XDD6_MMCD6
XDD7_MMCD7

SD-CD
SD-WP
SD-CMD

1
2
25

SDCD
SDWP
SDCMD

R1398 1
R1416 1
R1417 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

SD_CD#
MMI_WPI#
SD_CMD

MS-SCLK
MS-BS
MS-INS

26
13
22

XDCE_MSCLK
XDALE_MSBS
MSINS
R1406 1

2 0_0402_5%

MS_CD#

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

17
15
19
24

XDD0_MSD0
XDD1_MSD1
XDD2_MSD2
XDD3_MSD3

1
1
1
1
1

2
2
2
2
2

33_0402_5%~D
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

SD_CLK
MMC_SD_D0
MMC_SD_D1
MMC_SD_D2
MMC_SD_D3

TAITW_R015-A10-LM
A

All DATA spacing=8mil, CLK spacing=15mil

R1401
56.2_0402_1%

XD-VCC

MS_XD_D0
MS_XD_D1
MS_XD_D2
MS_XD_D3
MMC_XD_D4
MMC_XD_D5
MMC_XD_D6
MMC_XD_D7

21
28

R1407
5.1K_0402_1%

C1769
270P_0402_50V7K

Issued Date

2008/1/3

Deciphered Date

2009/01/3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Layout Note: Place close to OZ888 Chipset.

5

Compal Secret Data

Security Classification

Title

OZ888GS0L1N Media Card/1394

Size

Document Number

Rev
1.0

LA-4595P
Date:

Sheet

Tuesday, February 17, 2009

1

30

of

49

1
1

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
<7,17,27,30>

Check reset timing

PLT_RST#

<34> XTALSSIN
<15> CLK_NVSS_27M

R1150 1

CLK_PCIE_VGA
CLK_PCIE_VGA#

AB10
AC10

2 0_0402_5%~D AD9
PEX_TERMP
AG10

<34> XTALOUTBUFF

XTALOUTBUFF

1
R1158 1
R1159

2XTALSSIN_R
2 0_0402_5%~D
0_0402_5%~D

E9
D11
@

PEX_REFCLK
PEX_REFCLK_N

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

U6
U4
T5
R4
T4
V6
R6
VGA_DDCCLK
VGA_DDCDATA
I2CA_SCL
I2CA_SDA
VGA_CLK_LCD
VGA_DAT_LCD
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
EC_SMB_CK2
EC_SMB_DA2

AF3
AG4
AE4
AF4
AG3
AD25

PAD
PAD
PAD
PAD
PAD

AF10
AE10

XTALSSIN

2
R1148

VGA_DDCCLK <16>
VGA_DDCDATA <16>

<---CRT

VGA_CLK_LCD
VGA_DAT_LCD

<---LVDS

<16>
<16>

CLK

XTALOUT

SPDIF
BUFRST_N

NC0
NC1
NC2
NC3

THERMDP
THERMDN

C9
A10
C10
B10

STRAP0
STRAP1
STRAP2
STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1

C7
B9
A9
F10
F11
F9
N5

1
R722

1
R1149

VGA_DAT_LCD

R142
1

R273
1

CLOSE TO GPU
VGA_CRT_R
VGA_CRT_G

R1197

2.2K_0402_5%

2
200_0402_5%

D10

2.2K_0402_5%
EC_SMB_CK2 <4,16,27>
EC_SMB_DA2 <4,16,27>

CLK_NV_27M

0_0402_5%~D

<15>

STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1

E10

D+

C1283 @
2200P_0402_50V7K

Close to Sensor

D-

D-

Strap pin define

VGA_CLK_LCD

TP2
TP3
TP4
TP5
TP6
1
10K_0402_5%~D

2
1K_0402_1%~D
D+

D9
D8

+3VS

+3VS

VGA_CRT_B
XTALIN

STRAP0
STRAP1
STRAP2
STRAP_CAL_PD_3V3(NC)
STRAP_CAL_PD_MIOB(NC)

GENERAL

@
1
2
R721
1K_0402_1%~D
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

M6

NB9M-GS_BGA533~D
R1
T3
R2
R3
A2
B1
N2
N3
Y6
W6
A3
A4
T1
T2

PEX_RST_N
PEX_TERMP
XTALOUTBUFF

AA6
AC19
E15
T6

RFU0(NC)
RFU1(NC)
RFU2(NC)
RFU3(NC)
RFU4(NC)
RFU5(NC)
RFU6(NC)
RFU7(NC)

IFPE_RSET
ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N

2
1K_0402_1%~D

1
R1161
1
R1162
1
R1164
1
R1168
1
R1169

STRAP0
STRAP1
STRAP2
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

2
150_0402_5%~D
2
150_0402_5%~D
2
150_0402_5%~D
2
40.2K_0402_1%
2
40.2K_0402_1%

R1147
4.99K_0402_1%~D
2
1

DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_BLUE
DACC_GREEN
DACC_RSET
DACC_VREF

HDA_BCLK
HDA_SYNC
HDA_SDI
HDA_SDO
HDA_RST_N

1
R720

R1156
1K_0402_5%~D
2
1

IFPAB_RSET

R5
D3
D4
F5
F4
E4
D5
C3
C4
B3
B4

R1146
1K_0402_5%~D
2
1

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

1
R54

1
AB6
1K_0402_5%~D
A7
B7
A6
B6
2
C6
10K_0402_1%
C15
D15
J5
F6
J22
L22
AG9
AE9

IFPC_RSET
IFPE_AUX
IFPE_AUX_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

G4
G5
P4
N4
M5
M4
L4
K4
H4
J4

R1155
30K_0402_5%
2
1

1
R1140

F7
E6
E7
F8
D6
G6

2
@R1134
@
R1134

VGA_HSYNC <16>
VGA_VSYNC <16>
VGA_CRT_R <16>
VGA_CRT_B <16>
VGA_CRT_G <16>
2
124_0402_1%~D 1
2
C1272
0.1U_0402_10V7K~D

IFPC_AUX
IFPC_AUX_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

R1145
1K_0402_5%~D
2
1

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

T148PAD~D
T149PAD~D

VGA_HSYNC
VGA_VSYNC
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G
DACA_RSET
DACA_VREF

Part 3 of 5

R1154
15K_0402_5%
1
2

PEG_NRX_C_GTX_P0
PEG_NRX_C_GTX_N0
PEG_NRX_C_GTX_P1
PEG_NRX_C_GTX_N1
PEG_NRX_C_GTX_P2
PEG_NRX_C_GTX_N2
PEG_NRX_C_GTX_P3
PEG_NRX_C_GTX_N3
PEG_NRX_C_GTX_P4
PEG_NRX_C_GTX_N4
PEG_NRX_C_GTX_P5
PEG_NRX_C_GTX_N5
PEG_NRX_C_GTX_P6
PEG_NRX_C_GTX_N6
PEG_NRX_C_GTX_P7
PEG_NRX_C_GTX_N7
PEG_NRX_C_GTX_P8
PEG_NRX_C_GTX_N8
PEG_NRX_C_GTX_P9
PEG_NRX_C_GTX_N9
PEG_NRX_C_GTX_P10
PEG_NRX_C_GTX_N10
PEG_NRX_C_GTX_P11
PEG_NRX_C_GTX_N11
PEG_NRX_C_GTX_P12
PEG_NRX_C_GTX_N12
PEG_NRX_C_GTX_P13
PEG_NRX_C_GTX_N13
PEG_NRX_C_GTX_P14
PEG_NRX_C_GTX_N14
PEG_NRX_C_GTX_P15
PEG_NRX_C_GTX_N15

VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB1VGA_LVDSB2+
VGA_LVDSB2-

VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB1VGA_LVDSB2+
VGA_LVDSB2-

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

R1144
10K_0402_5%
1
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

DVI_MODE1
HDMI_DET1

AD2
AD1
AE2
AD3
AE3
AE1
AF1

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

AC4
AD4
V5
V4
AA5
AA4
W4
Y4
AB4
AB5
AB3
AB2
W1
V1
W3
W2
AA2
AA3
AB1
AA1

R1153
1K_0402_5%~D
2
1

NV_INVTPWM
PAD T145
VGA_LVDDEN
VGA_LVDDEN <16>
G7X_ENBKL
G7X_ENBKL <16,27>
For Internal Thermal
GPU_VID0
GPU_VID0 <45>
Sensor
GPU_VID1
GPU_VID1 <45>
MEM_VID
R1131 2
1
+3VS
PAD
VGA_THER
T150
10K_0402_5%
VGA_THER <27>
THER_ALERT#
2
1
+3VS
R1130 10K_0402_5%

VGA_LVDSAC+
VGA_LVDSACVGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA1VGA_LVDSA2+
VGA_LVDSA2-

VGA_LVDSAC+
VGA_LVDSACVGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA1VGA_LVDSA2+
VGA_LVDSA2-

R1143
1K_0402_5%~D
2
1

1
2

DACB_RED
DACB_BLUE
DACB_GREEN
DACB_RSET
DACB_CSYNC
DACB_VREF

U59C
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

R1152
10K_0402_5%
1
2

C1273
C1274
C1275
C1276
C1277
C1278
C1279
C1280
C1281
C1282
C1284
C1285
C1286
C1287
C1288
C1289
C1290
C1291
C1292
C1293
C1294
C1295
C1296
C1297
C1298
C1299
C1300
C1301
C1302
C1303
C1304
C1305

DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_RSET
DACA_VREF

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

R1142
45.3K_0402_1%~D
2
1

PEG_NRX_GTX_P0
PEG_NRX_GTX_N0
PEG_NRX_GTX_P1
PEG_NRX_GTX_N1
PEG_NRX_GTX_P2
PEG_NRX_GTX_N2
PEG_NRX_GTX_P3
PEG_NRX_GTX_N3
PEG_NRX_GTX_P4
PEG_NRX_GTX_N4
PEG_NRX_GTX_P5
PEG_NRX_GTX_N5
PEG_NRX_GTX_P6
PEG_NRX_GTX_N6
PEG_NRX_GTX_P7
PEG_NRX_GTX_N7
PEG_NRX_GTX_P8
PEG_NRX_GTX_N8
PEG_NRX_GTX_P9
PEG_NRX_GTX_N9
PEG_NRX_GTX_P10
PEG_NRX_GTX_N10
PEG_NRX_GTX_P11
PEG_NRX_GTX_N11
PEG_NRX_GTX_P12
PEG_NRX_GTX_N12
PEG_NRX_GTX_P13
PEG_NRX_GTX_N13
PEG_NRX_GTX_P14
PEG_NRX_GTX_N14
PEG_NRX_GTX_P15
PEG_NRX_GTX_N15

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

@ R1151
4.99K_0402_1%~D
2
1

MXM/DVI/DP

PEG_NTX_GRX_N[0..15]

Part 1 of 5

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

DVO / GPIO

PEG_NTX_GRX_P[0..15]

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

DACs

<9> PEG_NTX_GRX_N[0..15]

PEG_NTX_GRX_P0
PEG_NTX_GRX_N0
PEG_NTX_GRX_P1
PEG_NTX_GRX_N1
PEG_NTX_GRX_P2
PEG_NTX_GRX_N2
PEG_NTX_GRX_P3
PEG_NTX_GRX_N3
PEG_NTX_GRX_P4
PEG_NTX_GRX_N4
PEG_NTX_GRX_P5
PEG_NTX_GRX_N5
PEG_NTX_GRX_P6
PEG_NTX_GRX_N6
PEG_NTX_GRX_P7
PEG_NTX_GRX_N7
PEG_NTX_GRX_P8
PEG_NTX_GRX_N8
PEG_NTX_GRX_P9
PEG_NTX_GRX_N9
PEG_NTX_GRX_P10
PEG_NTX_GRX_N10
PEG_NTX_GRX_P11
PEG_NTX_GRX_N11
PEG_NTX_GRX_P12
PEG_NTX_GRX_N12
PEG_NTX_GRX_P13
PEG_NTX_GRX_N13
PEG_NTX_GRX_P14
PEG_NTX_GRX_N14
PEG_NTX_GRX_P15
PEG_NTX_GRX_N15

PCI EXPRESS

<9> PEG_NTX_GRX_P[0..15]

U59A
PEG_NRX_GTX_N[0..15]

I2C

<9> PEG_NRX_GTX_N[0..15]

TEST

<9> PEG_NRX_GTX_P[0..15]

@ C1077
0.1U_0402_10V7K~D
1
2

LVDS

PEG_NRX_GTX_P[0..15]

HDA

NB9M-GS_BGA533~D

I2CA_SCL
Y5
GND

OUT

IN

GND

I2CA_SDA

3
2

4
1
PEX_TERMP
2
2.49K_0402_1%

R1198
0_0402_5%~D
@

27MHZ_16PF_X7T027000BG1H-V~D
@
1

1
R1160

I2CD_SCL

C616
18P_0402_50V8J

1
1

I2CD_SDA
I2CE_SCL
I2CE_SDA

C617
I2CH_SCL

18P_0402_50V8J
2 @

I2CH_SDA

R143
1
R144
1
R145
1
R147
1
R148
1
R149
1
R150
1
R151
1

2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2

+3VS

Each strap pin represents a 4 bit value

Resistor

Multilevel

Tied to VCC

Pullup or Pulldown configures the MSB

3 Kohms

1000

0000

6 Kohms

1001

Tied to Ground

0001

Value

Resistor Value determines the 3 LSBs

Resistor range is R*n
where n is 0-9 and R is 5K ohm.

12 Kohms

1010

0010

24 Kohms

1011

0011
0100

48 Kohms

1100

96 Kohms

1101

192 Kohms

1110

284 Kohms

1111

0111

2 Kohms*

1xxx

0xxx

0101
0110

+3VS

C197
@
0.1U_0402_16V4Z
2
1

External Thermal sensor

R79
200_0402_5%
@
U7
1
VCC

D+

D-

3
VGA_THER

SCLK

DXP

SDA

DXN

ALERT#

OVERT#

GND

EC_SMB_CK2

EC_SMB_DA2

THER_ALERT#

DELL CONFIDENTIAL/PROPRIETARY
NVidia

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

MAX6649MUA+T_UMAX8~D
@

Title

NVG98 PCIE,GPIO,CLK,LVDS
Size
Date:

Document Number

Rev
1.0

LA-4595P
Tuesday, February 17, 2009

Sheet
1

31

of

49

FBAD[0:63]

FBAD[0:63] <35>

DQMA#[0:7]

FBAA[0..11]

FBAA[0..11] <35>

DQMA#[0:7] <35>

DQSA_WP[0:7]

DQSA_WP[0:7] <35>

DQSA_RN[0:7]

FBBA[2..5]

FBBA[2..5] <35>

DQSA_RN[0:7] <35>

U59B

FBAA4
F26
FBARAS#
J24
FBARAS# <35>
FBAA5
F25
FBA_BA1
M23
FBA_BA1 <35>
FBBA2
N27
FBBA4
M27
FBBA3
K26
J25
FBACS0#
J27
FBACS0# <35>
FBAA11
G23
FBACAS#
G26
FBACAS# <35>
FBAWE#
J23
FBAWE# <35>
FBA_BA0
M25
FBA_BA0 <35>
FBBA5
K27
FBAA12
G25
FBAA12
<35>
L24 FBA_RST_R
1
2 FBA_RST
FBA_RST <35>
FBAA7
R560
0_0402_5%
K23
FBAA10
R571
K24
FBA_CKE
10K_0402_5%
G22
FBA_CKE <35>
FBAA0
K25
FBAA9
H22
FBAA6
R563
M26
FBAA2
10K_0402_5%
H24
R571 & R563 Pull-down
FBAA8
F27
CKE & RESET/ODT
FBAA3
J26
FBAA1
G24
G27
FBA_BA2_CMD27 1
2 FBA_BA2
M24
FBA_BA2 <35>
SNN_FBA_CMD28
0_0402_5%
K22
T152PAD~D R561
2

DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

A24
C25
E19
A19
T22
T27
AA24
AA26

DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7

A16

FBA_VREF

F24
F23
N24
N23
M22

FBACLK0
FBACLK0#
FBACLK1
FBACLK1#

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_DEBUG

+1.8VS
1

B24
D25
E18
A18
R22
R27
Y24
AA27

2
1
R1174
10K_0402_5%~D

10mil
FBACLK0
FBACLK0#
FBACLK1
FBACLK1#
T153PAD~D
+1.8VS

<35>
<35>
<35>
<35>

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

FB_VREF

for initialization

R1173
1K_0402_1%~D

D23
C26
D19
B19
T24
T26
AA23
AB27

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

R1172
1K_0402_1%~D

NB9M-GS_BGA533~D

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

Part 2 of 5

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

MEMORY
INTERFACE

D21
C22
B22
A22
C24
B25
A25
A26
D22
E22
E24
D24
D26
D27
C27
B27
D16
E16
D17
F18
D20
F20
E21
F21
C16
B18
C18
D18
C19
C21
B21
A21
P22
P24
R23
R24
T23
U24
V23
V24
N25
N26
R25
R26
T25
V26
V25
V27
V22
W22
W23
W24
AA22
AB23
AB24
AC24
W25
W26
W27
AA25
AB25
AB26
AD26
AD27

C1310
0.1U_0402_10V7K~D

FBAD0
FBAD7
FBAD6
FBAD4
FBAD1
FBAD5
FBAD3
FBAD2
FBAD10
FBAD12
FBAD9
FBAD15
FBAD13
FBAD8
FBAD11
FBAD14
FBAD16
FBAD20
FBAD18
FBAD22
FBAD17
FBAD21
FBAD19
FBAD23
FBAD29
FBAD28
FBAD30
FBAD31
FBAD27
FBAD25
FBAD26
FBAD24
FBAD38
FBAD36
FBAD37
FBAD39
FBAD32
FBAD35
FBAD34
FBAD33
FBAD44
FBAD45
FBAD47
FBAD46
FBAD41
FBAD42
FBAD43
FBAD40
FBAD48
FBAD53
FBAD50
FBAD51
FBAD49
FBAD55
FBAD54
FBAD52
FBAD61
FBAD62
FBAD59
FBAD57
FBAD60
FBAD58
FBAD56
FBAD63

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

NVG98 Memory Interface

Size
Date:

Document Number

Rev
1.0

LA-4595P
Tuesday, February 17, 2009

Sheet
1

32

of

49

Place near GPU

+1.1V_GFX_PCIE

POWER

Place near Balls

+1.8VS

NVVDD_SENSE <45>

C1320
4.7U_0603_6.3V4Z~D

+PEX_PLLVDD

2
1
L101
10NH_LQG15HS10NJ02D_5%_0402~D

C1319
1U_0402_6.3V6K~D

Place near GPU

IFPAB_PLLVDD = 140 mA

+1.8VS
L105
BLM18AG121SN1D_0603~D
1
2

+IFPAB_PLLVDD

AD5
P6
N6

+IFPAB_PLLVDD

+IFPE_IOVDD

+IFPE_PLLVDD

C1384
4.7U_0603_6.3V6M~D

+IFPAB_IOVDD

C1389
4.7U_0603_6.3V6M~D

V3
V2
J6
H6

C1388
470P_0402_50V7K~D

C1381
4700P_0402_25V7K~D

+IFPX_IOVDD= 385mA

R1166 1
10K_0402_5%

IFPAB_IOVDD = 100mA

2
1
R1167 10K_0402_5%

+IFPX_PLLVDD= 160mA

+GPU_PLLVDD

GPU_PLLVDD = 140 mA

+1.1V_GFX_PCIE

+GPU_PLLVDD

2
L103
BLM18AG121SN1D_0603~D

C1376
1U_0402_6.3V6K~D

C1380
0.1U_0402_10V7K~D

C1374
0.1U_0402_10V7K~D

C1375
0.1U_0402_10V7K~D

C1390
4.7U_0603_6.3V6M~D

C1387
4.7U_0603_6.3V6M~D

NB9M-GS_BGA533~D

C1386
4700P_0402_25V7K~D

+1.8VS
L106
BLM18AG121SN1D_0603~D
1
2

+IFPAB_IOVDD
C1385
470P_0402_50V7K~D

+DACB_VDD
2
10K_0402_5%
+DACC_VDD
1
10K_0402_5%~D

C1392
4700P_0402_25V7K~D

1
R49
2
R1176

Place near Balls

W15

K5
K6
L6

C1372
0.1U_0402_10V7K~D

C1379
470P_0402_50V7K~D

C1378
4700P_0402_25V7K~D

C1377
4.7U_0603_6.3V6M~D

+DACA_VDD

PLLVDD
VID_PLLVDD
SP_PLLVDD

C1391
470P_0402_50V7K~D

DACA VDD= 120mA

L104
BLM18AG121SN1D_0603~D
1
2

FBCAL_PD_VDDQ

C1318
0.01U_0402_16V7K~D

B15

C1317
0.1U_0402_10V7K~D

+3VS

1
R1175

+1.1V_GFX_PCIE

10 mil

C1346
4.7U_0603_6.3V4Z~D

2 FB_CAL_PD_VDDQ
44.2_0402_1%~D

IFPAB_PLLVDD
IFPC_PLLVDD
IFPE_PLLVDD

C1347
1U_0402_6.3V6K~D

FB_PLLAVDD
FB_DLLAVDD

C195
0.47U_0402_6.3V6K

R19
T19

C916
22U_0805_6.3V6M

+FB_PLLVDD

C1344
1U_0402_6.3V6K~D

DACA_VDD
DACB_VDD
DACC_VDD

+DACB_VDD
+DACC_VDD

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPE_IOVDD

C194
0.47U_0402_6.3V6K

AG2
D7
W5

+DACA_VDD

+1.8VS

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

C917
22U_0805_6.3V6M

A12
B12
C12
D12
E12
F12

+PEX_PLLVDD

C1343
1U_0402_6.3V6K~D

C1371
0.1U_0402_10V7K~D

C1370
0.1U_0402_10V7K~D

C1369
1U_0402_6.3V6K~D

C843
4.7U_0603_6.3V6M~D

PEX_PLLVDD = 100mA
C193
0.47U_0402_6.3V6K

+3VS

C1316
4.7U_0603_6.3V4Z~D

+1.1V_GFX_PCIE

AF9

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

C1368
0.1U_0402_10V7K~D

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25

C1312
0.1U_0402_10V7K~D

VDD_SENSE

C1367
0.1U_0402_10V7K~D

PEX_PLLVDD

AC9
AD7
AD8
AE7
AF7
AG7
AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6

C1366
0.1U_0402_10V7K~D

C1437
0.47U_0402_6.3V6K

C1436
0.47U_0402_6.3V6K

C1435
0.1U_0402_10V7K~D

C1434
0.1U_0402_10V7K~D

C1433
0.1U_0402_10V7K~D

C1432
0.1U_0402_10V7K~D

C1431
0.1U_0402_10V7K~D

C1430
0.1U_0402_10V7K~D

C1421
0.01U_0402_16V7K~D

C1355
0.1U_0402_10V7K~D

+FB_PLLVDD
C1354
1U_0402_6.3V6K~D

C1353
4.7U_0603_6.3V6M~D

= 40 mA
C1425
0.1U_0402_10V7K~D

+1.1V_GFX_PCIE
FB_PLLVDD
L102
BLM18AG121SN1D_0603~D
1
2

Part 4 of 5

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11

C1365
0.1U_0402_10V7K~D

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42

C1311
0.1U_0402_10V7K~D

J10
J12
J13
J9
L9
M11
M17
M9
N11
N12
N13
N14
N15
N16
N17
N19
N9
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R17
R9
T11
T17
T9
U19
U9
W10
W12
W13
W18
W19
W9

C1325
0.1U_0402_10V7K~D

C192
0.47U_0402_6.3V6K

C188
0.47U_0402_6.3V6K

C180
0.47U_0402_6.3V6K

U59D

C1424
4.7U_0603_6.3V6M~D

C162
0.47U_0402_6.3V6K

C161
0.47U_0402_6.3V6K

C1423
4.7U_0603_6.3V6M~D

C1422
4.7U_0603_6.3V6M~D

Place near Balls

C1315
4.7U_0603_6.3V4Z~D

PEX_IOVDDQ = 1600mA
+VGA_CORE

C1327
1U_0402_6.3V6K~D

C1314
1U_0402_6.3V6K~D

PEX_IOVDD = 500mA

C1313
1U_0402_6.3V6K~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

NVG98 POWER
Size
Date:

Document Number

Rev
1.0

LA-4595P
Tuesday, February 17, 2009

Sheet
1

33

of

49

D_C

R708

D_C Internal pull up

1
2

1
2

R712
0_0402_5%~D

R711
10K_0402_5%~D

R710
10K_0402_5%~D

<31> XTALSSIN

U45
1
2
3
4

<31> XTALOUTBUFF

XIN/CLKIN XOUT
VSS
VDD
D_C
PD#
ModOUT REFCLK

8
7
6
5

C871
0.1U_0402_10V7K~D

+3VL
C870
10U_0805_10V4Z~D

0.875% (CENTER)

@
D

R709
10K_0402_5%~D

0
1

-1.75% (DOWN)

10K_0402_5%~D
2
1

+3VS

L50
@
BLM18AG121SN1D_0603~D
1
2

+3VS

@
1

P1819GF-08SR_SO8~D
@

U59E

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47

Part 5 of 5

GND

AC11
AC14
AC17
AC2
AC20
AC23
AC26
AC5
AC8
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF5
AF8
B11
B14
B17
B2
B20
B23
B26
B5
B8
E11
E14
E17
E2
E20
E23
E26
E5
E8
H2
H5
J11
J14
J17
K19
K9
L11
L12
L13
L14
L15

GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87

L16
L17
L2
L5
M12
M13
M14
M15
M16
P19
P2
P23
P26
P5
P9
T12
T13
T14
T15
T16
U11
U12
U13
U14
U15
U16
U17
U2
U23
U26
U5
V19
V9
W11
W14
W17
Y2
Y23
Y26
Y5

RFU_GND

AC6

GND_SENSE

W16

FBCAL_PU_GND
FBCAL_TERM_GND

A15
B16

Close to U44 pin W16

GND_SENSE

1
R707
FB_CAL_PU_GND
1
FB_CAL_TERM_GND R703 1
R702

0_0402_5%~D
2
2 30.9_0402_1%~D
40.2_0402_1%~D

NB9M-GS_BGA533~D
A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

NVG98 GND
Size

Document Number

Date:

Tuesday, February 17, 2009

Rev
1.0

LA-4595P
2

Sheet
1

34

of

49

+1.8VS

R925
1.05K_0402_1%
2

+VREFA0

+VREFB1

R926
2.49K_0402_1%

C944
0.01U_0402_16V7K

<32>
<32>
<32>
<32>
<32>

FBAA12
FBARAS#
FBACAS#
FBAWE#
FBACS0#

1
R919

DM0
DM1
DM2
DM3

DQSA_WP0
DQSA_WP2
DQSA_WP3
DQSA_WP1

D2
D11
P11
P2

WDQS0
WDQS1
WDQS2
WDQS3

+VREFA0
+VREFA1

H1
H12
J2
J3

VREF
VREF
RFU1
RFU2

FBARAS#
FBACAS#
FBAWE#
FBACS0#

H3
F4
H9
F9

RAS#
CAS#
WE#
CS#

FBA_CKE
FBACLK0
FBACLK0#

H4
J11
J10

CKE
CK
CK#

DQSA_RN0
DQSA_RN2
DQSA_RN3
DQSA_RN1

D3
D10
P10
P3

2
243_0402_1%

A4
A9

A2
A11
F1
F12
M1
M12
V2
V11

+1.8VS

FBA_RST
FBA_BA2

<32> FBA_RST

V4
V9
H10
J1
J12

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

ZQ
MF
RDQS0
RDQS1
RDQS2
RDQS3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SEN
RESET
BA2
VSSA
VSSA

VDDA
VDDA

FBADQS#[0..7]

FBAD1
FBAD3
FBAD2
FBAD5
FBAD7
FBAD4
FBAD0
FBAD6
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD27
FBAD25
FBAD24
FBAD26
FBAD31
FBAD28
FBAD30
FBAD29
FBAD10
FBAD12
FBAD9
FBAD15
FBAD8
FBAD13
FBAD11
FBAD14

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+1.8VS

R910
1.05K_0402_1%
+VREFB0
R914
2.49K_0402_1%

C948
0.01U_0402_16V7K

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9

DQMA#5
DQMA#4
DQMA#6
DQMA#7

E3
E10
N10
N3

DM0
DM1
DM2
DM3

DQSA_WP5
DQSA_WP4
DQSA_WP6
DQSA_WP7

D2
D11
P11
P2

WDQS0
WDQS1
WDQS2
WDQS3

+VREFB0
+VREFB1

H1
H12
J2
J3

VREF
VREF
RFU1
RFU2

H3
F4
H9
F9

RAS#
CAS#
WE#
CS#

FBA_CKE
FBACLK1
FBACLK1#

H4
J11
J10

CKE
CK
CK#

DQSA_RN5
DQSA_RN4
DQSA_RN6
DQSA_RN7

D3
D10
P10
P3

FBAA12

<32> FBAA12

FBARAS#
FBACAS#
FBAWE#
FBACS0#
+1.8VS
<32> FBACLK1
<32> FBACLK1#
1
R920

2
243_0402_1%

A4
A9

A2
A11
F1
F12
M1
M12
V2
V11

+1.8VS

+1.8VS
FBA_RST
FBA_BA2

K1
K12
1
C889
0.1U_0402_16V4Z

V4
V9
H10
J1
J12

C890
0.1U_0402_16V4Z

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

ZQ
MF
RDQS0
RDQS1
RDQS2
RDQS3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SEN
RESET
BA2

VDDA
VDDA

VSSA
VSSA

DQMA#[0..7]

<32> DQMA#[0:7]

FBAA[0..11]

<32> FBAA[0..11]

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

FBBA[2..5]

<32> FBBA[2..5]

FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD35
FBAD34
FBAD32
FBAD33
FBAD39
FBAD36
FBAD37
FBAD38
FBAD51
FBAD48
FBAD53
FBAD50
FBAD52
FBAD49
FBAD54
FBAD55
FBAD59
FBAD57
FBAD61
FBAD62
FBAD60
FBAD63
FBAD56
FBAD58

B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

FBA_BA0

<32> FBA_BA0

FBA_BA1

<32> FBA_BA1

FBA_BA2

<32> FBA_BA2

+1.8VS

+1.8VS

K1
K12
C891
0.1U_0402_16V4Z

C892
0.1U_0402_16V4Z

A3
A10
G1
G12
L1
L12
V3
V10

K4J52324QE-BC14_FBGA136~D

A3
A10
G1
G12
L1
L12
V3
V10

K4J52324QE-BC14_FBGA136~D

DQSA_WP[0:7]

<32> DQSA_WP[0:7]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

E3
E10
N10
N3

FBAA12

<32> FBA_CKE
<32> FBACLK0
<32> FBACLK0#

DQMA#0
DQMA#2
DQMA#3
DQMA#1

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.8VS

K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

C949
0.01U_0402_16V7K

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+VREFA1
R916
2.49K_0402_1%

U52

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

U51

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

1
R911
1.05K_0402_1%

FBAD[0..63]

<32> FBAD[0..63]
<32> DQSA_RN[0:7]

GDDR3 BGA MEMORY

2
2
1000P_0402_50V7K

2
2
2
0.01U_0402_16V7K 0.1U_0402_16V4Z

GDDR3 BGA MEMORY

+1.8VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1
1
1
1
1
1
1
1
C894
C895
C896
C897
C898
C899
C900
C901
2
0.1U_0402_16V4Z

10U_0805_10V4Z
1
1
C902
C903

2
1U_0402_6.3V4Z

C904

2
22U_0805_6.3V6M

2
2
1000P_0402_50V7K

FBACLK0

<32> FBACLK1

2
2
0.01U_0402_16V7K

2
0.1U_0402_16V4Z

FBACLK0#

<32> FBACLK1#

Issued Date

2
0.1U_0402_16V4Z

10U_0805_10V4Z
1
C914

C913

2
1U_0402_6.3V4Z

C915

2
22U_0805_6.3V6M

FBACLK1#

2007/02/12

Compal Electronics, Inc.

2008/02/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

1U_0402_6.3V4Z
1
C912

C911

Compal Secret Data

Security Classification

R614
475_0402_1%~D

1
<32> FBACLK0#

0.1U_0402_16V4Z
1
C909
C910

R613
475_0402_1%~D

FBACLK1

<32> FBACLK0

0.01U_0402_16V7K
0.1U_0402_16V4Z
1
1
1
1
C905
C906
C907
C908

+1.8VS

Title

VRAM GDDR3 A
Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

35

of

49

+3VALW to +3VS Transfer

+5VALW to +5VS Transfer

+3VALW

+1.8V to +1.8VS Transfer

+3VS

+B+_BIAS

+5VALW

+5VS

+1.8V

C271

SI4800DY_SO8
2 10U_0805_10V4Z~N

2
1
SUSP

1
2
R197
1
100K_0402_5%

RUNON

Q18
S SSM3K7002FU_SC70-3

2
G

C465

C256

C278

S
S
S
G

D
D
D
D

1
2
3
4

SI4800DY_SO8
2 10U_0805_10V4Z~N

C284

C283
10U_0805_10V4Z~N

2
2
0.1U_0402_16V4Z~N

3VS_GATE

RUNON 1
2 1 5VS_GATE
R267
C279
47K_0402_5%
0.01U_0402_25V7K~N
2

0.1U_0402_16V4Z~N
C264
0.01U_0402_25V7K~N

8
7
6
5

4.7A

U41

S
S
S
G

U39
R559
47K_0402_5%

R198

D
D
D
D

10U_0805_10V4Z~N

1
2
3
4

VGA_PWGOD#
SUSP

2
G

1 R665
2
@ 0_0402_5%

8
7
6
5

+1.8VS

+B+_BIAS

U40

330K_0402_5%

8
7
6
5

D
D
D
D

10U_0805_10V4Z~N

1
2
3
4

S
S
S
G

C727
SI4800DY_SO8
2 10U_0805_10V4Z~N

C728

C697
1

0.1U_0402_16V4Z~N
2
2

1.8VS ON 1
1.8VS_GATE
2
R608
1
100K_0402_5%
C696
D
0.01U_0402_25V7K~N
2
Q48
S SSM3K7002FU_SC70-3

+3VALW

R409

Q42
SSM3K7002FU_SC70-3

2
G

<26,27,43> SYSON

SYSON#
SYSON

100K_0402_5%

R365
10K_0402_5%

+5VALW
+VGA_CORE

2
SUSP
3

S Q61
SSM3K7002FU_SC70-3

+1.8V

1
D
VGA_PWGOD#

2
G

+5VS

S Q65
SSM3K7002FU_SC70-3

2
G

S Q62
SSM3K7002FU_SC70-3

+0.9VS

1
1

2
G

R338
10K_0402_5%

R609
470_0603_5%

SUSP

Q32
SSM3K7002FU_SC70-3

Discharge circuit-1

R647
470_0603_5%

R646
470_0603_5%

VGA Discharge circuit

2
G
3

<26,27,30,42,44,46> SUSP#

SUSP#

1 1

SUSP

SUSP

100K_0402_5%
<30,46>

+1.8VS
2

+1.1V_GFX_PCIE
R340

+1.5VS

+3VS

Q49
SSM3K7002FU_SC70-3

R382 @
470_0603_5%

R383
39_0603_5%

R391 @
470_0603_5%

S Q33 @
SSM3K7002FU_SC70-3

D
SUSP

2
G

S Q39 @
SSM3K7002FU_SC70-3

S Q12 @
SSM3K7002FU_SC70-3

D
SUSP

2
G

SUSP

2
G

SUSP

2
G

SYSON#
Q50
SSM3K7002FU_SC70-3
@

1
D

2
G

2
G

S Q37 @
SSM3K7002FU_SC70-3

2
G

S Q38
SSM3K7002FU_SC70-3

SYSON -> SUSP# -> VGA_ON->VGA_PWGOD

B

2007/1/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R351 @
470_0603_5%

1
2
1

VGA_PWGOD

<45> VGA_PWGOD

SUSP

VGA_PWGOD#

100K_0402_5%
4

1
R551
100K_0402_5%

R133 @
470_0603_5%

R536 @
470_0603_5%

R668

+3VALW
1

+5VALW

+1.8VS_CB

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

DC/DC Circuits
Size Document Number
Custom LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
E

36

of

49

KAL80 POWER UP SEQUENCE

ACIN/BATT-IN
51ON#
(only BATT-IN)

126ms
5VALW/3VALW
RSMRST#
Suspend Clock (32KHz)
ICH9 internal clock

SUSCLK
ON/OFF#
EC_ON
PWRBTN_OUT#
SYSON#
1.8V
SLP_S5#
SLP_S4#
SLP_S3#
SUSP#
+5VS
+3VS

644ms

864us

244ms

360ms

1.59ms
2.74ms

250ms
30.6us
30us

3.88s 888us
104us
112us

+1.5VS
2.02ms

1.46ms
24.1ms
1.20ms
5.26ms

+0.9VS
VCCP
VR_ON
CPU_CORE

This signal is
asserted high when
both SLP_S3# and
VRMPWRGD are high

VGATE

CK_PWRGD

1.03ns

114ms 1.20ms

1.06ms

2.20ms

CLK_MCH_BCLK
ICH_PWROK
PCI_RST#
H_PWRGOOD
H_RESET#

Title
Power Sequence
Size
Document Number
CustomLA-4595P
Date:
A

Tuesday, February 17, 2009

Rev
1.0
Sheet

37

of

49

Version Change List ( P. I. R. List )

Item Page#
D

Title

Request
Date Owner

Swap SW1

12/02

EE

Update JUSBP3 pin define

12/02

EE

R405 POP

12/02

EE

U50 unPOP & R1190 POP

12/02

EE

WWAN move to PORT6

12/02

BIOS

Page 1/1

Issue Description

Solution Description

Rev.
D

Add C1391 & C1392

12/02

NVidia

Swap JSPK1 Pin

12/02

EE

LVDS single channel issue

Short U59.V2 & U59.V3. Add C1391 C1392 for IFPB_IOVDD

R101

12/04

EE

TPM Con

12/04

EE

Modify to Con

10

R76 & R78 UnPOP

12/09

EE

EC update to Rev:C1

11

Q7 & Q9

12/09

EE

Update Q7 & 9 footprint

12

R658 & R281

12/11

EE

R685 UnPOP & R281 UnPOP for wake on LAN

13

U89 & WLANPW_DIS#

12/11

EE

Add U89 for wake on LAN. Add WLANPW_DIS# of EC

14

C1484 & C1485

12/11

EE

C1484 & C1485 modify to 1U form LAN vendor

15

Update PW schematic

12/12

PW

16

C260 & C252

12/15

EE

IDT ask UnPop

17

Add D29 D28

12/15

ESD

ESD for LAN

18

U9 Pop & U10 UnPop

12/15

ME

19

Wake On WLAN

12/16

EE

20

Add T49 & T53

12/16

Layout

21

C696

12/16

EE

Update PN

22

WLANPW_DIS#

12/17

EE

Move WLANPW_DIS# to EC-GPIO40 and Del BTOP_ON

23

L42 & L43

12/17

EMI

L42 & L43 update to Bead from 0 ohm

24

C3 C4 C6 C14 C17

12/17

EMI

POP 100 P

25

R69

12/17

EE

Update to Bead drom 100 ohm

26

Cap

12/17

EMI

Add C1469 C1470 C1471 C1472 C1481 R81

ESD ask POP

Change to 0805

Modify WLANPW_DIS# circuit

27

D21 D12 D17

12/17

ESD

28

Update PW schematic

12/17

PW

29

Update Q128 Q130 PN

12/18

EE

30

Update Board ID

12/18

EE

31

Add U16 for OZ888

12/18

EE

32

C1323 POP

12/18

EE

33

R1421 UnPOP

12/22

EE

34

C292 C297

12/22

EE

Modify to 22P form 18P (Crystal Vendor)

35

C1745 C1749

12/22

EE

Modify to 18P form 10P(C1749) and 15P from 10P(C1745)(Crystal Vendor)

36

C1211

12/22

EE

Modify to 12P form 15P (Crystal Vendor)

37

R1423 & R1422

01/07

EE

Add for O2

38

L6 & R1190

01/10

EE

Change to 0805

39

Modify LDO to +5VS

01/12

EE

40

Add C80 & D59 & D60

01/12

EE

41

Add components of JHP1

01/13

EE

For vendor

42

R360 & R361

01/19

EE

Update R360 & R361 to 56 ohm

43

U37

01/19

EE

Update U37 to SA00001KN10

44

R231

01/19

EE

Update Board ID

R231
For Kepart

2007/1/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

EEW PIR-1
Size Document Number
Custom
LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

38

of

49

PL16
FBM-L11-160808-601LMT 0603~D
2
1 DOCK_PSID

PJPDC1
TYCO_1566065-2~D

2
PR189
@ 1M_0402_1%~D
1
2
VIN

N40

N35

+
-

@
PC163
1000P_0402_50V7K~D

PU12A
O 1

VIN

CH751H-40PT_SOD323-2

1 1

RLS4148_LL34-2
1

5
PJP1
@ JUMP_43X118
1
2
1
2

PD4
2

BATT+

PR198
10K_0402_5%~D
1

LM393DR_SO8

RTCVREF

Vin Detector

51ON#

@
PR195
10K_0402_5%~D

L-->H
H-->L

VS

Max.
18.234
17.597

typ.
17.841
17.210

Min.
17.449
16.813

32.8
PC165
0.1U_0603_25V7K~D

<28>

<19,27,40>

PC164
2
1

PR206
22K_0402_1%~D
1
2

0.22U_1206_25V7K~D

1
PR205
100K_0402_5%~D

PQ50
TP0610K-T1-E3_SOT23-3
1

ACIN

3.3V

@
PU12B
7
O

PR203
PR204
68_1206_5% 68_1206_5%
CHGRTCP

@
PD1
RLZ4.3B_LL34

LM393DR_SO8

2
PD3

PC161
2
1

PR193
@ 22K_0402_1%~D
1
2

PR191
@ PR192
@PR192
10K_0402_5%~D
1K_0402_5%~D
1
2

PR194
19.6K_0402_1%~D
2
1

PC162
.1U_0402_16V7K~D

N41
@

PR190
82.5K_0402_1%~D

1
2

VS

VIN

0.01U_0402_25V7K~D

PC159
1000P_0402_50V7K~D
2
1

PC160
100P_0402_50V8J~D
2
1

1000P_0402_50V7K~D

PC157

1
2

PC158
100P_0402_50V8J~D

1
2

PC314
0.1U_0603_25V7K~D

PC312
1000P_0402_50V7K~D

DC-_2

GND_1
MH1
MH2

DC-_1

GND_2

VIN
PL17
SMB3025500YA_2P

DC+_2

GND_3

DC+_1

ADPIN

PC311
100P_0402_50V8J~D

Low_PWR
GND_4

PC313
0.01U_0402_25V7K~D

RTCVREF

PR207
200_0805_5%
APL5156-33DI-TRL_SOT89-3
PU14

+5VALWP

+3VALWP

PR208
1
2
0_0402_5%~D

PQ53
DOCK_PSID

PR212
33_0402_5%~D
1
2

PR209
2.2K_0402_5%~D
1
2

PC167
1U_0805_25V4Z~D

PD5
DA204U_SOT323

GND

VIN

PC166
2
1

4.7U_0805_6.3V6K~D

VOUT

3.3V

PS_ID

<27>

PJP5
@ JUMP_43X118
1
2
1
2

+VCCPP

+3VALWP

PJP7
@ JUMP_43X118
1 1
2 2

+3VALW

+1.8VP

PJP9
@ JUMP_43X118
1 1
2 2

+1.8V

PJP11
@ JUMP_43X118
1 1
2 2

PJP8
@ JUMP_43X118
1
2
1
2

+VCCP

2
G
PQ54
MMST3904-7-F_SOT323-3
E

@
PD7
SM24_SOT23

PD6
DA204U_SOT323

1
C

2
B

+0.9VS

+1.5VS

PR214
10K_0402_1%~D

+0.9VSP

PJP6
@ JUMP_43X118
1
2
1
2

+5VALW

+1.5VSP

+1.1V_GFX_PCIE

+5VALWP
+5VALWP

+5VALWP

PJP3
@ JUMP_43X118
1
2
1
2

PJP4
@ JUMP_43X118
1 1
2 2

+1.1V_GFX_PCIEP

PJP2
@ JUMP_43X118
1 1
2 2

PR215
PR213
15K_0402_1%~D 100K_0402_1%~D
1
2
1
2

FDV301N_NL_SOT23-3~D

PR216
1
@

PSID_DISABLE# <27>

2
10K_0402_1%~D

PJP10
@ JUMP_43X118
1 1
2 2

+VGA_COREP

PJP12
@ JUMP_43X118
1 1
2 2
PJP14
@ JUMP_43X118
1 1
2 2

+VGA_CORE

Compal Secret Data

Security Classification
Issued Date

2006/10/1

2007/5/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

DCIN / Vin Detector

Size Document Number
Custom
LA-4595P
Date:

Rev
1.0
Sheet

Tuesday, February 17, 2009

1

39

of

49

PR226
340K_0402_1%~D

DL_CHG

23

LODRV

OVPSET

Input OVP : 22.3V

9

AGND

LEARN

ACOFF

4
3
2
1
G
S
S
S
D
D
D
D
5
6
7
8

PC185
.1U_0402_16V7K~D
1
2

CELLS

20

1
2

<27>

VREF

PC186
0.1U_0603_25V7K~D

PC187
0.1U_0603_25V7K~D

CELLS

PC223
10U_1206_25V6M~D

PC173
4.7U_1206_25V6K~D

PC316
2
1000P_0402_50V7K~D
1

PC172
1
2

4.7U_1206_25V6K~D
2

PR227
54.9K_0402_1%

Fsw : 300KHz

21

BATT+

Input UVP : 16.98V

22

PGND
OVPSET

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=4.27A

PC315
2

CP setting

PQ58
FDS4435BZ_SO8

PC181
10U_1206_25V6M~D

PC361
2
1 2

1U_0603_10V6K~D

Icharge=(Vsrset/Vvdac)*(0.1/PR34)=3.34A

2
7 ACOP
PC184
0.47U_0603_16V7K~N

PC183
4

PQ59
FDS6690AS_NL_SO8

1
1

PC182
0.01U_0402_25V7K~D
@

RLS4148_LL34-2
PC179
0.1U_0603_25V7K~D

24

REGN

ACSET

PR225
100K_0402_1%~D

/BATDRV

PR218
100K_0402_1%~D

PC180
10U_1206_25V6M~D

5
6
7
8

ACSET

PR394
1

PH

PC168

PR222
PL18
0.02_2512_1%
10UH_SIL1045RA-100PF_4.5A_30%
1
2
1
4

LX_CHG
PD8

25

REGN

+3VALW

PR224
56.2K_0402_1%
1
2

ACDRV
ACDET

DH_CHG

26

HIDRV

3
2
1

ACN
ACP

PQ57
FDS8884_SO8

PR220
2.2_0603_5%~D
1
2

27

BTST

2
28

PVCC

4
5

ACDET

90W adapter

CHG_B+

5
6
7
8

CHGEN#

CHGEN

PC176
0.1U_0603_25V7K~D

PC178
0.1U_0603_25V7K~D

2
3

PR223
54.9K_0402_1%

PC177
0.1U_0805_25V7K
1
2

PU15
1

PC175
.1U_0402_16V7K~D
1
2

PR221
340K_0402_1%~D

PC169
2.2U_0805_25V6K

JUMP_43X118

1000P_0402_50V7K~D
1

2
@

PC171

4.7U_1206_25V6K~D

PJP15
1

8
7
6
5

D
D
D
D

PR219
100K_0402_1%~D

2
1

S
S
S
G

+B+
PR217
0.015_2512_1%

4.7_1206_5%~D

1
2
3
4
PC174
0.01U_0402_25V7K~D
2
1

1
2
3
4

2
1

1
1 2
2

PR272
PR339
3.3_1210_5%~D 3.3_1210_5%~D

S
S
S
G

PC170
0.01U_0603_50V7K~D

2
1

D
D
D
D

PQ56
FDS4435BZ_SO8

0.01U_0402_25V7K~D

8
7
6
5

680P_0603_50V7K~D

PQ55
FDS4435BZ_SO8

VIN

3
2
1

1
2

VADJ
2

REGN

IREF

<27>

100K_0402_1%~D
2

PR233
10_0603_5%~D

PR232
100K_0402_1%~D

PR230
PC191
@0.01U_0402_25V7K~D

ACIN
1

<27>

ACGOOD#

ADP_I
PC192
100P_0402_50V8J~D

CHGVADJ=9.3755*(charger voltage per cell - 4)

Current

2.968V

3A

+COINCELL

EC DA pin

CHGVADJ

PR1
1K_0402_5%~D

1
3

Z4012

CHGEN#
+RTCVCC

1
27.4

PQ65
SSM3K7002F_SC59-3

2
G

<27> FSTCHG
PD2
BAT54CW_SOT323~D

PR397
340K_0402_1%~D
2

+COINCELL

PQ90
SSM3K7002F_SC59-3

2
G

PR237
100K_0402_1%~D

PQ89
SSM3K7002F_SC59-3

2
G
D

PJP24

PR396
100K_0402_1%~D

1
3

PR395
200K_0402_1%~D
D

VREF

COIN RTC Battery

GATE

RTCVREF

VREF

VREF

PC362
.1U_0402_16V7K~D

IREF

PQ62
SSM3K7002F_SC59-3
3

4V

<19,27,39>

2
G

4.35V

0V

+B+_BIAS

ACOFF 1
RHU002N06_SOT323

PR234
100K_0402_1%~D

3.282V

1
S

2
1
49.9K_0402_1%~D

VADJ

2
D

15

Pre Cell

PR53 = 210K

0.1U_0805_25V7M~D

2
1
1

1
2
2
1

PC193

PQ64
2
G

220K_0402_5%

32.8

32.8

1SS355_SOD323-2 PR236
1
2

PD9

PR239

2
PR238
1
PC194
0.1U_0603_25V7K~D
2
1

220K_0402_5%

+5VALW

PQ63
TP0610K-T1-E3_SOT23-3
1

100_0805_5%~D

470K_0402_5%~D

BATDRV

BQ24751ARHDR_QFN28_5X5

CHGVADJ

PR54
499K_0402_1%~D

+B+

VREF
PR231

16

SRSET

IADAPT

PR51
@ 0_0402_5%~D
PR53
210K_0402_1%~D
1
2

<27> CHGVADJ

PR235

14

Cells selector
3

/BATDRV

RTCVREF

ICHG setting

ACGOOD

13

PC190
0.1U_0603_25V7K~D

29

TP

ACSET

12

1
3

17

BAT
VADJ

ACGOOD#
2
3cell/4cell# <48>
G
PQ61
SSM3K7002F_SC59-3

18

SRN

CELLS
D

19

SRP

VDAC

PC189
0.1U_0603_25V7K~D

1
2

1
PR371
0_0402_5%~D

+3VALW

PR229
47K_0402_1%~D

11

4 Cell

PR370
0_0402_5%~D

VREF

3 Cell

PC188
1U_0603_10V6K~D

VREF

GND

CELLS

PR228
100K_0402_1%~D
1
2 GATE

PQ60
SI2301BDS-T1-E3_SOT23-3
VREF

10

SUYIN_060003FA002G201NL~D
4

PC1
1U_0603_10V4Z~D

2006/10/1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/5/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title
Size
B
Date:

Charger/RTC BATTERY

Document Number

Rev
1.0

KML50

Tuesday, February 17, 2009

Sheet
E

40

of

49

TPS51427_B+

TPS51427_B+

+B+

VBST1

BST5A 2

PR245
1

2.2_0603_5%~D
PC205
0.1U_0603_25V7K~D

PQ69
AO4712_SO8
PC208

LL1

16

0.1U_0603_25V7K~D
LX5

DRVL1

18

DL5

PGND

22

VOUT1

10

FB1

11

VSW

LX3

LL2

3
2
1

25

DL3

23

FB3

30
32

VL

DRVL2

VOUT2

PC216
0.1U_0603_25V7K~D
2
1

PC200
2200P_0402_50V7K~D
2
1

PC199
4.7U_1206_25V6K~D
2
1

REFIN2

2VREF_TPS51427
1

PR246
61.9K_0402_1%~D
1
2

DH5

17

VBST2

PC198
4.7U_1206_25V6K~D
2
1

3
2
1

19
15

5
6
7
8

4.7U_0805_6.3V6K~D

PC203
2
1

1U_0603_10V6K~D

V5FILT

V5DRV

DRVH1

PC209

24

DRVH2

1
2
3

PR243
1 BST3A
2.2_0603_5%~D

TP

26

PR242
4.7_1206_5%~D
1
2
1

33

+5VALWP

PL21
2
1
3.3UH_1164AY-3R3N-P3_7.5A_30%

PC207
1U_0603_10V6K~D
1
2

PQ68
AO4712_SO8

VIN

8
7
6
5

DH3

1
+ PC210
330U_D3L_6.3VM_R25M

PR248
10K_0402_1%~D
1
2

PC206
PR241
680P_0603_50V8J~D
4.7_1206_5%~D
2
1
2
1

2
2

PR244
0_0402_5%~D

PC204
330U_D3L_6.3VM_R25M

PR247
10K_0402_1%~D

PU16

1
2
3

PQ67
AO4466_SO8

LDO

PC201
0.1U_0603_25V7K~D

PC202
1
2

8
7
6
5
PQ66
AO4466_SO8

PL20
1
2
3.3UH_1164AY-3R3N-P3_7.5A_30%

+3VALWP

5
6
7
8

VL

680P_0603_50V8J~D
2

PC197
2200P_0402_50V7K~D
2
1

PC196
4.7U_1206_25V6K~D
2
1

PC195
4.7U_1206_25V6K~D
2
1

PR240
0_0805_5%~D
1
2
PC215
0.1U_0603_25V7K~D
2
1

PJP20
@ JUMP_43X118
1 1
2 2

FB5

VREF2

PC211 0.22U_0603_10V7K~D

LDOREFIN

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

SKIPSEL

@ PR249
2

29

PR250
1

PGOOD1

13

EN2

PC213
0.047U_0603_16V7K~D

POK

<19>

PR253

TRIP1

12

TRIP1

309K_0402_1%
2
1

TRIP2

31

TRIP2

1
B

309K_0402_1%
SN0806081RHBR_QFN32_5X5

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

PR258
@

PC308

PR256
0_0402_5%~D

VL

0_0402_5%~D
2

PR255

GND

27

21

EN1
TONSE

14

VREF3

EN_LDO

2VREF_TPS51427 2

PQ74
TP0610K-T1-E3_SOT23-3

28

1U_0603_10V6K~D

0_0402_5%~D

PGOOD2

2
1

PR260
@ 47K_0402_5%~D

2VREF_TPS51427 1

<48> MAINPW ON

PR259

@ PR254
0_0402_5%~D

PR257

VL

PC214
0.047U_0402_16V7K~D
2
1

PC212
0.22U_0603_25V7K~D

806K_0603_1%~D

Iocp=8.94A

NC

20

PR251
100K_0402_1%~D
1
2

PD10
RLZ5.1B_LL34
1
2

VS

PR252
200K_0402_5%~D
1
2

3.3VALWP
Imax=6A

0_0402_5%~D
1

5VALWP
Imax=6A

0_0402_5%~D

Iocp=8.81A

PD16

1SS355TE-17_SOD323-2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/10/1

Issued Date

Deciphered Date

2007/05/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+3VALWP, +5VALWP

Size
Document Number
Custom
LA-4595P
Date:

Tuesday, February 17, 2009

Rev
1.0
Sheet
1

41

of

49

PJP25
VCCPP_B++

5
6
7
8
PR342

PQ79
FDS8884_SO8

3
2
1

PC218
0.1U_0603_25V7K~D

2
PQ80
FDS6676AS_SO8

TPS51117RGYR_QFN14_3.5x3.5

PC323
@ 680P_0603_50V8J~D

DRVL

PC325
4.7U_0805_10V6K~D

PC322

220U_D2_4VM

LG_VCCP

+VCCPP
PC321

PR346
@ 4.7_1206_5%~D

11
10

PR345
0_0603_5%~D

2 1

TRIP
V5DRV

PR347
TRIP_VCCP
1
2
10.2K_0402_1%~D
V5DRV_VCCP

5
6
7
8

LX_VCCP

PL29
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

G
S
S
S

TP

Iocp=14.04A
Fsw=298KHz

D
D
D
D

12

LL

4
3
2
1

PGOOD

UG_VCCP

PC326
47P_0402_50V8J~D
2
1

14

15

VFB

V5FILT

PGND

PC324
1U_0603_10V6K~D

FB_VCCP

13

VOUT

DRVH

+5VALW

VBST

TON

V5FILT_VCCP 4

1
2

EN_PSV

PU23

PR344
300_0603_5%~D
1
2

+5VALW

0.1U_0603_25V7K~D

TON_VCCP

PC319
1
2

2.2_0603_5%~D

GND

PC320
.1U_0402_16V7K~D
@

PR343
30.1K_0402_1%~D

BST_VCCP1

EN_VCCP

+B+

4.7U_0805_6.3V6K~D

PR341
0_0402_5%~D
2
1

1
JUMP_43X118
@

FDS6676AS
Rds(on)=5.9mohm~7.25mohm
VCCPP
Imax=9A

PR340
267K_0402_1%~D
1
2

<26,27,30,36,44,46> SUSP#

1
2

1
2

PC318
10U_1206_25V6M~D

PC317
10U_1206_25V6M~D

PC217
2200P_0402_50V7K~D
2
1

1
PR348
8.66K_0402_1%~D

PR349
21.5K_0402_1%~D

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/2/5

Issued Date

Deciphered Date

2009/2/5

+VCCPP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

42

of

49

PJP26
+1.8VP_B++

1
2

5
6
7
8
PR352

0.1U_0603_25V7K~D

PQ81
FDS8884_SO8

Iocp=10.95A
Fsw=297KHz

3
2
1
LG_1.8

DRVL

5
6
7
8
D
D
D
D
G
S
S
S

TP

TPS51117RGYR_QFN14_3.5x3.5

2 1

PC335
4.7U_0805_10V6K~D

PC331

PC334
@ 680P_0603_50V8J~D

PC332

+
220U_D2_4VM

PQ82
FDS6670AS_NL_SO8

PR356
@ 4.7_1206_5%~D

TRIP_1.81
2
12.1K_0402_1%~D
V5DRV_1.8

+1.8VP

11
10

PR355
0_0603_5%~D

TRIP
V5DRV

PR357

14

LX_1.8

PC336
47P_0402_50V8J~D
2
1

12

PL30
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

3
2
1

PGOOD

LL

VFB

UG_1.8

V5FILT

DRVH

13

FB_1.8

+5VALW

VBST

V5FILT_1.8

PGND

VOUT

PC333
1U_0603_10V6K~D

15

TON

EN_PSV

PU24

PR354
300_0603_5%~D
1
2

PC329
1
2

TON_1.8

+5VALW

2.2_0603_5%~D

GND

PC330
.1U_0402_16V7K~D
@

PR353
30.1K_0402_1%~D

BST_1.8

EN_1.8

+B+

4.7U_0805_6.3V6K~D

PR351
0_0402_5%~D
2
1

1
JUMP_43X118
@

FDS6670AS
Rds(on)=9mohm~11.5mohm
1.8VP
Imax=9A

PR350
267K_0402_1%~D
1
2

<26,27,36> SYSON

PC220
0.1U_0603_25V7K~D

1
2

1
2

PC328
10U_1206_25V6M~D

PC327
10U_1206_25V6M~D

PC219
2200P_0402_50V7K~D
2
1

1
PR358
30.1K_0402_1%~D

PR359
21.5K_0402_1%~D

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/10/1

Issued Date

Deciphered Date

2007/05/30

+1.8VP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

43

of

49

PJP27
+1.5VSP_B++

PC222
0.1U_0603_25V7K~D

1
2

PC338
10U_1206_25V6M~D

1
2

PC337
10U_1206_25V6M~D

PC221
2200P_0402_50V7K~D
2
1

+B+

JUMP_43X118
@

AO4712
Rds(on)=15mohm~18mohm
1.5VSP
Imax=3.5A

5
6
7
8

PR360
267K_0402_1%~D
1
2
PR362

0.1U_0603_25V7K~D

PQ83
AO4466_SO8

Iocp=6.87A
Fsw=298KHz

LG_1.5

TPS51117RGYR_QFN14_3.5x3.5

PC341

PC345
4.7U_0805_10V6K~D

PC344
@ 680P_0603_50V8J~D

PC342

220U_D2_4VM

DRVL

PQ84
AO4712_SO8
4

PR367
@ 4.7_1206_5%~D

TRIP_1.51
2
12K_0402_1%~D
V5DRV_1.5

+1.5VSP

11
10

PR366
0_0603_5%~D

2 1

TP

TRIP
V5DRV

PR365

PGOOD

LX_1.5

14

3
2
1

12

5
6
7
8

VFB

LL

PL31
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

3
2
1

V5FILT

UG_1.5

FB_1.5

13

V5FILT_1.5

DRVH

VOUT

PC346
47P_0402_50V8J~D
2
1

+5VALW

VBST

PGND

TON

PC343
1U_0603_10V6K~D

15

1
2

EN_PSV

PU25

PR364
300_0603_5%~D
1
2

PC339
1
2

TON_1.5

+5VALW

2.2_0603_5%~D

GND

PC340
.1U_0402_16V7K~D
@

PR363
30.1K_0402_1%~D

BST_1.5

EN_1.5

4.7U_0805_6.3V6K~D

PR361
0_0402_5%~D
2
1

<26,27,30,36,42,46> SUSP#

1
PR368
22.1K_0402_1%~D

PR369
22.1K_0402_1%~D

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/2/5

Issued Date

Deciphered Date

2009/2/5

+1.5VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

44

of

49

PJP28
VGA_B++

PHASE_VGA

6268_VGA

UG_VGA

PR399
10K_0402_1%~D

PR400

15

16

BOOT

UG

PVCC_VGA
2

VIN

PHASE

6268_VGA

2
PGOOD

8
GND

PVCC

14

LG

13

PGND

12

ISEN

11

Iocp=10.74A
Fsw=301KHz

PR401
0_0603_5%~D
PR403
4.7_0603_5%
1
2 6268_VGA

PQ85
FDS8884_SO8

PC368
1
2

LG_VGA

PL32
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

PC352

1
2

PC371

2
1

PR411
1.5K_0402_1%~D

1
2

1
2

2
<31>

2
1

PC379
0.01U_0402_16V7K~D

PR421
100K_0402_5%~D

1
1

PC380
0.01U_0402_16V7K~D

PR424
100K_0402_5%~D

PR423
10K_0402_5%~D
@

PQ87
BSS138W -7-F_SOT323

2
G

PR418
10K_0402_5%~D

PR415
4.7K_0402_1%~D

2
1

2
2
1

PR416
10K_0402_5%~D

PR420
10K_0402_5%~D
@

PR413
3K_0402_1%~D

+3VS

PC378
820P_0402_50V7K~D

2
PR419
10K_0402_5%~D

NVVDD_SENSE <33>

FB_VGA

PR417
11.5K_0402_1%~D

2
PR408
0_0402_5%~D

44.2K_0402_1%~D

PR414
0_0402_5%~D

+3VS

1
PC375
0.01U_0402_25V7K~D

PR410

output voltage adjustable network

PR422
10K_0402_5%~D

3
2
1

10

9
FSET_VGA

PR409
33K_0402_1%~D

PR407
10_0402_1%~D

PR412
0_0402_5%~D

<31> GPU_VID0

PC373
@ 680P_0603_50V8J~D

220U_X_2VM

VO

PR406
11.8K_0402_1%~D

2 1

PQ86
FDS6690AS_NL_SO8

4.7U_0805_6.3V6K~D

2
5
6
7
8
ISEN_VGA
1

1.17V
1
1

PC376
2200P_0402_25V7K~D

1
2

PC374

68P_0402_50V8J~D

COMP_VGA

0.90V 1.09V
GPU_VID_0
0
0
GPU_VID_1
0
1

+VGA_COREP

PR404
4.7_1206_5%~D

FSET

EN

PC372
.1U_0402_16V7K~D

FB

COMP

VGA_ON

EN_VGA

ISL6268CAZ-T_SSOP16

PR405
22K_0402_1%~D
1
2

<27>

PC370
2.2U_0603_6.3V6K~D

VCC

3
2
1

2.2U_0603_6.3V6K~D
PC369
0.1U_0603_25V7K~D
@

VIN_VGA

PC367 0.1U_0603_25V7K~D

2
1

BOOT_VGA

PU26

2.2_0603_5%~D
+5VALW

<36> VGA_PW GOD

PR402
0_0603_5%~D

FDS6690AS
Rds(on)=12mohm~15mohm
+VGA_COREP
Imax=7A

5
6
7
8

PC366
0.1U_0603_25V7K~D

PC365
10U_1206_25V6M~D
2
1

1
2

PC363
2
1

PC364
10U_1206_25V6M~D
2
1

JUMP_43X118
@

2200P_0402_50V7K~D

+B+

PC377
820P_0402_50V7K~D

PQ88
BSS138W -7-F_SOT323

2
G

GPU_VID1

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/2/5

Issued Date

Deciphered Date

2009/2/5

+VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size

Document Number

Rev
1.0

LA-4595P
Date:

Tuesday, February 17, 2009

Sheet
1

45

of

49

+5VALW

+1.5VSP

PJP18

1
1
2
2

NC

VREF

NC

VOUT

NC

TP

8
9

PC270

PQ78

PR320

PC271
1U_0603_10V6K~D

2
G

PC272
@
.1U_0402_16V7K~D

+0.9VSP

0_0402_5%~D
1
2

SUSP

<30,36>

+3VALW
4.7U_0805_6.3V6K~D

VCNTL

GND

PC268
2
1

1
2

PC267
4.7U_0805_6.3V6K~D

VIN

APL5331KAC-TRL_SO8

1
2

0.01U_0402_25V7K~D

PR318

PR323
2.61K_0402_1%~D

PC277
.1U_0402_16V7K~D
@

PR317
1K_0402_1%~D

APL5913-KAC-TRL_SO8

PC275
2

PC276
10U_0805_6.3V6M~D

VIN

+1.1V_GFX_PCIEP

0_0402_5%~D

FB

PJP17
@ JUMP_43X118

PU20

EN

PR322
1K_0402_1%~D
1

2
1
1
1
2

6
VOUT
VOUT

PR321
2

GND

<26,27,30,36,42,44> SUSP#

POK

VIN

VCNTL

PU21

+1.8V

@ JUMP_43X118

PC274
4.7U_0805_6.3V6K~D

1
2

PC273
1U_0603_10V6K~D

RHU002N06_SOT323
.1U_0402_16V7K~D
1K_0402_1%~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/1

2007/05/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+0.9VSP/+1.1V_GFX_PCIEP
Size Document Number
Custom
LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

46

of

49

1
2
1
1

PC226
0.1U_0603_25V7K~D

PC155
100U_25V_M

PC113
100U_25V_M

PC116
10U_1206_25V6M~D
2
1

PC115
10U_1206_25V6M~D
2
1

PC114
10U_1206_25V6M~D
2
1

0.01U_0402_25V7K~D

PC119
2
1

PC118
1U_0603_10V6K~D
2
1

PR160
10K_0402_1%~D
2
1

1
2

PC228
0.1U_0603_25V7K~D

PC127
10U_1206_25V6M~D
2
1

1
2

PC227
2200P_0402_50V7K~D
2
1

PR159
2

3.65K_1206_1%

4.7_1206_5%~D
680P_0603_50V8J~D

SI7636DP-T1-E3_SO8

D
S
S
S

PC123
PR158
2
1 2
1

3
2
1

VSUM

PR170
10K_0402_1%~D
2
1

1_0402_5%~D

1
PR171

PC133
680P_0603_50V8J~D

PR172

PR173 @ 0_0402_5%~D
1
2
PC135
1
2
B

0.22U_0603_16V7K~D
ISEN2

+CPU_B+

2.61K_0402_1%~D
PH3

PR186 1K_0402_1%~D PR187 3.57K_0402_1%~D

10KB_0603_ERTJ1VR103J
PC144 0.068U_0603_50V7K~N
1
2
PC145
0.22U_0603_16V7K~D

PC146 0.22U_0603_10V7K~D
2
1

Compal Secret Data

Security Classification
2007/1/15

Issued Date

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PC225
2200P_0402_50V7K~D
2
1

<5>

PC120
1U_0603_10V6K~D
SI7636DP-T1-E3_SO8

3
2
1
G

1
2
2

1
11K_0402_1%~D

PR185

1
2
PR183 0_0402_5%~D
PC143 180P_0402_50V8J~D
1
2

VCC_PRM

4
4

PL15

VSUM
PC142
0.01U_0603_25V7K~D

PC141
@ 330P_0402_50V7K~D

<5> VSSSENSE

PR168
4.7_1206_5%~D

PC139 10_0603_5%~D
0.1U_0603_25V7K~D

PR182

0_0402_5%~D

2
PC140 330P_0402_50V7K~D
1
2

PR180

PQ48

PR178

1K_0402_1%~D

<5> VCCSENSE

PR174 1_0603_5%~D
PC136
1U_0603_10V6K~D

+CPU_B+

VCC_PRM

PR179

+5VS

PQ47

3.65K_1206_1%

ISEN1
24

ISEN2

VDD

23

22

GND
21

VIN
20

VSUM
19

VO
18

DFB

DROOP

100P_0402_50V8J~D

PR177
PC138 2200P_0402_50V7K~D
1
2
1
2
100_0402_1%~D
1
2

PR184
100K_0402_1%~D
@

PR176
1K_0402_1%~D

29.1
ISEN1
ISEN2
2

PR161
1_0402_5%~D

2.2_0603_5%~D
0.22U_0603_10V7K~D

PU11

PC126
10U_1206_25V6M~D
2
1

25

PC125
10U_1206_25V6M~D
2
1

NC

+CPU_CORE

PR162 @ 0_0402_5%~D
1
2
PC124
1
2
VCC_PRM
ISEN1
0.22U_0603_16V7K~D

FB2

PL14

P_0.36H_ETQP4LR36W FC_24A_20%

1 2

12

UGATE_CPU2
PR167
PC130
BOOT_CPU2
1
2
1
2

26

PHASE_CPU2

SI7636DP-T1-E3_SO8

27

BOOT2

PQ46
SI7686DP-T1-E3_SO8

UGATE2

FB

LGATE_CPU2

S
S
S

COMP

11

VSUM

LGATE_CPU1

10

3
2
1

28

PHASE2

3
2
1

VW

1
29

PR175 97.6K_0402_1%~D PC134 270P_0402_50V7K~D

1
2
2
1

PC137

<5>

D
30

PGND2

PC132 1000P_0402_50V7K~D

<5>

37
VID0

38

VID2

39

40
VID3

41
VID4

42
VID5

43
VID6

46

45

47

44
VR_ON

VID1

32
31

13

33

PVCC

17

PC131
1
2
1000P_0402_50V7K~D
PR169 8.25K_0402_1%~D
1
2

PGND1

LGATE2

16

PR166 11.5K_0402_1%~D
1
2

PHASE_CPU1

PQ45

34

ISL6266ACRZ-T_QFN48_7X7

P_0.36H_ETQP4LR36W FC_24A_20%
2
1

S
S
S

OCSET

PHASE1

LGATE1

UGATE_CPU1

3
2
1

SOFT

36
35

S
S
S

NTC

@ 100K_0603_1%_TH11-4H104FT
1
2
@ 0.015U_0402_16V7K
PC128
0.068U_0603_50V7K~N PC129
1
2

PQ44 @

3
2
1

PH2

2 1

BOOT1
UGATE1

SI7636DP-T1-E3_SO8

VR_TT#

DPRSLPVR

RBIAS

CLK_EN#

DPRSTP#

49

48
3V3

PR164 147K_0402_1%~D
1
2

PMON

RTN

VR_TT#
@ 4.22K_0402_1%
1

PSI#

VSEN

PR165

2
10K_0402_1%~D
2
3

15

PGOOD

PR181
2
1

<27> PC147
1U_0603_10V6K~D
1

14

POW _MON

0.22U_0603_10V7K~D
2 1
2

2.2_0603_5%~D

H_PSI#

<5>
CPU_VID2
<5>
CPU_VID1
<5>
CPU_VID0
<5>

BOOT_CPU1

VDIFF

<5>

PC122
PR155

<7,19,27> VGATE

PQ43
SI7686DP-T1-E3_SO8

0_0402_5%~D
2

GND

499_0402_1%~D

0_0402_5%~D
2

1
PR156

PR157

1.91K_0402_1%~D
PC121
1U_0603_10V6K~D

+3VS

0_0402_5%~D
2

PR154
1

+3VS

PC117
0.01U_0402_25V7K~D
2
1

PR145
1

CLK_EN#

PL13
FBMA-L18-453215-900LMA90T_1812
1
2
+B+

2
1
PR146 0_0402_5%~D
2
1
PR147 0_0402_5%~D
2
1
PR148 0_0402_5%~D
2
1
PR149 0_0402_5%~D
2
1
PR150 0_0402_5%~D
2
1
PR151 0_0402_5%~D
2
1
PR152 0_0402_5%~D

PR144
1

<5,7,18> H_DPRSTP#

+CPU_B+

PR142
1_0603_5%~D

499_0402_1%~D
2

<7,19> DPRSLPVR

<27>
CPU_VID3

5600P_0402_25V7K

PR143

PR153
0_0402_5%~D
2
1

CPU_VID4

CPU_VID5

VR_ON

PC112

CPU_VID6

+5VS

Title

Compal Electronics, Inc.

+CPU_CORE

Size
Document Number
Custom
Date:

Rev
1.0

LA-4595P

Tuesday, February 17, 2009

Sheet
1

47

of

49

PD12
PJSOT24C_SOT23-3

BATT+

PD13
PJSOT24C_SOT23-3

BATT++

Battery Connect/OTP

Place clsoe to EC pin

PR324
47K_0402_5%~D
1
1

2 BATT_TEMP

1.BAT+
2.BAT+
3.ID
4.B/I
5.TS
6.SMD
7.SMC
8.GND
9.GND

PJPB1 battery connector

10
11

GND
GND

1
2
3
4
5
6
7
8
9

PR326

1
2
3
4
5
6
7
8
9

3cell/4cell#

PC280
.1U_0402_16V7K~D
@

PJP19

SMART
Battery:

BATT_TEMP <27>

PR325
1K_0402_5%~D

1
2

PC278
0.01U_0402_25V7K~D

+3VALWP
PC310
100P_0402_50V8J~D

PC279
1000P_0402_50V7K~D

1
2

PC309
100P_0402_50V8J~D
2
1

PL28
SMB3025500YA_2P

BATT+

BATT++

1K_0402_5%~D
3cell/4cell# <40>
2
1
1

+3VALWP

PR327
6.49K_0402_1%~D

SUYIN_200275MR009G186ZL

EC_SMB_DA1 <27>

PR328
100_0402_5%~D

CPU

EC_SMB_CK1 <27>

PR329
100_0402_5%~D

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL

VS

BATT+

VL
PR333
147K_0402_1%~D
1
2

2
1

PR331
10.7K_0402_1%~D

PR332
499K_0402_1%~D

PR334
205K_0402_1%~D

1
PD11

0
-

PR336
150K_0402_1%~D

MAINPWON <41>

1SS355_SOD323-2
PU22A
LM358ADR_SO8

PH4
100K_0603_1%_TH11-4H104FT

PR338
150K_0402_1%~D
2

PC283
1000P_0402_50V7K~D

PR337
86.6K_0402_1%

3
2

VL

LM358ADR_SO8
5

PR335
61.9K_0402_1%~D
1
2

PC281
0.1U_0603_25V7K~D

1
+

0
G

BATT_OVP

CPU

<27>

PU22B

PC282
0.01U_0402_25V7K~D

PR398
10K_0402_1%~D
2
1

PR330
453K_0402_1%~D

VS

PC284
1U_0603_10V6K~D

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/1

2007/05/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

BATTERY CONN
Size Document Number
Custom
LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

48

of

49

Version Change List ( P. I. R. List )

Item Page#
1
D

Title

39

DCIN /Vin Detector

2
Charger

Page 1/1

Date

Request
Owner

08/12/08

COMPAL

common circuit design modify

change PR203 from 33 to 68 and add PR204 to 68

0.3

08/12/08

COMPAL

design modify

change PL17 from SM010018880 to SM010008E10

0.3

08/12/08

COMPAL

vendor FAE suggest

change PR272 PR339 from 1 to 3.3

0.3

Issue Description

Solution Description

Rev.

40

48

BATTERY CONN

08/12/08

COMPAL

design modify

change PL28 from SM010018210 to SM010008E10

0.3

39

DCIN /Vin Detector

08/12/12

COMPAL

increase capacitor for EMI request

add PC313 at 0.01uf and PC314 at 0.1uf

0.3

42

VCCPP

08/12/12

COMPAL

change resister for EMI request

change PR342 from 0 to 2.2

0.3

43

1.8VP

08/12/12

COMPAL

change resister for EMI request

change PR352 from 0 to 2.2

0.3

44

1.5VSP

08/12/12

COMPAL

change resister for EMI request

change PR362 from 0 to 2.2

0.3

9
10
11
12
C

13
14
15
16
17
18
19
20
21
22

23

24
25
26
27
28
29
30
31
32
33
A

34

2007/1/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PW PIR-1
Size Document Number
Custom
LA-4595P
Date:

Rev
1.0

Tuesday, February 17, 2009

Sheet
1

49

of

49